Stimulus generation method, device, storage medium and stimulus generator

Abstract

The present application provides a stimulus generation method, device, storage medium and stimulus generator, wherein the method includes: reading a test stimulus description file, generating multiple constraint instances and multiple sequence instances based on the test stimulus description file, the test stimulus description file including a sequence array and a constraint array, the sequence array being used to record sequence information of each sequence in a test case, and the constraint array being used to record constraint information of each sequence in a test case; generating a transmission packet queue based on the multiple sequence instances and the multiple constraint instances, splitting each sequence and the constraints of each sequence in the test case and saving them independently, thereby improving maintainability and reliability, improving the efficiency of developing test cases, and thereby improving overall verification efficiency.

Description

Technical Field

[0001] The present application belongs to the field of chip technology, and specifically relates to an excitation generation method, device, storage medium and excitation generator. Background Art

[0002] In large-scale, parallel, high-performance computing systems, limited cache space necessitates large-scale, high-bandwidth, low-latency interconnects to handle the movement of large amounts of computational data. Verifying the functionality and performance of these interconnects is crucial. Because these interconnects often consist of multiple levels of modules and numerous routing modules, verifying these interconnects using chip verification methods like UVM (Universal Verification Methodology) often involves the repetitive development of multiple levels of incentive constraints and the introduction of extensive duplication of code, requiring significant manpower and resulting in high maintenance costs. Summary of the Invention

[0003] In view of this, the purpose of this application is to provide a stimulus generation method, device, storage medium and stimulus generator to improve chip verification efficiency.

[0004] In a first aspect, an embodiment of the present application provides a stimulus generation method, the method comprising: reading a test stimulus description file, generating multiple constraint instances and multiple sequence instances based on the test stimulus description file, the test stimulus description file including a sequence array and a constraint array, the sequence array being used to record sequence information of each sequence in a test case, and the constraint array being used to record constraint information of each sequence in a test case; generating a transmission packet queue based on the multiple sequence instances and the multiple constraint instances.

[0005] The above-mentioned incentive generation method splits each sequence and each sequence constraint in the test case and saves them independently. The sequence in the test case adopts building block superposition, abandons the traditional multi-level UVM incentive constraint, thereby greatly improving maintainability and reliability. When it is necessary to modify the sequence or constraint, it is only necessary to obtain the content that needs to be modified and modify it without rewriting it, which is convenient for developers to generate or modify the test case, reducing the workload of developers. In addition, sequences are combined to form test cases, and there is a combined constraint relationship between sequences, which avoids the multi-level constraint of sequences in the prior art, improves the efficiency of developing test cases, and then improves the overall verification efficiency.

[0006] In an optional embodiment of the present application, the index value of the constraint array in the test stimulus description file is the number of the sequence array.

[0007] In an optional embodiment of the present application, the sequence array includes: sequencers participating in the stimulus, number of entries, synchronization status, and end status.

[0008] In an optional embodiment of the present application, the constraint array includes: a stimulus address and a stimulus action.

[0009] In an optional embodiment of the present application, generating multiple sequence instances based on the test stimulus description file includes: obtaining each sequence in the sequence array; instantiating each sequence based on instance parameters in the sequence to generate the multiple sequence instances, wherein the instance parameters include sequencers participating in the stimulus and read / write types.

[0010] In an optional embodiment of the present application, generating multiple constraint instances based on the test stimulus description file includes: instantiating the constraint description of each constraint in the constraint array to generate the multiple constraint instances; and associating the constraint instance under the constraint to each sequence instance under the corresponding sequence.

[0011] In an optional embodiment of the present application, the test stimulus description file is a command line parameter.

[0012] The above method uses command-line parameters to define test sequences, avoiding the massive amount of repetitive code introduced by repeated test stimulus development. This reduces the need for extensive recompilation and improves simulation efficiency. Furthermore, since hierarchical constraints are converted to command-line combination constraints, this also improves test case development efficiency, thereby increasing overall verification efficiency.

[0013] In the second aspect, an embodiment of the present application provides a stimulus generator, which includes: a parameter processor for reading a test stimulus description file, and generating multiple constraint instances and multiple sequence instances based on the test stimulus description file, wherein the test stimulus description file includes a sequence array and a constraint array, the sequence array is used to record the sequence information of each sequence in the test case, and the constraint array is used to record the constraint information of each sequence in the test case; a transmission packet generator for generating a transmission packet queue based on the multiple sequence instances and the multiple constraint instances.

[0014] In a third aspect, an embodiment of the present application provides an electronic device comprising: a memory and a processor, the processor being connected to the memory; the memory being used to store programs; and the processor being used to call the programs stored in the memory to execute any of the methods described in the first aspect.

[0015] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the method described in any one of the first aspects is executed.

[0016] Other features and advantages of the present application will be described in the following description. The purpose and other advantages of the present application can be realized and obtained through the structures specifically pointed out in the written description and the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without inventive work. The above and other purposes, features and advantages of the present application will be more clearly shown through the drawings.

[0018] Figure 1 A schematic diagram of a flow chart of an incentive generation method provided in an embodiment of the present application is shown;

[0019] Figure 2 A schematic block diagram of a stimulus generator in a UVM verification platform provided in an embodiment of the present application is shown;

[0020] Figure 3 A schematic block diagram of an excitation generator provided in an embodiment of the present application is shown;

[0021] Figure 4 A schematic structural diagram of an electronic device provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0022] Hereinafter, embodiments of the present application are described in detail with reference to the accompanying drawings. It should be noted that although the same elements are shown in different drawings, they will be represented by the same reference numerals. In the following description, specific details such as detailed configuration and components are provided to only help a comprehensive understanding of the embodiments of the present application. Therefore, it should be clear to those skilled in the art that various changes and modifications to the embodiments described herein may be made without departing from the scope of the present application. In addition, for the sake of clarity and conciseness, descriptions of well-known functions and configurations have been omitted. The terms described below are defined in consideration of the functions in the present application and may vary according to the user, the user's intention or custom. Therefore, the definition of the terms should be determined based on the content throughout this specification.

[0023] The present application may have various modifications and various embodiments, and in the present application, the embodiments are described in detail below with reference to the accompanying drawings. However, it should be understood that the present application is not limited to the embodiments, but includes all modifications, equivalents and substitutes within the scope of the present application.

[0024] The terms used herein are only used to describe various embodiments of the present application and are not intended to limit the present application. Unless the context clearly indicates otherwise, the singular form is intended to include the plural form. In the present application, it should be understood that the term "including" or "having" indicates the presence of features, quantities, steps, operations, structural elements, parts or a combination thereof, and does not exclude the presence of one or more other features, quantities, steps, operations, structural elements, parts or a combination thereof, or the possibility of adding one or more other features, quantities, steps, operations, structural elements, parts or a combination thereof.

[0025] Unless defined differently, all terms used herein have the same meaning as understood by those skilled in the art to which this application belongs. Unless explicitly defined in this application, terms (such as those defined in general dictionaries) should be interpreted as having the same meaning as in the context of the relevant art and should not be interpreted as having an idealized or overly formal meaning.

[0026] The electronic device according to one embodiment may be one of various types of electronic devices. The electronic device may include, for example, a portable communication device (e.g., a smart phone), a computer, a portable multimedia device, a portable medical device, a camera, a wearable device, or a household appliance. According to one embodiment of the disclosure, the electronic device is not limited to those described above.

[0027] The term used in this application is not intended to limit the application, but is intended to include the various changes, equivalents or substitutes of corresponding embodiments. About the description of the accompanying drawings, similar reference numerals can be used to represent similar elements or related elements. Unless the relevant context clearly indicates otherwise, the singular form of the noun corresponding to the item can include one or more things. As used herein, each of the phrases such as "A or B", "at least one of A and B", "at least one of A or B", "A, B or C", "at least one of A, B and C" and "at least one of A, B or C" can include all possible combinations of the item enumerated together in the corresponding one in the phrase. As used herein, terms such as "the 1st", "the 2nd", "first" and "second" can be used to distinguish corresponding components from another component, and are not intended to limit components in other aspects (for example, importance or order). It is intended that if an element (e.g., a first element) is referred to as being “coupled with,” “coupled to,” “connected to,” or “connected to” another element (e.g., a second element), with or without the term “operably” or “communicatively,” it indicates that the element can be coupled with the other element directly (e.g., by wire), wirelessly, or via a third element.

[0028] As used herein, the term "module" may include a unit implemented in hardware, software, or firmware, and may be used interchangeably with other terms such as "logic," "logic block," "component," and "circuit." A module may be a single integrated component or its smallest unit or component adapted to perform one or more functions. For example, according to one embodiment, a module may be implemented in the form of an application-specific integrated circuit (ASIC).

[0029] To facilitate understanding, the following first introduces the relevant terms and concepts involved in the embodiments of this application.

[0030] UVM is the most popular verification methodology in current chip verification and is a method for functional verification using System Verilog. The framework involved in the UVM verification platform generally includes the testbench, which is composed of various testcases. The environment (abbreviated as env) is the top-level module of the verification platform. env is instantiated in the testcase. When running a testcase, the env component is dynamically built during the build phase. env includes components such as the agent and scoreboard, and completes the communication channel connection between the agent and scoreboard.

[0031] The agent (abbreviated as AGT) is the agent module, which includes the sequencer, driver, and monitor components. After building these components, the communication channel between the sequencer and driver is connected, and the monitor's communication port is connected to the agent's communication port, allowing the agent to connect to components such as the scoreboard.

[0032] The driver (DRV) converts the stimulus generated by the sequencer into a drive signal, which is then driven by the interface to the DUT (DUT). The monitor (MON) collects DUT signals for monitoring and comparison, such as sending them to the scoreboard for comparison.

[0033] In the prior art, test cases are often divided into two parts: an interpretation file and the underlying system Verilog code. Developers need to instantiate multiple test cases using a pre-defined base class method. Any instance generated by a base class test case can only inherit the definition of that class method. Therefore, in the definition of the base class method in the interpretation file, developers try to cover all modules that need to be stimulated. To achieve this effect, in some cases, cross-reference relationships between test case sequences are also set.

[0034] However, this comes with the disadvantage that when incentives or new test cases need to be modified, the base class methods must be rewritten, resulting in repeated development of multiple levels of incentive constraints and the introduction of a large amount of duplicate code. Furthermore, the hierarchical constraints imposed by the inter-reference relationships between test cases not only make it difficult for developers to make modifications, but also require lengthy analysis to locate the problem when incentive errors are discovered.

[0035] Based on the above problems, the application proposes a method for generating incentives, which splits each sequence and each sequence constraint in the test case and saves them independently. The sequence in the test case adopts a building block-like superposition, abandoning the traditional multi-level UVM incentive constraint, thereby greatly improving maintainability and reliability. When it is necessary to modify the sequence or constraint, only the content that needs to be modified needs to be modified, without the need to rewrite it, which is convenient for developers to generate or modify test cases, reducing the workload of developers. In addition, sequences are combined to form test cases, and there is a combined constraint relationship between sequences, which avoids the multi-level constraint of sequences in the prior art, improves the efficiency of developing test cases, and thus improves the overall verification efficiency.

[0036] like Figure 1 As shown, Figure 1 FIG. 1 shows a flow chart of a method for generating an incentive provided by an embodiment of the present application. Figure 1 As shown, the method includes steps 110 to 120:

[0037] Step 110, read the test stimulus description file, and generate multiple constraint instances and multiple sequence instances based on the test stimulus description file. The test stimulus description file includes a sequence array and a constraint array. The sequence array is used to record the sequence information of each sequence in the test case, and the constraint array is used to record the constraint information of each sequence in the test case.

[0038] The sequence information describes the relevant information of the sequences sent to the sequencer under the test case, such as which sequencers are involved and how many records are involved. The constraint information constrains the sequences sent to the sequencer.

[0039] By splitting sequences and constraints and defining them directly, sequences and constraints can be flexibly added or deleted. UVM incentive constraints become a building block-like superimposable relationship, abandoning the traditional multi-level UVM incentive constraints. Developers only need to disassemble and develop the most important incentive constraints, which greatly improves maintainability and reliability.

[0040] When a sequence array or constraint array is in array form, the sequence information can be stored as multiple lines of data. Furthermore, each line of data can represent a sequence. In this case, a line of data, i.e., a sequence, is a stimulus description of a test case. If the stimulus description needs to be sent in sequence, each sequence will be numbered according to the order in which it is sent. For example, if a sequence needs to be sent first, the sequence will be numbered as sequence 0.

[0041] In one embodiment of the present application, the test stimulus description file is a command line parameter.

[0042] The test stimulus description file can be a command line parameter that has been compiled. In this application, the test stimulus description file describes the content at the sequence level, so it can be compiled in advance, which improves the efficiency of the simulation.

[0043] The above method uses command-line parameters to define test sequences, avoiding the massive amount of repetitive code introduced by repeated test stimulus development. This reduces the need for extensive recompilation and improves simulation efficiency. Furthermore, since hierarchical constraints are converted to command-line combination constraints, this also improves test case development efficiency, thereby increasing overall verification efficiency.

[0044] like Figure 2 As shown, Figure 2 A schematic block diagram of a stimulus generator in a UVM verification platform provided by an embodiment of the present application is shown.

[0045] like Figure 2 As shown, the stimulus generator includes a command line parameter processor. The command line parameter processor will read the test stimulus description file 0, which includes a sequence array and a constraint array. Figure 2 In , the sequence array is in the form of an array, and the sequence information can be stored as multiple rows of data, each row of data represents a sequence, then Figure 2 The sequence array includes sequence 0 to sequence n.

[0046] In one embodiment of the present application, the sequence array includes: sequencers participating in the stimulus, number of items, synchronization status, and end status. The sequence information recorded in the sequence array describes which sequencers participate in the test case, how many items participate, whether synchronization is required, waiting for the end together, etc. Figure 2Each sequence in the sequence array includes the sequencer number, read / write type, read / write amount, etc. These data are used to describe the sequence information. For example, when the sequencer number is 1, 2, 3, it means that the sequencers participating in the stimulus are sequencer 1, sequencer 2, and sequencer 3. For another example, when the sequencer number is all, it means that all sequencers participating in the stimulus are sequencer 1, sequencer 2, sequencer 3, and sequencer 4.

[0047] In one embodiment of the present application, the constraint array includes: a stimulus address and a stimulus action. Figure 2 In the constraint array, the constraint information can be stored as multiple rows of data, each row of data represents a constraint. Figure 2 The constraint array in [ ] includes constraints 0 to m. Constraint information is a constraint on the sequence. For example, if the sequencer wants to send 10 writes to the same address, two constraints can be added: same address and write. Figure 2 Each constraint includes a sequence number and a constraint class name. The sequence number is the sequence that the constraint targets, and the constraint class name indicates the constraint method used by the constraint.

[0048] exist Figure 2 In the illustrated embodiment, the index value of the constraint array in the test stimulus description file is the number of the sequence array.

[0049] like Figure 2 As shown, the sequence number in the sequence array included in a row of constraints in the constraint array can be used as the index value of the constraint, allowing for quick association between the sequence and the constraint. For example, when a sequence is read, all constraints for that sequence can be found by simply searching the constraint array based on its sequence number.

[0050] The array in the sequence array or constraint array of the present application only refers to a data storage form, and does not limit the sequence information or constraint information to be stored only in the form of an array. The storage method can be diverse.

[0051] Instantiate the sequence and constraints described in the test stimulus description file to generate multiple constraint instances and multiple sequence instances. For example, the content of sequence 0 described in the test stimulus description file is: 1, 3, 5, read, 100 records, etc., read the preset sequence class, which is a preset class function, and use the sequence class to serialize according to the content described in sequence 0 to obtain a sequence instance. For constraints, assuming that the content of constraint 0 described in the test stimulus description file is: 1, 2, 4, constraint class 1, constraint class 2, after reading constraint 0, find the class functions corresponding to constraint class 1 and constraint class 2 from the preset library, instantiate the read class functions, and generate multiple constraint instances.

[0052] In one embodiment of the present application, generating multiple sequence instances based on the test stimulus description file includes: obtaining each sequence in the sequence array; instantiating each sequence based on instance parameters in the sequence to generate the multiple sequence instances, wherein the instance parameters include sequencers participating in the stimulus and read / write types.

[0053] For each sequence in the sequence array, it is necessary to determine whether there are instance parameters. Instance parameters are predefined and can be parameters for generating different sequences, such as the sequencers involved in the stimulus, read / write types, etc. For example, the description of sequence 0 in the test stimulus description file is: 1, 3, 5, read, 100 records, etc., where the sequencers involved in the stimulus are 1, 3, and 5. Sequences should be generated for sequencers 1, 3, and 5. Therefore, using the sequence class to instantiate sequence 0 will generate three sequence instances: sequence instances 1, 2, and 3. Sequence instance 1 is the sequence instance pointing to sequencer 1.

[0054] It should be noted that when the instance parameters in each sequence in the stimulus test description file are set to use only single data, there is no need to serialize based on the instance parameters. For example, when the sequence is restricted to only write the name of one sequencer, serialization can be performed directly without reading the instantiation parameters to generate multiple instances.

[0055] like Figure 2 As shown, the command line parameter processor reads the stimulus test description file 0 to generate multiple sequence instances. Figure 2 Different sequence instances can be further combined to generate multiple sequence tables. For example, sequences belonging to the same sequencer can be associated to generate a sequence table. When a sequence table is read, the embodiment to which the sequencer relates can be immediately known.

[0056] The generating of multiple constraint instances based on the test stimulus description file includes: instantiating the constraint description of each constraint in the constraint array to generate the multiple constraint instances; and associating the constraint instance under the constraint to each sequence instance under the corresponding sequence.

[0057] For each constraint in the constraint array, instantiate it according to the constraint description of the constraint, thereby instantiating the constraint array into multiple constraint instances. Figure 2 As shown, after the command line parameter processor reads a constraint, it obtains the constraint class name from the constraint, searches for the class function corresponding to the constraint class name from the preset library, instantiates the read class function, and generates multiple instances of the constraint class.

[0058] After obtaining the constraint instances, it is also necessary to associate these constraint instances with sequence instances to implement the constraints on the sequences. According to the preset correspondence, the sequence corresponding to each constraint is searched, and for all constraint instances generated by the constraint, these constraint instances are associated with each sequence instance under its corresponding sequence. For example, it is assumed that the correspondence between the constraint instance and the sequence instance is that the index value of the constraint array is the number of the sequence array. For example, if the index value of constraint 0 is 0, constraint 0 includes constraint class 1 and constraint class 2, and constraint 0 will generate constraint instance 1 and constraint instance 2. According to the index value, it can be known that sequence 0 is constrained by the constraint. Therefore, each sequence instance in sequence instances 1, 2, and 3 generated by sequence 0 will be associated with constraint class 1 and constraint class 2. For example, pointers to constraint class 1 and constraint class 2 can be added to sequence instances 1, 2, and 3.

[0059] Step 120: Generate a transmission packet queue according to the plurality of sequence instances and the plurality of constraint instances.

[0060] Generates the corresponding underlying transport packet queue based on the generated constraint instance and the specific description in the sequence instance. Optionally, after the UVM_run_phase starts, it also checks the sequence instance and constraint instance generated by the command line parameter processor, such as detecting the association between the sequence instance and the constraint instance. Figure 2 In the embodiment, the transmission packet generator reads the constraint instance and sequence instance generated by the command line parameter processor, and generates a corresponding bottom transmission packet queue according to the generated constraint instance and sequence instance.

[0061] like Figure 2 As shown in the figure, after the transmission packet queue is generated, the transmission packet listener will send the transmission packets as a UVM sequence to the sequencer one by one when it detects that the transmission packet queue is not empty. It will be started on the sequencer and finally the transmission packet will be sent to the driver. This completes the entire process from stimulus description to final sending to the test module.

[0062] The above-mentioned incentive generation method splits each sequence in the test case and the constraints of each sequence out and saves them independently. The sequence in the test case adopts the superposition of building blocks, abandons the traditional multi-level UVM incentive constraint, thereby greatly improving maintainability and reliability. When it is necessary to modify the sequence or constraint, it is only necessary to obtain the content that needs to be modified and modify it without rewriting it. It is convenient for developers to generate or modify the test case, reducing the workload of developers. In addition, sequences are combined to form test cases, and there is a combined constraint relationship between sequences, which avoids the multi-level constraint of sequences in the prior art, improves the efficiency of developing test cases, and then improves overall verification efficiency.

[0063] Furthermore, each sequence and each sequence constraint in the test case can be separated out, and a function can be developed for each sequence and constraint. When a sequence or constraint is needed, only the existing function needs to be called, avoiding the huge amount of repetitive code introduced by repeated development of test stimuli.

[0064] like Figure 3 As shown, Figure 3 FIG. 3 shows a schematic block diagram of an excitation generator 300 provided in an embodiment of the present application. Figure 3 As shown, the method includes: a parameter processor 310 and a transmission packet generator 320.

[0065] The parameter processor 310 is used to read the test stimulus description file and generate multiple constraint instances and multiple sequence instances based on the test stimulus description file. The test stimulus description file includes a sequence array and a constraint array. The sequence array is used to record the sequence information of each sequence in the test case, and the constraint array is used to record the constraint information of each sequence in the test case.

[0066] The transmission packet generator 320 is configured to generate a transmission packet queue according to the plurality of sequence instances and the plurality of constraint instances.

[0067] In one embodiment of the present application, the index value of the constraint array in the test stimulus description file is the number of the sequence array.

[0068] In one embodiment of the present application, the sequence array includes: sequencers participating in the stimulus, number of entries, synchronization status, and end status.

[0069] In one embodiment of the present application, the constraint array includes: a stimulus address and a stimulus action.

[0070] In one embodiment of the present application, generating multiple sequence instances based on the test stimulus description file includes: obtaining each sequence in the sequence array; instantiating each sequence based on instance parameters in the sequence to generate the multiple sequence instances, wherein the instance parameters include sequencers participating in the stimulus and read / write types.

[0071] In one embodiment of the present application, generating multiple constraint instances based on the test stimulus description file includes: instantiating the constraint description of each constraint in the constraint array to generate the multiple constraint instances; and associating the constraint instance under the constraint to each sequence instance under the corresponding sequence.

[0072] In one embodiment of the present application, the test stimulus description file is a command line parameter.

[0073] The excitation generator 300 provided in the embodiment of the present application has the same implementation principle and technical effects as those in the aforementioned method embodiment. For the sake of brief description, for matters not mentioned in the device embodiment, reference may be made to the corresponding contents in the aforementioned method embodiment.

[0074] like Figure 4 As shown, Figure 4 FIG. 4 is a block diagram of an electronic device 400 according to an embodiment of the present application. The electronic device 400 includes a processor 410 and a memory 420 .

[0075] The processor 410, the memory 420 and each component are directly or indirectly electrically connected to each other to achieve data transmission or interaction. For example, these components can be electrically connected to each other through one or more communication buses or signal lines. The memory 220 is used to store computer programs, such as Figure 3 The software functional module shown in the figure is the stimulus generator 300. The stimulus generator 300 includes at least one software functional module that can be stored in the memory 420 in the form of software or firmware or fixed in the operating system (OS) of the electronic device 400. The processor 410 is used to execute the executable module stored in the memory 420, such as the software functional module or computer program included in the stimulus generator 300.

[0076] Among them, the memory 420 can be, but is not limited to, random access memory (RAM), read only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), etc.

[0077] The processor 410 may be an integrated circuit chip with signal processing capabilities. The above-mentioned processor may be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), a microprocessor, etc.; it may also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components. The various methods, steps and logic block diagrams disclosed in the embodiments of the present application can be implemented or executed. Alternatively, the processor 410 may also be any conventional processor, etc.

[0078] An embodiment of the present application further provides a non-volatile computer-readable storage medium (hereinafter referred to as storage medium), on which a computer program is stored. When the computer program is run by a computer such as the above-mentioned electronic device 400, the above-mentioned stimulus generation method is executed.

[0079] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same and similar parts between the various embodiments can be referenced to each other.

[0080] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device embodiments described above are merely illustrative. For example, the flowcharts and block diagrams in the accompanying drawings show the possible architectures, functions and operations of the devices, methods and computer program products according to the multiple embodiments of the present application. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of the code, and the module, program segment or a part of the code contains one or more executable instructions for implementing the specified logical functions. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in an order different from that marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, and the combination of boxes in the block diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or action, or can be implemented using a combination of dedicated hardware and computer instructions.

[0081] In addition, the functional modules in each embodiment of the present application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0082] If the functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a computer-readable storage medium, including a number of instructions for enabling a computer device (which can be a personal computer, a laptop, a server, or an electronic device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned computer-readable storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0083] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present application should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A method for generating an incentive, characterized in that: The method comprises: Read a test stimulus description file, and generate multiple constraint instances and multiple sequence instances based on the test stimulus description file, wherein the test stimulus description file includes a sequence array and a constraint array, the index value of the constraint array is the number of the sequence array associated with the constraint array, the sequence array includes: sequencers participating in the stimulus, the number of items, the synchronization status, and the end status, the sequence array is used to record sequence information of each sequence in the test case, the sequence information is multiple lines of data, and each line of data represents a sequence, the constraint array includes: a stimulus address and a stimulus action, the constraint array is used to record constraint information of each sequence in the test case, the constraint information is multiple lines of data, and each line of data represents a constraint; generating a transmission packet queue according to the plurality of sequence instances and the plurality of constraint instances; The step of generating multiple sequence instances according to the test stimulus description file includes: Get each sequence in the sequence array; Instantiating each sequence according to instance parameters in the sequence to generate the plurality of sequence instances, wherein the instance parameters include sequencers involved in the stimulation and read / write types; Generating a plurality of constraint instances according to the test stimulus description file includes: Instantiate according to the constraint description of each constraint in the constraint array to generate the plurality of constraint instances; Associate the constraint instance under the constraint to each sequence instance under the corresponding sequence.

2. The method according to claim 1, characterized in that The test stimulus description file is a command line parameter.

3. An excitation generator, characterized in that: The excitation generator comprises: A parameter processor is used to read a test stimulus description file and generate multiple constraint instances and multiple sequence instances based on the test stimulus description file. The test stimulus description file includes a sequence array and a constraint array. The index value of the constraint array is the number of the sequence array associated with the constraint array. The sequence array includes: sequencers participating in the stimulus, the number of items, the synchronization status, and the end status. The sequence array is used to record sequence information of each sequence in the test case. The sequence information is multiple lines of data, and each line of data represents a sequence. The constraint array includes: a stimulus address and a stimulus action. The constraint array is used to record constraint information of each sequence in the test case. The constraint information is multiple lines of data, and each line of data represents a constraint. a transmission packet generator, configured to generate a transmission packet queue according to the plurality of sequence instances and the plurality of constraint instances; The step of generating multiple sequence instances according to the test stimulus description file includes: Get each sequence in the sequence array; Instantiating each sequence according to instance parameters in the sequence to generate the plurality of sequence instances, wherein the instance parameters include sequencers involved in the stimulation and read / write types; Generating a plurality of constraint instances according to the test stimulus description file includes: Instantiate according to the constraint description of each constraint in the constraint array to generate the plurality of constraint instances; Associate the constraint instance under the constraint to each sequence instance under the corresponding sequence.

4. An electronic device, characterized in that: include: a memory and a processor, wherein the processor is connected to the memory; The memory is used to store programs; The processor is configured to call a program stored in the memory to execute the method according to claim 1 or 2.

5. A computer-readable storage medium, characterized in that A computer program is stored thereon, and when the computer program is executed by a processor, the method according to claim 1 or 2 is executed.

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