Isolated transceiver

Abstract

The application provides an isolated transceiver, and relates to the technical field of signal transmission. The isolated transceiver comprises a transmitter, a transformer and a receiver. The receiver is connected with a first coil of the transformer, and the transmitter is connected with a second coil of the transformer. The receiver comprises a first receiver and a second receiver. First and second input ends of the first receiver are connected with a first and a second port of the first coil respectively, first and second input ends of the second receiver are connected with the first and the second port of the first coil respectively, an output end of the first receiver is connected with a disable port of the second receiver, an output end of the second receiver is connected with a disable port of the first receiver, and the same port of the first coil is connected with opposite input ends of the first receiver and the second receiver. The application can adopt a single transformer for signal transmission, avoid the interference of accompanying pulses and ensure the reliability of signals.

Description

Technical Field

[0001] This invention relates to the field of signal transmission technology, and more specifically, to an isolated transceiver. Background Technology

[0002] An isolation transceiver is a device that uses a transformer to isolate the signal transmitter and the signal receiver for signal transmission.

[0003] Isolation transceivers need to transmit rising edge signals and falling edge signals. One transmission method is to use two transformers to transmit the rising edge and falling edge separately. Another method is to use a single transformer and use different numbers of pulses to transmit the rising edge and falling edge.

[0004] However, using dual transformers is costly, while using a single transformer requires waiting time to determine the number of pulses, resulting in long transmission delays. Furthermore, since the rising and falling edges use pulses of different polarities, due to the transformer's inherent characteristics, a large-amplitude, opposite-phase accompanying pulse will follow the signal pulse. When the amplitude of the accompanying pulse exceeds the receiver's threshold voltage, the receiver will identify the accompanying pulse as the signal pulse, which can easily lead to decoding errors. Summary of the Invention

[0005] The purpose of this invention is to address the shortcomings of the prior art by providing an isolation transformer that enables signal transmission using a single transformer, thereby avoiding interference from accompanying pulses and ensuring signal reliability.

[0006] To achieve the above objectives, the technical solutions adopted in the embodiments of this application are as follows:

[0007] In a first aspect, embodiments of this application provide an isolated transceiver, the isolated transceiver comprising: a transmitter, a transformer, and a receiver, wherein the receiver is connected to a first coil of the transformer, and the transmitter is connected to a second coil of the transformer;

[0008] The receiver includes: a first receiver and a second receiver;

[0009] The first input terminal and the second input terminal of the first receiver are respectively connected to the first port and the second port of the first coil to receive a first polarity pulse signal through the first coil, and output a first receive signal and a second disable signal according to the first polarity pulse signal.

[0010] The first input terminal and the second input terminal of the second receiver are respectively connected to the first port and the second port of the first coil to receive the second polarity pulse signal through the first coil, and output a second receive signal and a first disable signal according to the second polarity pulse signal;

[0011] The output of the first receiver is connected to the disable port of the second receiver so that the second receiver is prevented from outputting the second receive signal by the second disable signal while the first receiver is outputting the first receive signal;

[0012] The output of the second receiver is connected to the disable port of the first receiver, so that the first receiver is prevented from outputting the first receive signal by the first disable signal while the second receiver is outputting the second receive signal;

[0013] The same port of the first coil is connected to the opposite input terminals of the first receiver and the second receiver.

[0014] Optionally, the receiver further includes: a decoder;

[0015] The first input terminal of the decoder is connected to the output terminal of the first receiver, and the second input terminal of the decoder is connected to the output terminal of the second receiver. The decoder is used to output a decoded signal based on the first received signal or the second received signal.

[0016] Optionally, the transmitter includes: a first driver and a second driver;

[0017] The first driver and the second driver are respectively connected to the first port and the second port of the second coil to output the first drive signal and the second drive signal respectively.

[0018] Optionally, the transmitter further includes: an encoder;

[0019] The input terminal of the encoder is used to encode the input signal to obtain a first encoded signal and a second encoded signal in multiple states. The first output terminal of the encoder is connected to the first driver so that the first driver outputs a first driving signal in multiple states based on the first encoded signal in multiple states.

[0020] The second output terminal of the encoder is connected to the second driver, so that the second driver outputs the second drive signal in the plurality of states based on the second encoded signal in the plurality of states.

[0021] Optionally, the plurality of states include: a first state, a second state, and a third state;

[0022] In the first state, the first driving signal and the second driving signal are in-phase driving signals;

[0023] The first and second drive signals in the second state are inverted drive signals;

[0024] The first driving signal in the second state and the third state is an inverted driving signal, and the second driving signal in the second state and the third state is an inverted driving signal.

[0025] Optionally, the encoder is configured to output a first encoded signal and a second encoded signal of the second state when the input signal changes from a first logic level to a second logic level, causing the first driver and the second driver to enter the second state; or,

[0026] The encoder is used to output a first encoded signal and a second encoded signal of the third state when the input signal changes from a second logic level to a first logic level, so that the first driver and the second driver enter the third state.

[0027] Optionally, the encoder is configured to output a first encoded signal and a second encoded signal of the first state when the input signal is held at a first logic level or a second logic level, so that the first driver and the second driver are held at the first state.

[0028] Optionally, the encoder is configured to output a first encoded signal and a second encoded signal that switch between the first state and the second state when the input signal is held at the second logic level, so that the first driver and the second driver switch between the first state and the second state; when the input signal is held at the first logic level, the first driver and the second driver switch between the first state and the third state.

[0029] Optionally, the encoder is configured to output a first encoded signal and a second encoded signal of the first state when the input signal is held at a logic level, so that the first driver and the second driver are held in the first state;

[0030] The encoder is further configured to output a first encoded signal and a second encoded signal that switch between the first state and the second state when the input signal is held at another logic level, so that the first driver and the second driver switch between the first state and the second state; or, output a first encoded signal and a second encoded signal that switch between the first state and the third state, so that the first driver and the second driver switch between the first state and the third state.

[0031] Optionally, the encoder is used to output a first encoded signal and a second encoded signal of the working state when the input signal is held at a logic level, so that the first driver and the second driver remain in the working state;

[0032] The encoder is also configured to output a first encoded signal and a second encoded signal in a silent state when the input signal is held at another logic level, so that the first driver and the second driver remain in a silent state.

[0033] Optionally, both the first receiver and the second receiver are comparator circuits with a disable function, wherein the first input terminal and the second input terminal of the comparator circuit are the first input terminal and the second input terminal of each receiver, the disable port of the comparator circuit is the disable port of each receiver, and the output terminal of the comparator circuit is the output terminal of each receiver.

[0034] Optionally, the comparator circuit includes: a timing circuit, a first comparator, and a digital logic circuit;

[0035] The input terminal of the sequential circuit is the disabled port of the comparator circuit, and the output terminal of the sequential circuit is connected to the first input terminal of the digital logic circuit.

[0036] The first input terminal of the first comparator is the first input terminal of the comparator circuit, the second input terminal of the first comparator is the second input terminal of the comparator circuit, the output terminal of the first comparator is connected to the second input terminal of the digital logic circuit, and the output terminal of the digital logic circuit is the output terminal of the comparator circuit.

[0037] Optionally, the digital logic circuit includes: an inverter and a NOR gate;

[0038] The first input terminal of the NOR gate is the first input terminal of the digital logic circuit, the input terminal of the inverter is the second input terminal of the digital logic circuit, the output terminal of the inverter is connected to the second input terminal of the NOR gate, and the output terminal of the NOR gate is the output terminal of the digital logic circuit.

[0039] Optionally, the comparator circuit includes: a second comparator and a bias current;

[0040] The bias current is connected to the power supply terminal of the second comparator, the control terminal of the bias current is the disable port of the comparator circuit, the first input terminal of the second comparator is the first input terminal of the comparator circuit, the second input terminal of the second comparator is the second input terminal of the comparator circuit, and the output terminal of the second comparator is the output terminal of the comparator circuit.

[0041] The beneficial effects of this application are:

[0042] This application provides an isolated transceiver, in which the receivers are a first receiver and a second receiver that are cross-disabled. The first receiver receives a first polarity pulse signal, and the second receiver receives a second polarity pulse signal. While the first receiver outputs a first received signal based on the first polarity pulse signal, the second receiver is prohibited from outputting a second received signal based on the second polarity pulse signal. While the second receiver outputs a second received signal based on the second polarity pulse signal, the first receiver is prohibited from outputting a first received signal based on the first polarity pulse signal. This avoids interference from accompanying pulse signals and ensures the accuracy and reliability of signal transmission. Attached Figure Description

[0043] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0044] Figure 1 This is a schematic diagram of conventional single-transformer signal transmission;

[0045] Figure 2 The signal transmission waveform diagram of an existing isolated transceiver;

[0046] Figure 3 A schematic diagram of an isolated transceiver provided in an embodiment of this application. Figure 1 ;

[0047] Figure 4 A schematic diagram of an isolated transceiver provided in an embodiment of this application. Figure 2 ;

[0048] Figure 5 A schematic diagram of an isolated transceiver provided in an embodiment of this application. Figure 3 ;

[0049] Figure 6 A schematic diagram of an isolated transceiver provided in an embodiment of this application. Figure 4 ;

[0050] Figure 7 A signal transmission waveform diagram of an isolated transceiver provided in an embodiment of this application;

[0051] Figure 8 Another signal transmission waveform diagram of the isolated transceiver provided in the embodiments of this application;

[0052] Figure 9 Schematic diagram of the comparator circuit provided in the embodiments of this application Figure 1 ;

[0053] Figure 10 The principle of the comparator circuit provided in the embodiments of this application Figure 1 ;

[0054] Figure 11 The principle of the comparator circuit provided in the embodiments of this application Figure 2 ;

[0055] Figure 12 Schematic diagram of the comparator circuit provided in the embodiments of this application Figure 2 ;

[0056] Figure 13 A three-dimensional view of a transformer provided in an embodiment of this application;

[0057] Figure 14 This is a schematic diagram of the outer diameter of the coil provided in an embodiment of this application. Detailed Implementation

[0058] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some embodiments of the present invention, but not all embodiments.

[0059] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0060] Furthermore, the terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Additionally, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0061] It should be noted that, where there is no conflict, the features in the embodiments of this application can be combined with each other.

[0062] Please refer to Figure 1 This is a schematic diagram of conventional single-transformer signal transmission, such as... Figure 1As shown, due to the finite inductance of the transmitter coil in the transformer, its magnetizing current increases over time when a fixed voltage is applied. Based on the characteristic of inductance to conduct DC and block AC, if a fixed DC voltage is maintained, the transmitter coil will eventually exhibit a small resistance, leading to a short circuit and high power consumption. Therefore, after the transmitter coil is turned on, it needs to be turned off within a short period; that is, the driving waveform of the transmitter coil is a short pulse containing both a rising and falling edge. According to the transformer's characteristics, the rising edge will generate a positive pulse in the receiving coil, while the falling edge will generate a negative pulse. This negative pulse accompanying the positive pulse will significantly interfere with signal recognition.

[0063] For example, please refer to Figure 2 The above is a waveform diagram of the signal transmission of an existing isolated transceiver, such as... Figure 2 As shown, a positive pulse signal accompanied by a negative pulse signal, or a negative pulse signal accompanied by a positive pulse signal, may be misjudged as a single pulse signal, leading to incorrect identification of the output signal.

[0064] Based on this, this application proposes to provide an isolated transceiver, wherein the receivers of the isolated transceiver are a first receiver and a second receiver that are cross-disabled. The first receiver receives a first polarity pulse signal, and the second receiver receives a second polarity pulse signal. While the first receiver outputs a first received signal based on the first polarity pulse signal, the second receiver is prohibited from outputting a second received signal based on the second polarity pulse signal; while the second receiver outputs a second received signal based on the second polarity pulse signal, the first receiver is prohibited from outputting a first received signal based on the first polarity pulse signal, thereby avoiding interference from accompanying pulse signals and ensuring the accuracy and reliability of signal transmission.

[0065] Please refer to Figure 3 This is a schematic diagram of the isolated transceiver provided in the embodiments of this application. Figure 1 ,like Figure 3 As shown, the isolated transceiver includes: a transmitter 10, a transformer 20, and a receiver 30. The receiver 30 is connected to the first coil of the transformer 20, and the transmitter 10 is connected to the second coil of the transformer 20.

[0066] The receiver 30 includes a first receiver 31 and a second receiver 32.

[0067] The first input terminal and the second input terminal of the first receiver 31 are respectively connected to the first port 1 and the second port 2 of the first coil to receive the first polarity pulse signal through the first coil, and output the first receive signal OUT1 and the second disable signal according to the first polarity pulse signal.

[0068] The first input terminal and the second input terminal of the second receiver 32 are respectively connected to the first port 1 and the second port 2 of the first coil to receive the second polarity pulse signal through the first coil, and output the second receive signal OUT2 and the first disable signal according to the second polarity pulse signal.

[0069] The output of the first receiver 31 is connected to the disable port DIS of the second receiver 32 so that the second receiver 32 is prohibited from outputting a second receive signal by the second disable signal while the first receiver 31 is outputting a first receive signal.

[0070] The output of the second receiver 32 is connected to the disable port DIS of the first receiver 31 so that the first receiver 31 is prohibited from outputting the first receive signal by the first disable signal while the second receiver 32 is outputting the second receive signal.

[0071] The same port of the first coil is connected to the opposite input terminals of the first receiver 31 and the second receiver 32.

[0072] In this embodiment, the transmitter generates short pulses with rising and falling edges at either port 1 or port 2 of the second coil based on the high-low level transition of the input signal. The short pulse generated at port 1 of the second coil forms a positive pulse signal and an accompanying negative pulse signal on the first coil; similarly, the short pulse generated at port 2 of the second coil forms a negative pulse signal and an accompanying positive pulse signal on the first coil. The high-low level transition of the input signal corresponds to the short pulse generated at either port 1 or port 2 of the second coil.

[0073] A positive pulse signal is a pulse signal in which the difference between the voltage at the first port and the voltage at the second port of the first coil is positive; a negative pulse signal is a pulse signal in which the difference between the voltage at the first port and the voltage at the second port of the first coil is negative.

[0074] The first coil has two connection methods with the first receiver 31 and the second receiver 32. The first connection method is as follows: the first port 1 of the first coil is connected to the non-inverting input terminal V+ of the first receiver 31 and the inverting input terminal V- of the second receiver 32, and the second port 2 of the first coil is connected to the inverting input terminal V- of the first receiver 31 and the non-inverting input terminal V+ of the second receiver 32. Based on this connection method, the first polarity pulse signal received by the first receiver 31 through the first coil is a positive pulse signal, and the second polarity pulse signal received by the second receiver 32 through the first coil is a negative pulse signal.

[0075] The second connection method is as follows: the first port 1 of the first coil is connected to the inverting input terminal V- of the first receiver 31 and the non-inverting input terminal V+ of the second receiver 32, and the second port 2 of the first coil is connected to the non-inverting input terminal V+ of the first receiver 31 and the inverting input terminal V- of the second receiver 32. Based on this connection method, the first polarity pulse signal received by the first receiver 31 through the first coil is a negative pulse signal, and the second polarity pulse signal received by the second receiver 32 through the first coil is a positive pulse signal.

[0076] Taking the first receiver 31 as an example, the function of the disabled port of the first receiver 31 and the second receiver 32 will be explained.

[0077] When the disabled port is at the first control level, the output of the first receiver 31 remains at the first output level regardless of whether the differential voltage between the non-inverting input and the inverting input of the first receiver 31 is greater than the threshold voltage of the first receiver 31.

[0078] When the disabled port is at the second control level, if the differential voltage between the non-inverting input and the inverting input of the first receiver 31 is greater than the threshold voltage of the first receiver 31, the output of the first receiver 31 is at the second output level; if the differential voltage between the non-inverting input and the inverting input of the first receiver 31 is less than the threshold voltage of the first receiver 31, the output of the first receiver 31 is at the first output level.

[0079] For example, the first control level can be high, the second control level can be low, the first output level can be low, and the second output level can be high.

[0080] The function of disabling the port of the second receiver 32 is exactly the same as that of the first receiver 31, and will not be described again here.

[0081] When the first coil generates a first polarity pulse signal and an accompanying second polarity pulse signal, the first receiver 31 outputs a first receive signal OUT1 and a high-level second disable signal according to the first polarity pulse signal. The first receive signal OUT1 is a pulse signal with a pulse width of T1. The high-level second disable signal prevents the second receiver 32 from outputting a second receive signal according to the accompanying second polarity pulse signal, thus avoiding interference from the accompanying second polarity pulse signal.

[0082] The duration td2 of the high-level second disable signal is greater than the duration of the first polarity pulse signal and the accompanying second polarity pulse signal. After that, the second disable signal becomes low.

[0083] When the first coil generates a second polarity pulse signal and an accompanying first polarity pulse signal, the second receiver 32 outputs a second receive signal OUT2 and a high-level first disable signal according to the second polarity pulse signal. The second receive signal OUT2 is a pulse signal with a pulse width of T2. The high-level first disable signal prevents the first receiver 31 from outputting the first receive signal according to the accompanying first polarity pulse signal, thus avoiding interference from the accompanying first polarity pulse signal.

[0084] The duration td1 of the high-level first disable signal is greater than the duration of the second polarity pulse signal and the accompanying first polarity pulse signal. After that, the first disable signal becomes low-level.

[0085] The isolated transceiver provided in the above embodiments has two receivers: a first receiver and a second receiver that are cross-disabled. The first receiver receives a first polarity pulse signal, and the second receiver receives a second polarity pulse signal. While the first receiver outputs a first received signal based on the first polarity pulse signal, the second receiver is prohibited from outputting a second received signal based on the second polarity pulse signal. While the second receiver outputs a second received signal based on the second polarity pulse signal, the first receiver is prohibited from outputting a first received signal based on the first polarity pulse signal. This avoids interference from accompanying pulse signals and ensures the accuracy and reliability of signal transmission.

[0086] In one possible implementation, please refer to Figure 4 This is a schematic diagram of the isolated transceiver provided in the embodiments of this application. Figure 2 ,like Figure 4 As shown, the receiver may also include a decoder 40.

[0087] The first input terminal of the decoder 40 is connected to the output terminal of the first receiver 31, and the second input terminal of the decoder 40 is connected to the output terminal of the second receiver 32. The decoder 40 is used to output a decoded signal according to the first received signal or the second received signal.

[0088] In this embodiment, the decoder 40 outputs a corresponding decoding signal based on the received signal and the predefined correspondence between the received signal and the decoding signal. Specifically, if the decoder 40 receives a first received signal, it outputs a first decoding signal; if the decoder 40 receives a second received signal, it outputs a second decoding signal; and if the decoder 40 does not receive either the first or the second received signal, it keeps the current output signal unchanged.

[0089] In some embodiments, the high-low level conversion of the input signal corresponds to the polarity of the short pulse generated at the port of the second coil and the pulse signal generated on the first coil. The polarity of the pulse signal corresponds to the receiver. Therefore, the correspondence between the received signal and the decoded signal can be established based on these correspondences.

[0090] For example, if the isolated transceiver is configured such that when the input signal transitions from a low level to a high level, the first port 1 of the second coil generates a short pulse, and the short pulse at the first port 1 of the second coil generates a positive pulse signal on the first coil; and when the input signal transitions from a high level to a low level, the second port 2 of the second coil generates a short pulse, and the short pulse at the second port 2 of the second coil generates a negative pulse signal on the first coil.

[0091] The first port 1 of the first coil is connected to the non-inverting input of the first receiver 31 and the inverting input of the second receiver 32. The second port 2 of the first coil is connected to the inverting input of the first receiver 31 and the non-inverting input of the second receiver 32. At this time, the first receiver 31 will output a first receiving signal according to the positive polarity pulse signal, and the second receiver 32 will output a second receiving signal according to the negative polarity pulse signal. The correspondence between the receiving signal and the decoding signal is determined as follows: the first receiving signal corresponds to a high-level signal, and the second receiving signal corresponds to a low-level signal.

[0092] When the decoder 40 receives the first receive signal output by the first receiver 31 based on the positive polarity pulse signal, it generates a high-level decoding signal. When the decoder 40 receives the second receive signal output by the second receiver 32 based on the negative polarity pulse signal, it generates a low-level decoding signal.

[0093] In some embodiments, the decoder 40 may include an RS latch, wherein the S-terminal and R-terminal of the RS latch are respectively connected to the output terminal of the first receiver 31 and the output terminal of the second receiver 32, and are used to receive the first received signal and the second received signal, respectively. When the S-terminal receives the received signal, the RS latch outputs a high-level signal, and when the R-terminal receives the received signal, the RS latch outputs a low-level signal. Therefore, the connection relationship between the S-terminal and R-terminal of the RS latch and the first receiver 31 and the second receiver 32 can be determined according to the correspondence between the received signal and the high and low level signals.

[0094] If the first received signal corresponds to a high-level signal and the second received signal corresponds to a low-level signal, then the S terminal of the RS latch is connected to the output terminal of the first receiver 31 to receive the first received signal, and the R terminal of the RS latch is connected to the output terminal of the second receiver 32 to receive the second received signal.

[0095] The isolated transceiver provided in the above embodiments decodes the first or second received signal and outputs a decoded signal through a decoder. Due to the cross-disabling of the first and second receivers, the first and second received signals will not be interfered with by the accompanying pulse signal, thus ensuring the accuracy and reliability of the decoded signal.

[0096] In one possible implementation, please refer to Figure 5 This is a schematic diagram of the isolated transceiver provided in the embodiments of this application. Figure 3 ,like Figure 5 As shown, the transmitter 10 may include: a first driver 11 and a second driver 12.

[0097] The first driver 11 and the second driver 12 are respectively connected to the first port 1 and the second port 2 of the second coil to output the first driving signal and the second driving signal respectively.

[0098] In this embodiment, the first driver 11 and the second driver 12 output a first driving signal and a second driving signal respectively according to the input signal, forming a short pulse with a rising edge and a falling edge at the first port 1 of the second coil to generate a positive pulse signal and an accompanying negative pulse signal at both ends of the first coil; or, forming a short pulse with a rising edge and a falling edge at the second port 2 of the second coil to generate a negative pulse signal and an accompanying positive pulse signal at both ends of the first coil; or, not generating short pulses at the first port 1 and the second port 2 of the second coil, so that there is no pulse signal at both ends of the first coil.

[0099] In some embodiments, different first driving signals and second driving signals can be output based on the high-low level conversion of the input signal and the high-low level maintenance.

[0100] For example, if the input signal changes from low level to high level (or from high level to low level), the first driving signal and the second driving signal cause a short pulse to be formed on the first port 1 of the second coil; if the input signal changes from high level to low level (or from low level to high level), the first driving signal and the second driving signal cause a short pulse to be formed on the second port 2 of the second coil; if the input signal remains at low level or high level, the first driving signal and the second driving signal cause no pulse between the first port 1 and the second port 2 of the second coil.

[0101] In some embodiments, both the first driver 11 and the second driver 12 are composed of inverters with progressively increasing current capabilities.

[0102] The isolated transceiver provided in the above embodiments generates a first driving signal and a second driving signal through a first driver and a second driver, and forms pulse signals of different polarities according to a single transformer composed of a first coil and a second coil. This eliminates the need to use dual transformers to transmit rising and falling edges separately, thus reducing the cost of the isolated transceiver.

[0103] In one possible implementation, please refer to Figure 6 This is a schematic diagram of the isolated transceiver provided in the embodiments of this application. Figure 4 ,like Figure 6 As shown, the transmitter 10 may also include an encoder 50.

[0104] The input terminal of encoder 50 is used to encode the input signal to obtain a first encoded signal and a second encoded signal in multiple states. The first output terminal of encoder 50 is connected to the first driver 11 so that the first driver 11 outputs a first driving signal in multiple states based on the first encoded signal in multiple states. The second output terminal of encoder 50 is connected to the second driver 12 so that the second driver 12 outputs a second driving signal in multiple states based on the second encoded signal in multiple states.

[0105] In this embodiment, the encoder 50 encodes the input signal and outputs a first encoded signal and a second encoded signal in multiple states according to the level state of the input signal. These multiple states may include: a state where the input signal transitions from a high level to a low level, a state where it transitions from a low level to a high level, and a state where it remains at a low or high level. The first encoded signal and the second encoded signal output in these three states are different.

[0106] The first driver 11 and the second driver 12 output first driving signals and second driving signals in three states based on the first encoded signal and the second encoded signal in three states. The first driving signal and the second driving signal in three states cause a short pulse with a rising edge and a falling edge to be formed on the first port 1 or the second port 2 of the second coil, or cause no pulse between the first port 1 and the second port 2 of the second coil.

[0107] In some embodiments, the multiple states include: a first state, a second state, and a third state.

[0108] In the first state, the first driving signal and the second driving signal are in-phase driving signals; in the second state, the first driving signal and the second driving signal are out-of-phase driving signals; in the second and third states, the first driving signal is out-of-phase driving signal, and in the second and third states, the second driving signal is out-of-phase driving signal.

[0109] In this embodiment, both the first driving signal and the second driving signal in the first state are at a high level or a low level. When both the first driving signal and the second driving signal are at a high level or a low level, the voltage between the first port 1 and the second port 2 of the second coil is equal, and no pulse signal is transmitted to the first coil.

[0110] In the second state, the first and second driving signals are inverted driving signals, that is, if the first driving signal is high, the second driving signal is low, or if the first driving signal is low, the second driving signal is high.

[0111] In the third state, the first and second driving signals are also inverted driving signals. The first driving signal is inverted in both the second and third states, and the second driving signal is also inverted in both states. That is, if the first driving signal is high and the second driving signal is low in the second state, then the first driving signal is low and the second driving signal is high in the third state; or if the first driving signal is low and the second driving signal is high in the second state, then the first driving signal is high and the second driving signal is low in the third state.

[0112] The encoder 50 can drive the first driver 11 and the second driver 12 to switch between a first state, a second state and a third state according to the level state of the input signal, so as to change the voltage of the first port 1 and the second port 2 of the second coil, thereby generating pulse signals of different polarities at both ends of the first coil.

[0113] In one possible implementation, the encoder is used to output a first encoded signal and a second encoded signal of a second state when the input signal changes from a first logic level to a second logic level, causing the first driver and the second driver to enter the second state; or, the encoder is used to output a first encoded signal and a second encoded signal of a third state when the input signal changes from a second logic level to a first logic level, causing the first driver and the second driver to enter the third state.

[0114] In this embodiment, when the input signal switches from the first logic level to the second logic level, the encoder 50 drives the first driver 11 and the second driver 12 to enter the second state and outputs the inverted first drive signal and the second drive signal; when the input signal switches from the second logic level to the first logic level, the encoder 50 drives the first driver 11 and the second driver 12 to enter the third state and inputs the inverted first drive signal and the second drive signal.

[0115] In order to generate short pulses with rising and falling edges on the second coil, in addition to entering the second or third state when the logic level of the input signal changes, the first driver 11 and the second driver also need to switch between the second or third state and the first state.

[0116] In some embodiments, the encoder is used to output a first encoded signal and a second encoded signal of a first state when the input signal is held at a first logic level or a second logic level, so that the first driver and the second driver are held in the first state.

[0117] In this embodiment, when the input signal switches from the first logic level to the second logic level, the encoder 50 drives the first driver 11 and the second driver 12 from the first state to the second state. When the input signal remains at the second logic level, the encoder 50 drives the first driver 11 and the second driver 12 to exit the second state and return to the first state. Since the first drive signal and the second drive signal are inverted drive signals in the second state and in the first state, the signal at one port of the second coil undergoes two level flips during this process, that is, a short pulse with rising edge and falling edge is generated at one port of the second coil. During this process, a single polarity pulse signal is generated at both ends of the first coil.

[0118] When the input signal switches from the second logic level to the first logic level, the encoder 50 drives the first driver 11 and the second driver 12 from the first state to the third state. When the input signal remains at the first logic level, the encoder 50 drives the first driver 11 and the second driver 12 to exit the third state and return to the first state. Since the first and second drive signals are inverted drive signals in the third state and in the first state, the signal at one port of the second coil undergoes two level flips during this process, that is, a short pulse with rising and falling edges is generated at one port of the second coil. During this process, polarized pulse signals are generated at both ends of the first coil.

[0119] For example, in the first state where both the first and second driving signals are low, in the second state where the first driving signal is high and the second driving signal is low, and in the third state where the first driving signal is low and the second driving signal is high, the process of generating the polarity pulse signal will be explained.

[0120] When the input signal switches from the first logic level to the second logic level, the encoder 50 drives the first driver 11 and the second driver 12 to enter the second state from the first state, and the level of the first port 1 of the second coil changes from low to high. When the input signal remains at the second logic level, the encoder 50 drives the first driver 11 and the second driver 12 to exit the second state and return to the first state, and the level of the first port 1 of the second coil changes from high to low. During this process, the signal at the first port 1 of the second coil undergoes two level flips, that is, short pulses with rising and falling edges are generated at the first port 1 of the second coil. During this process, positive pulse signals and accompanying negative pulse signals are generated at both ends of the first coil.

[0121] When the input signal switches from the second logic level to the first logic level, the encoder 50 drives the first driver 11 and the second driver 12 to enter the third state from the first state, and the level of the second port 2 of the second coil changes from low to high. When the input signal remains at the first logic level, the encoder 50 drives the first driver 11 and the second driver 12 to exit the second state and return to the first state, and the level of the second port 2 of the second coil changes from high to low. During this process, the signal at the second port 2 of the second coil undergoes two level flips, that is, short pulses with rising and falling edges are generated at the second port 2 of the second coil. During this process, negative pulse signals and accompanying positive pulse signals are generated at both ends of the first coil.

[0122] In other embodiments, the encoder is used to output a first encoded signal and a second encoded signal that switch between a first state and a second state when the input signal is held at a second logic level, such that the first driver and the second driver switch between the first state and the second state; when the input signal is held at a first logic level, the first driver and the second driver switch between a first state and a third state.

[0123] In this embodiment, when the input signal switches from the first logic level to the second logic level, the encoder 50 drives the first driver 11 and the second driver 12 to enter the second state from the first state. When the input signal remains at the second logic level, the encoder 50 drives the first driver 11 and the second driver 12 to switch between the first state and the second state. Since the first driving signal and the second driving signal are in-phase driving signals in the first state and the first driving signal and the second driving signal are out-of-phase driving signals in the second state, the signal at one port of the second coil undergoes multiple level flips during the switching process between the first state and the second state. That is, multiple short pulses with rising and falling edges are generated at one port of the second coil. During this process, multiple polarity pulse signals are generated at both ends of the first coil.

[0124] When the input signal switches from the second logic level to the first logic level, the encoder 50 drives the first driver 11 and the second driver 12 to enter the third state from the first state. When the input signal remains at the first logic level, the encoder 50 drives the first driver 11 and the second driver 12 to switch between the first state and the third state. Since the first drive signal and the second drive signal are in-phase drive signals in the first state and the first drive signal and the second drive signal are out-of-phase drive signals in the third state, the signal at one port of the second coil undergoes multiple level flips during the switching process between the first state and the third state. That is, multiple short pulses with rising and falling edges are generated at one port of the second coil. During this process, multiple polarity pulse signals are generated at both ends of the first coil.

[0125] For example, in the first state where both the first and second driving signals are low, in the second state where the first driving signal is high and the second driving signal is low, and in the third state where the first driving signal is low and the second driving signal is high, the process of generating the polarity pulse signal will be explained.

[0126] When the input signal switches from the first logic level to the second logic level, the encoder 50 drives the first driver 11 and the second driver 12 to enter the second state from the first state, and the level of the first port 1 of the second coil changes from low to high. When the input signal remains at the second logic level, the encoder 50 drives the first driver 11 and the second driver 12 to switch between the first state and the second state, and the level of the first port 1 of the second coil undergoes multiple high-low level transitions, that is, multiple short pulses with rising and falling edges are generated on the first port 1 of the second coil. During this process, multiple positive pulse signals and accompanying negative pulse signals are generated at both ends of the first coil.

[0127] When the input signal switches from the second logic level to the first logic level, the encoder 50 drives the first driver 11 and the second driver 12 to enter the third state from the first state, and the level of the second port 2 of the second coil changes from low to high. When the input signal remains at the first logic level, the encoder 50 drives the first driver 11 and the second driver 12 to switch between the first state and the third state, and the level of the second port 2 of the second coil undergoes multiple high-low level transitions, that is, multiple short pulses with rising and falling edges are generated on the second port 2 of the second coil. During this process, multiple negative pulse signals and accompanying positive pulse signals are generated at both ends of the first coil.

[0128] In some other embodiments, the encoder is configured to output a first encoded signal and a second encoded signal of a first state when the input signal is held at one logic level, such that the first driver and the second driver remain in the first state; the encoder is also configured to output a first encoded signal and a second encoded signal that switch between the first state and the second state when the input signal is held at another logic level, such that the first driver and the second driver switch between the first state and the second state; or, output a first encoded signal and a second encoded signal that switch between the first state and the third state, such that the first driver and the second driver switch between the first state and the third state.

[0129] In this embodiment, when the input signal is held at the first logic level, the encoder 50 drives the first driver 11 and the second driver 12 to remain in the first state. When the input signal switches from the first logic level to the second logic level, the encoder 50 drives the first driver 11 and the second driver 12 to enter the second state from the first state. When the input signal is held at the second logic level, the encoder 50 drives the first driver 11 and the second driver 12 to switch between the first state and the second state. During this process, the signal at one port of the second coil undergoes multiple level flips, that is, multiple short pulses with rising and falling edges are generated at one port of the second coil. During this process, multiple polarity pulse signals are generated at both ends of the first coil.

[0130] When the input signal is maintained at the second logic level, the encoder 50 drives the first driver 11 and the second driver 12 to remain in the first state. When the input signal switches from the second logic level to the first logic level, the encoder 50 drives the first driver 11 and the second driver 12 to enter the third state from the first state. When the input signal is maintained at the first logic level, the encoder 50 drives the first driver 11 and the second driver 12 to switch between the first state and the third state. During this process, the signal at one port of the second coil undergoes multiple level flips, that is, multiple short pulses with rising and falling edges are generated at one port of the second coil. During this process, multiple polarity pulse signals are generated at both ends of the first coil.

[0131] It should be noted that the first logic level corresponds to maintaining the first state, while the second logic level corresponds to switching between the first and second states. Alternatively, the second logic level corresponds to maintaining the first state, while the first logic level corresponds to switching between the first and third states. Only one of these two methods can be selected.

[0132] In some embodiments, when the drive signal switches between the first state and the second state, the first receiver outputs a first receiving signal after detecting a first polarity pulse signal on the first coil, and the disabled port of the second receiver prohibits the output of the second receiving signal within a disabled time Tp1, the disabled time Tp1 being greater than the duration of the second state; furthermore, the disabled time Tp1 is greater than the sum of the duration of the second state and the duration of the accompanying pulse signal, ensuring that the output generated by the accompanying pulse signal is prohibited.

[0133] When the drive signal switches between the first state and the third state, the second receiver outputs the second receiving signal after detecting the second polarity pulse signal on the first coil. The disable port of the first receiver prohibits the output of the first receiving signal within the disable time Tp2, which is greater than the duration of the third state. Furthermore, the disable time Tp2 is greater than the sum of the duration of the third state and the duration of the accompanying pulse signal, ensuring that the output generated by the accompanying pulse signal is prohibited.

[0134] For example, please refer to Figure 7 The image shows a signal transmission waveform of an isolated transceiver provided in an embodiment of this application. Figure 7 As shown, when the input signal switches from the first logic level to the second logic level, the first output terminal of the encoder performs rising edge encoding (edge), and the second output terminal has no encoding signal, causing the first driver and the second driver to enter the second state. While the input signal maintains the second logic level, the encoder periodically performs rising edge encoding (refresh) at the first output terminal, causing the first driver and the second driver to switch between the first state and the second state, so that the first port 1 of the second coil generates multiple short pulses, thereby generating multiple positive pulse signals and accompanying negative pulse signals at both ends of the first coil. The first receiver generates a first receive signal and a second disable signal based on the positive pulse signal, and the decoder outputs the second logic level based on the first receive signal.

[0135] When the input signal switches from the second logic level to the first logic level, there is no encoded signal at the first output of the encoder, and the second output performs rising edge encoding, causing the first driver and the second driver to enter the third state. While the input signal maintains the first logic level, the encoder periodically performs rising edge encoding at the second output, causing the first driver and the second driver to switch between the first state and the third state, so that the second port 2 of the second coil generates multiple short pulses, thereby generating multiple negative pulse signals and accompanying positive pulse signals at both ends of the first coil. The second receiver generates a second receive signal and a first disable signal based on the negative pulse signal, and the decoder outputs the first logic level based on the second receive signal.

[0136] The isolated transceiver provided in the above embodiments encodes the input signal through an encoder to drive the first driver and the second driver to work in multiple states. It generates pulse signals of different polarities based on a single transformer composed of the first coil and the second coil, eliminating the need to use dual transformers to transmit rising and falling edges separately, thus reducing the cost of the isolated transceiver.

[0137] In another possible implementation, the encoder is used to output a first encoded signal and a second encoded signal of the working state when the input signal is held at one logic level, so that the first driver and the second driver are held in the working state; the encoder is also used to output a first encoded signal and a second encoded signal of the silent state when the input signal is held at another logic level, so that the first driver and the second driver are held in the silent state.

[0138] In this embodiment, an isolated transceiver with a silent function is provided. That is, except for logic level switching, the isolated transceiver is in working state when the input signal is maintained at one logic level, and in silent state when the input signal is maintained at another logic level.

[0139] Specifically, taking the first logic level corresponding to the silent state and the second logic level corresponding to the working state as an example, when the input signal changes from the first logic level to the second logic level, the first driver and the second driver enter the second state. When the input signal remains at the second logic level, the second driver can choose to remain in the first state or switch between the first state and the second state. When the input signal changes from the second logic level to the first logic level, the first driver and the second driver enter the third state. When the input signal remains at the first logic level, the first driver and the second driver do not output a drive signal.

[0140] For example, please refer to Figure 8 This is another signal transmission waveform diagram of the isolated transceiver provided in the embodiments of this application, such as... Figure 8 As shown, in the silent state, the first driver and the second driver do not output drive signals, and no pulse signals are generated at the two ends of the first coil.

[0141] The isolation transceiver provided in the above embodiments is in working state only when the input signal is held at one logic level, and in silent state when the input signal is held at another logic level, which can effectively save the power consumption of the isolation transceiver.

[0142] The specific implementation of the receiver will be described below with reference to the embodiments.

[0143] In one possible implementation, both the first receiver and the second receiver are comparator circuits with a disable function.

[0144] Please refer to Figure 9 A schematic diagram of the comparator circuit provided in the embodiments of this application. Figure 1 ,like Figure 9 As shown, the first and second input terminals of the comparator circuit are the first and second input terminals of each receiver, the disable port DIS of the comparator circuit is the disable port of each receiver, and the output terminal OUT of the comparator circuit is the output terminal of each receiver.

[0145] The first and second input terminals of the comparator circuit are the non-inverting input V+ and the inverting input V-, respectively.

[0146] In some embodiments, please refer to Figure 10 The principle of the comparator circuit provided in the embodiments of this application. Figure 1 ,like Figure 10 As shown, the comparator circuit includes: a sequential circuit 61, a first comparator 62, and a digital logic circuit 63.

[0147] The input terminal of the sequential circuit 61 is the disabled port DIS of the comparator circuit, and the output terminal of the sequential circuit 61 is connected to the first input terminal of the digital logic circuit 63; the first input terminal of the first comparator 62 is the first input terminal of the comparator circuit, the second input terminal of the first comparator 62 is the second input terminal of the comparator circuit, the output terminal of the first comparator 62 is connected to the second input terminal of the digital logic circuit 63, and the output terminal of the digital logic circuit 63 is the output terminal of the comparator circuit.

[0148] In this embodiment, the input terminal of the timing circuit 61 is used to receive the disable signal provided by the output terminal of another receiver, and the timing circuit 61 provides a certain duration for the disable signal. The positive input terminal V+ of the first comparator 62 is the non-inverting input terminal of the receiver, and the negative input terminal V- of the first comparator 62 is the inverting input terminal of the receiver.

[0149] The disable signal and the output of the first comparator 62 are simultaneously input to the digital logic circuit 63. The digital logic circuit is used to keep the output unchanged when the disable signal is at the first control level, and to perform in-phase or out-of-phase conversion on the output according to the output of the first comparator 62 when the disable signal is at the second control level.

[0150] For some implementation methods, please refer to Figure 11 The principle of the comparator circuit provided in the embodiments of this application. Figure 2 ,like Figure 11 As shown, the digital logic circuit 63 includes an inverter and a NOR gate.

[0151] The first input terminal of the NOR gate is the first input terminal of the digital logic circuit 63, the input terminal of the inverter is the second input terminal of the digital logic circuit 63, and the output terminal of the inverter is connected to the second input terminal of the NOR gate. The output terminal of the NOR gate is the output terminal of the digital logic circuit 63.

[0152] In this embodiment, the output of the first comparator 62 is inverted by an inverter and then subjected to a OR-NOT logic operation with a disable signal to output a first receive signal. If the disable signal is high, the first receive signal remains low; if the disable signal is low, the first receive signal is in phase with the output of the first comparator 62.

[0153] In another possible implementation, please refer to Figure 12 A schematic diagram of the comparator circuit provided in the embodiments of this application. Figure 2 ,like Figure 12 As shown, the comparator circuit includes: a second comparator 64 and a bias current I. B .

[0154] Bias current I B Connect the power supply terminal of the second comparator 64, and set the bias current I. B The control terminal is the disable port of the comparator circuit. The first input terminal of the second comparator 64 is the first input terminal of the comparator circuit. The second input terminal of the second comparator 64 is the second input terminal of the comparator circuit. The output terminal of the second comparator 64 is the output terminal of the comparator circuit.

[0155] In this embodiment, when the disable signal is at the first control level, the bias current I of the second comparator 64 is... B When disabled, the output of the second comparator 64 has no pull-up capability; therefore, the output of the second comparator 64 can only maintain the first output level. When the disable signal is at the second control level, the bias current I of the second comparator 64 is reduced. B When turned on, the second comparator 64 operates normally, and its output follows its input.

[0156] The following describes the specific implementation of the transformer used between the transmitter and receiver.

[0157] In this embodiment, the transformer is a chip-level integrated micro-transformer. For an example, please refer to [reference needed]. Figure 13 This is a three-dimensional view of the transformer provided in the embodiments of this application, such as... Figure 13 As shown, the miniature transformer consists of two sets of parallel coils. One set of coils is connected to the transmitter, and the other set is connected to the receiver. Both sets of coils are helical coils. For example, the longitudinal spacing between the two sets of coils is 5µm-300µm, preferably between 5µm-30µm.

[0158] In some embodiments, the inductance of the coil connected to the receiver is Lr, and the inductance of the coil connected to the transmitter is Lt.

[0159] To ensure the quality and amplitude of the transmitted signal, the ratio range of Lr to Lt is: 0.5 < Lr / Lt < 3.0. Preferably, the inductance of the coil connected to the receiver is not less than the inductance Lt of the coil connected to the transmitter, that is, Lr ≥ Lt.

[0160] In some embodiments, the outer diameter ratio of the two sets of coils is between 1:3 and 3:1, that is, the outer diameter of the larger coil does not exceed 3 times the outer diameter of the smaller coil. The outer diameter is the diameter of the circumcircle of the main body part of the coil (excluding auxiliary structures such as connection pads). The maximum outer diameter of the two sets of coils does not exceed 2 mm.

[0161] For example, please refer to Figure 14 , which is a schematic diagram of the outer diameter of the coil provided by the embodiment of the present application. As Figure 14 shown, the ratio of the outer diameter D1 of the top-layer coil to the outer diameter D2 of the bottom-layer coil satisfies 3 ≥ D1 / D2 ≥ 1 / 3, and D1 < 2 mm, D2 < 2 mm.

[0162] In some embodiments, both sets of coils are fabricated using the back-end process of integrated circuits and are located on the surface of the integrated circuit.

[0163] The above are only the specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, and all of them should be covered by the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims

1. An isolated transceiver, characterized in that, The isolated transceiver includes a transmitter, a transformer, and a receiver, wherein the receiver is connected to the first coil of the transformer, and the transmitter is connected to the second coil of the transformer. The receiver includes: a first receiver and a second receiver; The first input terminal and the second input terminal of the first receiver are respectively connected to the first port and the second port of the first coil to receive a first polarity pulse signal through the first coil, and output a first receive signal and a second disable signal according to the first polarity pulse signal. The first input terminal and the second input terminal of the second receiver are respectively connected to the first port and the second port of the first coil to receive the second polarity pulse signal through the first coil, and output a second receive signal and a first disable signal according to the second polarity pulse signal; The output of the first receiver is connected to the disable port of the second receiver so that the second receiver is prevented from outputting the second receive signal by the second disable signal while the first receiver is outputting the first receive signal; The output of the second receiver is connected to the disable port of the first receiver, so that the first receiver is prevented from outputting the first receive signal by the first disable signal while the second receiver is outputting the second receive signal; The same port of the first coil is connected to the opposite input terminals of the first receiver and the second receiver; Both the first receiver and the second receiver are comparator circuits with a disable function. The first input terminal and the second input terminal of the comparator circuit are the first input terminal and the second input terminal of each receiver. The disable port of the comparator circuit is the disable port of each receiver, and the output terminal of the comparator circuit is the output terminal of each receiver.

2. The isolated transceiver as described in claim 1, characterized in that, The receiver further includes: a decoder; The first input terminal of the decoder is connected to the output terminal of the first receiver, and the second input terminal of the decoder is connected to the output terminal of the second receiver. The decoder is used to output a decoded signal based on the first received signal or the second received signal.

3. The isolated transceiver as described in claim 1, characterized in that, The transmitter includes: a first driver and a second driver; The first driver and the second driver are respectively connected to the first port and the second port of the second coil to output the first drive signal and the second drive signal respectively.

4. The isolated transceiver as described in claim 3, characterized in that, The transmitter also includes: an encoder; The input terminal of the encoder is used to encode the input signal to obtain a first encoded signal and a second encoded signal in multiple states. The first output terminal of the encoder is connected to the first driver so that the first driver outputs a first driving signal in multiple states based on the first encoded signal in multiple states. The second output terminal of the encoder is connected to the second driver, so that the second driver outputs the second drive signal in the plurality of states based on the second encoded signal in the plurality of states.

5. The isolated transceiver as described in claim 4, characterized in that, The plurality of states includes: a first state, a second state, and a third state; In the first state, the first driving signal and the second driving signal are in-phase driving signals; The first and second drive signals in the second state are inverted drive signals; The first driving signal in the second state and the third state is an inverted driving signal, and the second driving signal in the second state and the third state is an inverted driving signal.

6. The isolated transceiver as described in claim 5, characterized in that, The encoder is used to output a first encoded signal and a second encoded signal of the second state when the input signal changes from a first logic level to a second logic level, causing the first driver and the second driver to enter the second state; or... The encoder is used to output a first encoded signal and a second encoded signal of the third state when the input signal changes from a second logic level to a first logic level, so that the first driver and the second driver enter the third state.

7. The isolated transceiver as described in claim 6, characterized in that, The encoder is used to output a first encoded signal and a second encoded signal of the first state when the input signal is held at a first logic level or a second logic level, so that the first driver and the second driver are held at the first state.

8. The isolated transceiver as described in claim 6, characterized in that, The encoder is used to output a first encoded signal and a second encoded signal that switch between the first state and the second state when the input signal is held at the second logic level, so that the first driver and the second driver switch between the first state and the second state; when the input signal is held at the first logic level, the first driver and the second driver switch between the first state and the third state.

9. The isolated transceiver as described in claim 6, characterized in that, The encoder is used to output a first encoded signal and a second encoded signal of the first state when the input signal is held at a logic level, so that the first driver and the second driver are held in the first state; The encoder is also configured to output a first encoded signal and a second encoded signal that switch between the first state and the second state when the input signal is held at another logic level, so that the first driver and the second driver switch between the first state and the second state; Alternatively, a first encoded signal and a second encoded signal are output to switch between the first state and the third state, causing the first driver and the second driver to switch between the first state and the third state.

10. The isolated transceiver as claimed in claim 4, characterized in that, The encoder is used to output a first encoded signal and a second encoded signal of the working state when the input signal is held at a logic level, so that the first driver and the second driver are held in the working state. The encoder is also configured to output a first encoded signal and a second encoded signal in a silent state when the input signal is held at another logic level, so that the first driver and the second driver remain in a silent state.

11. The isolated transceiver as claimed in claim 1, characterized in that, The comparator circuit includes: a sequential circuit, a first comparator, and a digital logic circuit; The input terminal of the sequential circuit is the disabled port of the comparator circuit, and the output terminal of the sequential circuit is connected to the first input terminal of the digital logic circuit. The first input terminal of the first comparator is the first input terminal of the comparator circuit, the second input terminal of the first comparator is the second input terminal of the comparator circuit, the output terminal of the first comparator is connected to the second input terminal of the digital logic circuit, and the output terminal of the digital logic circuit is the output terminal of the comparator circuit.

12. The isolated transceiver as claimed in claim 11, characterized in that, The digital logic circuit includes: an inverter and a NOR gate; The first input terminal of the NOR gate is the first input terminal of the digital logic circuit, the input terminal of the inverter is the second input terminal of the digital logic circuit, the output terminal of the inverter is connected to the second input terminal of the NOR gate, and the output terminal of the NOR gate is the output terminal of the digital logic circuit.

13. The isolated transceiver as claimed in claim 1, characterized in that, The comparator circuit includes: a second comparator and a bias current; The bias current is connected to the power supply terminal of the second comparator, the control terminal of the bias current is the disable port of the comparator circuit, the first input terminal of the second comparator is the first input terminal of the comparator circuit, the second input terminal of the second comparator is the second input terminal of the comparator circuit, and the output terminal of the second comparator is the output terminal of the comparator circuit.

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