Multi-ion regulated synaptic transistor and preparation method and application thereof

Abstract

The application belongs to the technical field of transistors, and particularly relates to a multi-ion regulated synapse transistor and a preparation method and application thereof. A plurality of metal salts are doped in a solid electrolyte, and metal ions in the metal salts are migrated to the interface between a dielectric layer and a channel layer under the action of a positive gate voltage, so that electrons in the channel layer are induced; after the voltage is removed, the ions do not immediately return to the initial position, but have a certain relaxation, so that the conductance of the channel layer can be changed in a short-term or long-term; wherein, metal ions with small mass such as sodium ions and lithium ions have a short relaxation time, and are beneficial to the simulation of short-term memory; and metal ions with large mass such as calcium ions, potassium ions and zinc ions have a long relaxation time, and are beneficial to the simulation of long-term memory. The synapse transistor can more perfectly simulate the synapse characteristics, and realize learning and memory behaviors such as double-pulse facilitation, short-term memory and long-term memory.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of transistors, and particularly relates to a multi-ion regulated synaptic transistor and a preparation method and application thereof. BACKGROUND

[0002] In recent years, with the advent of the information age, people have increasingly high requirements for the ability of computers to process information. However, the traditional von Neumann computer has problems such as high energy consumption and slow processing speed, and is difficult to meet the needs of modern applications. Compared with the traditional computer, the human brain is a system that can efficiently process information, and has characteristics such as high parallelism and high fault tolerance. Neurons and synapses are the basic units of information transmission and processing in the human brain, and synapses, as the connection points of neurons, can store and process information, achieving efficient parallel and low-power computing. Therefore, manufacturing electronic devices that can realize the function of synapses is a key factor in building a brain-like computing system.

[0003] At present, researchers have proposed a series of synaptic electronic devices, among which synaptic transistors have attracted widespread attention due to their three-terminal regulation and capacitive coupling working mode. When a voltage is applied to the gate of the synaptic transistor, ions in the dielectric layer can move to the dielectric layer / channel layer interface, inducing carriers in the channel layer to form a double electric layer, thereby simulating synaptic characteristics. Among them, the dielectric layer capable of forming a double electric layer includes ionic liquid, ionic gel and solid-state electrolyte, and the solid-state electrolyte has been widely studied because it is compatible with flexible substrates, can be printed and prepared, and is compatible with monolithic integrated circuits. However, the solid-state electrolyte has the disadvantage of low ion mobility, which affects the realization of synaptic simulation.

[0004] Researchers have found that by doping salt into the solid-state electrolyte, the ion mobility can be effectively improved, and there have been many reports that by doping lithium salt or sodium salt into PEO, synaptic characteristics have been successfully simulated. Although these synaptic transistors based on proton migration or ion migration successfully simulate synaptic characteristics such as excitatory postsynaptic current, double-pulse facilitation and short-term memory, in these synaptic transistors, when the gate voltage is removed, the protons or ions will quickly return to the equilibrium position, and the relaxation time is short, so that long-term memory cannot be well simulated. SUMMARY

[0005] The application aims to provide a multi-ion regulated synaptic transistor and a preparation method and application thereof, and the synaptic transistor provided by the application can more perfectly simulate synaptic performance and realize simulation of short-term memory and long-term memory.

[0006] In order to achieve the above-mentioned purpose, the application provides the following technical scheme:

[0007] The application provides a multi-ion regulated synaptic transistor, including a synaptic transistor with a bottom gate structure or a synaptic transistor with a top gate structure, wherein the synaptic transistor with the top gate structure sequentially comprises, from bottom to top, a substrate, a channel layer, a source-drain electrode, a dielectric layer and a gate electrode; and the synaptic transistor with the bottom gate structure sequentially comprises, from bottom to top, a substrate, a gate electrode, a dielectric layer, a channel layer and a source-drain electrode.

[0008] The material of the dielectric layer is a solid-state electrolyte / metal salt chemical compound.

[0009] The metal salt includes a heavy metal salt and a light metal salt; the heavy metal salt includes one or more of magnesium salt, calcium salt, aluminum salt, zinc salt and potassium salt; and the light metal salt includes one or more of lithium salt and sodium salt.

[0010] Preferably, the substrate is prepared from raw materials including one or more of silicon wafer, PET, PI, PEN, glass, diamond and aluminum oxide.

[0011] The channel layer is prepared from raw materials including one or more of ITO, IZO, IGZO, In2O3, VO2, NiO, Ga2O3 and SnO2.

[0012] The source-drain electrode is prepared from raw materials including one or more of ITO, Cu, Au, Ag, Al, Fe, Pt, Pd and W.

[0013] The gate electrode is prepared from raw materials including one or more of Au, Ag, Cu, Al and Fe.

[0014] Preferably, the thickness of the substrate is 0.1-3 mm.

[0015] The thickness of the channel layer is 10-150 nm.

[0016] The thickness of the source-drain electrode is 10-200 nm.

[0017] The thickness of the dielectric layer is 10-200 nm.

[0018] The thickness of the gate electrode is 10-200 nm.

[0019] Preferably, the mass ratio of the solid-state electrolyte to the metal salt is 1-3:0.1-0.3.

[0020] Preferably, the solid-state electrolyte is a chemically synthesized polymer or a bio-organic material.

[0021] Preferably, the chemical synthetic polymer comprises one or more of polyethylene oxide, polyvinylpyrrolidone, polyethylene oxide, polyvinyl alcohol and polypropylene; and the bio-organic material comprises one or more of chitosan, sodium alginate, starch, cellulose and protein.

[0022] The application also provides a preparation method of the multi-ion regulated synaptic transistor as described in the above scheme.

[0023] When the synaptic transistor is in a top-gate structure, the preparation method comprises the following steps: preparing a channel layer on a substrate, preparing a source-drain electrode on the channel layer, preparing a dielectric layer on the source-drain electrode, and preparing a gate electrode on the dielectric layer to obtain a synaptic transistor in a top-gate structure.

[0024] When the synaptic transistor is in a bottom-gate structure, the preparation method comprises the following steps: preparing a gate electrode on a substrate, preparing a dielectric layer on the gate electrode, preparing a channel layer on the dielectric layer, and preparing a source-drain electrode on the channel layer to obtain a synaptic transistor in a bottom-gate structure.

[0025] Preferably, when the synaptic transistor is in a top-gate structure, the preparation method of the channel layer comprises one of spin coating, drop casting, magnetron sputtering and electrospinning; the preparation method of the source-drain electrode comprises one of sputtering, PECVD, MOCVD, ALD and evaporation; the preparation method of the dielectric layer comprises one of coating, inkjet printing, spin coating and aerosol jet printing; and the preparation method of the gate electrode comprises one of coating, sputtering, PECVD, MOCVD, ALD, MBE, PLD and evaporation.

[0026] When the synaptic transistor is in a bottom-gate structure, the preparation methods of the gate electrode, the dielectric layer, the channel layer and the source-drain electrode are the same as those of the synaptic transistor in a top-gate structure.

[0027] Preferably, when the synaptic transistor is in a top-gate structure or a bottom-gate structure, the channel layer, the source-drain electrode, the dielectric layer and the gate electrode are independently further subjected to a patterning process by photolithography.

[0028] The application also provides an application of the synaptic transistor as described in the above scheme or the synaptic transistor obtained by the preparation method as described in the above scheme in a computer, an implantable non-medical device and a wearable device.

[0029] The application provides a multi-ion regulated synaptic transistor. The synaptic transistor of the application regulates synaptic plasticity by using multiple ions, improves the ion mobility of the dielectric layer, and at the same time simulates the behavior of biological synapses from the principle of biological synaptic behavior, so that the synaptic behavior can be better simulated at the behavior level, learning and memory behaviors such as double-pulse facilitation, short-term memory and long-term memory are realized, and synaptic plasticity is more perfectly simulated. The specific mechanism is as follows:

[0030] The present application incorporates multiple metal salts into the solid electrolyte (for example, double-ion regulation, principle as shown in Figure 1 The present application incorporates multiple metal salts into the solid electrolyte (for example, double-ion regulation, principle as shown in

[0031] The present application also provides a preparation method of the synaptic transistor with multiple-ion regulation as described in the above scheme. The preparation method provided by the present application has simple steps, convenient operation, high feasibility, low cost, and can be mass-produced industrially.

[0032] The present application also provides the application of the synaptic transistor as described in the above scheme or the synaptic transistor obtained by the preparation method as described in the above scheme in computers, implantable non-medical devices and wearable devices. The synaptic transistor provided by the present application is compatible with the current process, does not need to use special process in application, reduces the application difficulty and cost of the synaptic transistor of the present application; the chemical synthetic polymer and the biological organic material used in the present application have the properties of biocompatibility, biodegradability and flexibility, so that the synaptic transistor can be applied in implantable non-medical devices and wearable devices, greatly expanding the application scenarios of the neural synaptic device. BRIEF DESCRIPTION OF DRAWINGS

[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed in the embodiments will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor on the basis of these drawings.

[0034] Figure 1 The principle diagram of short-term and long-term plasticity of the synaptic transistor with multiple-ion regulation (for example, double-ion) provided by the present application is shown in the figure.

[0035] Figure 2 The flow chart for preparing the synaptic transistor with multiple-ion regulation in embodiment 1 of the present application is shown in the figure.

[0036] Figure 3 The schematic diagram of electrospinning in embodiment 1 of the present application is shown in the figure.

[0037] Figure 4A structural schematic diagram of a multi-ion regulated synaptic transistor of the present application embodiment 1;

[0038] Figure 5 A short-term memory test diagram of the multi-ion regulated synaptic transistor of the present application embodiment 1;

[0039] Figure 6 A long-term memory test diagram of the multi-ion regulated synaptic transistor of the present application embodiment 1;

[0040] Figure 7 A structural schematic diagram of a multi-ion regulated synaptic transistor of the present application embodiment 2. DETAILED DESCRIPTION

[0041] The present application provides a multi-ion regulated synaptic transistor, including a synaptic transistor of bottom gate structure or a synaptic transistor of top gate structure, the synaptic transistor of top gate structure sequentially includes substrate, channel layer, source-drain electrode, dielectric layer and gate electrode from bottom to top; the synaptic transistor of bottom gate structure sequentially includes substrate, gate electrode, dielectric layer, channel layer and source-drain electrode from bottom to top.

[0042] The material of the dielectric layer is solid-state electrolyte / metal salt chemical compound.

[0043] The metal salt includes heavy mass metal salt and small mass metal salt; the heavy mass metal salt includes one or more of magnesium salt, calcium salt, aluminum salt, zinc salt and potassium salt; the small mass metal salt includes one or more of lithium salt and sodium salt.

[0044] The multi-ion regulated synaptic transistor provided by the present application includes substrate; the substrate is preferably prepared from raw materials including one or more of silicon wafer, PET, PI, PEN, glass, diamond and aluminum oxide; the glass is preferably ITO film coated glass; the thickness of the substrate is preferably 0.1-3mm, more preferably 0.3-2.5mm, and further preferably 0.5-1mm.

[0045] The multi-ion regulated synaptic transistor provided by the present application includes channel layer; the channel layer is preferably prepared from raw materials including one or more of ITO, IZO, IGZO, In2O3, VO2, NiO, Ga2O3 and SnO2; the thickness of the channel layer is preferably 10-150nm, more preferably 50-150nm, and further preferably 80-120nm; the length of the channel of the channel layer is preferably 1000μm, and the width is preferably 150μm.

[0046] The multi-ion regulated synaptic transistor provided by the present application comprises a source-drain electrode (source electrode and drain electrode); the source-drain electrode is preferably prepared from raw materials comprising one or more of ITO, Cu, Au, Ag, Al, Fe, Pt, Pd and W, and more preferably Al, Ag or ITO (the same material is used for the source electrode and the drain electrode); when the source-drain electrode is prepared from raw materials comprising two or more of Cu, Au, Ag, Al, Fe, Pt, Pd and W, the source-drain electrode is a composite metal (alloy); the thickness of the source-drain electrode is preferably 10-200 nm, more preferably 100-200 nm, and further preferably 120-170 nm; and the size of the source-drain electrode is preferably 0.3-0.6 mm 2 , more preferably 0.40-0.55 mm 2 , and further preferably 0.45-0.50 mm 2 .

[0047] The multi-ion regulated synaptic transistor provided by the present application comprises a dielectric layer; the material of the dielectric layer is a solid-state electrolyte / metal salt chemical composite (a composite obtained by chemical reaction of a solid-state electrolyte and a metal salt); and the thickness of the dielectric layer is preferably 10-200 nm, more preferably 100-200 nm, and further preferably 120-160 nm.

[0048] In the present application, the mass ratio of the solid-state electrolyte to the metal salt is preferably 1-3:0.1-0.3, more preferably 1.5-2.5:0.1-0.3, and further preferably 1.8-2.2:0.2. By controlling the ratio of the solid-state electrolyte to the metal salt within the above range, the ion mobility of the synaptic transistor can be effectively improved, and the synaptic function can be more effectively simulated.

[0049] In the present application, the solid-state electrolyte is preferably a chemically synthesized polymer or a biological organic material; the chemically synthesized polymer preferably comprises one or more of polyethylene oxide, polyvinylpyrrolidone, polyethylene oxide, polyvinyl alcohol and polypropylene; and the biological organic material preferably comprises one or more of chitosan, sodium alginate, starch, cellulose and protein.

[0050] In the present application, the anion of the metal salt preferably comprises one or more of fluoride ion, chloride ion, bromide ion, acetate ion, nitrate ion, sulfate ion and perchlorate; the magnesium salt is preferably MgCl2; the calcium salt is preferably CaCl2; the aluminum salt is preferably AlCl3; the zinc salt is preferably ZnSO4; the potassium salt preferably comprises one or both of KCl and potassium perchlorate; the lithium salt preferably comprises one or more of Li2SO4 and LiClO4; and the sodium salt preferably comprises one or more of NaCl, Na2SO4 and NaClO4.

[0051] The multi-ion regulated synaptic transistor provided by the application comprises a gate electrode; the gate electrode is preferably prepared from raw materials comprising one or more of Au, Ag, Cu, Al and Fe; when the gate electrode is prepared from raw materials comprising two or more of Au, Ag, Cu, Al and Fe, the gate electrode is a composite metal; the thickness of the gate electrode is preferably 10-200 nm, more preferably 50-200 nm, further preferably 80-150 nm, and more further preferably 100-120 nm.

[0052] The application further provides a preparation method of the multi-ion regulated synaptic transistor described in the above scheme.

[0053] When the synaptic transistor is of a top-gate structure, the preparation method comprises the following steps: preparing a channel layer on a substrate, preparing a source-drain electrode on the channel layer, preparing a dielectric layer on the source-drain electrode, and preparing a gate electrode on the dielectric layer to obtain a synaptic transistor of a top-gate structure.

[0054] When the synaptic transistor is of a bottom-gate structure, the preparation method comprises the following steps: preparing a gate electrode on a substrate, preparing a dielectric layer on the gate electrode, preparing a channel layer on the dielectric layer, and preparing a source-drain electrode on the channel layer to obtain a synaptic transistor of a bottom-gate structure.

[0055] In the application, the channel layer, the source-drain electrode, the dielectric layer and the gate electrode are independently preferably further subjected to a patterning treatment by photolithography.

[0056] In the application, the substrate is preferably subjected to pretreatment before use; the pretreatment is preferably ultrasonic treatment of the substrate in acetone, then in ethanol and then in deionized water, followed by drying and UV treatment; the ultrasonic treatment in acetone is preferably for 15 min; the ultrasonic treatment in ethanol is preferably for 10 min; the ultrasonic treatment in deionized water is preferably for 25 min; the deionized water is preferably replaced every 8 min during the ultrasonic treatment in deionized water; the drying is preferably oven drying; the atmosphere for the UV treatment is preferably O3; and the UV treatment is preferably for 15 min. The pretreatment removes impurities and organic matter on the surface of the substrate and enhances the contact of the substrate surface.

[0057] In the application, when the synaptic transistor is of a top-gate structure, the size of the substrate is preferably (0.8-1.5) cm x (1.0-2.0) cm, more preferably (1.0-1.4) cm x (1.2-1.8) cm, and further preferably 1.2 cm x 1.5 cm.

[0058] In the present application, when the synaptic transistor is a top-gate structure, the preparation method of the channel layer preferably comprises one of spin coating, drop casting, magnetron sputtering and electrospinning; the voltage of the electrospinning is preferably 10-15 V, more preferably 12-14 V, further preferably 12.5 V, the flow rate of the liquid flow is preferably 0.3-1.2 mL / s, more preferably 0.6-1.0 mL / s, further preferably 0.8 mL / s; the environmental humidity of the electrospinning is preferably 20-40%, more preferably 25-35%, further preferably 30%, the environmental temperature is preferably 15-30℃, more preferably 20-25℃; the distance from the needle to the collection device in the electrospinning is preferably 12-18 cm, more preferably 14-16 cm, further preferably 15 cm. Among them, electrospinning as an economical and efficient method can effectively regulate the diameter and surface morphology of nanofibers, and the nanowires prepared have a large surface area to volume ratio, which can improve the performance of the synaptic transistor.

[0059] In the present application, the electrospinning preferably further comprises viscosity adjustment of the electrospinning precursor solution before electrospinning; the viscosity adjusting agent is preferably a thickening agent; and the thickening agent is preferably polyvinylpyrrolidone. In the present application, the viscosity of the precursor solution is increased by the thickening agent before electrospinning to achieve the required viscosity for electrospinning; and in the subsequent annealing process, the thickening agent is eliminated.

[0060] In the present application, the electrospinning preferably further comprises annealing and UV treatment of the nanofiber after electrospinning; the annealing temperature is preferably 400-600℃, more preferably 450-550℃, further preferably 480-520℃, the holding time is preferably 1.5-2.5 h, more preferably 1.8-2.2 h, further preferably 2 h; the UV treatment time is preferably 30-60 min, more preferably 40-50 min, further preferably 45 min.

[0061] In the present application, when the synaptic transistor is a top-gate structure, the preparation method of the source-drain electrode preferably comprises one of sputtering, PECVD, MOCVD, ALD and evaporation; the vacuum degree of the sputtering is preferably less than 3×10 -3 Pa, more preferably less than 2×10 -3 Pa, the electrode thickness is preferably 5-30 nm, more preferably 10-25 nm, further preferably 15-20 nm.

[0062] In the present application, when the synaptic transistor is a top-gate structure, the preparation method of the dielectric layer preferably comprises one of coating, inkjet printing, spin coating and aerosol jet printing; the preparation of the dielectric layer preferably comprises the following steps: mixing a solid-state electrolyte and a metal salt to obtain a mixed solution, then coating, inkjet printing, spin coating or aerosol jet printing the mixed solution, and then standing (denoted as first standing); the mixing is preferably stirring; the stirring rate is preferably 300-800 rpm, more preferably 400-700 rpm, and further preferably 500-600 rpm; the stirring time is preferably 5-10 h, more preferably 6-9 h, and further preferably 7-8 h; and the standing time is preferably 8-15 h, and more preferably 10-12 h.

[0063] In the present application, when the synaptic transistor is a bottom-gate structure, the preparation method of the gate electrode preferably comprises one of coating, sputtering, PECVD, MOCVD, ALD and evaporation.

[0064] In the present application, the gate electrode is coated, sputtered, PECVD, MOCVD, ALD, MBE, PLD or evaporated and then allowed to stand (denoted as second standing); the second standing time is preferably 3-10 h, and more preferably 6-8 h.

[0065] In the present application, when the synaptic transistor is a bottom-gate structure, the size of the substrate is preferably (0.8-1.5) cm x (1.0-2.0) cm, more preferably (1.0-1.4) cm x (1.2-1.8) cm, and further preferably 1.2 cm x 1.5 cm.

[0066] In the present application, when the synaptic transistor is a bottom-gate structure, the preparation method of the gate electrode preferably comprises one of coating, sputtering, PECVD, MOCVD, ALD and evaporation.

[0067] In the present application, when the synaptic transistor is a bottom gate structure, the preparation method of the dielectric layer preferably comprises one of coating, inkjet printing, spin coating and aerosol jet printing; the preparation of the dielectric layer preferably comprises the following steps: mixing a solid-state electrolyte and a metal salt to obtain a mixed solution, and then coating, inkjet printing, spin coating or aerosol jet printing the mixed solution and drying; the mixing is preferably stirring; the stirring rate is preferably 300-800 rpm, more preferably 400-700 rpm, and further preferably 500-600 rpm; the stirring time is preferably 5-10 h, more preferably 6-9 h, and further preferably 7-8 h; the spin coating speed is preferably 2000-6000 rpm, more preferably 4000 rpm; and the spin coating time is preferably 10-50 s, more preferably 30 s; and the drying is preferably air drying; and the drying time is preferably 2-6 h, more preferably 4 h.

[0068] In the present application, when the synaptic transistor is a bottom gate structure, the preparation method of the channel layer preferably comprises one of spin coating, drop casting, magnetron sputtering and electrospinning; the rate of the magnetron sputtering is preferably 20.5 standard cubic centimeters per minute, the air pressure is preferably 0.2-0.8 Pa, more preferably 0.5 Pa, the power is preferably 10-60 W, more preferably 35 W, and the time is preferably 1-6 min, more preferably 4 min.

[0069] In the present application, when the synaptic transistor is a bottom gate structure, the preparation method of the source-drain electrode preferably comprises one of sputtering, PECVD, MOCVD, ALD and evaporation; the vacuum degree of the evaporation is preferably less than 3x10 -3 Pa, more preferably less than 2x10 -3 Pa.

[0070] The present application also provides the use of the synaptic transistor prepared by the preparation method described in the above scheme in computers, implantable non-medical devices and wearable devices.

[0071] The synaptic transistor provided by the present application is compatible with the current process, does not need to use special process in application, reduces the application difficulty and cost of the synaptic transistor of the present application; the chemical synthetic polymer and the biological organic material used in the present application have the properties of biocompatibility, biodegradability and flexibility and stretchability, so that the synaptic transistor can be applied in implantable non-medical devices and wearable instruments and devices, greatly expanding the application scenarios of the neural synaptic device.

[0072] In order to further illustrate the present application, the schemes of the present application are described in detail below in combination with the drawings and examples, but they should not be understood as limiting the scope of protection of the present application.

[0073] Example 1

[0074] The embodiment prepares a double-ion regulated synaptic transistor with a top gate structure, and the flow is as shown in the figure, including the following steps: Figure 2

[0075] (1) The channel layer is prepared by electrospinning (the electrospinning process is as shown in the figure): 0.13749 g of indium nitrate is dissolved in 3 mL of N,N-dimethylformamide, stirred at room temperature, 0.3 g of thickening agent polyvinylpyrrolidone is added after uniform stirring, and continues to be stirred at room temperature for 6 h until completely dissolved to obtain a mixed solution; Figure 3

[0076] (2) The mixed solution in step (1) is sucked into the needle tube of electrospinning by a needle, the distance between the needle and the silicon substrate is controlled to be 15 cm, the liquid flow rate is set to 0.5 mL / s, the voltage is set to 12.5 V, the environmental humidity is controlled to be 35%, and the temperature is controlled to be 20°C, the equipment is operated, and the nanofiber is obtained on the silicon substrate;

[0077] (3) The nanofiber in step (2) and the silicon substrate are annealed together at 500°C for 2 h, and then taken out, UV treated for 50 min, to obtain indium oxide nanowire as the channel layer;

[0078] (4) The source and drain electrodes are prepared by magnetron sputtering: ITO electrodes are sputtered onto the channel layer as source and drain electrodes, the vacuum degree of sputtering is less than 3×10 -3 Pa, the thickness of the sputtered electrode is 15 nm, and the silicon substrate-channel layer-source and drain electrodes are obtained;

[0079] (5) 0.04 g of polyethylene oxide PEO, 0.004 g of potassium perchlorate and 0.004 g of lithium perchlorate are dissolved in 3 mL of deionized water, stirred at room temperature for 8 h until completely dissolved to obtain a medium layer solution;

[0080] (6) The medium layer solution in step (5) is coated on the channel layer, source electrode and drain electrode prepared in step (4), the coating solution volume is 20 mL, and the coating solution is left to stand for 12 h to form a solid electrolyte after the solvent is volatilized, to obtain a silicon substrate-channel layer-source and drain electrodes-medium layer;

[0081] (7) The Ag glue is coated on the medium layer in step (6) and left to stand for 6 h to form a solid electrode as a gate electrode, to obtain a double-ion regulated synaptic transistor, and the structure of the synaptic transistor is as shown in the figure; Figure 4

[0082] (8) The synaptic transistor prepared above is subjected to double-pulse facilitation test, and the test result is as shown in the figure. According to Figure 5 Figure 5 ​​​​It can be seen that the double-pulse facilitation index of the synaptic transistor is 190%, indicating that the device has a good short-term memory effect.

[0083] (9) The prepared synaptic transistor is subjected to long-term memory test, and 20 continuous pulses are applied, and the test result is as shown in Figure 6 Figure 6 It can be seen that the device has a good long-term memory effect.

[0084] Example 2

[0085] This embodiment prepares a multi-ion regulated synaptic transistor with a bottom gate structure, comprising the following steps:

[0086] (1) The substrate is selected as a glass substrate (3×4 cm 2 ), and there is an ITO film with a conductivity of 105S / cm on the substrate; the ITO glass substrate is ultrasonically treated in a clean acetone beaker for 15 min, then the substrate is placed in a beaker containing alcohol and ultrasonically treated for 10 min with a clean forceps, and then the substrate is placed in a beaker containing deionized water and ultrasonically treated for 25 min, and the deionized water is replaced every 8 min, to remove impurities and organic matter on the surface of the substrate;

[0087] (2) The substrate is dried in a clean culture dish, and after drying, the substrate is treated with UV in O3 for 15 min to enhance the surface contact of the substrate;

[0088] (3) 0.04g of PEO, 0.004g of calcium perchlorate, 0.004g of potassium perchlorate and 0.004g of lithium perchlorate are dissolved in 3mL of deionized water, stirred at room temperature for 8h until completely dissolved, to obtain a medium layer solution;

[0089] (4) 400μL of the medium layer solution of step (3) is taken by a pipette and spin-coated on the substrate treated in step (2), the spin-coating speed is 4000rpm, the spin-coating time is 30s, and the obtained film is air-dried for 4h to obtain a medium layer;

[0090] (5) An IZO conductive channel layer is deposited on the medium layer of step (4) by magnetron sputtering, the mass ratio of In2O3 and ZnO in the IZO target is 67%:33%, and the length / width of the IZO channel is 150×1000μm; during the sputtering process, the mass ratio of Ar:O2 is controlled at 20:0.5 standard cubic centimeters per minute, the gas pressure and power are 0.5Pa and 35W respectively, and the time lasts for 4min.

[0091] (6) Metal aluminum is deposited on the IZO conductive channel layer by thermal evaporation, the vacuum degree during evaporation is less than 3×10 -3 Pa, and the size of the Al source-drain electrode is 0.55mm​2 , to obtain a multi-ion regulated synaptic transistor, and a structure of the synaptic transistor is as shown in Figure 7 .

[0092] From the above examples, the synaptic transistor provided by the application can more perfectly simulate the synaptic performance, and realize the simulation of short-term memory and long-term memory.

[0093] Although the above examples make a detailed description of the application, it is only a part of the embodiments of the application, not all the embodiments, and other embodiments can be obtained according to the embodiments without creativity, and these embodiments all belong to the protection scope of the application.

Claims

1. A multi-ion regulated synaptronic transistor, comprising: The synaptic transistor includes a bottom gate structure or a top gate structure, and the top gate structure includes, from bottom to top, a substrate, a channel layer, a source-drain electrode, a dielectric layer and a gate electrode; the bottom gate structure includes, from bottom to top, a substrate, a gate electrode, a dielectric layer, a channel layer and a source-drain electrode; The dielectric layer is made of a solid-state electrolyte / metal salt chemical compound; The metal salt includes a heavy metal salt and a light metal salt; the heavy metal salt includes one or more of magnesium salt, calcium salt, aluminum salt, zinc salt and potassium salt; and the light metal salt includes one or more of lithium salt and sodium salt.

2. The synapse transistor according to claim 1, wherein The substrate is made of raw materials including one or more of silicon wafer, PET, PI, PEN, glass, diamond and aluminum oxide; The channel layer is made of raw materials including one or more of ITO, IZO, IGZO, In2O3, VO2, NiO, Ga2O3 and SnO2; The source-drain electrode is made of raw materials including one or more of ITO, Cu, Au, Ag, Al, Fe, Pt, Pd and W; The gate electrode is made of raw materials including one or more of Au, Ag, Cu, Al and Fe.

3. The synapse transistor according to claim 1 or 2, wherein The thickness of the substrate is 0.1-3 mm; The thickness of the channel layer is 10-150 nm; The thickness of the source-drain electrode is 10-200 nm; The thickness of the dielectric layer is 10-200 nm; The thickness of the gate electrode is 10-200 nm.

4. The synapse transistor according to claim 1, wherein The mass ratio of the solid-state electrolyte to the metal salt is 1-3:0.1-0.

3.

5. The synapse transistor according to claim 1 or 4, wherein The solid-state electrolyte is a chemically synthesized polymer or a biological organic material.

6. The synapse transistor according to claim 5, wherein The chemically synthesized polymer includes one or more of polyethylene oxide, polyvinylpyrrolidone, polyethylene oxide, polyvinyl alcohol and polypropylene; and the biological organic material includes one or more of chitosan, sodium alginate, starch, cellulose and protein.

7. A method for preparing the multi-ion regulated synaptic transistor according to any one of claims 1-6, comprising the following steps: When the synaptic transistor is a top-gate structure, the preparation method comprises the following steps: Preparation of a channel layer on a substrate, a source-drain electrode on the channel layer, a dielectric layer on the channel layer and the source-drain electrode, and a gate electrode on the dielectric layer, to obtain a synaptic transistor with a top gate structure; When the synaptic transistor has a bottom gate structure, the preparation method comprises the following steps: preparation of a gate electrode on a substrate, a dielectric layer on the gate electrode, a channel layer on the dielectric layer, and a source-drain electrode on the channel layer, to obtain a synaptic transistor with a bottom gate structure.

8. The preparation method according to claim 7, characterized in that, When the synaptic transistor has a top gate structure, the channel layer is prepared by one of spin coating, drop casting, magnetron sputtering and electrospinning; the source-drain electrode is prepared by one of sputtering, PECVD, MOCVD, ALD and evaporation; the dielectric layer is prepared by one of coating, inkjet printing, spin coating and aerosol jet printing; and the gate electrode is prepared by one of coating, sputtering, PECVD, MOCVD, ALD, MBE, PLD and evaporation. When the synapse transistor is a bottom gate structure, the preparation method of the gate electrode, the dielectric layer, the channel layer and the source-drain electrode is the same as that of the synapse transistor with a top gate structure.

9. The production method according to claim 7 or 8, characterized by, When the synapse transistor is a top gate structure or a bottom gate structure, the channel layer, the source-drain electrode, the dielectric layer and the gate electrode independently further comprise a patterning process by photolithography.

10. The synapse transistor of any one of claims 1-6 or the synapse transistor obtained by the preparation method of any one of claims 7-9 for use in a computer, an implantable non-medical device and a wearable device.

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