A gas sensor chip integrated with a silicon lens and a preparation method thereof

Abstract

The embodiment of the present disclosure provides a gas sensor chip integrated with a silicon lens and a preparation method, which comprises: the chip comprises a silicon lens array structure and a chip body; the silicon lens array structure comprises a silicon substrate and a plurality of filters; the silicon substrate has opposite first and second surfaces, and the first surface is formed with a lens array; the second surface of the silicon substrate is provided with the filters; the positions of the lenses and the filters correspond to each other; the first surface of the silicon substrate is integrally connected with the upper surface of the chip body; wherein the lenses correspond to the positions of the central hot end of the chip body, and are used for converging the energy of an external infrared light source to the central hot end of the chip body; and the lens array comprises a concave lens array. In the present disclosure, the filters are integrated on the chip body, the lens array is formed on the silicon substrate of the filter carrier, the concave lens converges the energy of the external infrared light source to the central hot end of the chip, and the sensitivity of the chip is improved.

Description

Technical Field

[0001] The embodiments disclosed herein belong to the field of gas sensor technology, specifically relating to a gas sensor chip with an integrated silicon lens and its fabrication method. Background Technology

[0002] Non-dispersive infrared (NDIR) gas sensors utilize the principle of infrared absorption to detect gas composition by detecting the absorption of specific wavelengths of infrared radiation by specific gas molecules in ambient air. An NDIR gas sensor mainly consists of a light source, a sample chamber, a spectral filter, and a detector. Ambient air is passed through the sample chamber, where gas molecules irradiated by the infrared light source absorb infrared radiation of specific wavelengths. The amount of absorbed infrared radiation is proportional to the gas concentration. Subsequently, the sensor uses a spectral filter to select the wavelength of interest, ensuring it reaches only the detector. The detector measures the intensity of the absorbed infrared radiation, thus reflecting the gas concentration.

[0003] NDIR infrared gas sensors utilize the unique molecular structures of different gases, resulting in specific absorption spectra for infrared light. In other words, different gases have the ability to absorb infrared light within a specific wavelength band. This specific wavelength band is called the infrared absorption peak of the gas. Different gases have different infrared absorption peaks, and even in a mixed gas environment, the infrared absorption of different gases does not interfere with each other. This property does not change with external conditions. The amount of energy absorbed by a particular gas is related to its concentration in the infrared region; the higher the concentration, the more energy is absorbed. When infrared light passes through a gas, energy attenuation occurs at the corresponding frequency, and the degree of energy attenuation is related to the gas concentration. By analyzing the degree of infrared light attenuation, the concentration of the gas can be calculated. The absorption of infrared light by the gas obeys the Lambert-Beer law. NDIR gas sensors utilize this characteristic to perform qualitative and quantitative analysis of specific gas concentrations.

[0004] Compared to other sensors, NDIR gas sensors offer advantages such as high detection accuracy, fast response speed, good stability, and strong anti-interference capabilities, and can detect a variety of gas components. Therefore, NDIR gas sensors are widely used in air quality monitoring, industrial emission monitoring, and medical diagnostics.

[0005] In the industry, NDIR gas sensor detectors typically require chips that are used in conjunction with externally purchased filters for specific wavelengths to detect characteristic gases. However, this approach has the following drawbacks: 1. Low detection sensitivity; 2. The externally purchased filters require TO packaging with the gas chip, resulting in a large sensor size, which is inconvenient for customers to install and use, and the consistency of the components is uncontrollable; 3. Inability to detect different types of gas concentrations; 4. Poor anti-interference capability for gas concentration detection.

[0006] Therefore, how to solve the above problems has become a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0007] The embodiments disclosed herein aim to at least solve one of the technical problems existing in the prior art, and provide a gas sensor chip with an integrated silicon lens and a method for its fabrication.

[0008] A first aspect of the embodiments of this disclosure provides a gas sensor chip with an integrated silicon lens, comprising:

[0009] The chip includes a silicon lens array structure and a chip body; the silicon lens array structure includes a silicon substrate and a plurality of filters; the silicon substrate has a first surface and a second surface opposite to each other, the first surface having a lens array formed thereon; the second surface of the silicon substrate has the filters disposed thereon; the lenses and the filters are positioned correspondingly.

[0010] The first surface of the silicon substrate is integrated and connected to the upper surface of the chip body; wherein, the lens corresponds to the position of the central hot end of the chip body, and is used to concentrate the energy of the external infrared light source to the central hot end of the chip body; the lens array is formed by femtosecond laser processing; the lens array includes a concave lens array.

[0011] Optionally, the filter includes a methane filter, a reference comparison filter, and a carbon dioxide filter.

[0012] Optionally, the methane filter comprises an AgF film or a MgF2 film; the reference comparison filter comprises an Al(NO3)3 film; and the carbon dioxide filter comprises an AlGaS film.

[0013] Furthermore, it also includes:

[0014] A resonant cavity array structure is disposed on the lower surface of the chip body; the resonant cavity array structure forms an array of pits;

[0015] The substrate of the chip body has a back cavity, which corresponds to the central hot end of the chip body.

[0016] The surface of the recess is provided with a reflective layer; the recess is correspondingly arranged with the back cavity, and the recess and the back cavity together constitute a resonant cavity.

[0017] Optionally, the back cavity is convex; the back cavity and the recess together form a concave-convex resonant cavity.

[0018] Optionally, the pit array includes pits of different depths.

[0019] Optionally, the pit depth is 1 / 4λ to 3 / 4λ, where λ is the infrared wavelength.

[0020] Optionally, the chip body includes a semiconductor structure layer and a CMOS device structure and a MEMS device structure integrated within the semiconductor structure layer.

[0021] A second aspect of the embodiments of this disclosure provides a method for fabricating a gas sensor chip with an integrated silicon lens, for fabricating the chip described above, comprising:

[0022] Fabrication of silicon lens array structures;

[0023] Fabrication of the chip body;

[0024] The silicon lens array structure and the chip body are integrated; wherein the lenses of the silicon lens array structure correspond to the positions of the central hot ends of the chip body.

[0025] Optionally, the fabrication of the silicon lens array structure includes:

[0026] Provide a silicon substrate and perform cleaning and thinning processes;

[0027] The surface of the silicon substrate is etched using femtosecond laser processing technology to form a lens array on the silicon substrate;

[0028] A filter is integrated onto the surface of the silicon substrate opposite to the lens array to fabricate the silicon lens array structure; wherein the filter corresponds to the position of the lens.

[0029] The beneficial effects of the embodiments of this disclosure include:

[0030] In this disclosure, by integrating a filter on the chip body and forming a lens array on the silicon substrate of the filter carrier, the concave lens can concentrate the energy of the external infrared light source to the central hot end of the chip body, thereby improving the chip sensitivity. Attached Figure Description

[0031] Figures 1-8 This is a flowchart illustrating the fabrication process of a gas sensor chip with an integrated silicon lens according to an embodiment of the present disclosure.

[0032] Figures 9-15 This is a flowchart illustrating a chip body fabrication process according to an embodiment of the present disclosure;

[0033] Figure 16 This is a schematic diagram of a chip body array structure according to an embodiment of the present disclosure;

[0034] Figures 17-23 This is a flowchart illustrating the fabrication process of a multi-gas detection array chip according to an embodiment of the present disclosure;

[0035] Figure 24 This is a schematic diagram of a gas sensor chip structure with an integrated silicon lens according to an embodiment of the present disclosure;

[0036] Figure 25 This is a diagram illustrating the infrared light incident effect of an SOC-integrated silicon microconcave lens with an integrated filter, a bottom reflective layer, and an NDIR infrared gas sensor chip, according to an embodiment of this disclosure. Detailed Implementation

[0037] To enable those skilled in the art to better understand the technical solutions of this disclosure, the disclosure will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0038] The embodiments of this application will be further described in detail below with reference to the accompanying drawings and examples. The detailed descriptions and accompanying drawings of the following embodiments are used to exemplarily illustrate the principles of this application, but should not be used to limit the scope of this application; that is, this application is not limited to the described embodiments. In the description of this application, it should be noted that, unless otherwise stated, "a plurality of" means two or more; the terms "upper," "lower," "left," "right," "inner," "outer," etc., indicating orientation or positional relationships are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. "Vertical" is not strictly vertical, but within the allowable error range. "Parallel" is not strictly parallel, but within the allowable error range.

[0039] In the description of this application, it should also be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in this application depending on the specific circumstances.

[0040] like Figure 7-8As shown, a gas sensor chip with an integrated silicon lens includes:

[0041] The chip includes a silicon lens array structure 10 and a chip body 11. The silicon lens array structure 10 includes a silicon substrate 1 and a plurality of filters. The silicon substrate 1 has opposing first and second surfaces, and a lens array is formed on the first surface. Filters are disposed on the second surface of the silicon substrate 1, and the lenses and filters are positioned correspondingly.

[0042] The first surface of the silicon substrate 1 is integrated and connected to the upper surface of the chip body 11, wherein the lens corresponds to the position of the central hot end of the chip body 11. The lens array is formed by femtosecond laser processing. The lens array includes a concave lens array.

[0043] In this disclosure, by integrating a filter on the chip body 11 and forming a lens array on the silicon substrate 1 of the filter carrier, the concave lens can concentrate the energy of the external infrared light source to the center hot end of the chip body 11, thereby improving the chip sensitivity.

[0044] In some embodiments, the filter is a narrowband spectral thin film filter.

[0045] In some embodiments, the lens array includes a concave lens array.

[0046] In this disclosure, by integrating a filter on the chip body 11 and forming a concave lens array on the silicon lens array structure 10 of the filter carrier, the concave lens can effectively concentrate the energy of the external infrared light source to the central hot end of the chip body 11, thereby significantly improving the chip sensitivity.

[0047] In some embodiments, reference is made to Figure 7 The filters include a methane filter 6, a reference filter 7, and a carbon dioxide filter 8. The methane filter includes an AgF film or a MgF2 film, the reference filter includes an Al(NO3)3 film, and the carbon dioxide filter includes an AlGaS film.

[0048] In this disclosure, a reference filter is used for comparison to eliminate external environmental interference. Furthermore, by selecting different filter film materials to integrate the same chip, it is possible to detect the concentration of various gases and eliminate the need for TO packaging of external discrete devices. Using chip-level integrated packaging reduces size and facilitates customer installation and use. Simultaneously, because it is a one-piece wafer fabrication process, the process is controllable, thus ensuring the consistency of the integrated device.

[0049] refer to Figure 20-24In some embodiments, the gas sensor chip further includes a resonant cavity array structure 20. The resonant cavity array structure 20 is disposed on the lower surface of the chip body, and the resonant cavity array structure 20 forms an array of pits of different depths. A back cavity is formed on the substrate of the chip body, and the back cavity corresponds to the central hot end position of the chip body. A reflective layer is provided on the surface of the pits, and the pits and the back cavity are correspondingly arranged, and the pits and the back cavity together constitute a resonant cavity.

[0050] In this disclosure, different infrared bands and wavelengths are required for the detection of different gas concentrations, thus requiring different resonant cavity heights. This disclosure incorporates recesses of varying depths to form resonant cavities of different heights with the back cavity, enabling the detection of multiple gases. Furthermore, the reflective layer causes light to propagate back and forth within the resonant cavity, continuously enhancing the light energy transmitted through the narrowband filter and generating self-excited oscillations. This further increases the reception and focusing of the weak light intensity emitted by the light source at the chip's central area, thereby enhancing the chip's sensitivity to the detection of specific gases.

[0051] Furthermore, the filters correspond to the positions of the recesses, and different filters are used for recesses of different depths. This setup allows for the detection of various gases.

[0052] In some embodiments, the pit includes a first pit 117, a second pit 118, and a third pit 119.

[0053] In a specific example, the first recess 117 is set to correspond to the methane filter, the second recess 118 is set to correspond to the reference comparison filter, and the third recess 119 is set to correspond to the carbon dioxide filter.

[0054] In some embodiments, reference is made to Figure 16 and Figure 22 The back cavity 45 is convex, and the back cavity 45 and the pit together form the concave-convex resonant cavity 13.

[0055] In this disclosure, the concave-convex resonant cavity formed by the convex surface of the back cavity 45 and the concave surface of the substrate bottom of the chip body 11 can significantly enable light to propagate back and forth in the resonant cavity, thereby continuously enhancing the energy of the transmitted narrow-band light, forming self-excited oscillation, further increasing the reception and convergence of the weak light intensity emitted by the light source at the center of the chip, and thus enhancing the chip's sensitivity to the detection of specific gases.

[0056] In some embodiments, reference is made to Figure 20 The pit array includes pits of varying depths.

[0057] In some embodiments, the pit depth is 1 / 4λ to 3 / 4λ, where λ is the infrared wavelength.

[0058] In this disclosure, pits of different depths correspond to different infrared bands and wavelengths required for detecting various gas concentrations, and consequently, different heights of the resonant cavity. Furthermore, resonant cavities of different heights are selected to generate self-excited oscillations, increasing the reception and focusing of the weak light intensity emitted by the infrared light source at the center of the chip.

[0059] In some embodiments, reference is made to Figure 12-16 and Figure 22-24 The chip body 11 includes a semiconductor structure layer and a CMOS device structure and a MEMS device structure integrated within the semiconductor structure layer.

[0060] MEMS device structure includes several thermocouple pairs formed on semiconductor structure layer. The thermocouple pairs include cold junction thermocouple pairs and hot junction thermocouple pairs. The hot junction thermocouple pairs are located at the hot junction of the center of the chip body.

[0061] In this configuration, one cold-junction thermocouple is connected as the positive terminal to the drain of the CMOS device structure, while the other cold-junction thermocouple is connected as the negative terminal to the P+ contact GND terminal. The gate is connected to a multiplexer (also known as a signal multiplexer) in the peripheral circuitry. The multiplexer (signal multiplexer (MUX) 122) is used to select the gas chip channel in the gas chip array. Specifically, the CMOS device structure uses the signal multiplexer (MUX) 122 to select and control the MEMS thermopile gas chip by adjusting the gate voltage 30 of different cells in the array, thereby selectively detecting different gas concentrations.

[0062] Specifically, the chip body 11 includes a semiconductor structure layer and a CMOS device structure and a MEMS device structure integrated within the semiconductor structure layer. The semiconductor structure layer includes a substrate and a support layer, an oxide layer 41 and a passivation layer 44 stacked on the substrate.

[0063] refer to Figure 11-14 The CMOS device structure includes a P-well structure 24 formed on the substrate, and a source 29, a gate 30, a drain 31, and a P+ contact GND terminal 36.

[0064] Specifically, the MEMS device structure includes a thermopile formed on the support layer, and the thermopile includes several thermocouple pairs.

[0065] In this configuration, one cold junction thermocouple is connected to the drain 31 as the positive terminal, and the other cold junction thermocouple is connected to the P+ contact GND terminal 36 as the negative terminal. The gate 30 is connected to the multiplexer of the peripheral circuit.

[0066] In this disclosure, a thermopile gas chip is integrated using CMOS-MEMS technology. The designed CMOS device is integrated with the thermopile technology, which can innovatively utilize the CMOS device to selectively control the MEMS thermopile gas chip, thereby realizing the detection of different types of gas concentrations by different cells in the array.

[0067] In some embodiments, the gas sensor integrates CMOS device structures and MEMS device structure arrays.

[0068] In some embodiments, reference is made to Figure 12 The support layer includes a first support layer 25, a second support layer 26, and a third support layer 27 sequentially stacked on the substrate. The first support layer 25 serves as the oxide layer for the gate 30, and the third support layer 27 serves as a field oxide / wet oxide layer for electrical isolation between CMOS device structures.

[0069] In some embodiments, the stresses of the first support layer 25 and the third support layer 27 are opposite to those of the second support layer 26.

[0070] Specifically, for the MEMS device structure, the three support layers are fabricated by reversing the stress of the first support layer 25 and the third support layer 27 with that of the second support layer 26 to improve the stress of the support film. For the CMOS device structure, the first support layer 25 can serve as the oxide layer of the gate 30, the third support layer 27 can serve as a field oxide / wet oxide layer for electrical isolation between CMOS device structures, and the second support layer 26 can serve as a barrier mask layer for the growth of the third support layer 27.

[0071] In some embodiments, the first support layer 25 is a silicon oxide support layer, the second support layer 26 is a silicon nitride support layer, and the third support layer 27 is a silicon oxide support layer.

[0072] refer to Figure 1-8 In one embodiment of this disclosure, a method for fabricating a gas sensor chip with an integrated lens is provided, comprising:

[0073] S101, Fabrication of silicon lens array structure 10;

[0074] S102, Prepare chip body 11;

[0075] S103, integrated silicon lens array structure 10 and chip body 11; wherein, the lens of silicon lens array structure 10 corresponds to the position of the central hot end of chip body 11.

[0076] In some embodiments, step S101, fabricating the silicon lens array structure 10, includes:

[0077] S1011, Provide silicon substrate 1, and perform cleaning and thinning treatment.

[0078] In some embodiments, reference is made to Figure 1 The silicon substrate 1 is a P-type double-polished silicon wafer. Further, the P-type double-polished silicon wafer is sequentially ultrasonicated for 5 minutes each in acetone, anhydrous ethanol, and deionized water according to standard procedures. After ultrasonic treatment, the wafer is placed on a hot plate and heated at 100°C for half an hour. This cleaning process removes contaminants and dust particles from the surface of the silicon wafer.

[0079] Furthermore, after cleaning, the silicon wafers are thinned to a thickness of 400-600 μm. A predetermined number of thinned silicon wafers are prepared for use as needed.

[0080] S1012. The surface of the silicon substrate is etched using femtosecond laser processing technology to form a lens array on the silicon substrate.

[0081] In some embodiments, the cleaned and thinned silicon wafer (silicon substrate 1) is placed on a high-precision three-dimensional moving platform, and a laser with a wavelength of 800 nm, a pulse width of 100–300 fs, a repetition frequency of 1–3 kHz, a pulse number of 100–200, and a laser energy range of 50–100 nJ / cm² is used. 2 A linearly polarized femtosecond laser is used, and the laser is focused onto the surface of a silicon wafer through an objective lens with a numerical aperture of 0.8 (magnification of 80x).

[0082] Further, refer to Figure 2 By moving a three-dimensional moving platform, a microporous structure array with a certain arrangement is prepared on the surface of a silicon wafer. Specifically, after laser modification at a specific location, the sample is ultrasonically treated in deionized water for 5 minutes to remove particles generated by surface laser ablation and scattered on the sample surface. After removing the surface particles, a preliminary solid pit array 2 is formed inside the silicon wafer.

[0083] Furthermore, after laser modification, the silicon wafer with the solid pit array 2 is placed in the etching chamber of an inductively coupled plasma etching system (ICP) and dry etching is performed in an SF6 gas plasma environment. ICP was chosen because of its controllability in both lateral and longitudinal etching.

[0084] In some embodiments, the adjustable ranges of the upper and lower radio frequency source power of the etching system are 400–500W and 200–300W, respectively, and the airflow is 40–100 sccm.

[0085] In some embodiments, the etching process includes two stages: first, the rapid etching of the laser-modified solid pit array 2 in the initial stage; and second, the subsequent expansion of the concave structure as the etching time increases. The rapid etching of the laser-modified solid pit array 2 in the initial stage lasts 3–5 minutes.

[0086] refer to Figure 3 During the laser ablation process to form the solid pit array 2 of the laser-modified region, oxygen in the air reacts with silicon atoms to form silicon oxide, and the crystal type of the silicon lattice in the ablation region changes from a single-crystal state to a polycrystalline or amorphous state. Therefore, in the first 3-5 minutes of etching, the solid pit array 2 of the laser-modified region is rapidly etched away, and the etching depth quickly reaches a maximum value. In the initial stage of etching, the solid pit array 2 of the laser-modified region is rapidly etched away to form the hollow pit array 3, where the etching rate of the modified region is approximately 4-8 times faster than that of the unmodified region.

[0087] Further, refer to Figure 4 During the expansion phase, the size of the micropore structure increases with the etching time, gradually expanding to form concave lenses 4. Specifically, the silicon substrate has opposing first and second surfaces, wherein the concave lens array is formed on the first surface.

[0088] In some embodiments, the etching time for the extended etching phase is 5 to 50 minutes.

[0089] When the etching time is between 5 and 20 minutes, the lateral dimension of the concave lens increases approximately linearly with the increase of etching time. Therefore, the lateral etching rate is relatively stable with the increase of etching time. Furthermore, as the etching time increases to 20–50 minutes, the surface of the concave structure becomes smoother and smoother.

[0090] During the etching process described above, the etching depth gradually decreases and eventually becomes constant as the etching time increases. This is due to aspect ratio-dependent etching (ARDE, or aperture effect). The aperture effect causes insufficient local gas supply and delayed emission of reaction products, resulting in a decrease in the etching rate at the bottom of the concave lens 4, while the external etching rate remains unaffected. As the etching time increases, the aspect ratio of the concave lens 4 also gradually decreases, thus weakening the aperture effect and causing the etching depth to gradually become constant.

[0091] S1013. Integrate the filter onto the surface of the opposing lens array on the silicon substrate 1 to fabricate the silicon lens array structure 10. The filter and lens are positioned correspondingly to focus the energy of an external infrared light source to the central hot end of the chip body.

[0092] For details, please refer to Figure 5 A layer of photoresist is coated onto the bottom silicon plane of the silicon substrate 1 and photolithography is performed to form the structure of photoresist 5, which serves as the mask structure for subsequent filter integration. Specifically, the bottom surface is the second surface of the silicon substrate 1.

[0093] refer to Figure 6An AgF thin film with a thickness of 400–700 nm or a MgF2 thin film with a thickness of 800–1400 nm is deposited on the second surface of the aforementioned silicon substrate 1. Both of these functional materials have high transmittance in the 3.43 μm infrared band. Since methane gas has a strong absorption characteristic of infrared light in the 3.43 μm band, the concentration of methane gas can be detected by feeding back the magnitude of the infrared light energy in the 3.43 μm band using a gas chip.

[0094] Therefore, integrating a high-transmittance filter with a specific infrared band onto the surface of a gas-sensitive chip can greatly improve detection sensitivity. Furthermore, different gases absorb different infrared bands, thus this method exhibits high selectivity in gas concentration detection. In this case, integrating a specific 3.43µm high-transmittance infrared filter allows for the detection of methane gas concentration.

[0095] refer to Figure 7 Similarly, Al(NO3)3 thin films with a thickness of 400–800 nm and AlGaS thin films with a thickness of 500–1000 nm were deposited on the surface of the aforementioned silicon substrate 1 to fabricate a silicon lens array structure 10. These two functional materials exhibit high transmittance in the 3.95 μm and 4.26 μm infrared bands, respectively. Most gases do not absorb infrared light in the 3.95 μm band; only water vapor exhibits significant absorption. Therefore, the Al(NO3)3 thin film functional material is used as a reference to eliminate external environmental interference. Carbon dioxide gas has a strong absorption characteristic in the 4.26 μm infrared band, so the concentration of carbon dioxide gas can be detected by feedback from the magnitude of the infrared light energy in the 4.26 μm band using a gas chip. Therefore, the three functional materials on the surface of silicon substrate 1 function as monomers for methane gas concentration detection, reference monomers, and monomers for carbon dioxide gas concentration detection, respectively.

[0096] In some embodiments, the method further includes: S1014, integrating the silicon lens array structure 10 with the integrated filter film and the chip body 11 into a single-chip integrated circuit (SOC) using an optical adhesive 9. The chip body 11 is an NDIR infrared gas sensor chip array. See details... Figure 8 .

[0097] Specifically, the first step involves ultra-precision polishing of the bonding surfaces of the integrated devices. For the silicon lens array structure 10, the bonding surfaces are the front sides facing the lens surfaces, while for the NDIR infrared gas sensor chip array, the bonding surfaces are thermistor surfaces facing upwards. The second step involves isothermal treatment of the silicon lens array structure 10 and the NDIR infrared gas sensor chip array, which are to be photo-bonded. The two photo-bonded components are placed in an environment of 50-100℃ and kept at that temperature for approximately 3 hours to ensure uniform device temperature and promote strong photo-bonding. The third step involves cleaning the photo-bonded components. The photo-bonded surfaces are cleaned using a soft material from the same environment, and then covered with a dust-free glass cover. The fourth step involves applying pressure to the two devices to achieve photo-bonding, followed by coating a thin layer of photosensitive adhesive on the outer edge of the contact surface to enhance the photo-bonding effect.

[0098] refer to Figure 9-16 In another embodiment of this disclosure, a method for fabricating an array chip for detecting multiple gases is provided, comprising:

[0099] S201, Fabrication of silicon lens array structure 10;

[0100] S202, Fabrication of chip body 11;

[0101] S203, Fabrication of resonant cavity array structure 20;

[0102] S204, integrated silicon lens array structure 10, resonant cavity array structure 20 and chip body 11.

[0103] In some embodiments, the fabrication of the chip body 11 in step S202 includes:

[0104] S2021, Provide substrate 21.

[0105] In some embodiments, reference is made to Figure 9 The substrate 21 is a P-type double-polished silicon wafer that has been cleaned and thinned.

[0106] In some embodiments, P-type double-polished silicon wafers are sequentially ultrasonicated for 5 minutes each in acetone, anhydrous ethanol, and deionized water, according to standard procedures. After ultrasonic treatment, the wafers are placed on a hot plate and heated at 100°C for half an hour. This cleaning process removes contaminants and dust particles from the surface of the silicon wafer.

[0107] Furthermore, after cleaning, the silicon wafers are thinned to a thickness of 400-600 μm. A predetermined number of thinned silicon wafers are prepared for use as needed.

[0108] In some embodiments, reference is made to Figure 10 A barrier layer 22 is implanted on the surface of substrate 21 using a hot oxidation (dry oxidation) process, wherein the hot oxidation current is 500-1000A.

[0109] In some embodiments, photolithography is performed on the structural layer consisting of substrate 21 and barrier layer 22.

[0110] For details, please refer to Figure 11 A layer of photoresist 23 is coated on the surface of the barrier layer 22, wherein the photoresist 23 exposes the CMOS region of the substrate 21. Further, boron ions are implanted into the CMOS region to form a lightly doped P-well structure 24, and the photoresist 23 is removed.

[0111] S2022, An upper support layer, an oxide layer 41, and a passivation layer 44 are sequentially formed on the substrate 21 to prepare a semiconductor structure layer.

[0112] Further, refer to Figure 12 The support layer includes a first support layer 25, a second support layer 26 and a third support layer 27.

[0113] In some embodiments, the first support layer 25 is a silicon oxide support layer, the second support layer 26 is a silicon nitride support layer, and the third support layer 27 is a silicon oxide support layer.

[0114] In some embodiments, forming a support layer on the substrate 21 includes: depositing a first support layer 25 with a thickness of 0.1 to 5 μm on the surface of the structural layer formed by the substrate 21 and the barrier layer using a thermal oxidation process; and depositing a second support layer 26 with a thickness of 0.01 to 0.5 μm and a third support layer 27 with a thickness of 0.01 to 0.5 μm on the surface of the first support layer 25 using front-side low-pressure chemical vapor deposition.

[0115] In this disclosure, for MEMS device structures, three support layers are fabricated by reversing the stress of silicon nitride and silicon oxide to improve the stress of the support film. For CMOS device structures, the first support layer 25 can serve as the oxide layer of the gate 30, the third support layer 27 can serve as a field oxide / wet oxide layer for electrical isolation between CMOS devices, and the second support layer 26 can serve as a barrier mask layer for the growth of the third support layer 27.

[0116] S2023. Fabricate CMOS device structures and MEMS device structures on semiconductor structure layers.

[0117] For details, please refer to Figure 13 A layer of polycrystalline silicon 28 with a thickness of 0.1 to 2 μm is sputtered on the surface of the third support layer 27 using a plasma-enhanced chemical vapor deposition process, and phosphorus ions are doped by ion implantation and diffusion to form an N-type polycrystalline silicon semiconductor.

[0118] Furthermore, the source 29, gate 30, and drain 31 of the CMOS device structure are formed on the structural layer composed of the substrate 21 and the support layer through a heavy doping process. A thermopile for the MEMS device structure is formed on the polysilicon 28 through a heavy doping process. The gas chip thermopile for the MEMS device structure includes a first cold-junction thermocouple 32 and a second cold-junction thermocouple 35 of another thermocouple pair. The gas chip thermopile also includes a first hot-junction thermocouple 33 and a second hot-junction thermocouple 34 of another thermocouple pair.

[0119] Furthermore, boron ions are doped into polycrystalline silicon 28 using ion implantation and diffusion methods to form a P-type polycrystalline silicon semiconductor.

[0120] Further, refer to Figure 14 The P+ contact GND terminal 36 of the CMOS transistor is formed on the structural layer composed of substrate 21 and support layer through a heavy doping process. This provides a low-impedance connection point for the CMOS transistor and suppresses reverse breakdown of the source-drain junction and leakage current. Simultaneously, the third cold-junction thermocouple 37 and the fourth cold-junction thermocouple 40 of another thermocouple pair are formed on polysilicon 28 through a heavy doping process. The third hot-junction thermocouple 38 and the fourth hot-junction thermocouple 39 of another thermocouple pair are also formed on polysilicon 28. The third hot-junction thermocouple 38 (P-type polysilicon) and the first hot-junction thermocouple 33 (N-type polysilicon) form a hot-junction thermocouple pair. The fourth hot-junction thermocouple 39 (P-type polysilicon) and the second hot-junction thermocouple 34 (N-type polysilicon) form a hot-junction thermocouple pair. The third cold junction thermocouple 37 (P-type polycrystalline silicon) and the first cold junction thermocouple 32 (N-type polycrystalline silicon) form a cold junction thermocouple pair. The fourth cold junction thermocouple 40 (P-type polycrystalline silicon) and the second cold junction thermocouple 35 (N-type polycrystalline silicon) form a hot junction thermocouple pair.

[0121] In some embodiments, the thermocouples are connected in series via Al metal, and the potential is accumulated to form a highly sensitive thermopile. The infrared gas chip formed by the thermopile can provide real-time feedback of infrared light energy.

[0122] In some embodiments, reference is made to Figure 15 A top oxide layer 41 with a thickness of 0.01 to 10 μm is deposited on polycrystalline silicon 28 using plasma-enhanced chemical vapor deposition to form a top oxide layer 41 for electrical insulation.

[0123] In some embodiments, a layer of aluminum with a thickness of 100-500 nm is deposited using magnetron sputtering, and photolithography is performed to form a conductive layer 42. The conductive layer 42 is used to connect the thermocouple pairs of each MEMS part, and at the same time connects the third cold junction thermocouple 37 (positive electrode) of the MEMS gas chip to the drain 31 of the CMOS part.

[0124] Furthermore, a silicon nitride layer with a thickness of 0.01–10 μm is deposited on the surface of the oxide layer 41 by plasma-enhanced chemical vapor deposition to form a passivation layer 44.

[0125] In some embodiments, reference continues to be made to Figure 15 A tungsten-gold layer with a thickness of 100–500 nm was deposited using a secondary magnetron sputtering method to serve as the PAD layer 43 metal, while simultaneously exposing the PAD layer 43 metal to connect with the peripheral board-level circuitry. Further, refer to... Figure 16 Deep silicon etching is used to etch the bottom surface of the silicon substrate 21 to form a back cavity 45, so as to release the hot end position of the device center, forming a back release cavity, and completing the fabrication of the MEMS gas chip. The back cavity 45 is used to reduce the heat loss of the hot end center, thereby forming a temperature difference between the hot and cold ends.

[0126] In some embodiments, a second cold junction thermocouple 35 (negative electrode) of the MEMS gas chip is connected to the P+ contact GND terminal 36 of the CMOS part in an array using two layers of tungsten gold, forming a MEMS gas sensor chip that integrates an electronic switch CMOS transistor, wherein the thermopile unit and the CMOS device are connected in a one-to-one correspondence.

[0127] Furthermore, the array gate 30 is connected in parallel to the peripheral circuit multiplexer MUX. By adjusting the gate voltage of different cells in the array, selective detection of different gas concentrations is achieved. When the supply voltage of the gate 30 is greater than the threshold voltage, these electrons form an N-type thin layer on the surface of the P substrate 21 near the gate 30, which is connected to the two N+ regions, forming an N-type conductive channel between the drain and source. At this time, the CMOS transistor is in the on state; otherwise, it is in the off state.

[0128] In some embodiments, step S203, fabricating the resonant cavity array structure 20, includes:

[0129] S2031, Provides P-type double-polished silicon wafer 110, which undergoes cleaning and thinning processes. See details. Figure 17 .

[0130] In some embodiments, the P-type double-polished silicon wafer 110 is sequentially ultrasonicated for 5 minutes each in acetone, anhydrous ethanol, and deionized water according to standard procedures. After ultrasonic treatment, the silicon wafer is placed on a hot plate and heated at 100°C for half an hour. This cleaning process can remove contaminants and dust particles from the surface of the silicon wafer.

[0131] Furthermore, after cleaning, the silicon wafers are thinned to a thickness of 400-600 μm. A predetermined number of thinned silicon wafers are prepared for use as needed.

[0132] S2032. The silicon wafer surface is etched using femtosecond laser processing technology to form an array of pits on the silicon wafer.

[0133] For details, please refer to Figure 18 The cleaned and thinned silicon wafer 110 was placed on a high-precision three-dimensional moving platform, and a laser with a wavelength of 800nm, a pulse width of 100-300fs, a repetition frequency of 1-3kHz, a pulse number of 20-50, and a laser energy range of 20-50nJ / cm² was used. 2 The first solid pit 111 was fabricated using a linearly polarized femtosecond laser. The laser pulse number ranged from 100 to 200, and the laser energy ranged from 50 to 100 nJ / cm². 2 The second solid pit 112 was fabricated using a linearly polarized femtosecond laser. The laser pulse number ranged from 300 to 500, and the laser energy ranged from 100 to 150 nJ / cm². 2 The third solid pit 113 was prepared by linearly polarized femtosecond laser.

[0134] In some embodiments, reference is made to Figure 19 The laser-modified silicon wafer 110 is placed in the etching chamber of an inductively coupled plasma (ICP) etching system, and dry etching is performed in an SF6 gas plasma environment to form a first hollow pit 114, a second hollow pit 115, and a third hollow pit 116. Further, refer to... Figure 20 The etching duration is 20 to 50 minutes to form first pit 117, second pit 118 and third pit 119 of different depths.

[0135] S2033, A reflective layer is formed on the surface of the pit.

[0136] For details, please refer to Figure 21 A metal reflective layer 125, with a thickness of 300–500 nm, is deposited on the concave silicon surface of the pit using LPCVD to complete the fabrication of the resonant cavity array structure 20. The resonant cavity array structure 20 is a solid-bottom silicon structure.

[0137] Aluminum-chromium alloys can reflect over 90% of infrared light, increasing the heat output of the gas chip's hot end and thus improving the sensitivity for gas concentration detection. The different depths of the indentations are due to the different infrared bands and wavelengths required for detecting different gas concentrations, which in turn influences the height of the bottom section used as the resonant cavity.

[0138] In some embodiments, the height of the resonant cavity is generally 1 / 4λ to 3 / 4λ, where λ is the infrared wavelength. The wavelengths selected in this disclosure are 3.43µm, 3.95µm, and 4.26µm, respectively. Therefore, resonant cavities of different heights are selected to form self-excited oscillations, thereby increasing the reception and focusing of the weak light intensity emitted by the infrared light source at the center of the chip.

[0139] In some embodiments, reference is made to Figure 22 The resonant cavity array structure 20 is integrated with the chip body 11 via adhesive 120 for SOC integration, wherein the chip body 11 is an NDIR gas sensor chip.

[0140] In some embodiments, reference is made to Figure 23 The gate 30 of the electronic switch CMOS of the gas chip array with integrated resonant cavity array structure 20 is connected to the signal multiplexer (MUX) 122 through gold wire 121, and the signal multiplexer (MUX) 122 is used to select the chip channel of the gas chip array.

[0141] Furthermore, the entire chip array is fixedly packaged onto the bottom PCB board 124 using die-attach adhesive 123. The bottom is a resonant cavity array structure 20 substrate structure. In this disclosure, compared to a back cavity structure, the solid bottom silicon structure is more convenient for WLP packaging in practical use, improving the overall reliability and practicality of the gas chip array. Further, refer to... Figure 24 A gas sensor chip with integrated silicon lenses is fabricated by encapsulating a silicon lens array structure 10, a chip body 11, and a resonant cavity array structure 20.

[0142] In some embodiments, reference is made to Figure 25 , Figure 25 This diagram illustrates the infrared light incident effect of a SOC integrating a silicon microconcave lens with an integrated filter, a bottom reflective layer, and an NDIR infrared gas sensor chip. Using the design disclosed herein, the infrared light energy emitted by the infrared light source can be concentrated as much as possible at the hot end. The microconcave lens and the bottom concave-convex resonant cavity can focus the energy of the infrared light source onto the sensitive area of ​​the infrared chip, improving the chip output and thus enhancing the gas concentration detection sensitivity.

[0143] It is understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of this disclosure, and this disclosure is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and substance of this disclosure, and these modifications and improvements are also considered to be within the scope of protection of this disclosure.

Claims

1. A gas sensor chip with an integrated silicon lens, characterized in that, The chip includes a silicon lens array structure and a chip body; the silicon lens array structure includes a silicon substrate and a plurality of filters; the silicon substrate has a first surface and a second surface opposite to each other, the first surface having a lens array formed thereon; the second surface of the silicon substrate has the filters disposed thereon; the lenses and the filters are positioned correspondingly. The first surface of the silicon substrate is integrated and connected to the upper surface of the chip body; wherein, the lens corresponds to the position of the central hot end of the chip body, and is used to concentrate the energy of the external infrared light source to the central hot end of the chip body; the lens array is formed by femtosecond laser processing; the lens array is a concave lens array.

2. The chip according to claim 1, characterized in that, The filters include a methane filter, a reference comparison filter, and a carbon dioxide filter.

3. The chip according to claim 2, characterized in that, The methane filter comprises an AgF film or a MgF2 film; the reference comparison filter comprises an Al(NO3)3 film; and the carbon dioxide filter comprises an AlGaS film.

4. The chip according to claim 1, characterized in that, Also includes: A resonant cavity array structure is disposed on the lower surface of the chip body; the resonant cavity array structure forms an array of pits; The substrate of the chip body has a back cavity, which corresponds to the central hot end of the chip body. The surface of the recess is provided with a reflective layer; the recess is correspondingly arranged with the back cavity, and the recess and the back cavity together constitute a resonant cavity.

5. The chip according to claim 4, characterized in that, The back cavity is convex; the back cavity and the pit together form a concave-convex resonant cavity.

6. The chip according to claim 4, characterized in that, The pit array includes pits of different depths.

7. The chip according to claim 6, characterized in that, The depth of the pit is 1 / 4λ to 3 / 4λ, where λ is the infrared wavelength.

8. The chip according to claim 1, characterized in that, The chip body includes a semiconductor structure layer and CMOS device structures and MEMS device structures integrated within the semiconductor structure layer.

9. A method for fabricating a gas sensor chip with an integrated silicon lens, characterized in that, include: Fabrication of silicon lens array structures; Fabrication of the chip body; The silicon lens array structure and the chip body are integrated; wherein the lenses of the silicon lens array structure correspond to the positions of the central hot ends of the chip body; The fabrication of the silicon lens array structure includes: Provide a silicon substrate and perform cleaning and thinning processes; The surface of the silicon substrate is etched using femtosecond laser processing technology to form a lens array on the silicon substrate; A filter is integrated onto the surface of the silicon substrate opposite to the lens array to fabricate the silicon lens array structure; wherein the filter corresponds to the position of the lens.

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