FPGA-based general radar timing real-time generation and updating method

Abstract

The application belongs to the technical field of radar system, and particularly relates to a general radar timing real-time generation and updating method based on FPGA. The application specifically comprises establishing a radar working mode table according to different radar systems, and updating radar working mode parameters in real time for each CPI. When the radar working mode parameters are updated, a timing state machine in a reference timing module is used to switch and control a timing generation counter in real time. Thus, the timing pulses required by the radar system can be generated in real time and can be updated in real time. The application overcomes the poor generalization of the conventional radar timing module, and only needs to design different working mode tables for different radar systems to complete the generation of timing pulses in different working modes without updating the FPGA program of the timing module. Meanwhile, the application can realize the real-time switching of the timing in different working modes through the ping-pong switching of the timing state, thereby improving the stability of the radar system working.

Description

Technical Field

[0001] This invention belongs to the field of radar system technology, specifically relating to a general-purpose radar timing real-time generation and update method based on FPGA. Background Technology

[0002] Radar is an electronic device that uses electromagnetic waves to detect targets. Its basic function is to detect targets by utilizing the scattering (diffraction) of electromagnetic waves by the target, and to calculate information such as the target's distance, speed, angle, and altitude from the radar. With the development of radar system technology, various types of radar systems have emerged. We can classify radar systems according to different characteristics into continuous wave radar, pulse radar, phased array radar, Doppler radar, and synthetic aperture radar, etc. Different types of radar play important roles in different application scenarios. A radar system generally consists of an antenna, transmitter, receiver, signal processor, terminal display device, servo system, and synchronization device. The radar timing generation module is a crucial component of each radar system, mainly used to generate various timing signals, ensuring that all parts of the radar system operate under unified timing conditions to guarantee the normal operation of the radar system. In early radar systems, the radar timing generation module typically consisted of analog devices such as trigger pulse generators, modulators, and pre-modulators. With the development of digital technology, radar timing modules can also be generated based on digital circuits. Currently, radar timing modules are often designed for specific radar systems, resulting in poor reusability. At the same time, when frequently and rapidly switching between different radar operating modes, there is a certain delay in the timing switching and data update of the radar timing module, which may lead to timing disorder in the radar system. Summary of the Invention

[0003] The purpose of this invention is to address the problems of poor versatility of timing modules in different radar systems, such as pulse radar and phased array radar, and the delay in timing module updates during rapid switching between different radar operating modes. This invention proposes a highly versatile real-time radar timing generation and update method based on FPGA.

[0004] The technical solution of this invention is as follows:

[0005] A general-purpose radar timing real-time generation and update method based on FPGA includes the following steps:

[0006] S1. Construct a radar operating mode table based on the radar's operating modes. The operating mode table should include timing parameters such as CPI, PRI, pulse width, data acquisition window width, and delay.

[0007] S2. A reference timing module is built based on FPGA. When the radar is working, it acquires the real-time working mode parameters at each CPI and obtains the parameters related to the radar timing by parsing the parameters, thereby generating the reference timing pulse.

[0008] S3. Each working module in the radar system generates corresponding control pulses based on the reference timing pulse and signal pulse width, acquisition window length, and delay parameters.

[0009] S4. When the radar system switches operating modes, the reference timing module switches synchronously and generates a new corresponding reference timing pulse, so as to realize the synchronous real-time update of the control pulses of each working module in the radar system.

[0010] Furthermore, the reference timing module includes a data decoding unit, a timing state machine, and a timing counter. The data decoding unit is used to parse the working mode table, obtain radar timing parameters, and then send them to the timing state machine. The timing state machine is used to clear or accumulate the timing counter according to the radar timing parameters to obtain the reference timing pulse.

[0011] Furthermore, the timing state machine is defined as including a first timing state unit and a second timing state unit. The specific working method of the reference timing module is as follows: after initially acquiring the working mode table from the radar system, in the first CPI, all timing parameters are assigned values, and all timing counters are cleared. Two different sets of parameters are defined as the first set of CPI period parameters, the first set of PRI period parameters, the first set of pulse width parameters, the first set of dwell count parameters, and the second set of CPI period parameters, the second set of PRI period parameters, the second set of pulse width parameters, and the second set of dwell count parameters. At the same time, timing counters are defined as the first set of CPI period counters, the second set of CPI period counters, the PRI period counter, and the dwell count counter.

[0012] Upon entering the first timing state unit, the first set of timing parameters takes effect, and the PRI cycle counter accumulates. A PRI reference timing pulse is generated based on the first set of pulse width parameters. When the PRI cycle counter accumulates to equal the first set of PRI cycle parameters, the dwell count counter increments by 1, the PRI cycle counter is cleared, and accumulation continues until the dwell count counter equals the first set of dwell count parameters, at which point accumulation stops and the current value is maintained. Simultaneously, the first set of CPI cycle counters also accumulates in the first timing state unit, generating a CPI reference pulse. Accumulation stops when the first set of CPI cycle counters accumulates to equal the first set of CPI cycle counts, and the timing state machine is switched from the first timing state unit to the second timing state unit. At this point, all the second set of timing parameters takes effect, and the PRI cycle counter and the second set of CPI counters accumulate and count as described in the first timing state unit, generating the next PRI and CPI reference timing pulses.

[0013] Except for the first CPI, where all timing parameters are assigned values ​​and all timing counters are cleared, in subsequent CPIs, all timing parameters of the first group are assigned values ​​in the second timing state unit, and all counters of the first group are cleared in the second timing state unit and take effect in the first timing state unit; all timing parameters of the second group are assigned values ​​in the first timing state unit, and all counters of the second group are cleared in the first timing state unit and take effect in the second timing state unit.

[0014] The beneficial effects of this invention are as follows: Specifically, this invention includes establishing a radar operating mode table according to different radar systems. Each CPI updates the radar operating mode parameters in real time. When the radar operating mode parameters are updated, the timing state machine in the reference timing module switches and controls the timing generation counter in real time. This allows for the real-time generation and updating of the timing pulses required by the radar system. This invention overcomes the shortcomings of traditional radar timing modules in terms of poor versatility. By designing different operating mode tables for different radar systems, timing pulse generation under different operating modes can be completed without updating the timing module FPGA program. Simultaneously, this invention achieves real-time switching of timing between different operating modes through ping-pong switching of timing states, thereby improving the stability of the radar system. Attached Figure Description

[0015] Figure 1 This is a system block diagram of a radar timing real-time generation and update method based on FPGA.

[0016] Figure 2 The diagram below shows the block diagram of the baseline timing module scheme.

[0017] Figure 3 Flowchart for real-time switching of radar operating modes.

[0018] Figure 4 This is an example of a baseline timing pulse sequence.

[0019] Figure 5 This is an example of receiving timing pulses in a multi-channel system.

[0020] Figure 6 This is an example of a multi-channel transmit timing pulse.

[0021] Figure 7 A simulation example for generating timing pulses. Detailed Implementation

[0022] The specific embodiments of the present invention will now be clearly and completely described with reference to the accompanying drawings, so that those skilled in the art can better understand the invention.

[0023] This invention utilizes an FPGA (Field-Programmable Gate Array) hardware platform and a high-precision system clock to generate timing control pulses for the radar system in real time under different operating modes. It also updates and switches these timing pulses in real time during mode switching, ensuring seamless and high-precision timing control pulse continuity across the entire radar system. Furthermore, this method is highly versatile and can be ported to different radar systems without modifying the source code, thereby improving radar system development efficiency.

[0024] Figure 1 The diagram shows a system block diagram for a real-time radar timing generation and update method based on FPGA. It mainly includes a radar software system, a reference timing module, and timing generation modules for the receiver and transmitter. Considering the inconsistency in the operating modes of different radar systems, the radar software system or radar system designer first constructs a radar operating mode table, which must contain the parameters required for radar timing generation.

[0025] Once the operating mode table parameters are generated, they can be sent to the reference timing module via a high-speed data transmission interface, such as 10 Gigabit Ethernet or PCIe. The reference timing module parses the operating mode table data and extracts the radar timing parameters for use by the timing state machine. Then, under the control of the timing state machine, the timing counter is cleared or incremented, thereby generating reference timing pulses. These reference timing pulses serve as the timing reference standard for the entire radar system, used as a benchmark and combined with the timing parameters to generate multi-channel transmit and receive control pulses. Simultaneously, the reference reference pulses also synchronize the radar system software and the reference timing module via interrupts and can be output to other radar systems as a timing reference.

[0026] The block diagram of the reference timing module is as follows: Figure 2As shown, it mainly consists of a data decoding module, timing state 1, timing state 2, timing counter, etc., and its workflow is as follows: Figure 3 As shown. After the radar software system initially issues the working mode table parameters, the data decoding module decodes the working mode parameters and extracts parameters related to radar timing, such as CPI period, PRI period, pulse width, sampling window length, and dwell count. Since this is the first CPI, all timing parameters need to be assigned values ​​and all timing counters need to be cleared. Two different sets of parameters are defined here: CPI period parameter 1 (CPI_PERIOD_1), CPI period parameter 2 (CPI_PERIOD_2), PRI period parameter 1 (PRI_PERIOD_1), PRI period parameter 2 (PRI_PERIOD_2), pulse width parameter 1, pulse width parameter 2, dwell count parameter 1, dwell count parameter 2, etc., and counter parameters: CPI period counter 1, CPI period counter 2, PRI period counter, etc.

[0027] Then, the system enters timing state 1. All timing parameters with ordinal number 1 take effect in timing state 1. The PRI counter accumulates, generating a PRI reference timing pulse based on pulse width 1. When the PRI counter accumulates to equal the PRI period parameter 1, the dwell count counter increments by 1, the PRI counter is cleared, and accumulation continues until the dwell count counter equals the dwell count parameter 1, at which point accumulation stops and the current value is maintained. Simultaneously, the CPI period counter 1 also accumulates in timing state 1, generating a CPI reference pulse. Accumulation stops when the CPI period counter 1 accumulates to equal the CPI period number 1, and the timing state machine switches from timing state 1 to timing state 2. At this point, all timing parameters with ordinal number 2 take effect, and the PRI counter and CPI counter 2 accumulate as described in timing state 1, generating the next PRI and CPI reference timing pulses.

[0028] It is worth noting that, except for the first CPI where all timing parameters are assigned values ​​and all timing counters are cleared, in subsequent CPIs, all timing parameters with ordinal number 1 are assigned values ​​in timing state 2, all counters with ordinal number 1 are cleared in timing state 2, and take effect in timing state 1. Similarly, all timing parameters with ordinal number 2 are assigned values ​​in timing state 1, and all counters with ordinal number 2 are cleared in timing state 1, and take effect in timing state 2. This is because one timing state occupies one CPI length, and each timing state uses its own timing parameters. When switching between two timing states, the timing parameters also switch in a ping-pong fashion. This allows the radar software system to update the timing parameters at the end of each CPI, assigning values ​​to the timing parameters required for the next timing state under the current CPI, and making them effective in the next timing state. This enables real-time switching and effective operation of the operating mode for each CPI. Figure 4 The diagram shows an example of a reference timing pulse sequence. Under a high-precision system clock, reference timing pulses CPI and PRI are generated. Each CPI contains multiple PRIs and can be divided into four time stages: T1: signal transmission time, T2: signal acquisition and reception time, T3: signal processing and data processing time, and T4: timing parameter update time. If the timing parameters are updated in each CPI, then each CPI can use different timing parameters to generate a corresponding reference timing pulse, thereby completing the real-time update and switching of the operating mode.

[0029] Figure 5 , Figure 6 This paper demonstrates the generation of multi-channel receive control timing pulses and multi-channel transmit control timing pulses based on reference timing pulses. After the radar receiver and transmitter receive the reference timing pulse, they can generate corresponding transmit and acquire control pulses using the reference timing pulse as a reference, combined with parameters such as pulse width, sampling window length, and delay. Considering the different time delays between the reference timing pulse and different radar components, these delays can be measured and compensated, thereby enabling high-precision synchronization of each radar component under the control of the reference timing pulse.

[0030] This completes the implementation of a radar timing module that allows for real-time updates and switching of radar operating modes. The method is summarized as follows:

[0031] (1) Construct a radar operating mode table based on the radar's operating mode, which includes radar timing control parameters.

[0032] (2) When the radar system is working, the working mode parameters are updated to the reference timing module in real time during the CPI T4 time period.

[0033] (3) After the reference timing module receives the radar operating mode parameters, the data decoding module parses the parameters to obtain the parameters related to the radar timing.

[0034] (4) After obtaining the radar timing parameters, the timing state machine controls the timing counter to perform clearing or accumulation operations to generate reference timing pulses.

[0035] (5) The radar transmitter and receiver or other radar system can generate corresponding control pulses based on parameters such as reference timing pulse and signal pulse width, acquisition window length, and delay.

[0036] (6) When the radar system updates the working mode parameters and switches the working mode, the timing state is switched in a ping-pong manner, so that the reference timing pulse follows the timing state to switch and update parameters in real time. Finally, the control pulses of the radar transmitter and receiver are also updated synchronously in real time.

[0037] The radar timing module will be implemented below based on the actual timing parameters and the method described above.

[0038] (1) Construct the working mode table as shown in Table 1.

[0039] Table 1 Working Mode Table

[0040]

[0041]

[0042] Table 1 lists the timing parameters for three different operating modes.

[0043] (2) First, the timing parameters of working mode 1 in the working mode table are sent from the radar software system to the reference timing module via a 10 Gigabit network. Under the 200MHz system clock, after receiving the timing parameters, the reference timing module parses and extracts the timing parameters of working mode 1, enters timing state 1, and generates the reference pulses CPI and PRI corresponding to working mode 1 based on the timing parameters and timing counters corresponding to timing state 1. Figure 5 and Figure 6 Generate corresponding transmit control pulses and receive control pulses, with a timing pulse accuracy of 5ns.

[0044] (3) During the CPI T4 time phase corresponding to timing state 1, update the timing parameters of working mode 2 in the working mode table to the base timing module. At this time, extract the timing parameters of working mode 2 and assign values ​​to the timing parameters and counters corresponding to timing state 2. When CPI cycle counter 1 is equal to the CPI cycle in working mode 1, the timing state switches from timing state 1 to timing state 2.

[0045] (4) At this time, the timing counter corresponding to timing state 2 generates the corresponding reference timing pulses CPI and PRI based on the timing parameters of working mode 2. Similarly, during the CPI T4 time stage corresponding to timing state 2, the timing parameters of working mode 3 in the working mode table are updated to the reference timing module. At this time, the timing parameters of working mode 3 are extracted and assigned to the timing parameters and counters corresponding to timing state 1. When the CPI cycle counter 2 is equal to the CPI cycle in working mode 2, the timing state switches from timing state 2 back to timing state 1.

[0046] (5) At this time, the timing counter corresponding to the timing state machine 1 generates the corresponding reference timing pulses CPI and PRI based on the timing parameters of working mode 3.

[0047] (6) Repeat steps (2)-(4) to achieve real-time switching and updating between different working modes when the sequential state is switched.

[0048] (7) It is worth mentioning that when the timing parameters are not updated, the reference timing module will generate a reference timing pulse based on the last updated timing parameters. This continues until the radar system sends a stop command.

[0049] Figure 7 Examples of reference timing pulse simulations corresponding to the three different operating modes generated by the above process are provided. Although illustrative specific embodiments of the present invention have been described above to facilitate understanding by those skilled in the art, it should be understood that the present invention is not limited to the scope of the specific embodiments. Various modifications are readily apparent to those skilled in the art as long as they fall within the spirit and scope of the invention as defined and determined by the appended claims, and all inventions utilizing the concept of the present invention are protected.

Claims

1. A general-purpose radar timing real-time generation and update method based on FPGA, characterized in that, Includes the following steps: S1. Construct a radar operating mode table based on the radar's operating modes. The operating mode table should include at least CPI, PRI, pulse width, data acquisition window width, and delay parameters. S2. A reference timing module is constructed based on FPGA. During radar operation, it acquires real-time operating mode parameters at each CPI and obtains radar timing-related parameters through parameter parsing, thereby generating a reference timing pulse. The reference timing module includes a data decoding unit, a timing state machine, and a timing counter. The data decoding unit parses the operating mode table to obtain radar timing parameters, which are then sent to the timing state machine. The timing state machine performs clearing or incrementing operations on the timing counter based on the radar timing parameters to obtain the reference timing pulse. The timing state machine is configured to include a first timing state unit and a second timing state unit. The specific working method of the reference timing module is as follows: After initially acquiring the working mode table from the radar system, at the first CPI, all timing parameters are assigned values, and all timing counters are cleared. Two different sets of parameters are defined as the first set of CPI period parameters, the first set of PRI period parameters, the first set of pulse width parameters, the first set of dwell count parameters, and the second set of CPI period parameters, the second set of PRI period parameters, the second set of pulse width parameters, and the second set of dwell count parameters. At the same time, timing counters are defined as the first set of CPI period counters, the second set of CPI period counters, the PRI period counter, and the dwell count counter. Upon entering the first timing state unit, the first set of timing parameters takes effect in the first timing state unit, and the PRI cycle counter is incremented. The PRI reference timing pulse is generated based on the first set of pulse width parameters. When the PRI cycle counter accumulates to equal the first set of PRI cycle parameters, the dwell count counter is incremented by 1, the PRI cycle counter is cleared and continues to accumulate until the dwell count counter equals the first set of dwell count parameters, at which point the accumulation stops and the current value is maintained. At the same time, the first set of CPI cycle counters also accumulates in the first timing state unit, generating CPI reference pulses. The accumulation stops when the first set of CPI cycle counters accumulates to equal the first set of CPI cycle counts, and the state of the timing state machine is switched from the first timing state unit to the second timing state unit. At this time, all second set of timing parameters take effect, and the PRI cycle counter and the second set of CPI counters accumulate and count as described in the first timing state unit, generating the next PRI and CPI reference timing pulses. Except for the first CPI, where all timing parameters are assigned values ​​and all timing counters are cleared, in subsequent CPIs, all timing parameters of the first group are assigned values ​​in the second timing state unit, and all counters of the first group are cleared in the second timing state unit and take effect in the first timing state unit; all timing parameters of the second group are assigned values ​​in the first timing state unit, and all counters of the second group are cleared in the first timing state unit and take effect in the second timing state unit. S3. Each working module in the radar system generates corresponding control pulses based on the reference timing pulse and signal pulse width, acquisition window length, and delay parameters. S4. When the radar system switches operating modes, the reference timing module switches synchronously and generates a new corresponding reference timing pulse, so as to realize the synchronous real-time update of the control pulses of each working module in the radar system.

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