Operation life detection system of harmonic reducer in high temperature and high humidity environment

Abstract

This invention relates to a system for testing the operational life of harmonic reducers under high temperature and humidity environments, specifically a system for testing the operational life of harmonic reducers under such conditions. The invention addresses the aforementioned problems by providing a system for testing the operational life of harmonic reducers under high temperature and humidity environments. The invention includes an FPGA I / O and auxiliary circuit, an FPGA circuit, a variable storage circuit, an ambient temperature and humidity acquisition circuit, a touchscreen control circuit, a motor drive circuit, a device output control circuit, a device phase current acquisition circuit, a motor output angle acquisition circuit, a device temperature acquisition circuit, a device vibration acquisition circuit, and a device noise acquisition circuit. The key feature is that the power output ports of the FPGA I / O and auxiliary circuit are respectively connected to the power ports of the FPGA circuit, the variable storage circuit, the ambient temperature and humidity acquisition circuit, and the touchscreen control circuit.

Description

Technical Field

[0001] This invention belongs to the field of detection system technology, and in particular relates to a system for detecting the service life of a harmonic reducer under high temperature and high humidity conditions. Background Technology

[0002] A harmonic reducer is a speed reduction device consisting of a fixed internal gear, a flexible gear, and a wave generator that causes radial deformation of the flexible gear. Harmonic reducers sometimes operate for extended periods in harsh environments, leading to temperature rise and vibration. Corrosion and wear during operation also alter the equipment's noise level. Failure to detect these changes promptly can negatively impact the reducer's lifespan. Currently, there is no system specifically designed for harmonic reducers operating in high-temperature and high-humidity environments that simultaneously monitors temperature rise, vibration, and noise levels, assesses deformation and wear, and predicts their lifespan. Summary of the Invention

[0003] This invention addresses the aforementioned problems by providing a system for detecting the operational life of harmonic reducers under high temperature and high humidity environments.

[0004] To achieve the above objectives, the present invention adopts the following technical solution: the present invention includes FPGA I / O and auxiliary circuits, FPGA circuit, variable storage circuit, ambient temperature and humidity acquisition circuit, touch screen control circuit, motor drive circuit, device output control circuit, device phase current acquisition circuit, motor output angle acquisition circuit, device temperature acquisition circuit, device vibration acquisition circuit, and device noise acquisition circuit, characterized in that the FPGA... The power output ports of the IO and auxiliary circuits are connected to the power supply ports of the FPGA circuit, the variable storage circuit, the ambient temperature and humidity acquisition circuit, the touch screen control circuit, the motor drive circuit, the equipment output control circuit, the equipment phase current acquisition circuit, the motor output angle acquisition circuit, the equipment temperature acquisition circuit, the equipment vibration acquisition circuit, and the equipment noise acquisition circuit, respectively. The information transmission ports of the FPGA circuit are connected to the information transmission ports of the variable storage circuit and the touch screen control circuit, respectively. The detection signal input ports of the FPGA circuit are connected to the detection signal output ports of the ambient temperature and humidity acquisition circuit, the equipment phase current acquisition circuit, the motor output angle acquisition circuit, the equipment temperature acquisition circuit, the equipment vibration acquisition circuit, and the equipment noise acquisition circuit, respectively. The control signal output ports of the FPGA circuit are connected to the control signal input ports of the motor drive circuit and the equipment output control circuit, respectively.

[0005] As a preferred embodiment, the FPGA IO and auxiliary circuit of the present invention includes an LM2576-5.0 chip U1. Pin 1 of U1 is connected to one end of inductor L2 and +12V. The other end of L2 is connected to +12V2 and pin 3 of LD05-20B12 chip U2. Pin 2 of U2 is connected to L1C. Pin 1 of U2 is connected to L2C. Pin 4 of U2 is connected to GND2 and one end of inductor L18. The other end of L18 is connected to GND, pin 3 of U1, and pin 5 of U1. Pin 4 of U1 is connected to 5V and one end of inductor L1. The other end of L1 is connected to 5VA.

[0006] Pins 1, 2, and 3 of the TPS62040DGQ chip U5 are connected to 5V. Pins 7 and 8 of U5 are connected to one end of resistor R3 and VCC_1.2V respectively through inductor L20. The other end of R3 is connected to pin 5 of U5 and one end of resistor R7 respectively. The other end of R7 is connected to GND.

[0007] Pins 2 and 3 of the TPS62040DGQ chip U6 are connected to 5V. Pins 7 and 8 of U6 are connected to one end of resistor R5, VCC_3.3V, and one end of inductor L22 through inductor L21. The other end of L22 is connected to A3.3V. The other end of R5 is connected to pin 5 of U6 and one end of resistor R8. The other end of R8 is connected to GND.

[0008] Pin 3 of the AMS1117-2.5 chip U9 is connected to 5V, and pins 2 and 4 of U9 are connected to VCC_2.5V.

[0009] As another preferred embodiment, the FPGA circuit of the present invention uses EP4CE15E22I7 chip U11 and EPCS4SI8N chip U15. Pin 12 of U11 is connected to FPGA_DCLK through resistor R14. Pins 1, 2, 5, and 6 of U15 are respectively connected to FPGA_nCSO, FPGA_DATA0, FPGA_ASDO, and FPGA_DCLK. Pin 13 of U11 is connected to FPGA_DATA0 through resistor R18. Pins 6 and 8 of U11 are respectively connected to FPGA_ASDO and FPGA_nCSO.

[0010] Pins 58-61, 64-69, 71, and 72 of U11 are connected to OE2, DIR2, OE1, DIR1, and OUT1-OUT8 respectively.

[0011] Pins 76 and 87 of U11 are connected to CPU_VFO and DSCK respectively;

[0012] Pins 110-115, 119-121, and 125 of U11 are connected to CPU_ALM6-CPU_ALM0, ADCLK1, ADOUT1, ADDIN1, and ADCS1 respectively.

[0013] Pins 98-101, 103, and 104 of U11 are connected to COM3_RXD, COM3_RTS, COM3_TXD, COM4_RXD, COM4_RTS, and COM4_TXD respectively.

[0014] Pins 49 to 51 of U11 are connected to WP, SCL, and SDA respectively.

[0015] Pins 132-134, 143, and 144 of U11 are connected to COM1_RXD, COM1_RTS, COM1_TXD, SDAA, and SCLA respectively.

[0016] Pin 135 of U11 is connected to VCC_3.3V via resistor R28 and LED2 in sequence;

[0017] Pin 136 of U11 is connected to VCC_3.3V via resistor R30 and LED3 in sequence;

[0018] Pin 137 of U11 is connected to VCC_3.3V via resistor R33 and LED4.

[0019] As another preferred embodiment, the variable storage circuit of the present invention uses the FM24V02-GTR chip U20, and pins 5 to 7 of U20 are respectively connected to SDA, SCL and WP.

[0020] As another preferred embodiment, the environmental temperature and humidity acquisition circuit of the present invention uses the SHT30-DIS-B10KS chip U25, and pins 1 and 4 of U25 are respectively connected to SDAA and SCLA.

[0021] As another preferred embodiment, the touch screen control circuit of the present invention uses the SN65HVD12D chip U26. Pin 1 of U26 is connected to COM1_RXD, pins 2 and 3 of U26 are connected to COM1_RTS, and pins 4, 6 and 7 of U26 are connected to COM1_TXD, 485-A and 485-B respectively.

[0022] As another preferred embodiment, the motor drive circuit of the present invention includes a TAS50-15-W module U3. Pin 1 of U3 is connected to pin 2 of common mode inductor L14. Pin 1 of L14 is connected to L1C through thermistor TH1. Pin 4 of L14 is connected to L2C. Pin 3 of L14 is connected to pin 2 of U3. Pin 5 of U3 is connected to N1. Pin 9 of U3 is connected to pin 3 of 15V and UMW78L05 module U41 through inductor L17. Pin 1 of U41 is connected to F5V.

[0023] The collector of the output terminal of the TLP521-1XSM chip U42 is connected to ALM4, the emitter of the output terminal of U42 is grounded, the cathode of the input terminal of U42 is connected to N1, and the anode of the input terminal of U42 is connected to the cathodes of diodes D3, D4, and D5 in sequence through Zener diode D2 and resistor R37. The anode of D3 is connected to L1, the anode of D4 is connected to L2, and the anode of D5 is connected to L3. Pins 2 to 4 of DB1 of the D30XT80-7000 module are connected to L1 to L3 respectively.

[0024] Pin 1 of DB1 is connected to P1, and pin 5 of DB1 is connected to N1. P2 is connected via fuse FU1 to one end of thermistor TH2, pin 7 of JQC-3FF / 005-1HS relay RY1, and pin 8 of RY1. The other end of TH2 is connected to pin 5 of RY1, pin 6 of RY1, the anode of LED LD1, pin 1 of connector CN2, and DCPIN. Pin 2 of CN2 is connected to B3. The cathode of LD1 is connected via resistors R44 and R45 to... One end of resistor R47 is connected to MT3. The other end of R47 is connected to one end of resistor R49 and MT2. The other end of R49 is connected to one end of resistor R54 and MT1. The other end of R54 is connected to N1. The anode of D20 is connected to B, one end of resistor R48, and pin 2 of IRG4BC30V transistor IG1. The other end of R48 is connected to one end of resistor R55 and MT4. The other end of R55 is connected to N1. Pin 1 of IG1 is connected to QCTR1. Pin 3 of IG1 is connected to N1.

[0025] Pins 3 and 4 of RY1 are connected to the anodes of diodes D17, D18, and D19 respectively via resistor R40. The cathode of D17 is connected to W and pin 24 of the FNB34060T module respectively. The cathode of D18 is connected to V and one end of resistor R10, and the other end of R10 is connected to V- and pin 25 of the FNB34060T module respectively. The cathode of D19 is connected to U and one end of resistor R9, and the other end of R9 is connected to U- and pin 26 of the FNB34060T module respectively. Pin 27 of the FNB34060T module is connected to DCPIN.

[0026] Pins 21 to 23 of the FNB34060T module are connected to the UCSC via resistor R58;

[0027] Pins 17, 20, 13, 16, 9, 12, 8, and 6-2 of the FNB34060T module are connected to WP, N1, VP, N1, UP, N1, UCSC, VFO, WN, VN, UN, and N1 respectively.

[0028] The collector of the output terminal of the TLP521-1 chip PC1 is connected to CPU_VFO, the cathode of the input terminal of PC1 is connected to N1, and the anode of the input terminal of PC1 is connected to VFO through resistor R19.

[0029] Pin 2 of the ADR291FRZ chip U4 is connected to 15V through resistor R39, and pin 6 of U4 is connected to VREF.

[0030] Pin 3 of LM2903DR2G chip U7 is connected to VREF, pin 2 of U7 is connected to MT1, pin 1 of U7 is connected to the cathode of the PC9 input terminal of TLP521-1 chip through resistor R41, the anode of the PC9 input terminal is connected to 15V, the collector of the PC9 output terminal is connected to ALM2, and the emitter of the PC9 output terminal is grounded.

[0031] Pin 3 of the LM2903DR2G chip U8 is connected to MT3, pin 2 of U8 is connected to VREF, pin 1 of U8 is connected to the cathode of the PC10 input terminal of the TLP521-1 chip through resistor R43, the anode of the PC10 input terminal is connected to 15V, the collector of the PC10 output terminal is connected to ALM0, and the emitter of the PC10 output terminal is grounded.

[0032] Pin 3 of LM2903DR2G chip U10 is connected to MT4, pin 2 of U10 is connected to VREF, pin 1 of U10 is connected to the cathode of the PC11 input terminal of TLP521-1 chip through resistor R46, the anode of the PC11 input terminal is connected to 15V, the collector of the PC11 output terminal is connected to ALM6, and the emitter of the PC11 output terminal is grounded.

[0033] Pin 3 of the LM2903DR2G chip U13 is connected to VREF through resistor R57. Pin 2 of U13 is connected to MT2. Pin 1 of U13 is connected to the cathode of the PC12 input terminal of the TLP521-1 chip. The anode of the PC12 input terminal is connected to one end of resistor R53 and one end of resistor R56 respectively. The other end of R53 is connected to 15V. The other end of R56 is connected to pin 4 of U13. Pin 8 of U13 is connected to N1. The collector of the PC12 output terminal is connected to ALM5, and the emitter of the PC12 output terminal is grounded.

[0034] Pins 1, 3-5, 7-9, 12-14, and 16-19 of the SN74HCT245N chip U16 are respectively connected to DIR2, ALM6-ALM4, ALM2-ALM0, CPU_ALM0-CPU_ALM2, and CPU_ALM4-CPU_ALM6.

[0035] As another preferred embodiment, the output control circuit of the device of the present invention includes an NPN transistor Q1. The collector of Q1 is connected to pin 2 of the JQC-3FF / 005-1HS relay RY1. Pin 1 of RY1 is connected to 5V. The base of Q1 is connected to CTR8 through resistor R69. The emitter of Q1 is grounded.

[0036] Pin 1 of FOD8314 chip U18 is connected to 5V, pin 3 of U18 is connected to CTR7 through resistor R63, and pin 5 of U18 is connected to QCTR1 through resistor R62.

[0037] The TLP521-1 chip's PC4 input anode is connected to CTR2 via resistor R2, the PC4 input cathode is connected to CTR1 via resistor R6, the PC4 output collector is connected to 15V via resistor R24, and the PC4 output emitter is connected to UP.

[0038] The TLP521-1 chip's PC7 input anode is connected to CTR1 via resistor R52, the PC7 input cathode is connected to CTR2 via resistor R65, the PC7 output collector is connected to 15V via resistor R51, and the PC7 output emitter is connected to UN.

[0039] The TLP521-1 chip's PC3 input anode is connected to CTR4 via resistor R23, the PC3 input cathode is connected to CTR3 via resistor R26, the PC3 output collector is connected to 15V via resistor R21, and the PC3 output emitter is connected to VP.

[0040] The TLP521-1 chip's PC6 input anode is connected to CTR3 via resistor R50, the PC6 input cathode is connected to CTR4 via resistor R64, the PC6 output collector is connected to 15V via resistor R35, and the PC6 output emitter is connected to VN.

[0041] The TLP521-1 chip's PC2 input anode is connected to CTR6 via resistor R22, the PC2 input cathode is connected to CTR5 via resistor R25, the PC2 output collector is connected to 15V via resistor R20, and the PC2 output emitter is connected to WP.

[0042] The TLP521-1 chip's PC5 input anode is connected to CTR5 via resistor R36, the PC5 input cathode is connected to CTR6 via resistor R60, the PC5 output collector is connected to 15V via resistor R34, and the PC5 output emitter is connected to WN.

[0043] Pins 1-9 and 11-19 of the SN74HCT245N chip U21 are connected to DIR1, CTR1-CTR8, OUT8-OUT1, and OE1 respectively.

[0044] As another preferred embodiment, the phase current acquisition circuit of the device of the present invention includes an HCPL-7840-360E chip U17. Pin 2 of U17 is connected to U through resistor R29, pin 3 of U17 is connected to U- through resistor R32, and pins 6 and 7 of U17 are connected to IU- and IU+ respectively.

[0045] The HCPL-7840-360E chip U19 has pin 2 connected to V through resistor R27, pin 3 connected to V- through resistor R31, and pins 6 and 7 connected to IV- and IV+ respectively.

[0046] Pin 6 of the AD8602ARZ chip U12 is connected to IV- through resistor R74, pin 5 of U12 is connected to IV+ through resistor R77, pin 5 of U12 is connected to pins 1 and 2 of U12 through resistor R78, pin 3 of U12 is connected to VCC_1.2V, and pin 7 of U12 is connected to IV through resistor R75.

[0047] Pin 2 of the AD8602ARZ chip U14 is connected to IU- through resistor R82, pin 3 of U14 is connected to IU+ through resistor R86, pin 3 of U14 is connected to pins 6 and 7 of U14 through resistor R94, pin 5 of U14 is connected to VCC_1.2U, and pin 1 of U14 is connected to IU through resistor R83.

[0048] As another preferred embodiment, the motor output angle acquisition circuit of the present invention includes a magnetic ring L3, one end of L3 is connected to BA-, and the other end of L3 is connected to A-1 through a resistor R87; one end of magnetic ring L5 is connected to BA+, and the other end of L5 is connected to A+1 through a resistor R95.

[0049] One end of magnetic ring L7 is connected to BB-, and the other end of L7 is connected to B-1 through resistor R104; one end of magnetic ring L9 is connected to BB+, and the other end of L9 is connected to B+1 through resistor R108.

[0050] One end of magnetic ring L11 is connected to BZ-, and the other end of L11 is connected to Z-1 through resistor R114; one end of magnetic ring L15 is connected to BZ+, and the other end of L15 is connected to Z+1 through resistor R118.

[0051] One end of magnetic ring L4 is connected to BU-, and the other end of L4 is connected to U-1 through resistor R88; one end of magnetic ring L6 is connected to BU+, and the other end of L6 is connected to U+1 through resistor R96.

[0052] One end of magnetic ring L8 is connected to BV-, and the other end of L8 is connected to V-1 through resistor R105; one end of magnetic ring L10 is connected to BV+, and the other end of L10 is connected to V+1 through resistor R109.

[0053] One end of magnetic ring L12 is connected to BW-, and the other end of L12 is connected to W-1 through resistor R115; one end of magnetic ring L16 is connected to BW+, and the other end of L16 is connected to W+1 through resistor R119.

[0054] Pins 1-3, 5-7, and 9-11 of the MAX3096ESE+T chip U24 are connected to A+1, A-1, ALVC14, BLVC14, B-1, B+1, Z+1, Z-1, and ZLVC14 respectively.

[0055] Pins 1-3, 5-7, and 9-11 of the MAX3096ESE+T chip U23 are respectively connected to W+1, W-1, WLVC14, VLVC14, V-1, V+1, U+1, U-1, and ULVC14;

[0056] Pins 1-8 and 10-13 of the MCP3208T-BI / SL chip U22 are respectively connected to ALVC14, BLVC14, ZLVC14, ULVC14, VLVC14, WLVC14, IU, IV, ADCS1, ADDIN1, ADOUT1, and ADCLK1.

[0057] As another preferred embodiment, the temperature acquisition circuit of the device described in this invention uses the DS18B20+ chip U29, with pin 2 of U29 connected to DSCK.

[0058] Secondly, the vibration acquisition circuit of the device described in this invention includes an SN65HVD12D chip U28. Pin 1 of U28 is connected to COM3_RXD, pins 2 and 3 of U28 are connected to COM3_RTS, pin 4 of U28 is connected to COM3_TXD, pin 7 of U28 is connected to one end of resistor R89 ​​and pin 1 of connector P2, pin 2 of P2 is connected to one end of resistor R123 and pin 6 of U28; the other end of R89 is connected to pin 2 of ACT45B-510-2P-TL003 common mode inductor L24, pin 1 of L24 is connected to the other end of R123; pin 3 of L24 is connected to pin 2 of LH-ST-485 vibration sensor J5, and pin 3 of J5 is connected to pin 4 of L24.

[0059] In addition, the noise acquisition circuit of the device described in this invention includes an SN65HVD12D chip U27. Pin 1 of U27 is connected to COM4_RXD, pins 2 and 3 of U27 are connected to COM4_RTS, pin 4 of U27 is connected to COM4_TXD, pin 7 of U27 is connected to one end of resistor R79 and pin 1 of connector P1, pin 2 of P1 is connected to one end of resistor R122 and pin 6 of U27, the other end of R79 is connected to pin 2 of ACT45B-510-2P-TL003 common mode inductor L23, pin 1 of L23 is connected to the other end of R122, pin 3 of L23 is connected to pin 2 of QL108 noise sensor J4, and pin 3 of J4 is connected to pin 4 of L23.

[0060] The beneficial effects of this invention.

[0061] The environmental temperature and humidity acquisition circuit of this invention can acquire the temperature and humidity of the environment in which the harmonic reducer is used.

[0062] The temperature acquisition circuit of this invention can acquire the operating temperature of the harmonic reducer.

[0063] The vibration acquisition circuit of this invention can collect the working vibration of the harmonic reducer.

[0064] The noise acquisition circuit of this invention can acquire the operating noise of a harmonic reducer.

[0065] The variable storage circuit of this invention can store test environment settings, temperature rise values, vibration values, noise values, and configuration information. Configuration information may include recording frequency, start time, cumulative test time, etc.

[0066] The touch screen control circuit of this invention can be used to view historical data collected for various parameters; view the currently detected temperature rise, vibration, and noise values; set the power and speed of the drive motor; record the time of historical data collection; and output relevant data collection information to a computer.

[0067] This invention allows for the acquisition of data related to the operation of harmonic reducers under high temperature and high humidity environments. Based on this data, a lifespan decay curve of the harmonic reducer can be obtained, enabling the assessment of its lifespan under these conditions. Furthermore, this invention can be used to test the product quality of harmonic reducers. Attached Figure Description

[0068] The present invention will be further described below with reference to the accompanying drawings and specific embodiments. The scope of protection of the present invention is not limited to the following description.

[0069] Figure 1 This is the schematic diagram of the FPGA I / O and auxiliary circuit of this invention.

[0070] Figure 2 , 3 This is the FPGA circuit schematic diagram of the present invention.

[0071] Figure 4 This is a schematic diagram of the variable storage circuit of the present invention.

[0072] Figure 5 This is a schematic diagram of the environmental temperature and humidity acquisition circuit of the present invention.

[0073] Figure 6 This is a schematic diagram of the touch screen control circuit of the present invention.

[0074] Figure 7 , 8 This is a schematic diagram of the motor drive circuit of the present invention.

[0075] Figure 9 This is a schematic diagram of the output control circuit of the device of the present invention.

[0076] Figure 10 This is a schematic diagram of the phase current acquisition circuit of the device of the present invention.

[0077] Figure 11This is a schematic diagram of the motor output angle acquisition circuit of the present invention.

[0078] Figure 12 This is a schematic diagram of the temperature acquisition circuit of the device of the present invention.

[0079] Figure 13 This is a schematic diagram of the vibration acquisition circuit of the device of the present invention.

[0080] Figure 14 This is a schematic diagram of the noise acquisition circuit of the device of the present invention. Detailed Implementation

[0081] As shown in the figure, this invention includes FPGA I / O and auxiliary circuits, FPGA circuit, variable storage circuit, ambient temperature and humidity acquisition circuit, touch screen control circuit, motor drive circuit, device output control circuit, device phase current acquisition circuit, motor output angle acquisition circuit, device temperature acquisition circuit, device vibration acquisition circuit, and device noise acquisition circuit. The power output ports of the IO and auxiliary circuits are connected to the power supply ports of the FPGA circuit, the variable storage circuit, the ambient temperature and humidity acquisition circuit, the touch screen control circuit, the motor drive circuit, the equipment output control circuit, the equipment phase current acquisition circuit, the motor output angle acquisition circuit, the equipment temperature acquisition circuit, the equipment vibration acquisition circuit, and the equipment noise acquisition circuit, respectively. The information transmission ports of the FPGA circuit are connected to the information transmission ports of the variable storage circuit and the touch screen control circuit, respectively. The detection signal input ports of the FPGA circuit are connected to the detection signal output ports of the ambient temperature and humidity acquisition circuit, the equipment phase current acquisition circuit, the motor output angle acquisition circuit, the equipment temperature acquisition circuit, the equipment vibration acquisition circuit, and the equipment noise acquisition circuit, respectively. The control signal output ports of the FPGA circuit are connected to the control signal input ports of the motor drive circuit and the equipment output control circuit, respectively.

[0082] The FPGA IO and auxiliary circuit includes an LM2576-5.0 chip U1. Pin 1 of U1 is connected to one end of inductor L2 and +12V. The other end of L2 is connected to +12V2 and pin 3 of LD05-20B12 chip U2. Pin 2 of U2 is connected to L1C. Pin 1 of U2 is connected to L2C. Pin 4 of U2 is connected to GND2 and one end of inductor L18. The other end of L18 is connected to GND, pin 3 of U1, and pin 5 of U1. Pin 4 of U1 is connected to 5V and one end of inductor L1. The other end of L1 is connected to 5VA.

[0083] Pins 1, 2, and 3 of the TPS62040DGQ chip U5 are connected to 5V. Pins 7 and 8 of U5 are connected to one end of resistor R3 and VCC_1.2V respectively through inductor L20. The other end of R3 is connected to pin 5 of U5 and one end of resistor R7 respectively. The other end of R7 is connected to GND.

[0084] Pins 2 and 3 of the TPS62040DGQ chip U6 are connected to 5V. Pins 7 and 8 of U6 are connected to one end of resistor R5, VCC_3.3V, and one end of inductor L22 through inductor L21. The other end of L22 is connected to A3.3V. The other end of R5 is connected to pin 5 of U6 and one end of resistor R8. The other end of R8 is connected to GND.

[0085] Pin 3 of the AMS1117-2.5 chip U9 is connected to 5V, and pins 2 and 4 of U9 are connected to VCC_2.5V.

[0086] By combining U2, U1, U5, U6, and U9, the required power supply voltage is supplied to each part of the system.

[0087] L1C and L2C are the 220V AC mains input terminals.

[0088] The FPGA circuit uses EP4CE15E22I7 chip U11 and EPCS4SI8N chip U15 (U15 is the external program storage chip of the FPGA). Pin 12 of U11 is connected to FPGA_DCLK through resistor R14. Pins 1, 2, 5, and 6 of U15 are connected to FPGA_nCSO, FPGA_DATA0, FPGA_ASDO, and FPGA_DCLK respectively. Pin 13 of U11 is connected to FPGA_DATA0 through resistor R18. Pins 6 and 8 of U11 are connected to FPGA_ASDO and FPGA_nCSO respectively.

[0089] Pins 58-61, 64-69, 71, and 72 of U11 are connected to OE2, DIR2, OE1, DIR1, and OUT1-OUT8 respectively.

[0090] Pins 76 and 87 of U11 are connected to CPU_VFO and DSCK respectively;

[0091] Pins 110-115, 119-121, and 125 of U11 are connected to CPU_ALM6-CPU_ALM0, ADCLK1, ADOUT1, ADDIN1, and ADCS1 respectively.

[0092] Pins 98-101, 103, and 104 of U11 are connected to COM3_RXD, COM3_RTS, COM3_TXD, COM4_RXD, COM4_RTS, and COM4_TXD respectively.

[0093] Pins 49 to 51 of U11 are connected to WP, SCL, and SDA respectively.

[0094] Pins 132-134, 143, and 144 of U11 are connected to COM1_RXD, COM1_RTS, COM1_TXD, SDAA, and SCLA respectively.

[0095] Pin 135 of U11 is connected to VCC_3.3V via resistor R28 and LED2 in sequence;

[0096] Pin 136 of U11 is connected to VCC_3.3V via resistor R30 and LED3 in sequence;

[0097] Pin 137 of U11 is connected to VCC_3.3V via resistor R33 and LED4.

[0098] LED2 is the operation indicator. LED3 is the overcurrent, overvoltage, and phase loss indicator. LED4 is the temperature rise, noise, and vibration over-set value indicator.

[0099] The variable storage circuit uses the FM24V02-GTR chip U20, with pins 5 to 7 of U20 connected to SDA, SCL, and WP respectively.

[0100] The ambient temperature and humidity acquisition circuit uses the SHT30-DIS-B10KS chip U25, with pins 1 and 4 of U25 connected to SDAA and SCLA respectively. The harmonic reducer under test can be placed in a constant temperature and humidity control box, along with the temperature sensor, to accurately acquire the ambient temperature and humidity of the harmonic reducer's operating environment.

[0101] By configuring the constant temperature and humidity control box, the operating parameters of the harmonic reducer can be tested under different environments.

[0102] For example, the service life and operational stability degradation of a harmonic reducer under harsh environmental conditions can be tested at 25℃ and 60% humidity; similarly, the service life and operational stability degradation can be tested at 30℃ and 60% humidity. Under a specific test environment and with a certain load, the harmonic reducer is continuously operated until the end of its service life. The temperature, humidity, vibration, and noise levels throughout the operation are recorded. By analyzing the charts generated from these indicators, the service life and the onset time of characteristic degradation can be determined, thus identifying the extreme values ​​of the harmonic reducer under harsh environmental conditions and the quality of the reducer.

[0103] The touchscreen control circuit uses the SN65HVD12D chip U26. Pin 1 of U26 is connected to COM1_RXD, pins 2 and 3 of U26 are connected to COM1_RTS, and pins 4, 6, and 7 of U26 are connected to COM1_TXD, 485-A, and 485-B respectively.

[0104] Communication between the touchscreen and the FPGA is achieved through the 485-A and 485-B terminals.

[0105] The motor drive circuit includes a TAS50-15-W module U3. Pin 1 of U3 is connected to pin 2 of common mode inductor L14. Pin 1 of L14 is connected to L1C through thermistor TH1. Pin 4 of L14 is connected to L2C. Pin 3 of L14 is connected to pin 2 of U3. Pin 5 of U3 is connected to N1. Pin 9 of U3 is connected to pin 3 of 15V and UMW78L05 module U41 through inductor L17. Pin 1 of U41 is connected to F5V.

[0106] The collector of the output terminal of the TLP521-1XSM chip U42 is connected to ALM4, the emitter of the output terminal of U42 is grounded, the cathode of the input terminal of U42 is connected to N1, and the anode of the input terminal of U42 is connected to the cathodes of diodes D3, D4, and D5 in sequence through Zener diode D2 and resistor R37. The anode of D3 is connected to L1, the anode of D4 is connected to L2, and the anode of D5 is connected to L3. Pins 2 to 4 of DB1 of the D30XT80-7000 module are connected to L1 to L3 respectively.

[0107] Pin 1 of DB1 is connected to P1, and pin 5 of DB1 is connected to N1. P2 is connected via fuse FU1 to one end of thermistor TH2, pin 7 of JQC-3FF / 005-1HS relay RY1, and pin 8 of RY1. The other end of TH2 is connected to pin 5 of RY1, pin 6 of RY1, the anode of LED LD1, pin 1 of connector CN2, and DCPIN. Pin 2 of CN2 is connected to B3. The cathode of LD1 is connected via resistors R44 and R45 to... One end of resistor R47 is connected to MT3. The other end of R47 is connected to one end of resistor R49 and MT2. The other end of R49 is connected to one end of resistor R54 and MT1. The other end of R54 is connected to N1. The anode of D20 is connected to B, one end of resistor R48, and pin 2 of IRG4BC30V transistor IG1. The other end of R48 is connected to one end of resistor R55 and MT4. The other end of R55 is connected to N1. Pin 1 of IG1 is connected to QCTR1. Pin 3 of IG1 is connected to N1.

[0108] Pins 3 and 4 of RY1 are connected to the anodes of diodes D17, D18, and D19 respectively via resistor R40. The cathode of D17 is connected to W and pin 24 of the FNB34060T module respectively. The cathode of D18 is connected to V and one end of resistor R10, and the other end of R10 is connected to V- and pin 25 of the FNB34060T module respectively. The cathode of D19 is connected to U and one end of resistor R9, and the other end of R9 is connected to U- and pin 26 of the FNB34060T module respectively. Pin 27 of the FNB34060T module is connected to DCPIN.

[0109] Pins 21 to 23 of the FNB34060T module are connected to the UCSC via resistor R58;

[0110] Pins 17, 20, 13, 16, 9, 12, 8, and 6-2 of the FNB34060T module are connected to WP, N1, VP, N1, UP, N1, UCSC, VFO, WN, VN, UN, and N1 respectively.

[0111] The collector of the output terminal of the TLP521-1 chip PC1 is connected to CPU_VFO, the cathode of the input terminal of PC1 is connected to N1, and the anode of the input terminal of PC1 is connected to VFO through resistor R19.

[0112] Pin 2 of the ADR291FRZ chip U4 is connected to 15V through resistor R39, and pin 6 of U4 is connected to VREF.

[0113] Pin 3 of LM2903DR2G chip U7 is connected to VREF, pin 2 of U7 is connected to MT1, pin 1 of U7 is connected to the cathode of the PC9 input terminal of TLP521-1 chip through resistor R41, the anode of the PC9 input terminal is connected to 15V, the collector of the PC9 output terminal is connected to ALM2, and the emitter of the PC9 output terminal is grounded.

[0114] Pin 3 of the LM2903DR2G chip U8 is connected to MT3, pin 2 of U8 is connected to VREF, pin 1 of U8 is connected to the cathode of the PC10 input terminal of the TLP521-1 chip through resistor R43, the anode of the PC10 input terminal is connected to 15V, the collector of the PC10 output terminal is connected to ALM0, and the emitter of the PC10 output terminal is grounded.

[0115] Pin 3 of LM2903DR2G chip U10 is connected to MT4, pin 2 of U10 is connected to VREF, pin 1 of U10 is connected to the cathode of the PC11 input terminal of TLP521-1 chip through resistor R46, the anode of the PC11 input terminal is connected to 15V, the collector of the PC11 output terminal is connected to ALM6, and the emitter of the PC11 output terminal is grounded.

[0116] Pin 3 of the LM2903DR2G chip U13 is connected to VREF through resistor R57. Pin 2 of U13 is connected to MT2. Pin 1 of U13 is connected to the cathode of the PC12 input terminal of the TLP521-1 chip. The anode of the PC12 input terminal is connected to one end of resistor R53 and one end of resistor R56 respectively. The other end of R53 is connected to 15V. The other end of R56 is connected to pin 4 of U13. Pin 8 of U13 is connected to N1. The collector of the PC12 output terminal is connected to ALM5, and the emitter of the PC12 output terminal is grounded.

[0117] Pins 1, 3-5, 7-9, 12-14, and 16-19 of the SN74HCT245N chip U16 are respectively connected to DIR2, ALM6-ALM4, ALM2-ALM0, CPU_ALM0-CPU_ALM2, and CPU_ALM4-CPU_ALM6.

[0118] U3 provides the necessary power voltage to each part of the motor drive circuit.

[0119] U4 is used to provide a 2.5V reference power source.

[0120] Generate a 2.5V reference voltage VREF, which is used to compare the voltage with U7, U8, U10, and U13 to detect voltage status, such as undervoltage or overvoltage.

[0121] The self-test fault signal of FNB34060T is sent to FPGA after being isolated by PC1.

[0122] L1, L2, and L3 are the three-phase power input terminals.

[0123] P1 and P2 are used for external switches. In case of emergency shutdown, manually turn off the switches.

[0124] The external resistor CN2 is used to dissipate the brake power supply during braking.

[0125] U42 is the phase loss detection section. When all three phases are normal, U42 conducts. After a phase loss, the voltage is low, and U42 cannot conduct, sending an alarm signal to the FPGA circuit via ALM4. A phase loss will cause the DC bus voltage to be too low, resulting in overcurrent in the FNB34060T.

[0126] Phase loss is a relatively serious power failure.

[0127] RY1 is used for surge protection; it can also immediately stop the motor rotation when braking.

[0128] MT1 is used for undervoltage monitoring. MT2 is used to detect the termination of surge protection. MT3 is used for overvoltage protection. MT4 is used for brake discharge release depth and voltage control.

[0129] U7, U8, U10, and U13 are voltage comparators used for comparison with a reference voltage. They work in conjunction with the optocoupler at the back end to achieve isolated voltage detection.

[0130] The FNB34060T is an IPM module that encapsulates six switching transistors together to drive a three-phase bridge.

[0131] IN(UL): Signal input for low-side U phase. IN(VL): Signal input for low-side V phase. IN(WL): Signal input for low-side W phase. VFO: Fault output. IN(UH): Signal input for high-side U phase. IN(VH): Signal input for high-side V phase. IN(WH): Signal input for high-side W phase. U: U phase output. V: V phase output. W: W phase output. "Low side" and "high side" are common industry terms, referring to one end of the switching transistor and the other end. UCSC: Short circuit detection. The output current of the U, W, and V phases flows through resistors R61 and R59, generating a voltage to the CSC pin. Detecting this voltage yields the current value for short circuit protection.

[0132] U16 is used for level conversion to adapt to the voltage requirements of different components.

[0133] The output control circuit of the device includes an NPN transistor Q1. The collector of Q1 is connected to pin 2 of the JQC-3FF / 005-1HS relay RY1. Pin 1 of RY1 is connected to 5V. The base of Q1 is connected to CTR8 through resistor R69. The emitter of Q1 is grounded.

[0134] Pin 1 of FOD8314 chip U18 is connected to 5V, pin 3 of U18 is connected to CTR7 through resistor R63, and pin 5 of U18 is connected to QCTR1 through resistor R62.

[0135] The TLP521-1 chip's PC4 input anode is connected to CTR2 via resistor R2, the PC4 input cathode is connected to CTR1 via resistor R6, the PC4 output collector is connected to 15V via resistor R24, and the PC4 output emitter is connected to UP.

[0136] The TLP521-1 chip's PC7 input anode is connected to CTR1 via resistor R52, the PC7 input cathode is connected to CTR2 via resistor R65, the PC7 output collector is connected to 15V via resistor R51, and the PC7 output emitter is connected to UN.

[0137] The TLP521-1 chip's PC3 input anode is connected to CTR4 via resistor R23, the PC3 input cathode is connected to CTR3 via resistor R26, the PC3 output collector is connected to 15V via resistor R21, and the PC3 output emitter is connected to VP.

[0138] The TLP521-1 chip's PC6 input anode is connected to CTR3 via resistor R50, the PC6 input cathode is connected to CTR4 via resistor R64, the PC6 output collector is connected to 15V via resistor R35, and the PC6 output emitter is connected to VN.

[0139] The TLP521-1 chip's PC2 input anode is connected to CTR6 via resistor R22, the PC2 input cathode is connected to CTR5 via resistor R25, the PC2 output collector is connected to 15V via resistor R20, and the PC2 output emitter is connected to WP.

[0140] The TLP521-1 chip's PC5 input anode is connected to CTR5 via resistor R36, the PC5 input cathode is connected to CTR6 via resistor R60, the PC5 output collector is connected to 15V via resistor R34, and the PC5 output emitter is connected to WN.

[0141] Pins 1-9 and 11-19 of the SN74HCT245N chip U21 are connected to DIR1, CTR1-CTR8, OUT8-OUT1, and OE1 respectively.

[0142] The FPGA outputs a 3-phase bridge drive signal, which is shaped and level-converted by U21, and then connected to the FNB34060T via optocoupler isolation. QCTR1 is used for level shaping and conversion to make the drive waveform steeper.

[0143] The phase current acquisition circuit of the device includes an HCPL-7840-360E chip U17. Pin 2 of U17 is connected to U through resistor R29, pin 3 of U17 is connected to U- through resistor R32, and pins 6 and 7 of U17 are connected to IU- and IU+ respectively.

[0144] The HCPL-7840-360E chip U19 has pin 2 connected to V through resistor R27, pin 3 connected to V- through resistor R31, and pins 6 and 7 connected to IV- and IV+ respectively.

[0145] Pin 6 of the AD8602ARZ chip U12 is connected to IV- through resistor R74, pin 5 of U12 is connected to IV+ through resistor R77, pin 5 of U12 is connected to pins 1 and 2 of U12 through resistor R78, pin 3 of U12 is connected to VCC_1.2V, and pin 7 of U12 is connected to IV through resistor R75.

[0146] Pin 2 of the AD8602ARZ chip U14 is connected to IU- through resistor R82, pin 3 of U14 is connected to IU+ through resistor R86, pin 3 of U14 is connected to pins 6 and 7 of U14 through resistor R94, pin 5 of U14 is connected to VCC_1.2U, and pin 1 of U14 is connected to IU through resistor R83.

[0147] The device's phase current acquisition circuit promptly detects imbalances or phase loss in the three-phase output current, preventing damage to the output equipment. IU and IV are sent to the FPGA via U22.

[0148] Two-phase currents are obtained through resistors R9 and R10 (current-to-voltage conversion), and then through differential signal isolation amplifiers U17 and U19 to obtain isolated differential voltage values. Finally, U12 and U14 convert the differential signal into a single-ended signal. U12A and U14B raise the detection voltage point by 1.2V for the single-ended signal, improving detection accuracy.

[0149] The motor output angle acquisition circuit includes a magnetic ring L3, one end of which is connected to BA-, and the other end of which is connected to A-1 through a resistor R87; one end of the magnetic ring L5 is connected to BA+, and the other end of which is connected to A+1 through a resistor R95.

[0150] One end of magnetic ring L7 is connected to BB-, and the other end of L7 is connected to B-1 through resistor R104; one end of magnetic ring L9 is connected to BB+, and the other end of L9 is connected to B+1 through resistor R108.

[0151] One end of magnetic ring L11 is connected to BZ-, and the other end of L11 is connected to Z-1 through resistor R114; one end of magnetic ring L15 is connected to BZ+, and the other end of L15 is connected to Z+1 through resistor R118.

[0152] One end of magnetic ring L4 is connected to BU-, and the other end of L4 is connected to U-1 through resistor R88; one end of magnetic ring L6 is connected to BU+, and the other end of L6 is connected to U+1 through resistor R96.

[0153] One end of magnetic ring L8 is connected to BV-, and the other end of L8 is connected to V-1 through resistor R105; one end of magnetic ring L10 is connected to BV+, and the other end of L10 is connected to V+1 through resistor R109.

[0154] One end of magnetic ring L12 is connected to BW-, and the other end of L12 is connected to W-1 through resistor R115; one end of magnetic ring L16 is connected to BW+, and the other end of L16 is connected to W+1 through resistor R119.

[0155] Pins 1-3, 5-7, and 9-11 of the MAX3096ESE+T chip U24 are connected to A+1, A-1, ALVC14, BLVC14, B-1, B+1, Z+1, Z-1, and ZLVC14 respectively.

[0156] Pins 1-3, 5-7, and 9-11 of the MAX3096ESE+T chip U23 are respectively connected to W+1, W-1, WLVC14, VLVC14, V-1, V+1, U+1, U-1, and ULVC14;

[0157] Pins 1-8 and 10-13 of the MCP3208T-BI / SL chip U22 are respectively connected to ALVC14, BLVC14, ZLVC14, ULVC14, VLVC14, WLVC14, IU, IV, ADCS1, ADDIN1, ADOUT1, and ADCLK1.

[0158] J2 is the encoder interface for connecting to the motor and acquiring the motor angle. It includes two rotary encoders: the first rotary encoder corresponds to ports A, B, and Z, and the second rotary encoder corresponds to ports U, V, and W. Differential signal detection is performed using two sets of rotary encoders to improve measurement accuracy.

[0159] A rotary encoder is used to measure the angle of the motor output shaft.

[0160] The change value is measured, and the angle is measured by a rotary encoder, resulting in high measurement accuracy.

[0161] If A goes high first, then B goes high, it indicates clockwise rotation. If B goes high first, then A goes high, it indicates counterclockwise rotation. Z is used to detect the number of revolutions; Z goes high once for each revolution.

[0162] U23 and U24 convert differential inputs into single-ended outputs, providing high differential detection accuracy and strong anti-interference capabilities. U17 and U18 convert differential signals into single-ended signals required by processor U1.

[0163] U22 is an 8-channel ADC conversion circuit that converts detected analog signals into digital signals and sends them to the FPGA.

[0164] U+, U-, V+, V-, W+, W-: These wires are used to connect the encoder and the servo drive's synchronization signals. In servo systems, multiple encoders are used to provide higher accuracy and stability. U, V, and W represent different encoders, and + and - represent positive and negative polarities.

[0165] The temperature acquisition circuit of the device uses a DS18B20+ chip U29, with pin 2 of U29 connected to DSCK. The temperature sensor is located on the non-rotating part of the harmonic reducer.

[0166] The vibration acquisition circuit of the device includes an SN65HVD12D chip U28. Pin 1 of U28 is connected to COM3_RXD, pins 2 and 3 of U28 are connected to COM3_RTS, pin 4 of U28 is connected to COM3_TXD, pin 7 of U28 is connected to one end of resistor R89 ​​and pin 1 of connector P2, pin 2 of P2 is connected to one end of resistor R123 and pin 6 of U28, the other end of R89 is connected to pin 2 of ACT45B-510-2P-TL003 common mode inductor L24, pin 1 of L24 is connected to the other end of R123, pin 3 of L24 is connected to pin 2 of LH-ST-485 vibration sensor J5, and pin 3 of J5 is connected to pin 4 of L24.

[0167] The vibration sensor is installed on the non-rotating part of the harmonic reducer.

[0168] P2 is the connector used for debugging.

[0169] U28 is an RS485 communication chip used to connect to a vibration sensor.

[0170] The noise acquisition circuit of the device includes an SN65HVD12D chip U27. Pin 1 of U27 is connected to COM4_RXD, pins 2 and 3 of U27 are connected to COM4_RTS, pin 4 of U27 is connected to COM4_TXD, pin 7 of U27 is connected to one end of resistor R79 and pin 1 of connector P1, pin 2 of P1 is connected to one end of resistor R122 and pin 6 of U27, the other end of R79 is connected to pin 2 of ACT45B-510-2P-TL003 common mode inductor L23, pin 1 of L23 is connected to the other end of R122, pin 3 of L23 is connected to pin 2 of QL108 noise sensor J4, and pin 3 of J4 is connected to pin 4 of L23.

[0171] The noise sensor is installed on the non-rotating part of the harmonic reducer under test to capture the noise signal of the harmonic reducer, determine the strength of the noise signal, and determine the operating status of the harmonic reducer.

[0172] P1 is the connector used for debugging.

[0173] U27 is an RS485 communication chip used to connect to a noise sensor.

[0174] In this invention, both detection and driving are performed by FPGA. In order to detect sudden conditions as soon as possible, when slight vibration, noise, or temperature rise occurs, the rotation speed can be increased immediately to eliminate the possibility of misjudgment and confirm whether the vibration, noise, and temperature rise are proportional to the same frequency. If they are proportional to the same frequency, it can be confirmed that the signal is emitted by the harmonic reducer, thus improving the accuracy of detection.

[0175] It is understood that the above specific description of the present invention is only for illustrating the present invention and is not limited to the technical solutions described in the embodiments of the present invention. Those skilled in the art should understand that modifications or equivalent substitutions can still be made to the present invention to achieve the same technical effect; as long as the use needs are met, they are all within the protection scope of the present invention.

Claims

1. A lifespan monitoring system for harmonic reducers under high temperature and high humidity environments, comprising FPGA I / O and auxiliary circuits, FPGA circuits, variable storage circuits, ambient temperature and humidity acquisition circuits, touch screen control circuits, motor drive circuits, equipment output control circuits, equipment phase current acquisition circuits, motor output angle acquisition circuits, equipment temperature acquisition circuits, equipment vibration acquisition circuits, and equipment noise acquisition circuits, characterized in that... The power output ports of the FPGA IO and auxiliary circuits are connected to the power supply ports of the FPGA circuit, the variable storage circuit, the ambient temperature and humidity acquisition circuit, the touch screen control circuit, the motor drive circuit, the equipment output control circuit, the equipment phase current acquisition circuit, the motor output angle acquisition circuit, the equipment temperature acquisition circuit, the equipment vibration acquisition circuit, and the equipment noise acquisition circuit, respectively. The information transmission ports of the FPGA circuit are connected to the information transmission ports of the variable storage circuit and the touch screen control circuit, respectively. The detection signal input ports of the FPGA circuit are connected to the detection signal output ports of the ambient temperature and humidity acquisition circuit, the equipment phase current acquisition circuit, the motor output angle acquisition circuit, the equipment temperature acquisition circuit, the equipment vibration acquisition circuit, and the equipment noise acquisition circuit, respectively. The control signal output ports of the FPGA circuit are connected to the control signal input ports of the motor drive circuit and the equipment output control circuit, respectively. The motor drive circuit includes a TAS50-15-W module U3. Pin 1 of U3 is connected to pin 2 of common mode inductor L14. Pin 1 of L14 is connected to L1C through thermistor TH1. Pin 4 of L14 is connected to L2C. Pin 3 of L14 is connected to pin 2 of U3. Pin 5 of U3 is connected to N1. Pin 9 of U3 is connected to pin 3 of 15V and UMW78L05 module U41 through inductor L17. Pin 1 of U41 is connected to F5V. The collector of the output terminal of the TLP521-1XSM chip U42 is connected to ALM4, the emitter of the output terminal of U42 is grounded, the cathode of the input terminal of U42 is connected to N1, and the anode of the input terminal of U42 is connected to the cathodes of diodes D3, D4, and D5 in sequence through Zener diode D2 and resistor R37. The anode of D3 is connected to L1, the anode of D4 is connected to L2, and the anode of D5 is connected to L3. Pins 2 to 4 of DB1 of the D30XT80-7000 module are connected to L1 to L3 respectively. Pin 1 of DB1 is connected to P1, pin 5 of DB1 is connected to N1, and P2 is connected to one end of the thermistor TH2, pin 7 of JQC-3FF / 005-1HS relay RY1, and pin 8 of RY1 via fuse FU1. The other end of TH2 is connected to pin 5 of RY1, pin 6 of RY1, the anode of LED LD1, pin 1 of connector CN2, and DCPIN. Pin 2 of CN2 is connected to B3. The cathode of LD1 is connected to resistors R44 and R45 respectively. One end of resistor R47 is connected to MT3. The other end of R47 is connected to one end of resistor R49 and MT2. The other end of R49 is connected to one end of resistor R54 and MT1. The other end of R54 is connected to N1. The anode of D20 is connected to B, one end of resistor R48, and pin 2 of IRG4BC30V transistor IG1. The other end of R48 is connected to one end of resistor R55 and MT4. The other end of R55 is connected to N1. Pin 1 of IG1 is connected to QCTR1. Pin 3 of IG1 is connected to N1. Pins 3 and 4 of RY1 are connected to the anodes of diodes D17, D18, and D19 respectively via resistor R40. The cathode of D17 is connected to W and pin 24 of the FNB34060T module respectively. The cathode of D18 is connected to V and one end of resistor R10, and the other end of R10 is connected to V- and pin 25 of the FNB34060T module respectively. The cathode of D19 is connected to U and one end of resistor R9, and the other end of R9 is connected to U- and pin 26 of the FNB34060T module respectively. Pin 27 of the FNB34060T module is connected to DCPIN. Pins 21-23 of the FNB34060T module are connected to the UCSC via resistor R58; Pins 17, 20, 13, 16, 9, 12, 8, and 6-2 of the FNB34060T module are connected to WP, N1, VP, N1, UP, N1, UCSC, VFO, WN, VN, UN, and N1 respectively. The collector of the PC1 output terminal of the TLP521-1 chip is connected to CPU_VFO, the cathode of the PC1 input terminal is connected to N1, and the anode of the PC1 input terminal is connected to VFO through resistor R19. Pin 2 of the ADR291FRZ chip U4 is connected to 15V through resistor R39, and pin 6 of U4 is connected to VREF. Pin 3 of LM2903DR2G chip U7 is connected to VREF, pin 2 of U7 is connected to MT1, pin 1 of U7 is connected to the cathode of the PC9 input terminal of TLP521-1 chip through resistor R41, the anode of the PC9 input terminal is connected to 15V, the collector of the PC9 output terminal is connected to ALM2, and the emitter of the PC9 output terminal is grounded. Pin 3 of the LM2903DR2G chip U8 is connected to MT3, pin 2 of U8 is connected to VREF, pin 1 of U8 is connected to the cathode of the PC10 input terminal of the TLP521-1 chip through resistor R43, the anode of the PC10 input terminal is connected to 15V, the collector of the PC10 output terminal is connected to ALM0, and the emitter of the PC10 output terminal is grounded. Pin 3 of LM2903DR2G chip U10 is connected to MT4, pin 2 of U10 is connected to VREF, pin 1 of U10 is connected to the cathode of the PC11 input terminal of TLP521-1 chip through resistor R46, the anode of the PC11 input terminal is connected to 15V, the collector of the PC11 output terminal is connected to ALM6, and the emitter of the PC11 output terminal is grounded. Pin 3 of the LM2903DR2G chip U13 is connected to VREF through resistor R57. Pin 2 of U13 is connected to MT2. Pin 1 of U13 is connected to the cathode of the PC12 input terminal of the TLP521-1 chip. The anode of the PC12 input terminal is connected to one end of resistor R53 and one end of resistor R56 respectively. The other end of R53 is connected to 15V. The other end of R56 is connected to pin 4 of U13. Pin 8 of U13 is connected to N1. The collector of the PC12 output terminal is connected to ALM5, and the emitter of the PC12 output terminal is grounded. Pins 1, 3-5, 7-9, 12-14, and 16-19 of the SN74HCT245N chip U16 are respectively connected to DIR2, ALM6-ALM4, ALM2-ALM0, CPU_ALM0-CPU_ALM2, and CPU_ALM4-CPU_ALM6.

2. The system for testing the service life of a harmonic reducer under high temperature and high humidity conditions according to claim 1, characterized in that... The FPGA IO and auxiliary circuit includes an LM2576-5.0 chip U1. Pin 1 of U1 is connected to one end of inductor L2 and +12V. The other end of L2 is connected to +12V2 and pin 3 of LD05-20B12 chip U2. Pin 2 of U2 is connected to L1C. Pin 1 of U2 is connected to L2C. Pin 4 of U2 is connected to GND2 and one end of inductor L18. The other end of L18 is connected to GND, pin 3 of U1, and pin 5 of U1. Pin 4 of U1 is connected to 5V and one end of inductor L1. The other end of L1 is connected to 5VA. Pins 1, 2, and 3 of the TPS62040DGQ chip U5 are connected to 5V. Pins 7 and 8 of U5 are connected to one end of resistor R3 and VCC_1.2V respectively through inductor L20. The other end of R3 is connected to pin 5 of U5 and one end of resistor R7 respectively. The other end of R7 is connected to GND. Pins 2 and 3 of the TPS62040DGQ chip U6 are connected to 5V. Pins 7 and 8 of U6 are connected to one end of resistor R5, VCC_3.3V, and one end of inductor L22 through inductor L21. The other end of L22 is connected to A3.3V. The other end of R5 is connected to pin 5 of U6 and one end of resistor R8. The other end of R8 is connected to GND. Pin 3 of the AMS1117-2.5 chip U9 is connected to 5V, and pins 2 and 4 of U9 are connected to VCC_2.5V.

3. The system for testing the service life of a harmonic reducer under high temperature and high humidity conditions according to claim 1, characterized in that... The FPGA circuit uses EP4CE15E22I7 chip U11 and EPCS4SI8N chip U15. Pin 12 of U11 is connected to FPGA_DCLK through resistor R14. Pins 1, 2, 5, and 6 of U15 are connected to FPGA_nCSO, FPGA_DATA0, FPGA_ASDO, and FPGA_DCLK respectively. Pin 13 of U11 is connected to FPGA_DATA0 through resistor R18. Pins 6 and 8 of U11 are connected to FPGA_ASDO and FPGA_nCSO respectively. Pins 58-61, 64-69, 71, and 72 of U11 are connected to OE2, DIR2, OE1, DIR1, and OUT1-OUT8 respectively. Pins 76 and 87 of U11 are connected to CPU_VFO and DSCK respectively; Pins 110-115, 119-121, and 125 of U11 are connected to CPU_ALM6-CPU_ALM0, ADCLK1, ADOUT1, ADDIN1, and ADCS1 respectively. Pins 98-101, 103, and 104 of U11 are connected to COM3_RXD, COM3_RTS, COM3_TXD, COM4_RXD, COM4_RTS, and COM4_TXD respectively. Pins 49 to 51 of U11 are connected to WP, SCL, and SDA respectively. Pins 132-134, 143, and 144 of U11 are connected to COM1_RXD, COM1_RTS, COM1_TXD, SDAA, and SCLA respectively. Pin 135 of U11 is connected to VCC_3.3V via resistor R28 and LED2 in sequence; Pin 136 of U11 is connected to VCC_3.3V via resistor R30 and LED3 in sequence; Pin 137 of U11 is connected to VCC_3.3V via resistor R33 and LED4.

4. The system for testing the service life of a harmonic reducer under high temperature and high humidity conditions according to claim 1, characterized in that... The variable storage circuit uses the FM24V02-GTR chip U20, with pins 5 to 7 of U20 connected to SDA, SCL, and WP respectively.

5. The system for testing the service life of a harmonic reducer under high temperature and high humidity conditions according to claim 1, characterized in that... The ambient temperature and humidity acquisition circuit uses the SHT30-DIS-B10KS chip U25, with pins 1 and 4 of U25 connected to SDAA and SCLA respectively.

6. The system for detecting the service life of a harmonic reducer under high temperature and high humidity conditions according to claim 1, characterized in that... The output control circuit of the device includes an NPN transistor Q1. The collector of Q1 is connected to pin 2 of the JQC-3FF / 005-1HS relay RY1. Pin 1 of RY1 is connected to 5V. The base of Q1 is connected to CTR8 through resistor R69. The emitter of Q1 is grounded. Pin 1 of FOD8314 chip U18 is connected to 5V, pin 3 of U18 is connected to CTR7 through resistor R63, and pin 5 of U18 is connected to QCTR1 through resistor R62. The TLP521-1 chip's PC4 input anode is connected to CTR2 via resistor R2, the PC4 input cathode is connected to CTR1 via resistor R6, the PC4 output collector is connected to 15V via resistor R24, and the PC4 output emitter is connected to UP. The TLP521-1 chip's PC7 input anode is connected to CTR1 via resistor R52, the PC7 input cathode is connected to CTR2 via resistor R65, the PC7 output collector is connected to 15V via resistor R51, and the PC7 output emitter is connected to UN. The TLP521-1 chip's PC3 input anode is connected to CTR4 via resistor R23, the PC3 input cathode is connected to CTR3 via resistor R26, the PC3 output collector is connected to 15V via resistor R21, and the PC3 output emitter is connected to VP. The TLP521-1 chip's PC6 input anode is connected to CTR3 via resistor R50, the PC6 input cathode is connected to CTR4 via resistor R64, the PC6 output collector is connected to 15V via resistor R35, and the PC6 output emitter is connected to VN. The TLP521-1 chip's PC2 input anode is connected to CTR6 via resistor R22, the PC2 input cathode is connected to CTR5 via resistor R25, the PC2 output collector is connected to 15V via resistor R20, and the PC2 output emitter is connected to WP. The TLP521-1 chip's PC5 input anode is connected to CTR5 via resistor R36, the PC5 input cathode is connected to CTR6 via resistor R60, the PC5 output collector is connected to 15V via resistor R34, and the PC5 output emitter is connected to WN. Pins 1-9 and 11-19 of the SN74HCT245N chip U21 are connected to DIR1, CTR1-CTR8, OUT8-OUT1, and OE1 respectively.

7. The system for testing the service life of a harmonic reducer under high temperature and high humidity conditions according to claim 1, characterized in that... The phase current acquisition circuit of the device includes an HCPL-7840-360E chip U17. Pin 2 of U17 is connected to U through resistor R29, pin 3 of U17 is connected to U- through resistor R32, and pins 6 and 7 of U17 are connected to IU- and IU+ respectively. The HCPL-7840-360E chip U19 has pin 2 connected to V through resistor R27, pin 3 connected to V- through resistor R31, and pins 6 and 7 connected to IV- and IV+ respectively. Pin 6 of the AD8602ARZ chip U12 is connected to IV- through resistor R74, pin 5 of U12 is connected to IV+ through resistor R77, pin 5 of U12 is connected to pins 1 and 2 of U12 through resistor R78, pin 3 of U12 is connected to VCC_1.2V, and pin 7 of U12 is connected to IV through resistor R75. Pin 2 of the AD8602ARZ chip U14 is connected to IU- through resistor R82, pin 3 of U14 is connected to IU+ through resistor R86, pin 3 of U14 is connected to pins 6 and 7 of U14 through resistor R94, pin 5 of U14 is connected to VCC_1.2U, and pin 1 of U14 is connected to IU through resistor R83.

8. The system for detecting the service life of a harmonic reducer under high temperature and high humidity conditions according to claim 1, characterized in that... The motor output angle acquisition circuit includes a magnetic ring L3, one end of which is connected to BA-, and the other end of which is connected to A-1 through a resistor R87; one end of the magnetic ring L5 is connected to BA+, and the other end of which is connected to A+1 through a resistor R95. One end of magnetic ring L7 is connected to BB-, and the other end of L7 is connected to B-1 through resistor R104; one end of magnetic ring L9 is connected to BB+, and the other end of L9 is connected to B+1 through resistor R108. One end of magnetic ring L11 is connected to BZ-, and the other end of L11 is connected to Z-1 through resistor R114; one end of magnetic ring L15 is connected to BZ+, and the other end of L15 is connected to Z+1 through resistor R118. One end of magnetic ring L4 is connected to BU-, and the other end of L4 is connected to U-1 through resistor R88; one end of magnetic ring L6 is connected to BU+, and the other end of L6 is connected to U+1 through resistor R96. One end of magnetic ring L8 is connected to BV-, and the other end of L8 is connected to V-1 through resistor R105; one end of magnetic ring L10 is connected to BV+, and the other end of L10 is connected to V+1 through resistor R109. One end of magnetic ring L12 is connected to BW-, and the other end of L12 is connected to W-1 through resistor R115; one end of magnetic ring L16 is connected to BW+, and the other end of L16 is connected to W+1 through resistor R119. Pins 1-3, 5-7, and 9-11 of the MAX3096ESE+T chip U24 are connected to A+1, A-1, ALVC14, BLVC14, B-1, B+1, Z+1, Z-1, and ZLVC14 respectively. Pins 1-3, 5-7, and 9-11 of the MAX3096ESE+T chip U23 are respectively connected to W+1, W-1, WLVC14, VLVC14, V-1, V+1, U+1, U-1, and ULVC14; Pins 1-8 and 10-13 of the MCP3208T-BI / SL chip U22 are respectively connected to ALVC14, BLVC14, ZLVC14, ULVC14, VLVC14, WLVC14, IU, IV, ADCS1, ADDIN1, ADOUT1, and ADCLK1.

9. The system for detecting the service life of a harmonic reducer under high temperature and high humidity conditions according to claim 1, characterized in that... The vibration acquisition circuit of the device includes an SN65HVD12D chip U28. Pin 1 of U28 is connected to COM3_RXD, pins 2 and 3 of U28 are connected to COM3_RTS, pin 4 of U28 is connected to COM3_TXD, pin 7 of U28 is connected to one end of resistor R89 ​​and pin 1 of connector P2, pin 2 of P2 is connected to one end of resistor R123 and pin 6 of U28, the other end of R89 is connected to pin 2 of ACT45B-510-2P-TL003 common mode inductor L24, pin 1 of L24 is connected to the other end of R123, pin 3 of L24 is connected to pin 2 of LH-ST-485 vibration sensor J5, and pin 3 of J5 is connected to pin 4 of L24.

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