Optimization method for obtaining the shortest flying line path, electronic device and storage medium

Abstract

The present invention relates to the technical field of EDA, and in particular to an optimization method, electronic device and storage medium for obtaining the shortest flying line path, which applies for memory space according to the number of flying lines connecting any two nodes; obtains a target ordered flying line group according to a node and an SM, and the target flying line group is sorted according to the flying line length to obtain a target ordered flying line group; traverses the flying line length in sequence and processes it according to the order of elements in the target ordered flying line group to obtain the shortest flying line path; wherein the acquisition step of the ordered flying line group includes: obtaining an intermediate reference value ref; traversing all nodes to calculate the flying line length between any two nodes, when the flying line length is less than ref, the flying line length is sequentially saved in the positive order of the memory space to obtain the target flying line group; when the flying line length is greater than ref, it is sequentially saved in the reverse order of the memory space to obtain a candidate flying line group. The method provided by the present invention improves the efficiency of obtaining the shortest flying line path.

Description

Technical Field

[0001] The present invention relates to the technical field of EDA, and in particular to an optimization method for obtaining the shortest flying wire path, an electronic device and a storage medium. Background Art

[0002] When designing a chip, it is sometimes necessary to use flying line visualization to view the position distribution of pins with the same network name in mature components, so as to adjust the layout of other components, such as the placement of other components, whether they need to be flipped or rotated, etc. to adjust the layout; sometimes it is also necessary to use flying line visualization to view or verify the position distribution of pins with the same network in components in the design stage. Some unreasonable pin positions can be quickly observed, which is convenient for adjusting the pin position distribution inside the component.

[0003] At present, the existing technology generates the shortest path through a greedy algorithm, that is, finding another node Pk closest to the current node, and then finding another node closest to the current node again with Pk as the current node, and so on. The greedy algorithm can ensure that the flying line between two adjacent nodes is the shortest, but it cannot ensure that the final flying line path is the shortest. Therefore, a method that can generate the shortest flying line path is urgently needed. Summary of the invention

[0004] In view of the above technical problems, the technical solution adopted by the present invention is: an optimization method for obtaining the shortest flying line path, the method comprising:

[0005] P200, apply for memory space according to the number of flying lines connecting any two nodes, and the memory space SM satisfies: SM = n(n-1) / 2, where n is the number of nodes.

[0006] P400, obtains the target ordered flying line group according to the node and SM, including:

[0007] P420, obtain the intermediate reference value ref.

[0008] P440, traverse all nodes to calculate the length of the flying line between any two nodes. When the flying line length is less than ref, save the flying line length in the positive order of the memory space to obtain the target flying line group; when the flying line length is greater than ref, save it in the reverse order of the memory space to obtain the candidate flying line group.

[0009] P460, the target flying line group is sorted according to the flying line length to obtain the target ordered flying line group.

[0010] P600, traverses and processes the flying line lengths in the order of the elements in the target ordered flying line group to obtain the shortest flying line path.

[0011] In addition, the present invention also provides a non-transitory computer-readable storage medium, in which at least one instruction or at least one program is stored, and the at least one instruction or the at least one program is loaded and executed by a processor to implement the above method.

[0012] In addition, the present invention also provides an electronic device, including a processor and the above-mentioned non-transitory computer-readable storage medium.

[0013] The present invention has at least the following beneficial effects:

[0014] An embodiment of the present invention provides an optimization method, electronic device and storage medium for obtaining the shortest flying line path, which sorts the flying lines in a target flying line group that are smaller than a reference value, traverses the sorted flying line group to obtain a target ordered flying line group, and traverses and processes the flying line lengths in the order of the elements in the target ordered flying line group to obtain the shortest flying line path, thereby improving the efficiency of obtaining the shortest flying line path. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0016] Figure 1 A flow chart of a flying wire interconnection method between different components provided in the first embodiment of the present invention;

[0017] Figure 2 A flow chart of a method for obtaining the shortest flying line path provided in the second embodiment of the present invention;

[0018] Figure 3 A flow chart of an optimization method for obtaining the shortest flying line path provided in Embodiment 3 of the present invention. DETAILED DESCRIPTION

[0019] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0020] When the existing EDA tools are used for collaborative design, it is impossible to take into account the design of the flying wires at the same time when multiple designs are laid out, resulting in unreasonable layout of the flying wires. Therefore, a method for taking into account the layout design of the flying wires is urgently needed. In order to solve this technical problem, the present invention provides a first embodiment.

[0021] Embodiment 1

[0022] See also Figure 1 , which shows a flow chart of a flying wire interconnection method between different components, the method comprising the following steps:

[0023] S200, obtaining a first component D1 and a second component D2 to be connected, D1 having N pins, D2 having M pins, and D1 and D2 respectively including multiple pins with the same network name. It should be noted that multiple different pins with the same network name in the same component are physically interconnected.

[0024] Among them, D1 and D2 are components of different designs.

[0025] S400, specify K pairs of mapping relationships {PP1, PP2, ..., PP k ,…,PP K}, PP k is the mapping relationship of the kth pair of network names, and the value range of k is 1 to K; PP k The mapping relationship is the i-th network name net of D1 D1,i and the jth network name of D2 net D2,j Connection, where i and j are both greater than or equal to 1.

[0026] The mapping relationship specified is the mapping relationship between network names and network names. A flying line connection needs to be created between the two network names with the mapping relationship specified. When specifying the mapping relationship, K pairs of mapping relationships can be specified by the user.

[0027] S600, calculate the shortest distance between pins in the mapping relationship of each pair of network names, and create a flying line with the two pins with the shortest distance as the endpoints. This step can create flying lines for all network names with a specified mapping relationship. By creating flying lines, users can intuitively see the flying line layout between various devices, and adjust the devices by moving, flipping, etc., so as to update the flying line layout in real time, which can enable users to intuitively compare and select a more reasonable layout.

[0028] Further, PP k The steps to calculate the shortest distance between pins include:

[0029] S620, find the D1 with the net D1,i All the same pins are obtained as pin set S1.

[0030] S640, find the D2 with the net D2,j All the same pins are used to obtain the pin set S2.

[0031] S660, calculating the shortest distances from all pins in S1 to all pins in S2, and obtaining the shortest distance between pins in the kth pair of mapping relationships.

[0032] Specifically, when all pins in S1 are {P S1,1 ,P S1,2 ,…,P S1,q …,P S1,Q}, P S1,q is the qth pin in S1, Q is the total number of pins in S1, and the value range of q is 1 to Q; when all pins in S2 are {P S2,1 ,P S2,2 ,…,P S2,e, …,P S2,E}, P S2,e is the e-th pin in S2, E is the total number of pins in S2, and the value range of e is 1 to E; then the shortest distance D from all pins in S1 to all pins in S2 min The calculation steps of P are exhaustive, including: S1,1 The distance sequence D between all pins in S2 is obtained S1,1 ; Calculate P S1,2 The distance sequence D between all pins in S2 is obtained S1,2 , and so on, respectively calculate the distance between each pin in S1 and all pins in S2 to obtain the distance sequence corresponding to each pin in S1; sort the distance sequences of all pins in S1 to obtain the shortest distance. Other algorithms for calculating the shortest distance in the prior art all fall within the protection scope of the present invention.

[0033] As a preferred embodiment, the algorithm for calculating the shortest distance is further optimized. The steps for calculating the shortest distance from all pins in S1 to all pins in S2 include:

[0034] S662, obtaining reference difference coordinates and reference distance DD, the reference difference coordinates including abscissa reference difference dx and ordinate reference difference dy. Optionally, the initial values ​​of the reference difference coordinates and reference distance DD may be specified by the user.

[0035] As a preferred embodiment, S662 further includes the step of obtaining initial values ​​of reference difference coordinates and reference distance DD:

[0036] S6622, get the first pin pair CP by exhaustive method 1,1 .

[0037] It should be noted that the exhaustive method is to combine all the pins in S1 with all the pins in S2 to obtain different pin pairs. Among them, S1 and S2 are two arrays, and two layers of traversal are performed according to the index number of the array. The first layer of traversal is to traverse each pin in S1, and the second layer of traversal is to traverse each pin in S2. When traversing any pin in S1, the second layer of traversal is nested. Therefore, the first pin pair traversed is the first pin of the first layer traversal and the first pin of the second layer traversal.

[0038] S6624, Get CP 1,1 The difference coordinates include the difference dx of the horizontal coordinates of the pin pair. 1,1 The difference between the vertical coordinate and dy 1,1 As an example, when the pin pair has coordinates (x 11 ,y 11 ) and (x 21 ,y 21 ), then dx=x 11 -x 21 ,dy=y 11 -y 21 .

[0039] S6626, according to CP 1,1 The squared distance between the pin pairs is calculated by the difference coordinates to obtain the candidate distance DD 1,1 DD 1,1 Satisfaction: DD 1,1 =dx 1,1 2 +dy 1,1 2 .

[0040] S6628, CP 1,1 The difference coordinates are designated as the initial values ​​of the reference difference coordinates, and DD 1,1 Specify the initial value of the reference distance DD.

[0041] The difference coordinates of the first pin pair traversed are used as the initial value of the reference difference coordinates, and the candidate distance is used as the initial value of the reference distance DD. When traversing the next pin pair, the data of the next pin pair is compared with the reference value. Real-time updating of the reference value can reduce the computational complexity and improve the computational efficiency.

[0042] S664, process each pin pair in turn by exhaustive method to obtain the shortest distance; wherein, when the pin pair CP consisting of the wth pin in S1 and the vth pin in S2 is obtained w,v When , the processing steps include:

[0043] S6642, Get CP w,vThe difference coordinates include the difference dx of the horizontal coordinates of the pin pair. w,v The difference between the vertical coordinate and dy w,v .

[0044] S6644, when dx w,v Greater than dx and dy w,v When dx is greater than dy, the calculation ends and the next pin pair is obtained through exhaustive method; when dx w,v Less than dx and dy w,v When it is less than dy, according to CP w,v The squared distance between the pin pairs is calculated by the difference coordinates to obtain the candidate distance DD w,v , when DD w,v When it is less than DD, update DD to DD w,v And update the reference difference coordinates to CP w,v The difference coordinates of .

[0045] When dx w,v Greater than dx and dy w,v When it is greater than dy, the calculation is terminated, and a large number of pin pairs can be screened out without further calculating the candidate distance, saving a lot of hardware computing resources. Furthermore, by updating the reference difference coordinates and reference distance DD in real time, the shortest distance can be obtained while the exhaustive method is exhausted, further improving the calculation efficiency.

[0046] This calculation step can avoid the traditional method of calculating the distance between two pins by taking square roots, thereby improving the calculation efficiency. At the same time, since most of the pin pairs are shielded by the reference value, the calculation efficiency can be further improved.

[0047] As a preferred embodiment, the present invention further includes S300, obtaining a mapping table of pins and network names, including:

[0048] S320, obtain the mapping table PN of the pins and network names in D1 D1 ={PN D1,1 ,PN D1,2 ,…,PN D1,f ,…,PN D1,F}, PN D1,f is the name of the fth network in D1 D1,f With all the net D1,f The mapping relationship between the pins of , where the value of f ranges from 1 to F.

[0049] Then S620, according to PN D1 Find the net in D1 D1,i All the same pins are obtained to obtain the pin set S1. It should be noted that the network name is used as the index to search for PN D1Get the mapping relationship with the current network name, and all pins in the mapping relationship are S1.

[0050] S340, obtain the mapping table PN of the pin and network name in D2 D2 ={PN D2,1 ,PN D2,2 ,…,PN D2,h ,…,PN D2,H}, PN D2,h is the hth network name net in D2 D2,h With all the net D2,h The mapping relationship between the pins, where the value range of h is 1 to H.

[0051] Then S640, according to PN D2 Find the D2 with the net D2,j All the same pins are used to obtain the pin set S2.

[0052] Optionally, step S300 may be acquired before S200, or after S200 and before S600, or synchronously with S200.

[0053] Since the network names of the pins in the components have been specified during the design, the network name of each pin in the components is determined when in use. Therefore, a mapping table of pins and network names is obtained before calculating the shortest distance. After each move, flip and other operations, the corresponding pins can be obtained by searching the mapping table with the network name as the index during the search. There is no need to re-search all the pins corresponding to each network name each time, saving hardware computing resources.

[0054] As a preferred embodiment, the present invention further includes S500, executing S300 after S400 and before S600, and using either S500 or S300, that is, S300 and S500 do not appear at the same time in the method steps provided by the present invention. S500, obtaining a mapping table of pins and network names, including:

[0055] S520, obtain the mapping table PPN of pins and network names in D1 D1 = {PPN D1,1 ,PPN D1,2 ,…,PPN D1,r ,…,PPN D1,R},PPN D1,r The rth network name net in the specified D1 D1,r With all the net D1,r The mapping relationship between the pins of , where the value of r ranges from 1 to R.

[0056] Then S620, according to PPND1 Find the net in D1 D1,i All the same pins are obtained to obtain the pin set S1. It should be noted that the network name is used as the index to search for PN D1 Get the mapping relationship with the current network name, and all pins in the mapping relationship are S1.

[0057] S540, obtain the mapping table PPN of pins and network names in D2 D2 = {PPN D2,1 ,PPN D2,2 ,…,PPN D2,t ,…,PPN D2,T},PPN D2,r The tth network name net in the specified D2 D2,t With all the net D2,t The mapping relationship between the pins of , where the value range of t is 1 to T.

[0058] Then S640, according to PPN D2 Find the D2 with the net D2,j All the same pins are used to obtain the pin set S2.

[0059] It should be noted that the network names in the mapping table of pins and network names obtained in S500 are all the network names specified in S400, and no mapping relationship for unspecified network names is established. This step can further save hardware computing resources and cache space.

[0060] As a preferred embodiment, in S500, when the position of D1 or D2 moves, S600 is executed according to the coordinates of the moved pin.

[0061] The embodiment of the present invention provides a flying wire interconnection method between different components. The method obtains a first component D1 and a second component D2, and specifies a mapping relationship of network names, wherein D1 and D2 respectively have multiple pins; obtains pin sets S1 and S2 of all pins corresponding to the two network names in each mapping relationship, calculates the shortest distance between S1 and S2, and creates flying wires for the two pins corresponding to the shortest distance. The method can visualize the flying wire layout in real time, can create flying wires at the same time during design, and takes into account the flying wire layout, solving the problem that multiple designs in the prior art cannot take into account the flying wire layout design. And after each execution of operations such as moving and flipping, the flying wire layout can also be viewed in real time, which enables users to intuitively compare and select a more reasonable layout.

[0062] An embodiment of the present invention also provides a non-transitory computer-readable storage medium, which can be set in an electronic device to store at least one instruction or at least one program related to implementing a method in a method embodiment. The at least one instruction or the at least one program is loaded and executed by the processor to implement the method provided in the above embodiment.

[0063] An embodiment of the present invention further provides an electronic device, comprising a processor and the aforementioned non-transitory computer-readable storage medium.

[0064] An embodiment of the present invention further provides a computer program product, which includes program code. When the program product is run on an electronic device, the program code is used to enable the electronic device to execute the steps of the method according to various exemplary embodiments of the present invention described above in this specification.

[0065] Embodiment 1 realizes how to create the shortest flying line between two modules. After obtaining the shortest flying line, how to obtain the shortest flying line path between all modules becomes a technical problem to be solved urgently. At present, the prior art generates it through a greedy algorithm, that is, searching for another node Pk closest to the current node, and then searching for another node closest to the current node again with Pk as the current node, and so on, to generate the shortest path. The greedy algorithm can ensure that the flying line between two adjacent nodes is the shortest, but it cannot ensure that the flying line path finally obtained is the shortest, therefore, a method that can generate the shortest flying line path is urgently needed. In order to solve the problem that the flying line path finally generated is the shortest, the present invention provides embodiment 2.

[0066] Embodiment 1 of the present invention also provides a non-transitory computer-readable storage medium, which can be set in an electronic device to store at least one instruction or at least one program related to implementing a method in the method embodiment. The at least one instruction or the at least one program is loaded and executed by the processor to implement the method provided in the above embodiment.

[0067] Embodiment 1 of the present invention further provides an electronic device, including a processor and the aforementioned non-transitory computer-readable storage medium.

[0068] Embodiment 1 of the present invention further provides a computer program product, which includes program code. When the program product is run on an electronic device, the program code is used to enable the electronic device to execute the steps of the method according to various exemplary embodiments of the present invention described above in this specification.

[0069] Embodiment 2

[0070] See also Figure 2 , which shows a flow chart of a method for obtaining the shortest flying line path, the method comprising the following steps:

[0071] T100, obtain N1 flying lines that connect all nodes in sequence.

[0072] Among them, all nodes connected by N1 flying wires are different components, or are different pins with the same network name inside the same component.

[0073] Among them, when the multiple nodes connected by N1 flying wires are different components, and each flying wire is the shortest distance flying wire between two components. It should be noted that each component includes multiple pins, and each pin is configured with a network name. Each component includes L pins with the same network name, where L is greater than or equal to 0. Pins with the same network name between different components are physically interconnected. Therefore, after the mapping relationship between the network names of different components is configured, different components create flying wire interconnections through pins. There are many flying wire interconnection schemes, among which a flying wire can be obtained so that the distance between the two pins connected by the flying wire is the shortest.

[0074] As a preferred embodiment, when the multiple nodes connected by N1 flying wires are different components, the flying wires between the components are generated by the solution provided in Embodiment 1. The shortest distance flying wire created by Embodiment 1 makes the flying wire between any two components the shortest, and on this basis, the shortest flying wire path is obtained, and the final flying wire path finally obtained is the actual shortest flying wire path.

[0075] As a preferred embodiment, any two points are selected from all nodes to generate N1 flying lines, so the relationship between the number of nodes and flying lines satisfies: N1 = n(n-1) / 2, where n is the number of nodes.

[0076] T200, sort all the flying lines by length to get an ordered set of flying lines. Optionally, arrange them in ascending order of length, and traverse the flying lines in T400 in the order of arrival from the smallest.

[0077] T300, obtain the target number of flying wires M of the shortest flying wire path connecting all nodes, where M satisfies: M=n-1, where n is the number of nodes. The target number of flying wires is the number of flying wires contained in the shortest flying wire path, which is used to constrain the number of flying wires selected when traversing in sequence according to the length of the flying wires, so as to avoid traversing redundant flying wires and wasting computing resources.

[0078] T400, traversing the flying lines in the ordered set of flying lines in turn and processing all the selected flying lines, all the selected flying lines forming the shortest flying line path; wherein the processing steps when traversing the i-th flying line include:

[0079] T410, marking the branch index for the target node connected to both ends of the i-th flying line, and determining whether to select the flying line according to the branch index.

[0080] Further, T410 also includes: when the two target nodes connected at both ends of the i-th flying line are not marked with branch indexes, the i-th flying line is selected, and the two target nodes are marked as the same new branch index. When the two target nodes have been marked as branch indexes of two different path branches, the i-th flying line is selected, and all branch indexes of the two path branches are unified into the same branch index. When one of the target nodes is not marked with a branch index, the i-th flying line is selected, and the target node that is not marked with a branch index is marked as the branch index of the other target node. When the branch indexes of the two target nodes are the same, the i-th flying line is not selected.

[0081] It should be noted that before traversal, the branch indexes of all nodes are default values. When the branch index of a node is the default value, it means that the node is not marked with a branch index during the traversal process.

[0082] Optionally, when marking two target nodes as the same new branch index, the new branch index is different from the branch index mark that has been used.

[0083] Optionally, when all branch indexes of two path branches are unified into the same branch index, the unified same branch index can be any branch index of the two path branches, or a new branch index, where the new branch index is different from the branch index tag that has been used. For example, there are two path branches, one path branch connects J nodes, and the branch index of each node is val1; the other path branch connects G nodes, and the branch index of each node is val2; at this time, all val1 and val2 are unified into val1, or unified into val2, or unified into other new branch indexes that have not been used.

[0084] By marking the branch index, the flying line traversed each time can be the shortest flying line among the remaining unmarked flying lines. After traversing and connecting all the shortest flying line paths, the path finally marked can be the shortest flying line path.

[0085] T420, update the number H of selected flying lines, and stop traversal when the number H of selected flying lines is equal to M.

[0086] By marking the branch index mark, the shortest flying lines in the remaining flying lines can be traversed in sequence. When the number of selected flying lines is equal to the target number M of flying lines in the shortest flying line path, the shortest flying line path composed of the shortest flying lines is obtained.

[0087] The present invention provides a method for obtaining the shortest flying line path, which includes sorting the flying lines between nodes to obtain a flying line ordered set, traversing the flying lines in the flying line ordered set in sequence, marking branch indexes for target nodes connected at both ends of each flying line when traversing each flying line, and stopping traversal when the number of selected nodes H is equal to M, thereby obtaining the shortest flying line path. Since the shortest flying line is traversed in sequence in the traversal process, and the traversal is stopped when the number of selected flying lines is equal to the number of target flying lines, the flying line path finally obtained must be the shortest flying line path, and is the most efficient traversal method, without traversing redundant flying lines.

[0088] Embodiment 2 provides how to obtain the shortest flying wire path connecting multiple nodes, but in actual applications there are many flying wires. For example, for 40,000 pins, the method provided in embodiment 1 can obtain 40,000*39,999 flying wires, which is about 800 million flying wires. The time to traverse 800 million flying wires to obtain the shortest path is 104s, and the time to obtain the flying wires is relatively long. In order to improve the calculation efficiency of obtaining flying wires and reduce hardware computing resources, the present invention provides embodiment 3.

[0089] Embodiment 2 of the present invention also provides a non-transitory computer-readable storage medium, which can be set in an electronic device to store at least one instruction or at least one program related to implementing a method in the method embodiment. The at least one instruction or the at least one program is loaded and executed by the processor to implement the method provided in the above embodiment.

[0090] Embodiment 2 of the present invention further provides an electronic device, including a processor and the aforementioned non-transitory computer-readable storage medium.

[0091] Embodiment 2 of the present invention further provides a computer program product, which includes program code. When the program product is run on an electronic device, the program code is used to enable the electronic device to execute the steps of the method according to various exemplary embodiments of the present invention described above in this specification.

[0092] Embodiment 3

[0093] See also Figure 3 , which shows a flow chart of an optimization method for obtaining the shortest flying line path, the method comprising:

[0094] P200, apply for memory space according to the number of flying lines connecting any two nodes, and the memory space SM satisfies: SM = n(n-1) / 2, where n is the number of nodes.

[0095] It should be noted that if any two nodes are selected from n nodes and connected by flying wires, the total number of flying wires that need to be connected is n(n-1) / 2. If the memory is used to store these n(n-1) / 2 flying wires, n(n-1) / 2 memory spaces are required. Therefore, the size of the allocated memory space is equal to the number of flying wires.

[0096] Among them, the node is a pin or a component, and the node has the same meaning as the node in the first embodiment, which is not repeated here.

[0097] P400, obtains the target ordered flying line group according to the node and SM, including:

[0098] P420, obtain an intermediate reference value ref. The intermediate reference value is used to divide the flying wires of all design modules into a flying wire group greater than the reference value and a flying wire group less than the reference value.

[0099] Optionally, the intermediate reference value ref satisfies: ref = D / 2, D = [(x max -x min ) 2 +(y max -y min ) 2 ] 1 / 2 , where x min is the minimum horizontal coordinate of all nodes, x max is the maximum horizontal coordinate of all nodes, y min is the minimum ordinate of all nodes, y max is the maximum ordinate of all nodes.

[0100] As a preferred embodiment, in order to improve the calculation efficiency, the intermediate reference value ref satisfies: ref = D 2 / 4,D 2 =(x max -x min ) 2 +(y max -y min ) 2 .

[0101] P440, traverse all nodes to calculate the length of the flying line between any two nodes. When the flying line length is less than ref, save the flying line length in the positive order of the memory space to obtain the target flying line group; when the flying line length is greater than ref, save it in the reverse order of the memory space to obtain the candidate flying line group.

[0102] Among them, the positive order is the order of increasing from the smallest address of the memory space. That is, every time a flying line length less than ref is traversed, the flying lines are put into the memory in the order of increasing memory space. The reverse order is the order of decreasing from the largest address of the memory space. Since the number of flying lines is equal to the size of the memory space, the addresses that increase in positive order and the addresses that decrease in reverse order will gradually approach and eventually merge, so that the flying line data will be stored in each address in the memory space. Finally, the effect of dividing the data stored in the memory space into two different groups is achieved through ref.

[0103] P460, the target flying line group is sorted according to the flying line length to obtain the target ordered flying line group. It should be noted that if the number of elements in the target ordered flying line group is KK, the time consumed for sorting is the square of KK, where KK is less than SM. Compared with the square of the time SM consumed for directly sorting all the flying line lengths without grouping, the sorting efficiency is improved and the consumption of hardware computing resources is reduced.

[0104] P600, traverses and processes the flying line lengths in the order of the elements in the target ordered flying line group to obtain the shortest flying line path.

[0105] As a preferred embodiment, P400 also includes:

[0106] P470, when the number of elements in the target flying line group is less than the preset number threshold, the target flying line group is not updated; when the number of elements in the target flying line group is greater than or equal to the preset number threshold, the target flying line group is updated. The preset number threshold is used to limit the number of elements in the target flying line group. If the number of elements is too large, such as hundreds of millions of elements, the amount of sorting calculation is large and the sorting efficiency is very low. Therefore, the calculation efficiency can be improved by setting the number threshold.

[0107] Further, the updating steps include:

[0108] P472, a new reference value is obtained according to the average of the maximum length and the minimum length of the flying line in the target flying line group. Optionally, the new reference value ref1 satisfies: ref1 = (min + max) / 2, wherein min is the minimum length of the flying line in the target flying line group, and max is the maximum length of the flying line in the target flying line group. In the prior art, other methods for obtaining the intermediate value, mean, median or other numerical values ​​of the flying line in the target flying line group as reference values ​​also fall within the protection scope of the present invention.

[0109] P474, compare the length of each flying line in the target flying line group with the new reference value in positive order. When the length of the j-th flying line in the target flying line group is greater than the new reference value, compare it with the new reference value in reverse order. When the length of the k-th flying line is less than the new reference value, swap the storage positions of the j-th flying line and the k-th flying line in the memory space, and finally obtain a new target flying line group and a new candidate flying line group. It should be noted that this step shifts the flying lines in the target flying line group into two groups according to the new reference value, so that all those less than the new reference value are located in the new target flying line group and stored in the first half of the memory space. All those greater than the new reference value are located in the new candidate flying line group and stored in the second half of the memory space.

[0110] P476, when the number of flying lines in the new target flying line group is greater than the preset number threshold, execute P470 again.

[0111] As a preferred embodiment, P600 further includes:

[0112] P620, mark the branch index for the target node connected to both ends of the i-th flying line, and determine whether to select the flying line according to the branch index.

[0113] P640, update the number H of selected flying lines, and stop traversal when the number H of selected flying lines is equal to the target number M of flying lines, where M satisfies: M=n-1.

[0114] It should be noted that steps P620-P640 are the same as steps S410-S420 in the first embodiment and will not be described in detail.

[0115] As a preferred embodiment, P600 also includes:

[0116] P660, when the number of traversals H is less than M, sort the flying lines in the candidate flying line group according to the flying line lengths to obtain a candidate ordered flying line group; use the candidate ordered flying line group as a new target ordered flying line group and execute P620-P660 again.

[0117] As an example, when all the flying lines are saved as the target flying line group A1 and the candidate flying line group B1 in the memory space; if the number of flying lines in A1 is greater than the preset number threshold, A1 is saved again as the new target flying line group A according to step P470. 11 And candidate fly line group B 11 If A 11 If the number of flying lines in is still greater than the preset threshold, 11 Save as new target line group A according to step P470 again 111 And candidate fly line group B 111 In the case of A 111After sorting, the shortest flying line path is obtained by processing according to P600. If A 111 When the number of flying wires in is less than H, then 111 After sorting, traverse according to P600; if A 111 and B 111 If the total number of is still less than H, the candidate flying line group B 11 As the processing object, and so on, the traversal is stopped when the number of flying lines traversed by P600 is equal to M.

[0118] The efficiency of obtaining the shortest path by the method provided by the second embodiment of the present invention is much greater than that by the first embodiment of the present invention. For example, for 40,000 pins, the method provided by the first embodiment can obtain 40,000*39,999 flying wires, which is about 800 million flying wires. The time to traverse the 800 million flying wires to obtain the shortest path is 104 seconds. The time to obtain the shortest path by the method provided by the second embodiment of the present invention is 12 seconds.

[0119] An embodiment of the present invention provides an optimization method for obtaining the shortest flying wire path. The method saves the flying wires in a memory space of the same size, divides the flying wires saved in the memory space into two groups according to a reference value, sorts the flying wires in a target flying wire group that is smaller than the reference value, traverses the flying wires after sorting to obtain a target ordered flying wire group, traverses the flying wire lengths in sequence according to the order of the elements in the target ordered flying wire group and processes them to obtain the shortest flying wire path, thereby improving the efficiency of obtaining the shortest flying wire path.

[0120] Embodiment three of the present invention also provides a non-transitory computer-readable storage medium, which can be set in an electronic device to store at least one instruction or at least one program related to implementing a method in the method embodiment. The at least one instruction or the at least one program is loaded and executed by the processor to implement the method provided in the above embodiment.

[0121] Embodiment 3 of the present invention further provides an electronic device, comprising a processor and the aforementioned non-transitory computer-readable storage medium.

[0122] Embodiment 3 of the present invention further provides a computer program product, which includes program code. When the program product is run on an electronic device, the program code is used to enable the electronic device to execute the steps of the method according to various exemplary embodiments of the present invention described above in this specification.

[0123] Although some specific embodiments of the present invention have been described in detail by way of example, it will be appreciated by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present invention. It will also be appreciated by those skilled in the art that various modifications may be made to the embodiments without departing from the scope and spirit of the present invention. The scope of the present invention is defined by the appended claims.

Claims

1. An optimization method for obtaining the shortest flying line path, characterized in that: The method comprises: P200, apply for memory space according to the number of flying lines connecting any two nodes, and the memory space SM satisfies: SM = n(n-1) / 2, where n is the number of nodes; P400, obtains the target ordered flying line group according to the node and SM, including: P420, obtain the intermediate reference value ref; P440, traverse all nodes to calculate the length of the flying line between any two nodes. When the flying line length is less than ref, save the flying line length in the positive order of the memory space to obtain the target flying line group; when the flying line length is greater than ref, save it in the reverse order of the memory space to obtain the candidate flying line group; P460, the target flying line group is sorted according to the flying line length to obtain the target ordered flying line group; P600, traverses and processes the flying line lengths in the order of the elements in the target ordered flying line group to obtain the shortest flying line path.

2. The method according to claim 1, characterized in that P400 also includes: P470, when the number of elements in the target flying line group is less than the preset number threshold, the target flying line group is not updated; when the number of elements in the target flying line group is greater than or equal to the preset number threshold, the target flying line group is updated, and the updating step includes: P472, a new reference value is obtained according to the average of the maximum length and the minimum length of the flying line in the target flying line group; P474 compares the length of each flying line in the target flying line group with the new reference value in positive order, and when the length of the j-th flying line in the target flying line group is greater than the new reference value, compares it with the new reference value in reverse order, and when the length of the k-th flying line is less than the new reference value, exchanges the storage positions of the j-th flying line and the k-th flying line in the memory space, and finally obtains a new target flying line group and a new candidate flying line group; P476, when the number of flying lines in the new target flying line group is greater than the preset number threshold, execute P470 again.

3. The method according to claim 2, characterized in that The new reference value ref1 in P472 satisfies: ref1 = (min + max) / 2, wherein min is the minimum length of the flying line in the target flying line group, and max is the maximum length of the flying line in the target flying line group.

4. The method according to claim 1, characterized in that: P600, also includes: S620, marking a branch index for the target node connected to both ends of the i-th flying line, and determining whether to select the flying line according to the branch index; P640, update the number H of selected flying lines, and stop traversal when the number H of selected flying lines is equal to the target number M of flying lines, where M satisfies: M=n-1.

5. The method according to claim 1, characterized in that The P600 also includes: P660, when the number of traversals H is less than M, sort the flying lines in the candidate flying line group according to the flying line lengths to obtain a candidate ordered flying line group; use the candidate ordered flying line group as a new target ordered flying line group and execute P620-P660 again.

6. The method according to claim 1, characterized in that The intermediate reference value ref in P420 satisfies: The intermediate reference value ref satisfies: ref=D 2 / 4,D 2 =(x max -x min ) 2 +(y max -y min ) 2 , where x min is the minimum horizontal coordinate of all nodes, x max is the maximum horizontal coordinate of all nodes, y min is the minimum ordinate of all nodes, y max is the maximum ordinate of all nodes.

7. The method according to claim 1, characterized in that The nodes in P200 are pins or components.

8. The method according to claim 1, characterized in that The positive order in P440 is the order of increasing from the smallest address in the memory space, and the reverse order is the order of decreasing from the largest address in the memory space.

9. A non-transitory computer-readable storage medium, wherein at least one instruction or at least one program is stored in the storage medium, characterized in that: The at least one instruction or the at least one program is loaded and executed by the processor to implement the method according to any one of claims 1 to 8.

10. An electronic device, characterized in that: The invention comprises a processor and the non-transitory computer-readable storage medium as claimed in claim 9.

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