Systems and methods for chip operations using a Serial Peripheral Interface (SPI) without a chip select pin

Abstract

Systems and methods are disclosed for chip operation using a Serial Peripheral Interface (SPI) without a chip select pin. A communication link between a host and a device may include a clock line, a host-to-device line, and a device-to-host line. The host may signal a start or stop condition using the clock line, and the device may send an acknowledgement of the host's signaling over the device-to-host line. Once an acknowledgement is made, the host may then signal over the host-to-device line using a protocol such as SPI.

Description

[0001] Priority Application

[0002] This application claims priority to U.S. Patent Application Serial No. 17 / 484,419, titled "SYSTEMS AND METHODS FOR CHIP OPERATION USING SERIAL PERIPHERAL INTERFACE (SPI) WITHOUT A CHIP SELECT PIN", filed on September 24, 2021, which is hereby incorporated by reference in its entirety. Background

[0003] I. Field of Technology

[0004] The technology of the present disclosure generally relates to communication between two integrated circuits (ICs) operating using the Serial Peripheral Interface (SPI) specification.

[0005] II. Background Art

[0006] Computing devices, and more specifically mobile communication devices, have become increasingly common in modern society. The popularity of these mobile communication devices is due in part to the many functions now enabled on such devices. The increased processing power in such devices means that mobile communication devices have evolved from pure communication tools to complex mobile entertainment centers, enabling an enhanced user experience.

[0007] In many instances, these functions can be enabled by communicating circuits on different dies or chips with each other. For example, a processor chip can communicate with a memory chip or a sensor chip. Various standards and protocols have been developed to facilitate such communication. One popular standard for low-speed communication is the Serial Peripheral Interface (SPI) specification. SPI is widely adopted. Thus, improvements to SPI can provide a disproportionate impact across computing devices. Summary of the Invention

[0008] Aspects disclosed in the detailed description include systems and methods for chip operation using a Serial Peripheral Interface (SPI) without a chip select pin. Specifically, exemplary aspects contemplate eliminating the chip select pin for a host (also referred to as master) to single device (also referred to as slave) communication link. The communication link can include a clock line, a host-to-device line, and a device-to-host line. The host can use the clock line to signal start or stop conditions, and the device can send an acknowledgement of the host's signaling over the device-to-host line. Once the acknowledgement is made, the host can then signal over the host-to-device line using a protocol such as SPI. This arrangement eliminates the need for a dedicated chip select pin, which can save space on the chip and help reduce the complexity of wiring between chips.

[0009] In this regard, in one aspect, an integrated circuit (IC) is disclosed. The IC includes a bus interface. The bus interface includes a clock pin configured to be coupled to a clock line on an associated bus. The bus interface also includes an input pin configured to be coupled to an input line on the associated bus. The bus interface also includes an output pin configured to be coupled to an output line on the associated bus. The IC further includes a control circuit. The control circuit is configured to detect a change on the clock pin. The control circuit is also configured to send an acknowledgment (ACK) of the detected change on the output pin. The control circuit is also configured to detect a subsequent change on the clock pin after sending the ACK. The control circuit is also configured to send a second ACK on the output pin.

[0010] In another aspect, an IC is disclosed. The IC includes a bus interface. The bus interface includes a clock pin configured to be coupled to a clock line on an associated bus. The bus interface also includes an input pin configured to be coupled to an input line on the associated bus. The bus interface also includes an output pin configured to be coupled to an output line on the associated bus. The IC further includes a control circuit. The control circuit is configured to hold a clock signal on the clock pin at a logical high. The control circuit is also configured to change the clock signal to a logical low. The control circuit is also configured to receive an ACK of the detected change on the input pin. The control circuit is also configured to change the clock signal to a logical high after receiving the ACK. The control circuit is also configured to receive a second ACK on the input pin.

[0011] In another aspect, a method for controlling an SPI bus is disclosed. The method includes detecting a change on a clock pin. The method also includes sending an ACK of the detected change on an output pin. The method also includes detecting a subsequent change on the clock pin after sending the ACK. The method also includes sending a second ACK on the output pin.

[0012] In another aspect, a method for controlling an SPI bus is disclosed. The method includes holding a clock signal on a clock pin at a logical high. The method also includes changing the clock signal to a logical low. The method also includes receiving an ACK of the detected change on an input pin. The method also includes changing the clock signal to a logical high after receiving the ACK. The method also includes receiving a second ACK on the input pin. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1A is a block diagram of a conventional chip-to-multi-chip system that communicates using a daisy-chain serial peripheral interface (SPI) link;

[0014] Figure 1B is a block diagram of a conventional chip-to-multi-chip system that communicates using devices arranged independently on an SPI link;

[0015] Figure 1C is a block diagram of a conventional chip-to-chip system that communicates using an SPI link;

[0016] Figure 2 is a signaling diagram showing how lines within an SPI link can be used in a conventional SPI link;

[0017] Figure 3 is a block diagram of an exemplary chip-to-chip system that uses an SPI link without a chip select line according to an exemplary aspect of the present disclosure;

[0018] Figure 4 is to illustrate Figure 3 a flowchart of a start condition sequence of a chip-to-chip system;

[0019] Figure 5 is to show Figure 4 a signaling diagram of a start condition sequence;

[0020] Figure 6 is to illustrate Figure 3 a flowchart of a stop condition sequence of a chip-to-chip system;

[0021] Figure 7 is to show Figure 6 a signaling diagram of a stop condition sequence;

[0022] Figure 8 is to implement Figure 3 a block diagram of an exemplary circuit of a host or master chip;

[0023] Figure 9 is to implement Figure 3 a block diagram of an exemplary circuit of a device or slave chip;

[0024] Figure 10 is to include Figure 3 a block diagram of an exemplary mobile computing device of a chip-to-chip system; Detailed Description

[0025] Now referring to the drawings, several exemplary aspects of the present disclosure are described. The term "exemplary" is used herein to mean "serving as an example, instance, or illustration". Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or having an advantage over other aspects.

[0026] Aspects disclosed in the detailed embodiments include systems and methods for using a Serial Peripheral Interface (SPI) without a chip select pin for chip operations. Specifically, in an exemplary aspect, it is contemplated to eliminate the chip select pin for a host (also referred to as master) to single device (also referred to as slave) communication link. The communication link may include a clock line, a host-to-device line, and a device-to-host line. The host may use the clock line to signal start or stop conditions, and the device may send an acknowledgement of the host's signaling via the device-to-host line. Once the acknowledgement is made, the host may then use a protocol such as SPI to signal on the host-to-device line. This arrangement eliminates the need for a dedicated chip select pin, which can save space on the chip and help reduce the complexity of wiring between chips.

[0027] Before describing the exemplary aspects of the present disclosure, a brief overview of a chip-to-multi-chip system using an SPI link is provided in Figure 1A and Figure 1B and a chip-to-chip system using an SPI link is provided in Figure 1C to provide context for the subsequent discussion. Figure 2 A signaling diagram for a conventional SPI link is provided and the discussion of the exemplary aspects of the present disclosure begins with reference to Figure 3 below.

[0028] In this regard, Figure 1A is a block diagram of a conventional chip-to-multi-chip system 100 that uses an SPI link 102 to communicate between chips. As used herein, a chip is an integrated circuit (IC) or monolithic IC having a set of electronic circuits on a small piece of semiconductor material such as silicon. It should be understood that multiple chips may be stacked to form a System in Package (SiP), which may be multiple ICs enclosed in one or more chip carrier packages that can be stacked using a laminate package. The SiP performs all or most of the functions of an electronic system and is typically used inside mobile phones, digital music players, etc. The dies containing the ICs may be vertically stacked on a substrate. The dies are internally connected by fine wires bonded to the package. Alternatively, using flip-chip technology, solder bumps are used to bond the stacked chips together. The SiP is similar to a System on Chip (SoC), but is less tightly integrated and not on a single semiconductor die.

[0029] Continuing to refer to Figure 1A, the first chip 104 may be a host IC. Historically, a host IC has been referred to as a master IC, and such terms may be used interchangeably herein. The first chip 104 is coupled to a plurality of second chips 106(1)-106(N) via an SPI link 102, where as illustrated, N = 3. The second chips 106(1)-106(3) may be referred to as device chips or slave chips. The SPI link 102 includes a clock line (SCLK) 108, a master output slave input (MOSI) line 110, a master input slave output (MISO) line 112, and a slave select (SS) line 114. This slave select line 114 is also commonly referred to as a chip select (CS) line. In Figure 1A , the second chips 106(1)-106(3) are arranged in a daisy chain, where the MISO of the second chip 106(1) is connected to the MOSI of the second chip 106(2). The MISO of the second chip 106(2) is connected to the MOSI of the second chip 106(3), and the MISO of the second chip 106(3) is connected to the MISO of the first chip 104.

[0030] In contrast, as better illustrated by the chip-to-multi-chip system 100' as Figure 1B illustrated, the second chips may be arranged independently. The second chips 106(1)-106(N) are identical, but the SPI link 102' has additional slave select lines 114(1)-114(N) that individually couple the first chip 104' to the second chips 106(1)-106(N). Similarly, instead of daisy-chaining the second chips 106(1)-106(N), the MOSI line 110 couples the first chip 104' to each of the second chips 106(1)-106(N), and the MISO line 112 similarly couples each of the second chips 106(1)-106(N) to the first chip 104'.

[0031] Although the chip-to-multi-chip systems 100 and 100' are defined and used within computing devices in some instances, more commonly SPI is used to connect only a single chip pair, as better illustrated by the system 100" in Figure 1C . The system 100" includes a first chip 104 and only a single second chip 106. The SPI link 102 includes the previously discussed lines 108, 110, 112, and 114, but does not require a daisy-chain connection or additional chip select lines.

[0032] Figure 2Signal diagram 200 exemplifies a typical SPI link 102. In addition to specifying which second chips 106(1)-106(N) are enabled or selected, the CS line 114 also indicates an active transaction phase by asserting a logic low during an active transaction. The falling edge 202 indicates the start of a transaction, and the rising edge 204 indicates the end of a transaction. During the active transaction window 206, the clock line 108 provides a clock signal 208. Outside the active transaction window 206, the clock line 108 is held high. The first chip 104 can send a command 210 on the MOSI line 110 during the active transaction window 206, which causes the second chip 106 to send responsive data 212 on the MISO line 112.

[0033] It should be understood that SPI is a low-speed (usually below 50 megahertz (MHz), more commonly below 10 MHz, with a throughput range of about 10 megabits per second (Mbps) to 50 Mbps) synchronous serial communication interface specification mainly used for short-distance communication in embedded systems. Thus, while the exemplary aspects of the present disclosure focus on SPI as an exemplary aspect, the present disclosure is not limited thereto. Other synchronous serial communication systems that employ full-duplex communication and include a slave select line or chip select line may also benefit from the present disclosure.

[0034] Since the introduction of the SPI specification in the mid-1980s, the SPI specification has proven useful. However, more modern computing devices may have a central application processor or modem that has many associated sensor chips or peripheral chips that cannot be subordinated to daisy chaining or independent control on multiple slave buses. Thus, each of these sensor or peripheral chips may have its own SPI link with a corresponding four channels or lines therein. Each line requires its own pin or bump on each chip, which increases the cost and complexity of the two chips. Also, routing many lines between an application component and multiple peripheral chips can be challenging.

[0035] Exemplary aspects of the present disclosure allow for the elimination of chip select lines and corresponding chip select pins from both ends of an SPI link. In cases where a chip (such as an SoC or other chip) has multiple SPI master circuits, eliminating chip select lines and pins doubles the available space and saves cost. Exemplary aspects of the present disclosure not only eliminate chip select lines and pins, but also retain the active transaction indication function of the chip select line by introducing a signaling sequence between the host and the device using the remaining lines. Specifically, the host signals the start of a new transaction by manipulating the clock line of the SPI link and receiving an acknowledgement from the device on the MISO line. Similarly, the host signals the end of a transaction using the clock line and receives an acknowledgement on the MISO line.

[0036] Figure 3 Exemplary system 300 is illustrated. The system 300 includes a host (or master) chip 302 coupled to a device (or slave) chip 304 via a modified SPI link 306. The modified SPI link 306 has a clock (SCLK) line 308, a MISO line 310, and a MOSI line 312, but does not have a slave select line or a chip select line. The host chip 302 may include a clock 314 and control circuitry 316, as well as a bus interface 318 (sometimes referred to as a host bus interface). Similarly, the device chip 304 may include an internal clock 320 and control circuitry 322, as well as a bus interface 324 (sometimes referred to as a device bus interface to distinguish it from the host bus interface). It should be understood that the bus interfaces 318, 324 may include pins or bumps (although as used herein, the term "pin" is defined to include bumps). Specifically, the host bus interface 318 may include a clock pin 318A, an input pin 318B (corresponding to the MISO line 310), and an output pin 318C (corresponding to the MOSI line 312). Similarly, the device bus interface 324 may include a clock pin 324A, an output pin 324B (corresponding to the MISO line 310), and an input pin 324C (corresponding to the MOSI line 312).

[0037] In an exemplary aspect, the host chip 302 and the device chip 304 may initially be connected and perform handshake-based two-way synchronization. Handshake synchronization is well known in the art, but may be outlined as a request and confirmation mechanism to ensure that correct data is sampled into the destination clock domain regardless of the clock ratio between the source (e.g., the host chip 302 and the clock 314) and the destination clock (e.g., the device chip 304 and the internal clock 320). There may be other ways to synchronize the host chip 302 and the device chip 304, and this is within the scope of the present disclosure.

[0038] Related to the synchronization process, the device chip 304, specifically the control circuitry 322, may understand the ratio between the clocks 314, 320 and know or determine that N (i.e., some predetermined value) clock cycles of sampling across the internal clock 320 are required to reliably detect a change in state in the clock signal at the clock pin 324A and confirm that the change in state is being maintained. This ability is related to the transaction start sequence explained in more detail below with reference to Figure 4 More detailed explanation.

[0039] In this regard, Figure 4Illustrates a transaction start sequence process 400 including several preparatory steps, including the system 300 entering an idle state (block 402) and the host chip 302 driving the clock signal on the clock line 308 to logic low (block 404). The device chip 304 holds the MISO line 310 in the last state known to the host chip 302 (block 406). Note that in the initial startup, the host chip 302 knows that the MISO line 310 starts at logic low, so even if this particular idle state does not have a previous active state, the host chip 302 can still know the expected state of the MISO line 310.

[0040] Continuing with reference Figure 4 , the host chip 302 determines to exit the idle state (block 408). Exiting the idle state can be caused by the need to sample sensors, the need to access data within the device chip 304, etc. The host chip 302 asserts the clock signal on the clock line 308 to logic high (block 410). The device chip 304 samples the clock signal at the clock pin 324A within a predetermined number of clock cycles of the internal clock 320 to detect and confirm the change on the clock pin 324A (block 412). Note that this predetermined number can be programmable and can be a function of the ratio of the clock frequencies of the clocks 314, 320 and can be set during the handshake synchronization process. The device chip 304 sends an acknowledgement (ACK) by inverting the MISO line 310 within a predetermined number of clock cycles (of the internal clock 320) (block 414). The host chip 302 detects the ACK by sampling the MISO line 310 and de-asserts the clock signal (block 416).

[0041] Continuing with reference Figure 4 , the device chip 304 samples the clock signal within a predetermined number of clock cycles of the internal clock 320 to detect and confirm the change on the clock pin 324A. The device chip 304 enters the transaction phase (block 418) and sends a second ACK by inverting the MISO line 310 (block 420). The host chip 302 detects the second ACK and enters the transaction phase with the corresponding operation of the clock signal on the clock line 308 (block 422).

[0042] By using a transaction start sequence such as that shown in process 400, the transaction start function of the now missing chip select pin can be retained. Thus, even if the chip select pin is omitted, the device chip 304 can be instructed to enter the transaction state.

[0043] Process 400 corresponds to Figure 5The illustrated signaling diagram 500. The first line 502 corresponds to the state of the host chip 302, where the host chip 302 starts in the idle state 504, enters the start state 506, and then enters the transaction state 508. The host chip 302 controls the clock line 308 shown at line 510 and the MOSI line 312 shown at line 512, while the device chip 304 controls the MISO line 310 shown at line 514. The device chip 304 sees the host chip 302 assert the clock signal on the clock line 308 at time 516 (corresponding to block 410). When the clock is asserted, the device chip 304 samples the clock signal to detect and confirm the assertion. Then, the device chip 304 reverses the MISO line 310 at time 518 (shown both from low to high and from high to low) to provide the first ACK (corresponding to block 414). The host chip 302 detects this first ACK and de-asserts the clock line at time 520 (corresponding to block 416). The device chip 304 detects and confirms this state change of the clock line and sends a second ACK at time 522 by reversing the MISO line 310 (corresponding to block 420). As shown by line 524 with the state of the device chip 304, the device chip 304 starts in the idle state 526 and enters the start state 528 at time 518 by sending the first ACK. By sending the second ACK, the start state 528 ends at time 522 and the device chip 304 enters the transaction state 530. In the transaction state 530, the host chip 302 can send a command 532 on the MOSI line 312, which causes the device chip 304 to send data 534 on the MISO line 310.

[0044] Similarly, the present disclosure provides a stop transaction sequence to preserve the stop transaction function of the omitted chip select pin. Figure 6 This process 600 is illustrated. The process 600 begins with the host chip 302 determining that the end of a transaction has occurred and detecting the final MISO state (block 602). Note that the detection of the final MISO state is related to block 406 described above. Then, the host chip 302 holds the clock signal at a logical high (block 604). The device chip 304 samples the clock signal within a predetermined number of clock cycles of the internal clock 320 to detect and confirm the change to a logical high (block 606). The device chip 304 sends a stop ACK by reversing the MISO line (block 608). The host chip 302 receives the stop ACK and de-asserts the clock signal (block 610). The device chip 304 samples the clock within a predetermined number of clock cycles of the internal clock 320 to detect and confirm the logical low of the clock signal (block 612), and sends a second stop ACK by reversing the MISO line back to its original "final state" and enters the idle state (block 614). The host chip 302 receives the second stop ACK and enters the idle state (block 616).

[0045] Figure 7 A signaling diagram 700 that provides the stop sequence. The host chip 302 starts in the transaction state 702, where the clock signal is active (704) on the clock line 308 (shown by line 510). Also, data 706 is transmitted on the MISO line 310 (indicated by line 514). When transmitting data 706, the MOSI line 312 (indicated by line 512) is static. As the host chip 302 reaches the end of the transaction state 702, the host chip 302 drives the clock line 308 to a logic high 708 to enter the stop transaction state 710. The device chip 304 in the transaction state 712 initially holds the MISO line 310 in the last state (generally at 714), while the device chip 304 samples the clock line 308 at the clock pin 324A from the internal clock 320 for a sufficient number of clock cycles to determine and confirm the extended logic high, and then reverses the MISO line 310 (generally at 716) to provide a stop ACK to the host chip 302 and enter the stop state 718. Upon receiving the stop ACK, the host chip 302 drives the clock line 308 to a logic low at 720. The device chip 304 sends a second stop ACK by reversing the MISO line 310 again (generally at 722) and enters the idle state 724. Upon receiving the second stop ACK, the host chip 302 also enters the idle state 726.

[0046] Although there are various ways to implement the bus interfaces 318, 324 and the control circuits 316, 322, Figure 8 and Figure 9 two exemplary block diagrams are provided that respectively show how these bus interfaces and these control circuits can be implemented in the host chip 302 and the device chip 304. In this regard, Figure 8 a circuit 800 for the host chip 302 is illustrated, and Figure 9 a circuit 900 for the device chip 304 is illustrated.

[0047] Refer to Figure 8, the circuit 800 may have a state machine 802 that transitions between an idle state 804, a start state 806, a transaction state 808, and a stop state 810. When the state machine 802 enters the start state 806, a signal is sent to an "OR" gate 812, which sends a request to a handshake-based synchronizer circuit 814. When the state machine 802 enters the stop state 810, the "OR" gate 812 also receives a signal. The synchronizer circuit 814 receives a clock signal from a clock 314 and generates a request signal to a multiplexer 816, which controls the signal on the clock line 308. The multiplexer 816 also receives a clock signal from a host finite state machine (FSM) 818. A multiplexer 820 is similarly coupled to the MISO line 310, and an "AND" gate 822 is coupled to the MOSI line 312. The signal from the MISO line 310 is provided to the host FSM 818 and the synchronizer circuit 814, and this signal indicates that various ACKs have been received from the slave chip 304.

[0048] Reference Figure 9 , the circuit 900 may have a state machine 902 that transitions between an idle state 904, a start state 906, a transaction state 908, and a stop state 910. The clock signal from the clock line 308 is provided to a start / stop detector circuit 912, which uses a local clock 320 to test the clock signal for "N" cycles to determine whether the clock signal is being held at a logic high or a logic low. That is, if each sample in N cycles of the local clock 320 is the same, the device chip 304 infers that the clock signal is being held at a certain level. Then, the start / stop detector circuit 912 may output the detected signal 914 to the state machine 902. The clock signal is also applied to a multiplexer 916, which outputs a one or a zero depending on the state. The zero is output to a device FSM 918, while the one is output to a handshake-based synchronizer circuit 920. The synchronizer circuit 920 also receives a signal from the local clock 320 and outputs an ACK, as well as ACK_Edge1 and ACK_Edge2 signals, to a multiplexer 922. The device FSM 918 is also coupled to the multiplexer 922 to control the MISO line 310. The MOSI line 312 is coupled to an "AND" gate 924, which provides a signal to the device FSM 918.

[0049] Systems and methods for chip operations using a serial peripheral interface (SPI) without a chip select pin, in accordance with aspects disclosed herein, can be provided in or integrated into any processor-based device. Non-limiting examples include: set-top boxes, entertainment units, navigation devices, communication devices, fixed location data units, mobile location data units, global positioning system (GPS) devices, mobile phones, cellular phones, smart phones, session initiation protocol (SIP) phones, tablet devices, phablets, servers, computers, portable computers, mobile computing devices, wearable computing devices (e.g., smart watches, health or fitness trackers, glasses, etc.), desktop computers, personal digital assistants (PDAs), monitors, computer monitors, televisions, tuners, radios, satellite radios, music players, digital music players, portable music players, digital video players, video players, digital video disc (DVD) players, portable digital video players, automobiles, vehicle components, avionics systems, drones, and multi-rotor aircraft.

[0050] In this regard, Figure 10 is a system-level block diagram of an exemplary mobile terminal 1000 such as a smart phone, a mobile computing device tablet, etc. While the mobile terminal is specifically envisioned as being able to benefit from the exemplary aspects of the present disclosure, it should be understood that the present disclosure is not limited thereto and can be used in any system having an SPI bus.

[0051] Continuing to refer to Figure 10 , the mobile terminal 1000 includes an application processor 1004 (sometimes referred to as the host), which communicates with a mass storage element 1006 via a universal flash storage (UFS) bus 1008. The application processor 1004 may further be connected to a display 1010 via a display serial interface (DSI) bus 1012 and to a camera 1014 via a camera serial interface (CSI) bus 1016. Various audio components (such as a microphone 1018, a speaker 1020, and an audio codec 1022) may be coupled to the application processor 1004 via a serial low-power inter-chip multimedia bus (SLIMbus) 1024. Additionally, the audio components may communicate with each other via a SOUNDWIRE bus 1026. A modem 1028 may also be coupled to the SLIMbus 1024 and / or the SOUNDWIRE bus 1026. The modem 1028 may further be connected to the application processor 1004 via a peripheral component interconnect (PCI) or high-speed PCI (PCIe) bus 1030 and / or a system power management interface (SPMI) bus 1032.

[0052] Continuing to refer to Figure 10, the SPMI bus 1032 can also be coupled to a local area network (LAN or WLAN) IC (LAN IC or WLAN IC) 1034, a power management integrated circuit (PMIC) 1036, an accompanying IC (sometimes referred to as a bridge chip) 1038, and a radio frequency IC (RFIC) 1040. It should be understood that separate PCI buses 1042 and 1044 can also couple the application processor 1004 to the accompanying IC 1038 and the WLAN IC 1034. The application processor 1004 can further be connected to the sensor 1046 through a sensor bus 1048 (which can be an SPI bus). The modem 1028 and the RFIC 1040 can communicate using the bus 1050.

[0053] Continuing to refer Figure 10 , the RFIC 1040 can be coupled to one or more RFFE components, such as an antenna tuner 1052, a switch 1054, and a power amplifier 1056, through a radio frequency front end (RFFE) bus 1058. Additionally, the RFIC 1040 can be coupled to an envelope tracking power supply (ETPS) 1060 through a bus 1062, and the ETPS 1060 can communicate with the power amplifier 1056. These RFFE components (including the RFIC 1040) together can be considered an RFFE system 1064. It should be understood that the RFFE bus 1058 can be formed by a clock line and a data line (not illustrated).

[0054] Those skilled in the art will further appreciate that the various illustrative logical blocks, modules, circuits, and algorithms described in connection with the aspects disclosed herein can be implemented as electronic hardware, instructions stored in memory or another computer-readable medium and executed by a processor or other processing device, or a combination of both. As an example, the master and slave devices described herein can be employed in any circuit, hardware component, integrated circuit (IC), or IC chip. The memory disclosed herein can be of any type and size and can be configured to store any type of information desired. To clearly illustrate this interchangeability, the functions of the various illustrative components, blocks, modules, circuits, and steps have been described generally above. How such functionality is implemented depends on the particular application, design choices, and / or design constraints imposed on the overall system. Those skilled in the art can implement the described functionality in different ways for each particular application, but such specific implementation decisions should not be construed as causing a departure from the scope of the present disclosure.

[0055] The various illustrative logical blocks, modules, and circuits described in connection with the aspects disclosed herein may be implemented or performed with a processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. The processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors cooperating with a DSP core, or any other such configuration).

[0056] Aspects disclosed herein may be implemented in hardware and instructions stored in hardware, and may reside in, for example, random access memory (RAM), flash memory, read only memory (ROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, a hard disk, a removable disk, a CD-ROM, or any other form of computer readable medium known in the art. The exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a remote station. In the alternative, the processor and the storage medium may reside as discrete components in a remote station, base station, or server.

[0057] It is also noted that the operational steps described in any of the exemplary aspects herein are described for purposes of example and discussion. The described operations may be performed in numerous different orders other than the illustrated order. Additionally, the operations described in a single operational step may in fact be performed in multiple different steps. Further, one or more of the operational steps discussed in the exemplary aspects may be combined. It will be understood that numerous different modifications may be made to the operational steps illustrated in the flowcharts, as will be apparent to those of ordinary skill in the art. Those of ordinary skill in the art will also understand that any of a variety of different technologies and processes may be used to represent information and signals. For example, data, instructions, commands, information, signals, bits, symbols, and chips referred to throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0058] The previous description of the present disclosure is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to the present disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations. Therefore, the present disclosure is not intended to be limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0059] Specific implementation examples are described in the following numbered clauses:

[0060] 1. An integrated circuit (IC) comprising:

[0061] A bus interface, the bus interface comprising:

[0062] A clock pin configured to be coupled to a clock line on an associated bus;

[0063] An input pin configured to be coupled to an input line on the associated bus; and

[0064] An output pin configured to be coupled to an output line on the associated bus; and

[0065] A control circuit configured to:

[0066] Detect a change on the clock pin;

[0067] Send an acknowledgement (ACK) of detecting the change on the output pin;

[0068] After sending the ACK, detect a subsequent change on the clock pin; and

[0069] Send a second ACK on the output pin.

[0070] 2. The IC according to clause 1, wherein the bus interface comprises a serial peripheral interface (SPI) bus interface.

[0071] 3. The IC according to clause 2, wherein the bus interface does not include a chip select pin.

[0072] 4. The IC according to clause 2 or 3, wherein the input pin comprises a master output slave input (MOSI) pin, and the clock pin comprises an SCLK pin.

[0073] 5. The IC according to clauses 2 to 4, wherein the output pin comprises a master input slave output (MISO) pin.

[0074] 6. The IC according to any of the preceding clauses, further comprising an internal clock coupled to the control circuit.

[0075] 7. The IC according to clause 6, wherein the control circuit is configured to detect the change on the clock pin by detecting a transition from a logic high to a logic low for a predetermined number of clock cycles of the internal clock on the clock pin.

[0076] 8. The IC according to clause 6, wherein the control circuit is configured to detect the subsequent change on the clock pin by detecting a transition from a logic low to a logic high for a predetermined number of clock cycles of the internal clock on the clock pin.

[0077] 9. The IC according to clauses 6 to 8, wherein the control circuit is configured to send the ACK by reversing the logic level from an initial logic level on the output pin to a new logic level and maintaining the new logic level.

[0078] 10. The IC according to clause 9, wherein the control circuit is configured to send the second ACK by returning the output pin to the initial logic level and maintaining the initial logic level.

[0079] 11. The IC according to clause 9, wherein the control circuit is configured to determine the initial logic level based on the last state from a previous transaction.

[0080] 12. The IC according to any one of the previous clauses, wherein the control circuit is configured to detect a command on the input pin after sending the second ACK.

[0081] 13. The IC according to any one of the previous clauses, wherein the control circuit is further configured to detect a stop command by being configured to perform the following:

[0082] Detecting that the clock signal on the clock line is being held at a logic high;

[0083] Sending a first stop ACK on the output pin;

[0084] Detecting that the clock signal has changed to a logic low; and

[0085] Sending a second stop ACK on the output pin.

[0086] 14. An integrated circuit (IC) comprising:

[0087] A bus interface, the bus interface comprising:

[0088] A clock pin configured to be coupled to a clock line on an associated bus;

[0089] An input pin configured to be coupled to an input line on the associated bus; and

[0090] An output pin configured to be coupled to an output line on the associated bus; and

[0091] A control circuit configured to:

[0092] Hold the clock signal on the clock pin at a logic high;

[0093] Change the clock signal to a logic low;

[0094] Receive an acknowledgement (ACK) of the detected change on the input pin;

[0095] After receiving the ACK, change the clock signal to the logic high; and

[0096] Receive a second ACK on the input pin.

[0097] 15. The IC according to clause 14, wherein the bus interface includes a Serial Peripheral Interface (SPI) bus interface.

[0098] 16. The IC according to clause 15, wherein the bus interface does not include a chip select pin.

[0099] 17. The IC according to clause 15 or 16, wherein the output pin includes a Master Output Slave Input (MOSI) pin.

[0100] 18. The IC according to clauses 15 to 17, wherein the input pin includes a Master Input Slave Output (MISO) pin.

[0101] 19. The IC according to any one of clauses 14 to 18, wherein the control circuit is configured to send a command on the output pin after receiving the second ACK.

[0102] 20. The IC according to any one of clauses 14 to 19, wherein the control circuit is further configured to send a stop command by being configured to perform the following operations:

[0103] Hold the clock signal on the clock line at the logic high;

[0104] Receive a first stop ACK on the input pin;

[0105] Change the clock signal to the logic low; and

[0106] Receive a second stop ACK on the input pin.

[0107] 21. A method for controlling a Serial Peripheral Interface (SPI) bus, the method comprising:

[0108] Detecting a change on a clock pin;

[0109] Sending an acknowledgement (ACK) of detecting the change on an output pin;

[0110] After sending the ACK, detecting a subsequent change on the clock pin; and

[0111] Sending a second ACK on the output pin.

[0112] 22. The method according to clause 21, further comprising:

[0113] Detecting that a clock signal on the clock pin is being held at a logic high;

[0114] Sending a first stop ACK on the output pin;

[0115] Detecting that the clock signal has changed to a logic low; and

[0116] Sending a second stop ACK on the output pin.

[0117] 23. A method for controlling a Serial Peripheral Interface (SPI) bus, the method comprising:

[0118] Holding a clock signal on a clock pin at a logic high;

[0119] Changing the clock signal to a logic low;

[0120] Receiving an acknowledgement (ACK) of detecting the change on an input pin;

[0121] After receiving the ACK, changing the clock signal to the logic high; and

[0122] Receiving a second ACK on the input pin.

[0123] 24. The method according to clause 23, further comprising:

[0124] Holding the clock signal on the clock pin at the logic high;

[0125] Receiving a first stop ACK on the input pin;

[0126] Changing the clock signal to the logic low; and

[0127] Receiving a second stop ACK on the input pin.

Claims

1. An integrated circuit IC, comprising: A bus interface, the bus interface comprising: A clock pin configured to be coupled to a clock line on an associated bus; An input pin configured to be coupled to an input line on the associated bus; and An output pin configured to be coupled to an output line on the associated bus; and A control circuit configured to: Detect a change on the clock pin; Send an acknowledgement ACK of detecting the change on the output pin; After sending the ACK, detect a subsequent change on the clock pin; and Send a second ACK on the output pin.

2. The IC according to claim 1, wherein the bus interface comprises a Serial Peripheral Interface SPI bus interface.

3. The IC according to claim 2, wherein the bus interface does not include a chip select pin.

4. The IC according to claim 2, wherein the input pin comprises a Master Output Slave Input MOSI pin, and the clock pin comprises an SCLK pin.

5. The IC according to claim 2, wherein the output pin comprises a Master Input Slave Output MISO pin.

6. The IC according to claim 1, further comprising an internal clock coupled to the control circuit.

7. The IC according to claim 6, wherein the control circuit is configured to detect the change on the clock pin by detecting a transition from a logic high to a logic low that persists for a predetermined number of clock cycles of the internal clock on the clock pin.

8. The IC according to claim 6, wherein the control circuit is configured to detect the subsequent change on the clock pin by detecting a transition from a logic low to a logic high that persists for a predetermined number of clock cycles of the internal clock on the clock pin.

9. The IC according to claim 6, wherein the control circuit is configured to send the ACK by reversing a logic level from an initial logic level on the output pin to a new logic level and maintaining the new logic level.

10. The IC according to claim 9, wherein the control circuit is configured to send the second ACK by returning the output pin to the initial logic level and maintaining the initial logic level.

11. The IC according to claim 9, wherein the control circuit is configured to determine the initial logic level based on the last state from a previous transaction.

12. The IC according to claim 1, wherein the control circuit is configured to detect a command on the input pin after sending the second ACK.

13. The IC according to claim 1, wherein the control circuit is further configured to detect a stop command by being configured to perform the following operations: Detect that a clock signal on the clock line is being held at a logic high; Send a first stop ACK on the output pin; Detect that the clock signal has changed to a logic low; and Send a second stop ACK on the output pin.

14. An integrated circuit IC, comprising: A bus interface, the bus interface comprising: A clock pin configured to be coupled to a clock line on an associated bus; An input pin configured to be coupled to an input line on the associated bus; and An output pin configured to be coupled to an output line on the associated bus; and A control circuit configured to: Hold a clock signal on the clock pin at a logic high; Change the clock signal to a logic low; Receive an acknowledgement ACK of the detected change on the input pin; After receiving the ACK, change the clock signal to the logic high; and Receive a second ACK on the input pin.

15. The IC according to claim 14, wherein the bus interface comprises a Serial Peripheral Interface (SPI) bus interface.

16. The IC according to claim 15, wherein the bus interface does not include a chip select pin.

17. The IC according to claim 15, wherein the output pin comprises a Master Output Slave Input (MOSI) pin.

18. The IC according to claim 15, wherein the input pin comprises a Master Input Slave Output (MISO) pin.

19. The IC according to claim 14, wherein the control circuit is configured to send a command on the output pin after receiving the second ACK.

20. The IC according to claim 14, wherein the control circuit is further configured to send a stop command by being configured to perform the following operations: Hold the clock signal on the clock line at the logic high; Receive a first stop ACK on the input pin; Change the clock signal to the logic low; And Receive a second stop ACK on the input pin.

21. A method for controlling a Serial Peripheral Interface (SPI) bus, the method comprising: Detecting a change on a clock pin; Sending an acknowledgement ACK of the detected change on an output pin; After sending the ACK, detecting a subsequent change on the clock pin; and Sending a second ACK on the output pin.

22. The method according to claim 21, further comprising: Detecting that a clock signal on the clock pin is being held at a logic high; Sending a first stop ACK on the output pin; Detecting that the clock signal has changed to a logic low; and Sending a second stop ACK on the output pin.

23. A method for controlling a Serial Peripheral Interface (SPI) bus, the method comprising: Holding a clock signal on a clock pin at a logic high; Changing the clock signal to a logic low; Receiving an acknowledgement ACK of the detected change on an input pin; After receiving the ACK, changing the clock signal to the logic high; And Receiving a second ACK on the input pin.

24. The method according to claim 23, further comprising: Holding the clock signal on the clock pin at the logic high; Receiving a first stop ACK on the input pin; Changing the clock signal to the logic low; And Receive a second stop ACK on the input pin.

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