A VPX power supply with abnormal information recording function and its control method

Abstract

A VPX power supply with an abnormal information recording function and a control method, which relates to the VPX power supply in power supply technology. It includes a VPX connector, a main power supply circuit, and an intelligent management circuit. One end of the VPX connector is connected to the power input, passes through the main power supply circuit, and then is connected to the power output through the other end. The intelligent management circuit includes a management unit, which is responsible for power management and information reporting. It also includes an abnormal information recording circuit. The intelligent management circuit is connected to the abnormal information recording circuit and monitors the state of the main power supply circuit. The abnormal information recording circuit is used to record power abnormal information. The abnormal information recording circuit includes an emergency power supply circuit, an RTC real-time clock circuit, and an EEPROM storage circuit. The circuit of the present invention is simple, occupies a small space, is easy to implement, meets the requirements of the high-reliability server system for rapid maintainability, saves the later maintenance time and cost, and is more convenient, faster, and more accurate in troubleshooting problems.

Description

Technical Field

[0001] The present invention relates to a VPX power supply in power supply technology, and particularly to a design of a VPX power supply with an abnormal information recording function and an intelligent management function. Background Art

[0002] A VPX server is a multi-module server. Function modules such as a power supply module, a computing module, a storage module, a switching module, and a main control module can be inserted inside the chassis. The chassis integrally controls each function module to implement functions such as operation, storage, and network interaction. Each function module is interconnected through a backplane, and system power supply, heat dissipation, etc. are uniformly realized by the chassis management in an optimized manner. A power supply module adopting the VPX (VITA62) standard supplies power to each function module inside the VPX (VITA 46) server, provides greater power design support for the server, allows the server to integrate more functions, and meets the increasingly high performance requirements in the defense and aviation fields.

[0003] One of the main advantages of a server adopting the VPX architecture is the manageability of the device. The VPX architecture provides powerful chassis management capabilities for monitoring the health status of the device, error / event management, and providing an interface for system management. Management involves heat dissipation, power supply system, temperature monitoring, power-on and reset, etc.

[0004] Currently, the intelligent management function of a conventional VPX power supply is based on the normal power supply of the power supply. Once faults such as abnormal shutdown, abnormal power loss and restart of the input, and abnormal output voltage occur in the power supply, problems such as information cannot be reported and cannot be viewed will be faced. In addition, when a fault occurs, personnel are mostly not on site, the device location is remote, the user requires a limited troubleshooting time, and even the fault is not easy to reproduce, etc., which bring many difficulties to troubleshooting problems. Summary of the Invention

[0005] The present invention aims to solve at least one of the technical problems existing in the prior art.

[0006] The technical solution of the present invention is as follows: A VPX power supply with an abnormal information recording function includes a VPX connector, a main power supply circuit, and an intelligent management circuit. One end of the VPX connector is connected to the power input, passes through the main power supply circuit, and then is connected to the power output through the other end; the intelligent management circuit includes a management unit for responsible for power management and information reporting;

[0007] It further includes an abnormal information recording circuit,

[0008] The intelligent management circuit is connected to the abnormal information recording circuit and monitors the state of the main power supply circuit;

[0009] The abnormal information recording circuit is used to record power supply abnormal information,

[0010] The abnormal information recording circuit includes an emergency power supply circuit, an RTC real-time clock circuit, and an EEPROM storage circuit.

[0011] The emergency power supply circuit, the RTC real-time clock circuit, and the EEPROM storage circuit are respectively connected to the management unit.

[0012] The emergency power supply circuit supplies power to the management unit, the RTC real-time clock circuit, and the EEPROM storage circuit.

[0013] The RTC real-time clock circuit is used to provide time information to the management unit.

[0014] The management unit is responsible for collecting abnormal information and receiving time information, and records the detected abnormal information in the EEPROM storage circuit in the format of time, type, and numerical information.

[0015] The EEPROM storage circuit is used to store the abnormal information sent by the management unit.

[0016] The management unit is connected to the VPX connector through an external serial port interface, and then prints the abnormal information recorded in the EEPROM storage circuit.

[0017] The main power supply circuit includes an input filter circuit, multiple main power supplies, and a redundancy circuit. After the power input is filtered by the input filter circuit, it is converted into the voltage required by the backplane cards of the chassis by the multiple main power supplies, and then connected to the power output through the redundancy circuit to supply power to the backplane cards.

[0018] The power-on of all main power supplies is controlled by the ENABLE power-on signal and the INHIBIT inhibit signal, and meets the power-on timing requirements.

[0019] The intelligent management circuit further includes an auxiliary power supply, an LDO circuit, and an isolation buffer. After the power input is filtered by the input filter circuit, the auxiliary power supply supplies power to the management unit through the LDO circuit. The management unit collects the output voltage, current, and temperature information, controls the status of the power indicator, and communicates with the chassis through two I2C buses after passing through the isolation buffer, and reports the voltage, current, and temperature information of each path to the chassis.

[0020] The emergency power supply circuit includes a hot plug current limiting circuit, an emergency power supply conversion circuit, and an RCD buffer energy storage circuit. The input end of the emergency power supply conversion circuit is connected to the hot plug current limiting circuit, and the output end is connected to the RCD buffer energy storage circuit.

[0021] The hot plug current limiting circuit is connected to the input filter circuit and includes a fuse F1, a current limiting resistor RT1, and a current limiting resistor R1 connected in sequence.

[0022] The emergency power supply conversion circuit includes a module power supply G1. One path of the module power supply G1 supplies power to the management unit and the EEPROM storage circuit through an LDO circuit, and the other path supplies power to the RTC real-time clock circuit;

[0023] The RCD buffer energy storage circuit includes a resistor R2, capacitors C1, C2, C3, C4, an inductor L1, and a diode D1.

[0024] The capacitors C1, C2, C3, and C4 are connected in parallel. The resistor R2 and the capacitor C3 are connected in series. The diode D1 is connected in parallel with the resistor R2 and in series with the capacitor C3;

[0025] The inductor L1 and the capacitor C4 form an LC filter.

[0026] The single-chip microcomputer in the management unit uses the GigaDevice GD32F103RET6 chip.

[0027] The RTC real-time clock circuit uses the Shanghai Belling BM8563EMA chip.

[0028] The EEPROM storage circuit uses the Fudan Microelectronics FM24C512D chip.

[0029] A control method for a VPX power supply with an abnormal information recording function. The management unit is connected to the RTC real-time clock circuit and the EEPROM storage circuit through an I2C bus. When abnormal information is collected, it triggers log recording and stores the alarm log in a specified area;

[0030] Specifically, it includes power-on state detection, alarm state judgment, and alarm log storage that are executed in sequence;

[0031] The power-on state detection is used to detect whether the power supply is in the on state. After detecting that the power supply is turned on, the alarm state judgment is performed;

[0032] The alarm state judgment is used to judge whether there is abnormal information in the power supply. If there is abnormal information, it triggers log recording and stores the alarm log;

[0033] The alarm log storage is used to store abnormal information and record the abnormal information in a specified area in the format of time, type, and numerical information.

[0034] The alarm state judgment includes:

[0035] In the management unit, the single-chip microcomputer obtains power input, multi-channel output voltage, multi-channel output current, temperature, ENABLE, and INHIBIT signal data through ADC pins, compares the acquired data information with a preset threshold, and records the alarm information when any one of the power input, multi-channel output voltage, multi-channel output current, temperature, ENABLE, and INHIBIT signals is abnormal.

[0036] When there are abnormal data of the same type in the voltage or current data, the number of times of the alarm log information of this type is judged; if the collected data is normal, it is judged whether the previous collected data of the voltage or current is abnormal. If the previous collected data is abnormal, a log record of the status recovery of the voltage or current collected this time is made.

[0037] The alarm log storage includes:

[0038] A maximum storage quantity of log information is preset. When the number of stored logs reaches the set threshold, the subsequent stored data is rollback-recorded.

[0039] Each alarm log information consists of 12 bytes. Among them, the 1st to 7th bytes store the recording time of this log, the 8th byte stores the alarm type of this log, and the 9th to 12th bytes store the corresponding voltage or current value when this log is recorded.

[0040] When printing alarm log information, different alarms are separated by delimiters. After recording 3 to 4 pieces of the same alarm information, the recording stops until new abnormalities occur and then new alarms start to be recorded.

[0041] In the operation of the present invention, the original circuit resources are fully utilized, and the function of recording abnormal information is added. It has both the conventional VPX power supply function and can record abnormal information when the power supply fails. The management unit is used to collect abnormal information and receive the time information of the RTC real-time clock circuit. The detected abnormal information is recorded in the EEPROM storage circuit. When abnormal data is needed, the information recorded is printed out by connecting the single-chip microcomputer serial port to a computer, solving the problems that information cannot be reported, viewed, and the fault cannot be accurately located when the power supply fails. The circuit of the present invention is simple, occupies a small space, is easy to implement, meets the requirements of rapid maintainability of high-reliability server systems, saves the later maintenance time and cost, and is more convenient, faster, and more accurate in troubleshooting problems. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings required for the description of the specific embodiments or the prior art. In the drawings, each part is not necessarily drawn according to the actual ratio.

[0043] Figure 1 is the principle block diagram of the present invention,

[0044] Figure 2 is the emergency power supply circuit diagram,

[0045] Figure 3 is the connection relationship diagram of the single-chip microcomputer abnormal information record,

[0046] Figure 4 is the alarm log record flow chart,

[0047] Figure 5 is the power-on state detection flow chart,

[0048] Figure 6 is the alarm state judgment flow chart,

[0049] Figure 7 is the alarm log storage flow chart,

[0050] Figure 8 is the block diagram of the alarm log information composition,

[0051] Figure 9 is the alarm log print information diagram. Detailed implementation manners

[0052] The present invention provides a VPX power supply circuit with an abnormal information recording function, which includes a VPX connector, a main power supply circuit, an intelligent management circuit, and an abnormal information recording circuit. One end of the VPX connector is connected to the power input, passes through the main power supply circuit, and then is connected to the power output through the other end. The intelligent management circuit includes a management unit for responsible for power management and information reporting. The management unit is managed by a single-chip microcomputer;

[0053] Figure 1 The circuit in the dashed box is the added abnormal information recording circuit,

[0054] The intelligent management circuit is connected to the abnormal information recording circuit and monitors the state of the main power supply circuit.

[0055] The main power supply circuit mainly consists of an input filter circuit, multiple main power supplies, a redundancy circuit, etc. The power input from the VPX connector is filtered by the input filter circuit, and then is converted into the voltage required by the backplane cards of the chassis by the multiple main power supplies. After passing through the redundancy circuit, it reaches the output end of the VPX connector and supplies power to the backplane cards. The power-on of all main power supplies is controlled by the ENABLE power-on signal and the INHIBIT inhibit signal, and meets the power-on timing requirements.

[0056] The intelligent management circuit mainly consists of an auxiliary power supply, an LDO circuit, an isolation buffer, etc. The power input from the VPX connector is filtered by the input filter circuit, and then the auxiliary power supply supplies power to the LDO circuit. Among them, the auxiliary power supply has priority in power supply. After being converted by the LDO circuit into 3.3V, it supplies power to the management unit. The management unit collects the output voltage, current, and temperature information, and at the same time controls the status of the power indicator light, and communicates with the chassis through two I2C buses after passing through the isolation buffer, and reports the voltage, current, and temperature information of each path to the chassis. The LDO circuit and the redundant circuit in the present invention are conventional circuits.

[0057] The abnormal information recording circuit is responsible for recording power supply abnormal information.

[0058] The abnormal information recording circuit includes an emergency power supply circuit, an RTC real-time clock circuit, and an EEPROM storage circuit.

[0059] The management unit is respectively connected to the emergency power supply circuit, the RTC real-time clock circuit, and the EEPROM storage circuit.

[0060] The emergency power supply circuit supplies power to the management unit, the RTC real-time clock circuit, and the EEPROM storage circuit.

[0061] The emergency power supply circuit generates +5V_BACK2 standby power. One path is converted into 3.3V through the LDO circuit to supply power to the management unit and the EEPROM storage circuit, and the other path supplies power to the RTC real-time clock circuit, ensuring that even in the case of abnormal input power supply and auxiliary power supply, the single-chip microcomputer and the EEPROM storage circuit are supplied with power through the emergency power supply for several seconds until the single-chip microcomputer stores the detected abnormal information.

[0062] The abnormal recording function is not only effective when there is an internal fault in the power supply, but also can cope with the sudden power failure of the external input. It is realized by adding an emergency power supply circuit to supply power to the chips related to abnormal recording. In addition, the power supply of the chips related to abnormal recording adopts a dual redundancy measure, that is, both the auxiliary power supply and the emergency power supply are used for power supply, and the reliability is high.

[0063] The RTC real-time clock circuit is responsible for providing the time information of "year, month, day, hour, minute, second, week" to the single-chip microcomputer of the management unit.

[0064] The RTC real-time clock circuit is composed of a Shanghai Belling BM8563EMA (MSOP8 package) chip plus an oscillator circuit. It is a low-power CMOS real-time clock / calendar chip that provides a programmable clock output, an interrupt output, and a power-down detector. All addresses and data are serially transmitted through the I2C bus interface. It has two power supply channels, one from the two-way 5V standby power supply and the other from a 3V button battery, ensuring that the RTC circuit keeps continuous timing during both power-on and power-off periods. When the power is on, the 5V standby power supply is used to save battery power.

[0065] The EEPROM storage circuit is used to store the abnormal information sent by the single-chip microcomputer.

[0066] The EEPROM storage circuit is composed of a Fudan Microelectronics FM24C512D (TSSOP8 package) chip plus address configuration resistors. It is a 64KB serial electrically erasable programmable memory with 512 pages internally, and each page has 127 bytes. The address of any unit is 16 bits, with a compact structure and a large storage capacity.

[0067] The management unit is responsible for collecting abnormal information and receiving time information, and records the detected abnormal information in the EEPROM storage circuit in the format of time, type, and numerical information.

[0068] The single-chip microcomputer of the management unit is composed of a GigaDevice GD32F103RET6 (LQFP64 package) chip. It is a general-purpose 32-bit ARM processor with rich peripheral interfaces. The chip integrates various peripheral functions such as timers, CAN, ADC, SPI, I2C, and UART, and is especially suitable for microcontroller designs that balance high performance and low power consumption.

[0069] The management unit is connected to the VPX connector through an external serial port interface, and then prints the abnormal information recorded in the EEPROM storage circuit.

[0070] The external serial port interface is directly led out from the UART port of the single-chip microcomputer and is connected to the corresponding signals of the VPX connector. Through a serial-to-USB device, it is connected to the computer USB port to print the recorded information and can save the log in the form of a file.

[0071] The abnormal information detection signal in the present invention corresponds to the real-time state of the power supply, including power input, multiple output voltages, multiple output currents, temperature, ENABLE, and INHIBIT signals, and is used to send to the single-chip microcomputer for detection.

[0072] The power input, multiple output voltages, multiple output currents, temperature, ENABLE, and INHIBIT signals are connected to the ADC port of the single-chip microcomputer. The power input signal is used to monitor whether the external input power supply can supply power normally; the multiple output voltages are used to monitor whether the output voltages of each main power supply are normal; the multiple output currents are used to monitor whether the output currents of each main power supply exceed the maximum threshold; the temperature signal is used to monitor the heat dissipation of the power supply and whether it exceeds the maximum threshold; the ENABLE signal is used to monitor whether the power supply is in the boot state; the INHIBIT signal is used to monitor whether the output of the main power supply is prohibited.

[0073] The emergency power supply circuit includes a hot plug current limiting circuit, an emergency power supply conversion circuit, and an RCD buffer energy storage circuit. The specific circuit is as Figure 2 shown.

[0074] The input end of the emergency power supply conversion circuit is connected to the hot plug current limiting circuit, and the output end is connected to the RCD buffer energy storage circuit.

[0075] The hot plug current limiting circuit includes a fuse F1, a current limiting resistor RT1, and a current limiting resistor R1 connected in sequence.

[0076] The hot plug current limiting circuit prevents a large instantaneous current from being generated when the power supply is hot-plugged, which may cause impact damage to the VPX connector and the emergency power supply conversion circuit. Resistors R1 and RT1 are used for current limiting, and F1 is used for isolation after a fault.

[0077] The emergency power supply conversion circuit consists of a module power supply G1.

[0078] The module power supply G1 is a ultra-small volume module power supply with a wide voltage input and a 5V / 3W output. It is responsible for converting the AC power input into +5V_BACK2 standby power. One path is converted into 3.3V through an LDO circuit to supply power to the management unit and the EEPROM storage circuit, and the other path supplies power to the RTC real-time clock circuit.

[0079] The RCD buffer energy storage circuit includes a resistor R2, capacitors C1, C2, C3, C4, an inductor L1, and a diode D1.

[0080] Mainly utilize large-capacity electrolytic capacitors C2 and C3 to store electrical energy, so that even when the input power supply is abnormal, it can supply power to the subsequent circuit for several seconds, ensuring that the single-chip microcomputer stores the detected abnormal information in the EEPROM. Due to the requirement of the maximum capacitive load limit for the power conversion circuit, the capacitance of capacitor C2 cannot be infinitely large. Therefore, a buffer energy storage circuit composed of R2, C3 and D1 is adopted, which can not only expand the energy storage capacity from the capacity of C2 to the capacity of C2 + C3, but also solve the limitation of the maximum capacitive load. Among them, the resistor R2 is connected in series with the capacitor C3 to form a charging circuit, and the resistor R2 is used to limit the charging current. The diode D1 connected in parallel with the resistor R2 is connected in series with the capacitor C3 to form a discharging circuit, allowing the load to absorb the required energy from the capacitor C3 through the diode D1 without being hindered by the resistor. Once the power input is abnormal, the electrical energy stored in the electrolytic capacitors C2 and C3 supplies power to the subsequent circuit. The capacitance values of the capacitors C2 and C3 can be estimated according to parameters such as the load power, the required holding time, the maximum and minimum voltages that can maintain the normal operation of the subsequent stage on the capacitor.

[0081] The capacitors C1, C2, C3 and C4 are connected in parallel. The inductor L1 and the capacitor C4 form an LC filter to reduce the output ripple; the capacitor C1 is used for filtering to remove high-frequency noise.

[0082] The present invention makes full use of the original circuit resources, adds an abnormal information recording function, has both the conventional VPX power supply function and can record abnormal information when the power supply fails. The single-chip microcomputer of the management unit is used to collect abnormal information, receive the time information of the RTC real-time clock circuit, and record the detected abnormal information in the EEPROM storage circuit. When abnormal data is required, the information recorded is printed out by connecting the single-chip microcomputer serial port to a computer, providing information for quickly locating the power supply fault.

[0083] A control method for a VPX power supply with an abnormal information recording function provides alarm log recording and is designed based on the single-chip microcomputer GD32F103RET6, the storage chip FM24C512D and the clock chip BM8563EMA.

[0084] The single-chip microcomputer GD32F103RET6 is connected to the storage chip FM24C512D and the clock chip BM8563EMA through the I2C bus, and the connection relationship is as Figure 3 shown.

[0085] Once abnormal information is collected, trigger log recording and store the alarm log in the specified area of the FM24C512D chip.

[0086] The method for recording the alarm log is as Figure 4 shown, mainly composed of three processes: power-on state detection, alarm state judgment and alarm log storage, and they are executed in sequence.

[0087] The power-on state detection is used to detect whether the power supply is in the on state. After detecting that the power supply is turned on, the alarm state is then judged.

[0088] The power-on state detection process is as Figure 5 shown. The alarm log function starts recording after the power supply is turned on. The VPX power supply ENABLE enable signal is the power-on signal (i.e., the PC12 pin of the single-chip microcomputer). When the level of this pin is low, the current power supply is considered to be in the on state. When the level of this pin is high, the current power supply is considered to be in the off state. To prevent the abnormal ENABLE enable signal of the power supply, when the ENABLE enable signal of the power supply is detected to be high, the current 12V voltage of the power supply is further detected. If the 12V voltage is normal, the current power supply is considered to be in the on state, otherwise the current power supply is considered to be in the off state. After the power supply is first detected to be turned on, the current power-on time of the power supply is obtained, and the power-on log of the power supply is recorded. Here, not only the "ENABLE enable signal corresponding to the PC12 pin" is detected, but also the "main output 12V" is detected to prevent one of them from failing and ensure reliability.

[0089] The alarm state judgment is used to judge whether there is abnormal information in the power supply. If there is abnormal information, the log recording is triggered and the alarm log is stored.

[0090] The alarm state judgment process is as Figure 6 shown. The single-chip microcomputer obtains the power input, multi-channel output voltage, multi-channel output current, temperature, ENABLE, and INHIBIT signal data of the device through the ADC pin, and compares the obtained data information with the pre-set threshold. Once an abnormality is detected in any one of the power input, multi-channel output voltage, multi-channel output current, temperature, ENABLE, and INHIBIT signals, the alarm information is recorded. When there are abnormal data of the same type such as voltage or current, the number of times of this type of alarm log information is judged to avoid repeated and useless alarm information. If the collected data is normal, it is judged whether the previous collected data of the voltage or current and other signals is abnormal. If the previous collected data is abnormal, the log recording of the status recovery of the voltage or current and other signals collected this time is performed.

[0091] The alarm log storage is used to store the abnormal information, and the abnormal information is recorded in the specified area of the FM24C512D chip in the format of time, type, and numerical information.

[0092] The alarm log storage process is as Figure 7 shown. The alarm log information is stored in the storage chip FM24C512D. To prevent data overflow in storage, the maximum storage quantity of the log information can be pre-set. When the number of stored logs reaches the set threshold, the subsequent stored data is recorded in a rollback manner. The block diagram of the composition of the alarm log information is asFigure 8 As shown, each alarm log message consists of 12 bytes. Among them, the 1st to 7th bytes store the recording time of this log, the 8th byte stores the alarm type of this log, and the 9th to 12th bytes store the corresponding voltage or current values when this log is recorded. The alarm log print information is as Figure 9 shown. Different alarms are separated by delimiters. After recording 3 to 4 messages of the same alarm, the recording stops to prevent occupying storage space until a new exception occurs and then new alarms start to be recorded.

[0093] The present invention solves the problems that when conventional VPX power supplies have faults such as abnormal shutdown, abnormal power failure and restart of input, and abnormal output voltage, they cannot report information, cannot view information, and cannot accurately locate faults.

[0094] The alarm log record provided by the present invention is designed based on the single-chip microcomputer GD32F103RET6, the storage chip FM24C512D, and the clock chip BM8563EMA. The abnormal information is recorded in the specified area of the FM24C512D chip in the format of time, type, and numerical information. The information storage capacity is large, it is convenient to view, and the readability is strong.

[0095] The abnormal information recorded by the present invention is convenient to read and has strong operability. It does not require complex peripherals, does not require powering on the power supply, and does not require professional personnel. It can be used for users to assist in troubleshooting. Users view the relevant instruction documents in the manual, connect a laptop computer and a universal serial port to USB cable to the corresponding serial port of the power supply to read, and send the read file to professional personnel to facilitate quick fault location.

[0096] Although the embodiments of the present invention have been shown and described, for those of ordinary skill in the art, it can be understood that various changes, modifications, substitutions, and variations can be made to these embodiments without departing from the principles and spirit of the present invention. The scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A VPX power supply with an abnormal information recording function, comprising a VPX connector, a main power supply circuit and an intelligent management circuit. One end of the VPX connector is connected to the power input, passes through the main power supply circuit, and then is connected to the power output through the other end. The intelligent management circuit includes a management unit responsible for power management and information reporting. The main power supply circuit includes an input filter circuit, multiple main power supplies and a redundancy circuit. After being filtered by the input filter circuit, the power input is converted into the voltage required by the backplane cards of the chassis by the multiple main power supplies, and then is connected to the power output through the redundancy circuit to supply power to the backplane cards. The power-on of all main power supplies is controlled by the ENABLE power-on signal and the INHIBIT inhibit signal, and meets the power-on timing requirements. The intelligent management circuit further includes an auxiliary power supply, an LDO circuit and an isolation buffer. After being filtered by the input filter circuit, the power input is used to supply power to the management unit by the auxiliary power supply through the LDO circuit. The management unit collects the output voltage, current and temperature information, controls the status of the power indicator at the same time, and communicates with the chassis through two I2C buses after passing through the isolation buffer, and reports the voltage, current and temperature information of each path to the chassis. Characterized in that , further including an abnormal information recording circuit. The intelligent management circuit is connected to the abnormal information recording circuit and monitors the status of the main power supply circuit. The abnormal information recording circuit is used to record the power supply abnormal information. The abnormal information recording circuit includes an emergency power supply circuit, an RTC real-time clock circuit and an EEPROM storage circuit. The emergency power supply circuit, the RTC real-time clock circuit and the EEPROM storage circuit are respectively connected to the management unit. The emergency power supply circuit supplies power to the management unit, the RTC real-time clock circuit and the EEPROM storage circuit. The RTC real-time clock circuit is used to provide time information to the management unit. The management unit is responsible for abnormal information collection and receiving time information, and records the detected abnormal information in the EEPROM storage circuit in the format of time, type and numerical information. The EEPROM storage circuit is used to store the abnormal information sent by the management unit. The management unit is connected to the VPX connector through an external serial port interface, and then prints the abnormal information recorded in the EEPROM storage circuit. The emergency power supply circuit includes a hot plug current limiting circuit, an emergency power supply conversion circuit and an RCD buffer energy storage circuit. The input end of the emergency power supply conversion circuit is connected to the hot plug current limiting circuit, and the output end is connected to the RCD buffer energy storage circuit. The hot plug current limiting circuit is connected to the input filter circuit and includes a fuse F1, a current limiting resistor RT1 and a current limiting resistor R1 connected in sequence. The emergency power supply conversion circuit includes a module power supply G1. One path of the module power supply G1 supplies power to the management unit and the EEPROM storage circuit through an LDO circuit, and the other path supplies power to the RTC real-time clock circuit. The RCD buffer energy storage circuit includes a resistor R2, capacitors C1, C2, C3, C4, an inductor L1 and a diode D1. The capacitor C1, capacitor C2, capacitor C3, and capacitor C4 are connected in parallel. The resistor R2 and capacitor C3 are connected in series. The diode D1 is connected in parallel with the resistor R2 and in series with the capacitor C3; The inductor L1 and capacitor C4 form an LC filter.

2. The VPX power supply with an abnormal information recording function according to claim 1, wherein The single-chip microcomputer in the management unit uses the GigaDevice GD32F103RET6 chip.

3. A VPX power supply with an abnormal information recording function according to claim 1, characterized in that, The RTC real-time clock circuit uses the Shanghai Belling BM8563EMA chip.

4. A VPX power supply with an abnormal information recording function according to claim 1, characterized in that, The EEPROM storage circuit uses the Fudan Microelectronics FM24C512D chip.

5. A control method for a VPX power supply with an abnormal information recording function according to any one of claims 1-4, characterized in that, The management unit is connected to the RTC real-time clock circuit and the EEPROM storage circuit through the I2C bus. When abnormal information is collected, it triggers log recording and stores the alarm log in a specified area; Specifically, it includes power-on state detection, alarm state judgment, and alarm log storage executed in sequence; The power-on state detection is used to detect whether the power supply is in the on state. After detecting that the power supply is turned on, the alarm state judgment is performed; The alarm state judgment is used to judge whether there is abnormal information in the power supply. If there is abnormal information, it triggers log recording and stores the alarm log; The alarm log storage is used to store abnormal information and record the abnormal information in a specified area in the format of time, type, and numerical information; 6. The control method of a VPX power supply with an abnormal information recording function according to claim 5, characterized in that The alarm state judgment includes: The single-chip microcomputer in the management unit obtains power input, multi-channel output voltage, multi-channel output current, temperature, ENABLE, and INHIBIT signal data through the ADC pin, compares the obtained data information with a preset threshold, and records the alarm information when any one of the power input, multi-channel output voltage, multi-channel output current, temperature, ENABLE, and INHIBIT signals is detected to be abnormal; When the voltage or current data shows the same type of data abnormality, the number of times of the alarm log information of this type is judged; if the collected data is normal, it is judged whether the previous collected data of this voltage or current is abnormal. If the previous collected data is abnormal, a log record of the status recovery of the voltage or current collected this time is made.

7. The control method of a VPX power supply with an abnormal information recording function according to claim 5, characterized in that, The alarm log storage includes: The maximum storage quantity of log information is preset. When the number of stored logs reaches the set threshold, the subsequent stored data is rollback-recorded; Each alarm log information consists of 12 bytes. Among them, the 1st to 7th bytes store the recording time of this log, the 8th byte stores the alarm type of this log, and the 9th to 12th bytes store the corresponding voltage or current value at the time of this log recording; When printing the alarm log information, different alarms are separated by delimiters. After recording 3 to 4 pieces of the same alarm information, the recording stops until new abnormalities appear and then new alarms start to be recorded.

Images