Task allocation method, circuit, device, medium and program

Abstract

The present application discloses a task allocation method, circuit, device, medium and program, wherein the task allocation method comprises: obtaining the number of first registers matching the task to be allocated; determining the number of second registers in each of at least two stream processors that are in an idle state; determining a target stream processor from the stream processors whose number of the second registers is greater than or equal to the number of the first registers; and allocating the task to be allocated to the second register in the target stream processor. In this way, the allocation efficiency and processing efficiency of the task to be allocated in the structure composed of at least two stream processors can be improved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of information technology, and in particular, to a task allocation method, circuit, device, medium and program. Background Art

[0002] In the related art, when tasks are allocated in a system structure composed of multiple stream processors, there will usually be a stream processor that is saturated with related task processing due to polling and waiting, which will block the task scheduling of other stream processors; this may easily lead to a series of problems such as slow task processing efficiency due to untimely task allocation. Summary of the invention

[0003] In view of this, the embodiments of the present application at least provide a task allocation method, circuit, device, medium and program, which aim to improve the allocation efficiency and processing efficiency of the tasks to be allocated in a structure composed of at least two stream processors.

[0004] In order to achieve the above object, an embodiment of the present application provides a task allocation method, which includes:

[0005] Get the number of first registers matched by the task to be assigned;

[0006] In at least two stream processors, determining the number of second registers in each of the stream processors that are in an idle state;

[0007] Determine a target stream processor from stream processors whose number of the second registers is greater than or equal to the number of the first registers;

[0008] Allocate the task to be allocated to a second register in the target stream processor.

[0009] The present application provides a task allocation circuit, the task allocation circuit comprising:

[0010] The task management unit is configured to obtain the number of first registers matched by the task to be assigned;

[0011] A resource management unit is configured to determine, in at least two stream processors, a number of second registers in each of the stream processors that are in an idle state;

[0012] The resource management unit is further configured to determine a target stream processor from stream processors whose number of the second registers is greater than or equal to the number of the first registers;

[0013] The allocating unit is configured to allocate the to-be-allocated task to a second register in the target stream processor.

[0014] Accordingly, an embodiment of the present application provides a computer device, which includes a memory and a processor, wherein the memory stores computer executable instructions, and when the processor runs the computer executable instructions on the memory, it can implement any of the above-mentioned task allocation methods.

[0015] An embodiment of the present application provides a computer-readable storage medium, on which computer-executable instructions are stored. After the computer-executable instructions are executed, any of the above-mentioned task allocation methods can be implemented.

[0016] An embodiment of the present application provides a computer program product, which includes a computer program or instructions. When the computer program or instructions are executed by a processor, any of the above-mentioned task allocation methods is implemented.

[0017] The embodiment of the present application provides a task allocation method, circuit, device, medium and program. First, the number of first registers matched by the task to be allocated is obtained; and in at least two stream processors, the number of second registers in an idle state in each stream processor is determined; in this way, a parameter basis can be provided for the subsequent allocation of the task to be allocated to the target stream processor in at least two stream processors. Then, the target stream processor is determined from the stream processors whose number of second registers is greater than or equal to the number of first registers; and the task to be allocated is allocated to the second register in the target stream processor. In this way, the register resources (available register resources) in an idle state in each stream processor in multiple different stream processors and the resources of the first register matched by the task to be allocated are compared, so that the task to be allocated can be allocated conveniently and efficiently. And compared with the related art, it can reduce the phenomenon of blocking the scheduling of other stream processor tasks due to polling and waiting for the stream processors that are saturated with the related task processing, so as to improve the allocation efficiency and processing efficiency of the task to be allocated in the structure composed of at least two stream processors as a whole.

[0018] It should be understood that the above general description and the following detailed description are merely exemplary and explanatory, and are not intended to limit the technical solutions provided in the embodiments of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative work, among which:

[0020] Figure 1 Schematic diagram of the task allocation method provided in some embodiments of the present application Figure 1 ;

[0021] Figure 2 Schematic diagram of the task allocation method provided in some embodiments of the present application Figure 2 ;

[0022] Figure 3 Schematic diagram of the task allocation method provided in some embodiments of the present application Figure 3 ;

[0023] Figure 4 A diagram of a register resource framework corresponding to multiple stream processors in a graphics processor in the related art;

[0024] Figure 5 A management framework diagram corresponding to multiple different register resources in a single stream processor in the related art;

[0025] Figure 6 A schematic diagram of a resource management unit in a task allocation method provided in some embodiments of the present application;

[0026] Figure 7 A schematic diagram of discrete task allocation by the task allocation method provided in some embodiments of the present application;

[0027] Figure 8 A schematic diagram of a system framework for performing task allocation using a task allocation method provided in some embodiments of the present application;

[0028] Fig. 9 A schematic diagram of the structure of a task allocation circuit provided in some embodiments of the present application;

[0029] Fig.10 This is a schematic diagram of the composition structure of computer devices in some embodiments of the present application. DETAILED DESCRIPTION

[0030] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the specific technical solution of the invention will be further described in detail below in conjunction with the drawings in the embodiments of the present application. The following embodiments are used to illustrate the embodiments of the present application, but are not used to limit the scope of the embodiments of the present application.

[0031] In the following description, reference is made to “some embodiments”, which describe a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0032] In the following description, the terms "first\second\third" involved are merely used to distinguish similar objects and do not represent a specific ordering of the objects. It can be understood that "first\second\third" can be interchanged with a specific order or sequence where permitted, so that the embodiments of the present application described here can be implemented in an order other than that illustrated or described here.

[0033] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the technical field of the present application. The terms used herein are only for the purpose of describing the embodiments of the present application and are not intended to limit the embodiments of the present application.

[0034] Before further describing the embodiments of the present application in detail, the nouns and terms involved in the embodiments of the present application are explained. The nouns and terms involved in the embodiments of the present application are subject to the following interpretations.

[0035] 1) Stream processors: There are two types: programmable and non-programmable. Stream processors can process stream data and also output a stream of data. This stream data can be applied to other superscalar stream processors (SPs). Stream processors can run in groups or in large numbers, thereby greatly improving parallel processing capabilities.

[0036] 2) Register: Its function is to store binary code. It is composed of flip-flops with storage function. One flip-flop can store 1 bit of binary code, so a register that stores n bits of binary code needs to be composed of n flip-flops.

[0037] The following describes an exemplary application of the task allocation method provided in an embodiment of the present application. The task allocation method provided in an embodiment of the present application can be applied to various types of user terminals with image acquisition functions, such as laptop computers, tablet computers, desktop computers, cameras, mobile devices (for example, personal digital assistants, dedicated messaging devices, portable gaming devices), and the like, and can also be implemented as a server.

[0038] The task allocation method can be applied to a computer device. The functions implemented by the method can be implemented by calling a program code by a processor in the computer device. Of course, the program code can be stored in a computer storage medium. It can be seen that the computer device at least includes a processor and a storage medium.

[0039] The present application embodiment provides a task allocation method. In a possible implementation, the task allocation method is implemented by an integrated circuit. The integrated circuit is designed with a resource management unit, which manages discrete resources in one or more stream processors. Figure 1FIG. 1 is a flow chart of a task allocation method provided in some embodiments of the present application. Figure 1 ; The following combination Figure 1 The following steps are explained:

[0040] Step S101, obtaining the number of first registers matched by the tasks to be assigned.

[0041] In some embodiments of the present application, the task allocation method can be applied to a task allocation circuit, which includes at least two stream processors, that is, the number of stream processors included in the task allocation circuit can be determined according to actual needs (two, or more than two); and at least two stream processors can receive and process multiple tasks to be assigned in parallel.

[0042] In some embodiments of the present application, the task to be assigned may refer to attribute data associated with the related task or request before it is formed, or task data corresponding to the related task or request after it is formed.

[0043] In some embodiments of the present application, the number of first registers that match the task to be assigned may be determined based on the memory size required by the task to be assigned. Here, the default number of first registers may be converted using the memory size corresponding to the first register as a unit.

[0044] In some embodiments of the present application, the number of first registers matched by the tasks to be assigned may be one, or may be two or more, and the number here depends on the actual requirements of the tasks to be assigned.

[0045] It can be understood that, through the above steps, obtaining the number of first registers matching the task to be assigned can provide a parameter basis for subsequently allocating the task to be assigned to the registers in the corresponding stream processor, thereby more efficiently and accurately improving the allocation efficiency and processing efficiency of the task to be assigned in the multi-stream processor.

[0046] Step S102: in at least two stream processors, determine the number of second registers in each of the stream processors that are in an idle state.

[0047] In some embodiments of the present application, at least two stream processors may refer to a stream multiprocessor (Stream Multi-processor, SM), each of which may be regarded as a processor with a smaller structure. Here, continuing from the above description, since the number of stream processors can directly affect the processing performance of the device in the same level of architecture, when the task allocation circuit includes at least two stream processors, it has a higher processing capability.

[0048] It should be noted that when the task allocation circuit includes at least two stream processors, a resource management unit can usually be used to manage the at least two stream processors, such as: task allocation matters corresponding to each stream processor, the time corresponding to each stream processor processing related tasks, etc.

[0049] In some embodiments of the present application, the second register in an idle state in each stream processor may refer to a register that has no data, or a register that has no associated tasks assigned to it, or a register that is not currently processing any associated tasks, etc.

[0050] In some embodiments of the present application, the number of second registers in an idle state in different stream processors may be equal or different. For example, the number of second registers in an idle state in a first stream processor is 5, the number of second registers in an idle state in a second stream processor is 10, and so on.

[0051] The first stream processor and the second stream processor may be adjacent or non-adjacent stream processors.

[0052] In some embodiments of the present application, the number of second registers in an idle state in each stream processor can also be determined in at least two stream processors based on the task attributes associated with the task to be assigned. Exemplarily, when the task to be assigned is attribute data associated with the related task or request before generation, the number of attribute registers in an idle state in each stream processor can be determined; when the task to be assigned is task data corresponding to the related task or request after formation, the number of general registers in an idle state in each stream processor can be determined.

[0053] It should be noted that general registers can be used to transmit and temporarily store data, participate in arithmetic and logical operations, and save the results of operations. They can be accessed and used by any instruction in the program. At the same time, attribute registers are registers with specific functions, which are used to store relevant attribute data, such as private data, address information, attribute information, etc. Here, general registers and attribute registers play an important role in the device. The functions, quantities, register bit widths, and usage of the two are different. Among them, general registers and attribute registers cooperate with each other to complete various tasks of the device.

[0054] In some embodiments of the present application, the number of second registers in each stream processor that are in an idle state, that is, the number of second registers that can be currently used to store (load) the task to be assigned, can be counted. Here, when there are multiple second registers in an idle state in each stream processor, the corresponding register numbers of the multiple second registers in each stream processor can be continuous or discontinuous. In addition, the number of second registers in an idle state in the stream processor can be one, multiple, or zero, and the embodiments of the present application do not impose any limitation on this.

[0055] It can be understood that, through the above steps, obtaining the number of second registers in each stream processor that are in an idle state can also provide a parameter basis for subsequently allocating the tasks to be allocated to the registers in the corresponding stream processor.

[0056] Step S103: Determine a target stream processor from the stream processors whose number of the second registers is greater than or equal to the number of the first registers.

[0057] In some embodiments of the present application, the number of first registers may be compared with the number of second registers in each stream processor to select a target stream processor from at least two stream processors.

[0058] In some embodiments of the present application, first, the number of second registers in each stream processor can be compared with the number of first registers, so as to select at least one intermediate stream processor whose number of second registers is greater than or equal to the number of first registers; then, a target stream processor is selected from the at least one intermediate stream processor. Here, the target stream processor can be the stream processor corresponding to the largest number of second registers, or the second largest number, etc., in the at least one intermediate stream processor.

[0059] It should be noted that if there is no stream processor in at least two stream processors whose number of second registers is greater than or equal to the number of first registers, the allocation operation of the task to be allocated can be suspended, that is, waiting for the number of second registers in at least two stream processors to be updated (here, because the related allocated tasks before the task to be allocated have been executed, the registers will be released accordingly and changed to second registers in an idle state), so as to measure again whether there is a stream processor in at least two stream processors whose number of second registers is greater than or equal to the number of first registers based on the updated number of second registers.

[0060] It can be understood that, through the above steps, by performing a quantity comparison operation, a target stream processor is determined from at least two stream processors, so that the tasks to be assigned can be assigned conveniently and efficiently.

[0061] Step S104, allocating the task to be allocated to the second register in the target stream processor.

[0062] In some embodiments of the present application, the task to be assigned may be assigned to a second register in a target stream processor for caching or loading.

[0063] In some embodiments of the present application, when the number of second registers in the target stream processor to which the task to be assigned is assigned is multiple, the corresponding numbers in the target stream processor may be continuous or discontinuous. Here, the multiple discontinuous or continuous second registers may be virtualized as continuous storage space for storing the task to be assigned.

[0064] In some embodiments of the present application, it is further possible to determine whether other resources in the target stream processor are sufficient, so that when all resources in the target stream processor are sufficient, the task to be assigned is assigned to the second register in the target stream processor. In addition, after the task to be assigned is assigned to the second register in the target stream processor, the identification information corresponding to the second register and the identification information of the target stream processor can be synchronously fed back to the task assignment circuit, so that the task assignment circuit can subsequently query and retrieve the task to be assigned.

[0065] In some embodiments of the present application, the number of first registers can be further converted into the number of first register rows, wherein each register row includes at least two registers with consecutive numbers in the same stream processor. Accordingly, the number of second registers in each stream processor can be converted into the number of second register rows in each stream processor, so that the target stream processor can be determined from the stream processors whose number of second register rows is greater than or equal to the number of first register rows, so that the tasks to be assigned can be subsequently assigned to the second register rows in the target stream processor.

[0066] Continuing from the above description, first, according to the memory size occupied by the task to be assigned, the number of first registers required for the task to be assigned is determined, and at the same time, the number of second registers in each stream processor in at least two stream processors that are in an idle state is determined; then, the determined number of first registers and the number of second registers in each stream processor are compared to select a target stream processor from the at least two stream processors. Here, the comparison can be performed by converting the number of second registers and the number of first registers by register rows, thereby determining the corresponding target stream processor, and then allocating the task to be assigned to the second register in the target stream processor for caching.

[0067] It can be understood that, through the above steps, by comparing the register resources (available register resources) in the idle state in each stream processor among the multiple different stream processors and the resources of the first register matched by the task to be assigned, the task to be assigned can be efficiently assigned. And compared with the related art, it can reduce the phenomenon of blocking the scheduling of tasks of other stream processors due to the stream processors that are saturated with polling and waiting for the related tasks, thereby improving the overall allocation efficiency and processing efficiency of the task to be assigned in the structure composed of at least two stream processors.

[0068] In some embodiments of the present application, when each register row includes at least two consecutively numbered registers in the same stream processor, the number of the first registers can be converted into the number of the first register row, and the number of the second registers can be converted into the number of the second register row, so that the determination of the target stream processor in the above step S103 can be implemented by the following step S201, referring to Figure 2 , which is a flowchart of a task allocation method provided in some embodiments of the present application Figure 2 , combined with Figure 2 The steps shown are explained below:

[0069] Step S201 : determining the target stream processor from the stream processors whose number of the second register rows is greater than or equal to the number of the first register rows.

[0070] In some embodiments of the present application, the number of second registers can be converted into the number of second register rows, and the number of first registers can be converted into the number of first register rows. Exemplarily, when each register row includes 4 consecutively numbered registers in the same stream processor, the number of second registers is 32; correspondingly, the number of second register rows is 8, and the number of first registers is 30, and the corresponding number of first register rows is also 8.

[0071] In some embodiments of the present application, a target stream processor whose relevant parameters meet preset conditions is selected from stream processors whose number of second register rows is greater than or equal to the number of first register rows. Here, the stream processor with the largest number of second register rows, or the second largest number, or the stream processor with the longest idle time of the second register row may be selected, and the embodiments of the present application do not impose any limitation on this.

[0072] It should be noted that, in the multiple registers in the stream processor, discrete management or continuous management can be performed according to the corresponding allocation granularity. Here, the granularity corresponds to the size of the register; wherein the allocation granularity can be expressed as the minimum amount allocated each time the memory is requested.

[0073] In a feasible implementation, step S201 provided in the above embodiment can be implemented by the following steps S2011 and S2012 (not shown in the figure):

[0074] Step S2011: among the stream processors whose number of second register rows is greater than or equal to the number of first register rows, select the stream processor whose number of second register rows is the largest.

[0075] Step S2012: determine the stream processor with the largest number of the second register rows as the target register.

[0076] It can be understood that, through the above steps, the stream processor with the most available resources (the stream processor with the largest number of second register rows) is selected. In this way, in the architecture corresponding to at least two stream processors, not only the allocation strategy is made more accurate, but also more abundant resources can be reserved for subsequent new tasks.

[0077] Correspondingly, step S104 provided in the above embodiment can be implemented by the following step S202:

[0078] Step S202: Allocate the task to be assigned to the second register row in the target stream processor.

[0079] In some embodiments of the present application, the task to be assigned may be assigned to the second register row in the target stream processor. Here, when the number of the second register rows is two or more, the numbers of at least two second register rows are not limited to continuous or discrete.

[0080] It can be understood that, through the above steps, the target stream processor is determined in the stream processors whose number of second register rows is greater than or equal to the number of first register rows. On the one hand, it is possible to load or store the task to be assigned to the second register row in the target stream processor; on the other hand, because the index information of the register row is relatively small compared to the index information of the register, the index information of the subsequent related registers can be reduced, and thus the cache space of the related index information can be reduced.

[0081] In some embodiments of the present application, the above step S202 allocates the task to be allocated to the second register row in the target stream processor, which can be achieved by the following steps S301 and S302. Figure 3 FIG. 1 is a flow chart of a task allocation method provided in some embodiments of the present application. Figure 3 , combined with Figure 3 The steps shown are explained below:

[0082] Step S301, selecting N target register rows from the M second register rows in the target stream processor using a multi-way search method.

[0083] Wherein, M is the number of second register rows in the target stream processor; N is the number of the first register rows; and the row numbers corresponding to the N target register rows are continuous or discrete.

[0084] In some embodiments of the present application, N register rows whose row numbers may be continuous or discontinuous are selected from the M second register rows in the target stream processor. Here, M is greater than or equal to N (corresponding to the above-mentioned: the target stream processor is determined from the stream processors whose number of second register rows is greater than or equal to the number of first register rows); at the same time, in the target stream processor, a multi-way search method is adopted to improve the acquisition efficiency of determining multiple target register rows in the target stream processor.

[0085] It should be noted that in the embodiments of the present application, M and N are both positive integers.

[0086] In some embodiments of the present application, the allocation unit in the task allocation circuit (including at least two stream processors inside) may select N target register rows from the M second register rows in the target stream processor by using a multi-way search method. Here, the multi-way search method is to search for target information in relevant information through multiple paths or multiple nodes. That is to say, the allocation unit in the task allocation circuit selects N target register rows randomly or according to a preset selection rule from the M second register rows in the target stream processor by using a search method of multiple nodes or multiple paths. Exemplarily, when it is determined that there are M second register rows in the target stream processor, the M second register rows may be divided, such as being divided into I×J second register rows in equal proportion (here, J is less than N), and at least one target register row is selected from each of the J second register rows (such as: one target register row is selected from a part of the J register rows, and multiple target register rows are selected from a part of the J register rows) to obtain N target register rows.

[0087] In a feasible implementation, due to different attributes of the tasks to be assigned, the corresponding storage or load spaces in the stream processor, that is, the matched register types are different. Correspondingly, step S301 provided in the above embodiment can be implemented by dividing into the following two cases, namely, corresponding steps S3011 and S3012 (not shown in the figure):

[0088] Step S3011, when the task to be assigned is attribute data to be assigned before task formation, the N target attribute register rows are selected from the M attribute register rows in the target stream processor that are in an idle state using the multi-way search method.

[0089] Step S3012, when the task to be assigned is the assembled task data to be assigned, the N target general data register rows are selected from the M general data register rows in the idle state in the target stream processor using the multi-way search method.

[0090] In some embodiments of the present application, different registers within the target stream processor are selected based on the different attributes of the tasks to be assigned, so that the corresponding tasks to be assigned (i.e., the tasks to be assigned that have been assembled, or the tasks to be assigned before being assembled) are stored in the general data register rows, or, attribute register rows, within the target stream processor.

[0091] In some embodiments of the present application, the attribute data to be allocated before the task is formed can be used to characterize the attribute information of the thread data that forms the task, such as address information, private data, etc. Here, the thread data that forms the task, such as vertices, geometry, pixels, or computing units, etc.

[0092] It can be understood that, through the above steps, when the task to be assigned is the attribute data corresponding to the related task before it is formed, the corresponding storage space in the target stream processor is the attribute register, and when the task to be assigned is the task data corresponding to the task after it is formed, the corresponding storage space in the target stream processor is the general data register. In this way, based on the different attributes of the tasks, that is, the data types involved in the tasks to be assigned, the adapted register rows are correspondingly selected from the M second register rows in the target stream processor for allocation, so that the allocation is more accurate.

[0093] Step S302: virtualize the selected N target register rows into sequentially continuous storage spaces for storing the tasks to be assigned.

[0094] In some embodiments of the present application, the determined N target register rows may be defaulted to corresponding continuous storage spaces for storing related tasks to be assigned.

[0095] It can be understood that through the above steps, on the one hand, the use of a multi-way search method in the target stream processor can improve the acquisition efficiency of determining multiple target register rows in the target stream processor; on the other hand, by allocating the tasks to be assigned in the target stream processor without being limited to continuous storage space (registers), discrete allocation or continuous allocation can be performed, which can improve the allocation efficiency of the tasks to be assigned in the target stream processor.

[0096] Continuing from the above description, before obtaining the number of first registers matching the task to be assigned so as to subsequently assign the task to be assigned to the second register in the target stream processor, a compliance check needs to be performed on the task to be assigned, that is, the task assignment method provided in the embodiment of the present application can also perform the following steps A1 and A2:

[0097] Step A1, put the initial task,into the task sequence for compliance check.

[0098] Step A2: Remove the dependency of the initial task whose compliance check result is passed from the task sequence, and determine the initial task whose compliance check result is passed as the task to be assigned.

[0099] In some embodiments of the present application, for the initial task, that is, the task to which registers are subsequently allocated, a compliance check may first be performed. Here, the compliance check is used to ensure whether the initial task meets the preset requirements (which depend on the actual needs) so that after the initial task is subsequently allocated to the corresponding register, the relevant program or command can normally view or call the relevant information of the initial task.

[0100] It should be noted that the task sequence can be used to store multiple subsequent register allocation tasks. Here, before the initial task is placed in the task sequence, the task sequence may be empty or not empty (ie, tasks that are undergoing compliance checks or tasks waiting for compliance checks are stored therein).

[0101] In some embodiments of the present application, the result of the compliance check can be expressed as pass or fail, or as compliant or non-compliant, and the embodiments of the present application do not impose any limitation on this.

[0102] In some embodiments of the present application, when the result of the compliance check corresponding to the initial task is passed, the initial task can be released from the task sequence, that is, the dependency is released (the sequential dependency in the task sequence is released), and the initial task is determined as a task to be assigned.

[0103] It should be noted that if the result of the compliance check is failure, the initial task can be adjusted or processed according to the relevant execution strategy in the task allocation circuit.

[0104] It is understandable that through the above steps, based on the compliance check result, it is determined whether the initial task needs to perform subsequent register allocation, that is, whether it is a task to be allocated. In this way, a basis can be provided for the allocation of registers for subsequent tasks to be allocated, thereby ensuring the normal allocation of registers involved in subsequent tasks to be allocated.

[0105] Continuing with the above description, when the number of tasks to be assigned is at least two, the task assignment method provided in the embodiment of the present application may further perform the following steps B1 and B2:

[0106] Step B1, sorting the at least two tasks to be assigned from longest to shortest according to the waiting time for assignment, to obtain a queue of tasks to be assigned.

[0107] Step B2: Allocate the tasks to be assigned in sequence according to the order in the task queue to be assigned.

[0108] In some embodiments of the present application, at least two tasks to be assigned can be queued in order from long to short according to their corresponding waiting allocation time, so that the tasks to be assigned can be allocated in turn in the register row of the corresponding target stream processor according to the order of the tasks to be assigned in the queue.

[0109] Here, the execution logic corresponding to the tasks to be assigned may be further obtained, so as to jointly determine the assignment order of the related tasks to be assigned according to the order in the queue of tasks to be assigned and the execution logic corresponding to the tasks to be assigned.

[0110] It can be understood that through the above steps, by sorting the waiting allocation time of the tasks to be assigned, and selecting the tasks to be assigned with the longest waiting allocation time for priority sorting, the waiting time for allocation and processing of the related tasks to be assigned can be reduced, thereby further improving the allocation efficiency of the tasks to be assigned.

[0111] Based on the above embodiment, after the tasks to be assigned are stored in the N target register rows in the target stream processor, index information associated with the row numbers of the N target register rows may be generated accordingly, so as to facilitate the subsequent search and traversal of related information; that is, after executing step S302, the task assignment method provided in the embodiment of the present application may further execute the following steps C1 and C2:

[0112] Step C1, obtaining an index table corresponding to a register row in the target stream processor.

[0113] In some embodiments of the present application, the index table corresponding to the register row in the target stream processor may be stored in advance by the task allocation circuit, and it may change with the change of the register row in the target stream processor. For example, the index table may be characterized as: the address of register row 1: xx1-xx2, the address of register row 2: xx2-xx5, etc. Here, register row 1 and register row 2 are both register rows in the target stream processor.

[0114] It should be noted that an index table is a database structure, which is a special data structure composed of one or more columns in a data table. Its main function is to provide a fast data access method to facilitate data search and sorting. By creating a specific index structure on the data table, the index table can reduce the amount of data that the database needs to process, thereby improving query efficiency and overall system performance.

[0115] In some embodiments of the present application, there is an index table for registers in each stream processor of at least two stream processors, and correspondingly, a register row in each stream processor corresponds to an index table.

[0116] Step C2: determining, in the index table, index information associated with the row numbers of the N target register rows.

[0117] In some embodiments of the present application, the index information may be described using numerical values ​​or text, and may also be directly the row numbers of the N target register rows.

[0118] It should be noted that the index information is a correspondence table between column values ​​and record rows established in a certain order based on one or several columns in the table. In essence, it is an ordered table that describes the one-to-one correspondence between the column values ​​of the index column and the record rows in the original table.

[0119] It can be understood that, through the above steps, the index information associated with the row numbers of the N target register rows is obtained from the index table, so as to facilitate the subsequent search for loading or storing the task to be allocated.

[0120] In some embodiments, the number of corresponding available register rows in the target stream processor is updated synchronously, that is, determined based on the subtraction of M and N.

[0121] Correspondingly, after generating the corresponding index information, the task allocation method provided in the embodiment of the present application may further perform the following steps C3 and C4:

[0122] Step C3: when the execution of the task to be assigned is completed, clear the index information.

[0123] Step C4: based on the N, increase the number of available register rows in the updated target stream processor for use by the next task to be assigned.

[0124] The updated number of available register rows in the target stream processor is the difference between the M and the N.

[0125] In some embodiments of the present application, when the task to be assigned is completed, that is, the task to be assigned is executed in sequence according to the corresponding execution logic and ends as a whole, the relevant index information can be cleared, and the number of available register rows in the updated target stream processor, that is, the count value, is updated again for the next task to be assigned. The above operations are performed in a loop in sequence, so that the task allocation circuit including at least two stream processors, in the process of allocating registers for the task to be assigned, checks the register resources in each stream processor that are in an idle state, so as to select a more suitable target stream processor based on the register resources required by the task to be assigned, that is, the number of first registers, and allocate the task to be assigned to the relevant registers in the target stream processor for storage.

[0126] It can be understood that, through the above steps, the allocation efficiency and processing efficiency of the tasks to be allocated in the task allocation circuit including at least two stream processors can be improved as a whole.

[0127] The above-mentioned task allocation method is described below in conjunction with a specific embodiment. However, it is worth noting that this specific embodiment is only for better illustrating the embodiment of the present application and does not constitute an improper limitation on the embodiment of the present application.

[0128] Graphics Processing Unit (GPU) usually contains multiple register types of resources, such as general data registers, attribute registers, etc., which are usually used to store attribute data or private data or address related information, and the corresponding register usage is generally large. For example, in general, any system process (instance) of each Single Instruction Multiple Data (SIMD) Thread can be allocated dozens to more than 200. Figure 4 As shown, a multi-stream processor management unit 401 (here, a multi-stream processor is at least two stream processors) in a GPU manages multiple stream processors. Figure 4As shown, the management of any stream processor, that is, the register resources included in the stream processor 4011 is used as an example for explanation. The stream processor 4011 includes multiple different types of register resources, such as: general data register 40111, attribute register 40112, constant register 40113, constant register 40114, scalar register 40115 and mask register 40116; wherein, the general data register 40111, attribute register 40112 and constant register 40113 are usually dynamically allocated during the execution of related tasks, while the constant register 40114, scalar register 40115 and mask register 40116 are all bound and allocated. In addition, the related storage resources involved in the GPU, such as: Figure 4 As shown in: shared memory 4012, other available resources (including Figure 4 Other available resources 1, i.e. 4013, other available resources 2, i.e. 4014, . . .), etc. are shown in FIG.

[0129] It should be noted that the corresponding numbers of different types of registers included in any stream processor may be equal or unequal.

[0130] Here, if Figure 5 As shown, Figure 4 The register resources in the stream processor 4011 shown in FIG. 4 are usually managed by a unified resource management unit 501 in the GPU (the resource management unit 501 may be configured according to actual needs, such as: Figure 4 The multi-stream processor management unit 401 shown in FIG. 1 is integrated together or can be separated) to centrally manage, so that management is convenient and simple. Correspondingly, Figure 5 502 shown in the figure, namely: resource type 1 to resource type n, refer to register type 1 to register type n in sequence; and, each stream processor 4011 contains multiple types of registers of different types, and the register resources in each stream processor 4011 are managed separately.

[0131] It should be noted that the attribute registers in the stream processor are usually allocated before the task is formed. Through the method of pre-loading, all the corresponding relevant attribute data are loaded before the task is formed; and because the arithmetic logic unit (ALU) resources are relatively important, and the temporary (temp) resources (such as: general data registers in the stream processor) are limited. Therefore, the general data registers are usually requested to be allocated only when all tasks are ready and need to be scheduled to the stream processor for execution. In addition, in the system structure corresponding to the multi-stream processor, there is a situation where the relevant task data needs to be stored in the register in the stream processor 1, and the register resources in the stream processor 1 are temporarily unavailable, and there are available register resources in other stream processors; in the related technology, a conventional polling processing strategy is usually adopted, that is, the resource management unit and the allocation unit will always be in a state of requesting the stream processor 1 to allocate register resources for the task until the register resources are applied for in the stream processor 1, and then the allocation of the relevant task data is executed. In this way, there will be a phenomenon of blocking the task scheduling execution of other stream processors. Similarly, when scheduling related task data, when the task data to be assigned cannot continue to be assigned due to the execution logic, and the task cannot continue to be sent down for execution, the task scheduling execution of other stream processors will also be blocked.

[0132] That is to say, in a system structure composed of multiple stream processors, tasks may wait for each other when they are assigned. For example, when the tasks that have been assembled are released from dependency and task dispatch is executed, the general data registers in the stream processors that were initially pre-assigned may be saturated with storage tasks, which may cause the tasks that have been assembled to be unable to be dispatched, thus blocking the entire task dispatch exit.

[0133] Based on this, the embodiment of the present application provides a task allocation method, which fully utilizes the available register resources in each stream processor in the system structure composed of multiple stream processors to reduce the blockage in task allocation and scheduling of each stream processor, thereby achieving better task formation and task dispatch scheduling effects in the system architecture composed of multiple stream processors; the corresponding implementation ideas are as follows:

[0134] First, in a system structure composed of multiple stream processors (corresponding to the task allocation circuit provided in the embodiment of the present application), a unified resource management unit is designed, which can realize the counting of available register resources in each stream processor and perform discrete allocation management of the available register resources in each stream processor. Therefore, based on the unified resource management unit, the relevant task data in the system structure composed of multiple stream processors is allocated and counted. In this way, when assembling a new task, it is possible to determine a plurality of stream processors that can perform task allocation based on the count of available register resources of each stream processor in the multi-stream processor and the count of register resources required for assembling the new task. Here, the stream processor with the largest count of available registers and that can be allocated can be further selected for allocation. The corresponding unified resource management unit, that is, the resource management unit provided in the embodiment of the present application, can refer to the following. Figure 6 The resource management unit 501 shown in FIG. 1 can count the available amount of different register resources in each stream processor in the multi-stream processor, such as Figure 6 As shown in 601, resource type 1 (such as attribute register) increases available quantity counting information, resource type 2 (such as general data register) increases available quantity counting information, ... resource type n increases available quantity counting information, etc.

[0135] Correspondingly, if all stream processors in the system structure composed of multiple stream processors do not currently have sufficient available register resources, they can wait for the previous unfinished tasks to be completed to realize resource recovery, thereby correspondingly increasing the count of the amount of available register resources, and again performing the corresponding required register resources and available register resources comparison. At the same time, the allocation size information and the remaining amount count information are synchronized to the resource information detection unit in the task management module for recording, which is convenient for subsequent resource detection reference. In addition, after the relevant tasks are allocated to the available registers of the corresponding stream processor, the number of available registers of the corresponding stream processor, that is, the count value, can be reduced accordingly.

[0136] Exemplarily, for task data that needs to be allocated to general data registers, after completing the compliance check of the task sequence and removing the dependency, the remaining amount of available general data registers in each stream processor can be synchronously detected; the number of available general data registers is further compared, and the target stream processor is selected accordingly, and the task data is cached in the available general data registers. Here, the stream processor with the largest number of available general data registers can be selected as the target stream processor. In addition, when there are sufficient available general data registers, task allocation is performed based on the execution logic and the task data with the longest waiting time for allocation.

[0137] Here, after the task is scheduled and dispatched, it can enter the stream processor and wait for execution. When the execution is completed, the requested register resources are released, and the available register resource count is recovered and increased.

[0138] The following specific embodiment allocates the attribute parameters before task formation to the attribute registers in the corresponding target stream processor. The attribute register resource management can count the register rows according to the row allocation granularity and manage the allocation in a discrete form. Here, after the attribute register allocation amount is aligned according to the attribute register allocation granularity, based on the number of register rows that need to be allocated for the attribute parameters to be allocated, the allocable discrete available register rows are searched through a multi-way search method to allocate the attribute parameters to be allocated, and the allocated register row number is stored in the corresponding index. At the same time, the attribute register available count value is reduced by the corresponding row value; and when the task is released, the index information is cleared, and the attribute register available count value is increased by the above-mentioned released row value for use by subsequent newly allocated tasks. Figure 7 As shown, 701 is an example of entry 1 in the relevant index table, and 702 is an example of any index in entry 1 of 701, such as: showing index 1; and showing an example of an available attribute register row in a stream processor to which attribute data is assigned for index 1 in 702, 703, namely: available attribute register row 1 to available attribute register row 4. Here, the row numbers of available attribute register row 1 to available attribute register row 4 in the stream processor are discrete, i.e., discontinuous.

[0139] Compared with the related technologies, the task allocation method provided by this solution is applied to the multi-stream processor structure, and the corresponding system framework diagram when performing related task allocation is as follows: Figure 8 As shown, the multi-stream processor structure internally includes: a task management unit 801, a resource management unit 802, an allocation unit 803 and at least two stream processors 804. Here. Figure 8At least two stream processors 804 are shown to include: stream processor 1 to stream processor m; wherein m is greater than 2. Correspondingly, before the relevant assembled task data is assigned tasks in the multi-stream processor structure, the following steps need to be performed: first, through the task management unit 801, compliance check 8011 is performed in sequence: putting into the task queue for compliance check, and dependency release 8012: after the compliance check passes, the sequence number in the relevant task queue to be subjected to compliance check is released; second, after the dependency is released, register resource application 8022 is executed through the resource management unit 802. Here, before executing register resource application 8022, the resource management unit 802 needs to first perform resource information detection 8021 to obtain the count of available register resources in each stream processor in the multi-stream processor structure. In this way, the resource management unit 802 can compare the relevant available register resource information of each stream processor in the multi-stream processor structure based on the information obtained by executing resource information detection 8021, and select the stream processor in descending order according to the stream processor corresponding to the largest available remaining amount (register resource), the second largest, and so on, that is, to implement the execution application register resource 8022. The third step is to perform task allocation 8031 ​​through the allocation unit 803 to implement the allocation of task data to the target stream processor in 804 (here, the target stream processor is determined by the resource management unit 802 in the second step).

[0140] The task allocation method provided in the embodiment of the present application is applied to a task allocation circuit including at least two stream processors, which can realize that when the corresponding attribute data needs to allocate register resources before forming a task, the resource management unit can calculate in advance whether the available attribute register resources in each stream processor are sufficient, find out the stream processor with more available (idle) attribute register resources remaining, and allocate the corresponding attribute data therein. At the same time, the task data to be formed is sent to the task queue for unified scheduling management, and after the task data is released from dependency, the task data released from dependency is sent to the stream multiprocessor with sufficient available general data registers by selecting it to be sent to. In this way, in the system architecture composed of at least two stream processors, that is, in the task allocation circuit, there will be no phenomenon of blocking the corresponding allocation of other stream processors due to the queueing of related tasks to be allocated, thereby achieving the effect of making full use of the available register resources in multiple stream processors.

[0141] In addition, the task allocation method provided in the embodiment of the present application can also change some register resources into a discrete management structure when allocating related tasks to the stream processor, and use it when allocating data in the previous step, that is, judging whether the stream processor is available by counting the number of available registers as a whole. At the same time, the related tasks to be allocated can be allocated to the stream processor with the largest amount of available register resources remaining, so that the allocation of the tasks to be allocated is more accurate.

[0142] This embodiment of the application provides a task allocation circuit 900, Fig. 9 A schematic diagram of the structure of the task allocation circuit provided in the embodiment of the present application is shown in FIG. Fig. 9 As shown, the task allocation circuit 900 includes:

[0143] The task management unit 901 is configured to obtain the number of first registers matched by the tasks to be assigned;

[0144] The resource management unit 902 is configured to determine, in at least two stream processors, the number of second registers in each of the stream processors that are in an idle state;

[0145] The resource management unit 902 is further configured to determine a target stream processor from the stream processors whose number of the second registers is greater than or equal to the number of the first registers;

[0146] The allocating unit 903 is configured to allocate the to-be-allocated task to a second register in the target stream processor.

[0147] In some embodiments of the present application, each register row includes at least two consecutively numbered registers within the same stream processor; the number of the first registers includes the number of the first register rows, and the number of the second registers includes the number of the second register rows, and the resource management unit 902 is further configured to determine the target stream processor from the stream processors whose number of the second register rows is greater than or equal to the number of the first register rows; the allocation unit 903 is further configured to allocate the task to be allocated to the second register row within the target stream processor.

[0148] In some embodiments of the present application, the resource management unit 902 is further configured to select the stream processor with the largest number of second register rows among the stream processors whose number of second register rows is greater than or equal to the number of first register rows; and determine the stream processor with the largest number of second register rows as the target register.

[0149] In some embodiments of the present application, the allocation unit 903 is further configured to select N target register rows from the M second register rows in the target stream processor using a multi-way search method; wherein M is the number of second register rows in the target stream processor; N is the number of first register rows; the row numbers corresponding to the N target register rows are continuous or discrete; and the selected N target register rows are virtualized as sequentially continuous storage spaces for storing the tasks to be allocated.

[0150] In some embodiments of the present application, the allocation unit 903 is also configured to, when the task to be allocated is attribute data to be allocated before task formation, use the multi-way search method to select the N target attribute register rows from the M attribute register rows in an idle state in the target stream processor; and when the task to be allocated is task data to be allocated that has been formed, use the multi-way search method to select the N target general data register rows from the M general data register rows in an idle state in the target stream processor.

[0151] In some embodiments of the present application, the task management unit 901 is also configured to place the initial task into the task sequence for compliance check; remove the dependency of the initial task whose compliance check result is passed from the task sequence, and determine the initial task whose compliance check result is passed as the task to be assigned.

[0152] In some embodiments of the present application, when the number of tasks to be assigned is at least two, the task management unit 901 is further configured to sort the at least two tasks to be assigned from long to short according to the waiting assignment time to obtain a queue of tasks to be assigned; and to assign the tasks to be assigned in sequence according to the sorting in the queue of tasks to be assigned.

[0153] In some embodiments of the present application, the allocation unit 903 is further configured to obtain an index table corresponding to the register row in the target stream processor; in the index table, determine index information associated with the row numbers of the N target register rows.

[0154] In some embodiments of the present application, the allocation unit 903 is also configured to clear the index information when the execution of the task to be assigned is completed; based on the N, the number of available register rows in the updated target stream processor is increased for use by the next task to be assigned; wherein the number of available register rows in the updated target stream processor is the difference between the M and the N.

[0155] It should be noted that the description of the above task allocation circuit embodiment is similar to the description of the above method embodiment, and has similar beneficial effects as the method embodiment. For technical details not disclosed in the circuit embodiment of the present application, please refer to the description of the method embodiment of the present application for understanding.

[0156] It should be noted that in the embodiments of the present application, if the above-mentioned task allocation method is implemented in the form of a software function module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the embodiment of the present application can be essentially or partly reflected in the form of a software product that contributes to the prior art. The computer software product is stored in a storage medium, including a number of instructions to enable a computer device (which can be a terminal, server, etc.) to execute all or part of the methods described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a U disk, a sports hard disk, a read-only memory (ROM), a magnetic disk or an optical disk. In this way, the embodiments of the present application are not limited to any specific combination of hardware and software.

[0157] Correspondingly, an embodiment of the present application further provides a computer program product, which includes a computer program or instructions. When the computer program or instructions are executed by a processor, the task allocation method provided in the embodiment of the present application can be implemented.

[0158] Accordingly, an embodiment of the present application provides a computer device, Fig.10 Schematic diagram of the composition structure of the computer device of the embodiment of the present application, such as Fig.10 As shown, the computer device 1000 includes: a processor 1001, at least one communication bus 1004, a communication interface 1002, at least one external communication interface and a memory 1003. The communication interface 1002 is configured to realize the connection and communication between these components. The communication interface 1002 may include a display screen, and the external communication interface may include a standard wired interface and a wireless interface. The processor 1001 is configured to execute the processing program in the memory to implement the task allocation method provided in the above embodiment.

[0159] Accordingly, an embodiment of the present application further provides a computer-readable storage medium, on which computer-executable instructions are stored. When the computer-executable instructions are executed by a processor, the task allocation method provided in the above embodiment is implemented.

[0160] The description of the above task allocation circuit, computer device, storage medium and program product embodiments is similar to the description of the above method embodiment, and has similar technical descriptions and beneficial effects as the corresponding method embodiments. Due to space limitations, reference can be made to the records of the above method embodiments, so no further description is given here. For technical details not disclosed in the task allocation circuit, computer device, storage medium and program product embodiments in this application, please refer to the description of the method embodiments of this application for understanding.

[0161] It should be understood that the "one embodiment" or "one embodiment" mentioned throughout the specification means that the specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the embodiment of the present application. Therefore, "in one embodiment" or "in one embodiment" appearing throughout the specification may not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in various embodiments of the embodiment of the present application, the size of the sequence number of the above-mentioned processes does not mean the order of execution, and the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiment of the present application. The above-mentioned sequence number of the embodiment of the present application is only for description and does not represent the advantages and disadvantages of the embodiment. It should be noted that in this article, the term "include", "include" or any other variant thereof is intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements includes not only those elements, but also includes other elements that are not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of more restrictions, the elements defined by the sentence "include one..." do not exclude the existence of other identical elements in the process, method, article or device including the element.

[0162] In several embodiments provided in the embodiments of the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored, or not executed. In addition, the coupling, direct coupling, or communication connection between the components shown or discussed can be through some interfaces, and the indirect coupling or communication connection of the devices or units can be electrical, mechanical or other forms.

[0163] The units described above as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units; they may be located in one place or distributed on multiple network units; some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0164] In addition, all functional units in the embodiments of the present application can be integrated into one processing unit, or each unit can be a separate unit, or two or more units can be integrated into one unit; the above integrated unit can be implemented in the form of hardware or in the form of hardware plus software functional units. It can be understood by ordinary technicians in this field that all or part of the steps of the above method embodiments can be completed by hardware related to program instructions, and the above program can be stored in a computer-readable storage medium. When the program is executed, it executes the steps of the above method embodiments; and the above storage medium includes: mobile storage devices, ROM, disks or optical disks and other media that can store program codes.

[0165] Alternatively, if the above-mentioned integrated unit of the embodiment of the present application is implemented in the form of a software function module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the embodiment of the present application can be essentially or partly embodied in the form of a software product that contributes to the prior art. The computer software product is stored in a storage medium, including several instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the methods described in each embodiment of the embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as mobile storage devices, ROMs, magnetic disks or optical disks. The above is only a specific implementation method of the embodiment of the present application, but the protection scope of the embodiment of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or replacements within the technical scope disclosed in the embodiment of the present application, which should be covered within the protection scope of the embodiment of the present application.

Claims

1. A task allocation method, characterized in that: The task allocation method comprises: Get the number of first registers matched by the task to be assigned; Obtaining the available counts of different types of registers in each stream processor through a resource management unit, and determining the number of second registers in an idle state in each of the stream processors in at least two stream processors based on the task attributes associated with the task to be assigned; the second registers are a register set corresponding to the task attributes, and different task attributes correspond to different types of registers; Determine a target stream processor from the stream processors whose number of the second registers is greater than or equal to the number of the first registers; the target stream processor includes registers of different types corresponding to the task attributes associated with the task to be assigned; and in the second registers, the number of registers of each type is greater than or equal to the number of registers matching the task attributes associated with the task to be assigned; Based on the task attributes associated with the task to be assigned, selecting N target register rows of corresponding types from M attribute register rows in an idle state in the target stream processor; The selected N target register rows are virtualized as sequentially continuous storage spaces for storing the tasks to be assigned.

2. The task allocation method according to claim 1, characterized in that: Each register row includes at least two registers with consecutive numbers in the same stream processor; the number of the first registers includes the number of the first register row, the number of the second registers includes the number of the second register row, and determining the target stream processor from the stream processors whose number of the second registers is greater than or equal to the number of the first registers includes: The target stream processor is determined from stream processors whose number of the second register rows is greater than or equal to the number of the first register rows.

3. The task allocation method according to claim 2, characterized in that: The step of determining the target stream processor from the stream processors whose number of the second register rows is greater than or equal to the number of the first register rows comprises: Among the stream processors whose number of the second register rows is greater than or equal to the number of the first register rows, selecting the stream processor with the largest number of the second register rows; The stream processor with the largest number of the second register rows is determined as the target register.

4. The task allocation method according to claim 1, characterized in that: The selecting, based on the task attribute associated with the task to be assigned, N target register rows of corresponding types from the M attribute register rows in the target stream processor that are in an idle state, comprises: Among the M second register rows in the target stream processor, a multi-way search method is used to select N target register rows; wherein, M is the number of second register rows in the target stream processor; N is the number of first register rows; and the row numbers corresponding to the N target register rows are continuous or discrete.

5. The task allocation method according to claim 4, characterized in that: The method of selecting N target register rows from the M second register rows in the target stream processor by using a multi-way search method comprises: In the case where the to-be-assigned task is attribute data to be assigned before task formation, N target attribute register rows are selected from M attribute register rows in an idle state in the target stream processor by adopting the multi-way search method; In the case where the tasks to be assigned are assembled task data to be assigned, the multi-way search method is used to select N target general data register rows from the M general data register rows in the target stream processor that are in an idle state.

6. The task allocation method according to any one of claims 1 to 5, characterized in that: The task allocation method further comprises: Put the initial task into the task sequence for compliance check; The initial task whose compliance check result is passed is released from the task sequence, and the initial task whose compliance check result is passed is determined as the task to be assigned.

7. The task allocation method according to any one of claims 1 to 5, characterized in that: When the number of the tasks to be assigned is at least two, the task assignment method further includes: The at least two tasks to be assigned are sorted from longest to shortest according to the waiting time for assignment, to obtain a queue of tasks to be assigned; The tasks to be assigned are assigned in sequence according to the order in the task queue to be assigned.

8. The task allocation method according to claim 4, characterized in that: The task allocation method further comprises: Obtaining an index table corresponding to a register row in the target stream processor; In the index table, index information associated with row numbers of the N target register rows is determined.

9. The task allocation method according to claim 8, characterized in that: The task allocation method further comprises: When the execution of the task to be assigned is completed, clearing the index information; Based on the N, the number of available register rows in the updated target stream processor is increased for use by the next task to be assigned; wherein the number of available register rows in the updated target stream processor is the difference between the M and the N.

10. A task allocation circuit, characterized in that: The task allocation circuit comprises: The task management unit is configured to obtain the number of first registers matched by the task to be assigned; A resource management unit is configured to obtain the available counts of different types of registers in each stream processor through the resource management unit, and determine the number of second registers in an idle state in each of the stream processors in at least two stream processors based on the task attributes associated with the task to be assigned; the second registers are a register set corresponding to the task attributes, and different task attributes correspond to different types of registers; The resource management unit is further configured to determine a target stream processor from the stream processors whose number of the second registers is greater than or equal to the number of the first registers; the target stream processor includes registers of different types corresponding to the task attributes associated with the task to be assigned; and in the second registers, the number of registers of each type is greater than or equal to the number of registers matching the task attributes associated with the task to be assigned; an allocating unit, configured to allocate the to-be-allocated task to a second register in the target stream processor; The allocation unit is further configured to select N target register rows of corresponding types from M attribute register rows in an idle state in the target stream processor based on the task attributes associated with the task to be allocated; and virtualize the selected N target register rows into sequentially continuous storage spaces for storing the task to be allocated.

11. A computer device, characterized in that: The computer device includes a memory and a processor, the memory stores computer executable instructions, and the processor can implement the task allocation method described in any one of claims 1 to 9 when running the computer executable instructions on the memory.

12. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer-executable instructions, which, after being executed, can implement the task allocation method described in any one of claims 1 to 9.

13. A computer program product, characterized in that The computer program product includes a computer program or instructions, and when the computer program or instructions are executed by a processor, the task allocation method according to any one of claims 1 to 9 is implemented.

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