Pixel array

Abstract

The pixel array comprises a data line, a first scanning line, a second scanning line, a pixel, a first signal line, a second signal line, a third signal line, a first gate drive transistor, a second gate drive transistor and a third gate drive transistor. The pixel transistor of the sub-pixel of the pixel in the nth1 row and the nth2 column is provided with the first gate drive transistor. The pixel transistor of the sub-pixel of the pixel in the nth1+m1 row and the nth2+m2 column is provided with the second gate drive transistor. The pixel transistor of the sub-pixel of the pixel in the nth1+m1 row and the nth2 column is provided with the third gate drive transistor. The control end of the pixel transistor of the sub-pixel of the pixel in the nth1+m1 row and the nth2 column and the second end of the third gate drive transistor are electrically connected to the first scanning line. The first end of the third gate drive transistor is electrically connected to the third signal line. In the top view of the pixel array, the third signal line is located between the second signal line and the data line electrically connected to the first end of the pixel transistor of the sub-pixel of the pixel in the nth1+m1 row and the nth2+m2 column.

Description

TECHNICAL FIELD

[0001] The present application relates to a pixel array. BACKGROUND

[0002] In order to reduce the cost of purchasing the gate driving chip, the gate driving circuit, the multiplexer and the pixel array can be integrated on the same substrate of the display panel. Generally, the gate driving circuit and the multiplexer are mostly arranged in the frame area of the display panel, which causes the frame width to be unable to be further reduced. Therefore, the signal line and the gate driving transistor for outputting the gate opening signal in the gate driving circuit and the multiplexer can be periodically dispersed in the pixel area of the display panel. The size of the gate driving transistor has a key influence on the pixel charging rate of the display panel. In order to improve the pixel charging rate, the size of the gate driving transistor can be increased. However, the aperture ratio is greatly reduced when the size of the gate driving transistor is increased to improve the charging rate. SUMMARY

[0003] The present application provides a pixel array with good charging effect.

[0004] The pixel array of the present application comprises a plurality of data lines, a plurality of scan lines, a plurality of pixels, a plurality of signal lines, a plurality of gate lines and a plurality of gate drive transistors. The plurality of data lines are arranged in a first direction. The plurality of scan lines are arranged in a second direction, wherein the first direction and the second direction are staggered. Each pixel comprises a plurality of sub-pixels arranged in the first direction. Each sub-pixel comprises a pixel transistor and a pixel electrode, the pixel transistor has a first terminal, a second terminal and a control terminal, the first terminal of the pixel transistor is electrically connected to a corresponding data line, the control terminal of the pixel transistor is electrically connected to a corresponding scan line, the second terminal of the pixel transistor is electrically connected to the pixel electrode, the pixel electrode has opposite first and second sides, and the first and second sides are sequentially arranged in the first direction. The plurality of signal lines are arranged in the first direction. The plurality of gate lines are arranged in the second direction. Each gate drive transistor has a first terminal, a second terminal and a control terminal. The first terminal of each gate drive transistor is electrically connected to a corresponding signal line. The control terminal of each gate drive transistor is electrically connected to a corresponding gate line. The second terminal of each gate drive transistor is electrically connected to a corresponding scan line. The plurality of gate drive transistors comprises a first gate drive transistor, a second gate drive transistor and a third gate drive transistor. The plurality of scan lines comprises a first scan line and a second scan line. The plurality of signal lines comprises a first signal line, a second signal line and a third signal line. The plurality of pixels are arranged in a plurality of rows and a plurality of columns in the first direction and the second direction. The pixel transistor of the sub-pixel of the pixel in the nth1 row and the nth2 column is provided with the first gate drive transistor. The control terminal of the pixel transistor of the sub-pixel of the pixel in the nth1 row and the nth2 column and the second terminal of the first gate drive transistor are electrically connected to the first scan line. The first terminal of the first gate drive transistor is electrically connected to the first signal line. The first signal line and the data line electrically connected to the first terminal of the pixel transistor of the sub-pixel of the pixel in the nth1 row and the nth2 column are respectively located at the first side and the second side of the pixel electrode of the sub-pixel of the pixel in the nth1 row and the nth2 column. n1 and n2 are positive integers. The pixel transistor of the sub-pixel of the pixel in the nth1+m1 row and the nth2+m2 column is provided with the second gate drive transistor. The control terminal of the pixel transistor of the sub-pixel of the pixel in the nth1+m1 row and the nth2+m2 column and the second terminal of the second gate drive transistor are electrically connected to the second scan line. The first terminal of the second gate drive transistor is electrically connected to the second signal line. The second signal line and the data line electrically connected to the first terminal of the pixel transistor of the sub-pixel of the pixel in the nth1+m1 row and the nth2+m2 column are respectively located at the first side and the second side of the pixel electrode of the sub-pixel of the pixel in the nth1+m1 row and the nth2+m2 column. m1 and m2 are positive integers greater than or equal to 2. The pixel transistor of the sub-pixel of the pixel in the nth1+m1 row and the nth2 column is provided with the third gate drive transistor.The control terminal of the pixel transistor of the sub-pixel of the pixel in the nth1+m1 row and the nth2 column and the second terminal of the third gate driving transistor are electrically connected to the first scan line. The first terminal of the third gate driving transistor is electrically connected to the third signal line. In particular, in the top view of the pixel array, the third signal line is located between the second signal line and the data line electrically connected to the first terminal of the pixel transistor of the sub-pixel of the pixel in the nth1+m1 row and the nth2+m2 column. BRIEF DESCRIPTION OF DRAWINGS

[0005] Figure 1 A top view of a pixel array substrate according to an embodiment of the present application.

[0006] Figure 2 A top view of a pixel array substrate according to an embodiment of the present application. Figure 1 An enlarged view of a partial A1 of the pixel array substrate according to the embodiment of the present application.

[0007] Figure 3 An enlarged view of a partial A2 of the pixel array substrate according to the embodiment of the present application. Figure 1 An enlarged view of a partial A3 of the pixel array substrate according to the embodiment of the present application.

[0008] Figure 4 An enlarged view of a partial A4 of the pixel array substrate according to the embodiment of the present application. Figure 1 An enlarged view of a partial A4 of the pixel array substrate according to the embodiment of the present application.

[0009] Figure 5 An enlarged view of a partial A4 of the pixel array substrate according to the embodiment of the present application. Figure 1 An enlarged view of a partial A4 of the pixel array substrate according to the embodiment of the present application.

[0010] REFERENCE NUMERALS:

[0011] 10: pixel array

[0012] A1, A2, A3, A4: partial

[0013] C1, C2, C3, C4, C5, C_n1, C_n1+m1: row

[0014] DL: data line

[0015] d1: first direction

[0016] d2: second direction

[0017] GL: gate line

[0018] HC, HC1, HC2, HC3, HC4: signal line

[0019] PE: pixel electrode

[0020] PEa: main part

[0021] PEb: branch part

[0022] PX: pixel

[0023] R1, R2, R3, R4, R5, R_n2, R_n2+m2, R_n2+l2: column

[0024] SL, SL1, SL2: scan line

[0025] SPX: sub-pixel

[0026] T1: pixel transistor

[0027] T2, T21, T22, T23, T24: gate driver transistor

[0028] T1a, T2a: first terminal

[0029] T1b, T2b: second terminal

[0030] T1c, T2c: control terminal DETAILED DESCRIPTION

[0031] Reference will now be made in detail to the exemplary embodiments of the present application, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used in the drawings and the description to refer to the same or like parts.

[0032] It is to be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element or intervening elements can also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements present. As used herein, the term "connected" can mean physically and / or electrically connected. Further, "electrically connected" or "coupled" can be two elements exist other elements.

[0033] As used herein, "about," "approximately," or "substantially" includes the stated value and a range of values acceptable to one of ordinary skill in the art in view of the particular quantity being discussed (i.e., the limitations of the measurement system at hand) and the associated uncertainties in the measurements and in the representations thereof. For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value. Further, as used herein, "about," "approximately," or "substantially" can select a more acceptable range of deviation or standard deviation for optical properties, etching properties, or other properties, and can not apply one standard deviation to all properties.

[0034] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and this application and will not be interpreted in an overly idealized or formal sense unless expressly so defined herein.

[0035] Figure 1 A top view of a pixel array substrate according to an embodiment of the present application. Figure 2 A top view of a pixel array substrate according to an embodiment of the present application. Figure 1 An enlarged view of a partial A1 of a pixel array substrate according to an embodiment of the present application. Figure 3 An enlarged view of a partial A1 of a pixel array substrate according to an embodiment of the present application. Figure 1 An enlarged view of a partial A2 of a pixel array substrate according to an embodiment of the present application. Figure 4 An enlarged view of a partial A2 of a pixel array substrate according to an embodiment of the present application. Figure 1 An enlarged view of a partial A3 of a pixel array substrate according to an embodiment of the present application. Figure 5 An enlarged view of a partial A3 of a pixel array substrate according to an embodiment of the present application. Figure 1 An enlarged view of a partial A4 of a pixel array substrate according to an embodiment of the present application.

[0036] Please refer to Figure 1 The pixel array 10 includes a plurality of data lines DL, a plurality of scan lines SL, a plurality of pixels PX, a plurality of signal lines HC, a plurality of gate lines GL, and a plurality of gate drive transistors T2.

[0037] The plurality of data lines DL are arranged in a first direction d1. The plurality of scan lines SL are arranged in a second direction d2. The first direction d1 and the second direction d2 are staggered. For example, in an embodiment, the first direction d1 and the second direction d2 can be perpendicular, but the present application is not limited thereto.

[0038] Each of the plurality of pixels PX includes a plurality of sub-pixels SPX arranged in the first direction d1. For example, in an embodiment, each of the plurality of pixels PX can include three sub-pixels SPX arranged in the first direction d1, but the present application is not limited thereto. Please refer to Figure 1 and Figure 2 Each of the plurality of sub-pixels SPX includes a pixel transistor T1 and a pixel electrode PE. The pixel transistor T1 has a first terminal T1a, a second terminal T1b, and a control terminal T1c. The first terminal T1a of the pixel transistor T1 is electrically connected to a corresponding one of the plurality of data lines DL. The control terminal T1c of the pixel transistor T1 is electrically connected to a corresponding one of the plurality of scan lines SL. The second terminal T1b of the pixel transistor T1 is electrically connected to the pixel electrode PE. The pixel electrode PE has a first side (e.g., a left side) and a second side (e.g., a right side) opposite to each other, and the first side and the second side are arranged in order in the first direction d1.

[0039] For example, in one embodiment, the pixel electrode PE can have at least one trunk portion PEa and a plurality of branch portions PEb extending outwardly from the at least one trunk portion PEa. When the pixel array 10 is applied to a liquid crystal display module, the trunk portion PEa is located at a non-emitting region. However, the present application is not limited thereto, and in other embodiments, the shape of the pixel electrode PE can be designed differently according to actual requirements. In addition, the application of the pixel array 10 is not limited to liquid crystal display modules, and the pixel array 10 can also be applied to other types of displays.

[0040] Please refer to Figure 1 and Figure 2 , a plurality of signal lines HC are arranged in the first direction d1, a plurality of gate lines GL are arranged in the second direction d2, each gate drive transistor T2 has a first terminal T2a, a second terminal T2b, and a control terminal T2c, the first terminal T2a of each gate drive transistor T2 is electrically connected to a corresponding signal line HC, the control terminal T2c of each gate drive transistor T2 is electrically connected to a corresponding gate line GL, and the second terminal T2b of each gate drive transistor T2 is electrically connected to a corresponding scan line SL. The pixel array 10 includes an integrated gate driver-on-array disposed on a substrate (not shown) and a multiplexer electrically connected to the integrated gate driver-on-array. The integrated gate driver-on-array and the multiplexer can include signal lines HC, gate lines GL, and gate drive transistors T2 dispersed on a pixel area of the substrate. The integrated gate driver-on-array and the multiplexer can also include a main circuit (not shown) disposed on a frame area of the substrate, and the signal lines HC, the gate lines GL, and the gate drive transistors T2 dispersed on the pixel area are electrically connected to the main circuit located in the frame area.

[0041] Please refer to Figure 1 , a plurality of pixels PX are arranged in a plurality of rows C1, C2, C3, C4, C5 and a plurality of columns R1, R2, R3, R4, R5 in the first direction d1 and the second direction d2. The plurality of pixels PX in the same row C1 / C2 / C3 / C4 / C5 are arranged in the second direction d2. The plurality of pixels PX in the same column R1 / R2 / R3 / R4 / R5 are arranged in the first direction d1. Figure 1 A repeated unit of the pixel array 10 is shown. Figure 1 The repeated unit shown is an example of a plurality of pixels PX arranged in 5 rows and 5 columns. However, the present application is not limited thereto, and in other embodiments, the number of rows and columns included in a repeated unit of the pixel array 10 can be designed differently according to actual requirements.

[0042] Please refer to Figure 1 and Figure 2The pixel PX of the n1th row C_n1 and the n2th column R_n2 is provided with the first gate drive transistor T21 adjacent to the pixel transistor T1 of the sub-pixel SPX. The control terminal T1c of the pixel transistor T1 of the sub-pixel SPX of the pixel PX of the n1th row C_n1 and the n2th column R_n2 and the second terminal T2b of the first gate drive transistor T21 are electrically connected to the first scan line SL1. The first terminal T2a of the first gate drive transistor T21 is electrically connected to the first signal line HC1. The first signal line HC1 and a data line DL electrically connected to the first terminal T1a of the pixel transistor T1 of the sub-pixel SPX of the pixel PX of the n1th row C_n1 and the n2th column R_n2 are respectively located at the first side (for example, the left side) and the second side (for example, the right side) of the pixel electrode PE of the sub-pixel SPX of the pixel PX of the n1th row C_n1 and the n2th column R_n2, wherein n1 and n2 are positive integers.

[0043] For example, in an embodiment, n1=1, n2=1, the pixel PX of the first row C1 and the first column R1 is provided with the first gate drive transistor T21 adjacent to the pixel transistor T1 of the sub-pixel SPX. The control terminal T1c of the pixel transistor T1 of the sub-pixel SPX of the pixel PX of the first row C1 and the first column R1 and the second terminal T2b of the first gate drive transistor T21 are electrically connected to the first scan line SL1. The first terminal T2a of the first gate drive transistor T21 is electrically connected to the first signal line HC1. The first signal line HC1 and a data line DL electrically connected to the first terminal T1a of the pixel transistor T1 of the sub-pixel SPX of the pixel PX of the first row C1 and the first column R1 are respectively located at the first side (for example, the left side) and the second side (for example, the right side) of the pixel electrode PE of the sub-pixel SPX of the pixel PX of the first row C1 and the first column R1.

[0044] Please refer to Figure 1 and Figure 3, the plurality of gate driving transistors T2 further include a second gate driving transistor T22, the plurality of scan lines SL further include a second scan line SL2, the plurality of signal lines HC further include a second signal line HC2, a pixel transistor T1 of a sub-pixel SPX of a pixel PX of an n1+m1th row C_n1+m1 and an n2+m2th column R_n2+m2 is located beside the second gate driving transistor T22, a control terminal T1c of the pixel transistor T1 of the sub-pixel SPX of the pixel PX of the n1+m1th row C_n1+m1 and the n2+m2th column R_n2+m2 and a second terminal T2b of the second gate driving transistor T22 are electrically connected to the second scan line SL2, a first terminal T2a of the second gate driving transistor T22 is electrically connected to the second signal line HC2, the second signal line HC2 and a data line DL electrically connected to a first terminal T1a of the pixel transistor T1 of the sub-pixel SPX of the pixel PX of the n1+m1th row C_n1+m1 and the n2+m2th column R_n2+m2 are respectively located at a first side (for example, a left side) and a second side (for example, a right side) of a pixel electrode PE of the sub-pixel SPX of the pixel PX of the n1+m1th row C_n1+m1 and the n2+m2th column R_n2+m2, wherein m1 and m2 are positive integers greater than or equal to 2.

[0045] For example, in an embodiment, n1=1, n2=1, m1=2, m2=2, a pixel transistor T1 of a sub-pixel SPX of a pixel PX of a 3rd row C3 and a 3rd column R3 is located beside a second gate driving transistor T22, a control terminal T1c of the pixel transistor T1 of the sub-pixel SPX of the pixel PX of the 3rd row C3 and the 3rd column R3 and a second terminal T2b of the second gate driving transistor T22 are electrically connected to a second scan line SL2, a first terminal T2a of the second gate driving transistor T22 is electrically connected to a second signal line HC2, the second signal line HC2 and a data line DL electrically connected to a first terminal T1a of the pixel transistor T1 of the sub-pixel SPX of the pixel PX of the 3rd row C3 and the 3rd column R3 are respectively located at a first side (for example, a left side) and a second side (for example, a right side) of a pixel electrode PE of the sub-pixel SPX of the pixel PX of the 3rd row C3 and the 3rd column R3.

[0046] Please refer to Figure 1 and Figure 4The plurality of gate drive transistors T2 further includes a third gate drive transistor T23, and the plurality of signal lines HC further includes a third signal line HC3. The third gate drive transistor T23 is disposed beside a pixel transistor T1 of a sub-pixel SPX of a pixel PX of the n1+m1th row C_n1+m1 and the n2th column R_n2. The control terminal T1c of the pixel transistor T1 of the sub-pixel SPX of the pixel PX of the n1+m1th row C_n1+m1 and the n2th column R_n2 and the second terminal T2b of the third gate drive transistor T23 are electrically connected to the first scan line SL1. The first terminal T2a of the third gate drive transistor T23 is electrically connected to the third signal line HC3.

[0047] For example, in an embodiment, n1=1, n2=1, m1=2, m2=2, and in the top view of the pixel array 10, the third signal line HC3 is located between the second signal line HC2 and the data line DL electrically connected to the first terminal T1a of the pixel transistor T1 of the sub-pixel SPX of the pixel PX of the third row C3 and the third column R1.

[0048] Please refer to Figure 1 and Figure 3 It is worth noting that, in the top view of the pixel array 10, the third signal line HC3 is located between the second signal line HC2 and the data line DL electrically connected to the first terminal T1a of the pixel transistor T1 of the sub-pixel SPX of the pixel PX of the n1+m1th row C_n1+m1 and the n2+m2th column R_n2+m2. The first signal line HC1 and the third signal line HC3 have the same signal at the same time point. In detail, the first signal line HC1 and the third signal line HC3 can have the same waveform and synchronous signals in a certain time interval.

[0049] For example, in an embodiment, n1=1, n2=1, m1=2, m2=2, and in the top view of the pixel array 10, the third signal line HC3 is located between the second signal line HC2 and the data line DL electrically connected to the first terminal T1a of the pixel transistor T1 of the sub-pixel SPX of the pixel PX of the third row C3 and the third column R1.

[0050] By the above layout, the number of gate drive transistors T2 used to drive the plurality of pixels in the same column R1 can be increased. Without increasing the area of each gate drive transistor T2, using a larger number of gate drive transistors T2 to drive the plurality of pixels PX in the same column R1 can improve the charging capability and maintain the aperture ratio above a certain value.

[0051] Please refer toFigure 1 and Figure 4 In an embodiment, in a top view of the pixel array 10, the third signal line HC3 partially overlaps the pixel electrodes PE of the sub-pixels SPX of the pixels PX of the nth1+m1th row C_n1+m1and the nth2th column R_n2. In a further embodiment, in a top view of the pixel array 10, the pixel electrodes PE of the sub-pixels SPX of the pixels PX of the nth1+m1th row C_n1+m1and the nth2th column R_n2have at least one stem portion PEa and a plurality of branch portions PEb extending outwardly from the at least one stem portion PEa, and the third signal line HC3 overlaps the at least one stem portion PEa and does not overlap at least a portion of the plurality of branch portions PEb. In other words, in an embodiment, the third signal line HC3 disposed between the second signal line HC2 and the data line DL is configured to define a non-emissive region, and the configuration of the third signal line HC3 does not significantly reduce the aperture ratio of the pixel array 10.

[0052] For example, in an embodiment, n1 = 1, n2 = 1, m1 = 2, in a top view of the pixel array 10, the third signal line HC3 partially overlaps the pixel electrodes PE of the sub-pixels SPX of the pixels PX of the third row C3 and the first column R1. In a further embodiment, in a top view of the pixel array 10, the pixel electrodes PE of the sub-pixels SPX of the pixels PX of the third row C3 and the first column R1have at least one stem portion PEa and a plurality of branch portions PEb extending outwardly from the at least one stem portion PEa, and the third signal line HC3 overlaps the at least one stem portion PEa and does not overlap at least a portion of the plurality of branch portions PEb.

[0053] Please refer to Figure 1 and Figure 4 In an embodiment, in a top view of the pixel array 10, the third gate drive transistor T23 and the pixel transistor T1 of the sub-pixel SPX of the pixel PX of the nth1+m1th row C_n1+m1and the nth2th column R_n2are located between the second signal line HC2 and the data line DL electrically connected to the first terminal T1a of the pixel transistor T1 of the sub-pixel SPX of the pixel PX of the nth1+m1th row C_n1+m1and the nth2th column R_n2, and the third gate drive transistor T23 and the pixel transistor T1 of the sub-pixel SPX of the pixel PX of the nth1+m1th row C_n1+m1and the nth2th column R_n2are located on different sides of the third signal line HC3, respectively. For example, in an embodiment, n1 = 1, n2 = 1, m1 = 2, in a top view of the pixel array 10, the third gate drive transistor T23 and the pixel transistor T1 of the sub-pixel SPX of the pixel PX of the third row C3 and the first column R1are located between the second signal line HC2 and the data line DL electrically connected to the first terminal T1a of the pixel transistor T1 of the sub-pixel SPX of the pixel PX of the third row C3 and the first column R1, and the third gate drive transistor T23 and the pixel transistor T1 of the sub-pixel SPX of the pixel PX of the third row C3 and the first column R1are located on different sides of the third signal line HC3, respectively.

[0054] Please refer to Figure 1 , Figure 2 and Figure 5 In an embodiment, the aforementioned plurality of gate drive transistors T2 further comprises a fourth gate drive transistor T24; a pixel transistor T1 of a sub-pixel SPX of a pixel PX of the nth1 row C_n1 and the nth2+l2 column R_n2+l2 is provided with the fourth gate drive transistor T24; the aforementioned plurality of signal lines HC further comprises a fourth signal line HC4; the fourth signal line HC4 is electrically connected to the first end T2a of the fourth gate drive transistor T24; in the top view of the pixel array 10, the fourth signal line HC4 is located between the first signal line HC1 and the data line DL electrically connected to the first end T1a of the pixel transistor T1 of the sub-pixel SPX of the pixel PX of the nth1 row C_n1 and the nth2 column R_n2, wherein l2 is a positive integer greater than or equal to 2.

[0055] For example, in an embodiment, n1=1, n2=1, l2=3, the pixel transistor T1 of the sub-pixel SPX of the pixel PX of the first row C1 and the fourth column R4 is provided with the fourth gate drive transistor T24, and the fourth signal line HC4 is electrically connected to the first end T2a of the fourth gate drive transistor T24; in the top view of the pixel array 10, the fourth signal line HC4 is located between the first signal line HC1 and the data line DL electrically connected to the first end T1a of the pixel transistor T1 of the sub-pixel SPX of the pixel PX of the first row C1 and the first column R1.

[0056] Please refer to Figure 1 and Figure 5 In an embodiment, in the top view of the pixel array 10, the fourth gate drive transistor T24 and the pixel transistor T1 of the sub-pixel SPX of the pixel PX of the nth1 row C_n1 and the nth2+l2 column R_n2+l2 are located between the first signal line HC1 and the data line DL electrically connected to the first end T1a of the pixel transistor T1 of the sub-pixel SPX of the pixel PX of the nth1 row C_n1 and the nth2+l2 column R_n2+l2, and the fourth gate drive transistor T24 and the pixel transistor T1 of the sub-pixel SPX of the pixel PX of the nth1 row C_n1 and the nth2+l2 column R_n2+l2 are respectively located on different sides of the fourth signal line HC4.

[0057] For example, in one embodiment, n1=1, n2=1, l2=3, the fourth gate driving transistor T24 and the pixel transistor T1 of the sub-pixel SPX of the pixel PX in the first row C1 and the fourth column R4 are located between the first signal line HC1 and the data line DL electrically connected with the first terminal T1a of the pixel transistor T1 of the sub-pixel SPX of the pixel PX in the first row C1 and the fourth column R4, and the fourth gate driving transistor T24 and the pixel transistor T1 of the sub-pixel SPX of the pixel PX in the first row C1 and the fourth column R4 are respectively located at different sides of the fourth signal line HC4.

Claims

1. A pixel array, comprising: Multiple data lines are arranged in a first direction; Multiple scan lines are arranged in a second direction, wherein the first direction and the second direction intersect. A plurality of pixels, wherein each pixel includes a plurality of sub-pixels arranged in the first direction, each sub-pixel includes a pixel transistor and a pixel electrode, the pixel transistor having a first terminal, a second terminal and a control terminal, the first terminal of the pixel transistor being electrically connected to a corresponding data line, the control terminal of the pixel transistor being electrically connected to a corresponding scan line, the second terminal of the pixel transistor being electrically connected to the pixel electrode, the pixel electrode having a first side and a second side opposite to each other, and the first side and the second side being arranged sequentially in the first direction; Multiple signal lines are arranged in this first direction; Multiple gate lines are arranged in this second direction; as well as A plurality of gate driving transistors, wherein each gate driving transistor has a first terminal, a second terminal and a control terminal, the first terminal of each gate driving transistor is electrically connected to a corresponding signal line, the control terminal of each gate driving transistor is electrically connected to a corresponding gate line, and the second terminal of each gate driving transistor is electrically connected to a corresponding scan line. The gate driving transistors include a first gate driving transistor, a second gate driving transistor, and a third gate driving transistor; These scan lines include a first scan line and a second scan line; These signal lines include a first signal line, a second signal line, and a third signal line; These pixels are arranged in multiple rows and columns in the first direction and the second direction; A first gate driving transistor is provided next to the pixel transistor of the sub-pixel of the pixel in the n1st row and n2nd column. The control terminal of the pixel transistor of the sub-pixel of the pixel in the n1st row and n2nd column and the second terminal of the first gate driving transistor are electrically connected to the first scan line. The first terminal of the first gate driving transistor is electrically connected to the first signal line. The first signal line and a data line electrically connected to the first terminal of the pixel transistor of the sub-pixel of the pixel in the n1st row and n2nd column are respectively located on the first side and the second side of the pixel electrode of the sub-pixel of the pixel in the n1st row and n2nd column, where n1 and n2 are positive integers. A second gate driving transistor is provided next to the pixel transistor of the sub-pixel of the pixel in the n1+m1 row and the n2+m2 column. The control terminal of the pixel transistor of the sub-pixel of the pixel in the n1+m1 row and the n2+m2 column and the second terminal of the second gate driving transistor are electrically connected to the second scan line. The first terminal of the second gate driving transistor is electrically connected to the second signal line. The second signal line and a data line electrically connected to the first terminal of the pixel transistor of the sub-pixel of the pixel in the n1+m1 row and the n2+m2 column are respectively located on the first side and the second side of the pixel electrode of the sub-pixel of the pixel in the n1+m1 row and the n2+m2 column, where m1 and m2 are positive integers greater than or equal to 2. The third gate driving transistor is provided next to the pixel transistor of the sub-pixel of the pixel in the n1+m1 row and the n2 column. The control terminal of the pixel transistor of the sub-pixel of the pixel in the n1+m1 row and the n2 column and the second terminal of the third gate driving transistor are electrically connected to the first scan line. The first terminal of the third gate driving transistor is electrically connected to the third signal line. In the top view of the pixel array, the third signal line is located between the second signal line and the data line electrically connected to the first terminal of the pixel transistor of the sub-pixel of the pixel in the n1+m1 row and the n2+m2 column.

2. The pixel array as claimed in claim 1, wherein the first signal line and the third signal line have the same signal at the same point in time.

3. The pixel array of claim 1, wherein, in a top view of the pixel array, the third signal line partially overlaps the pixel electrode of the sub-pixel of the pixel in the n1+m1th row and the n2th column.

4. The pixel array of claim 3, wherein the pixel electrode of the sub-pixel of the pixel in the n1+m1th row and the n2th column has a main stem and a plurality of branches extending outward from the main stem, and the third signal line overlaps the main stem but does not overlap at least a portion of the branches.

5. The pixel array of claim 1, wherein, in a top view of the pixel array, the third gate driving transistor and the pixel transistor of the sub-pixel of the pixel in the n1+m1 row and the n2 column are located between the second signal line and the data line electrically connected to the first terminal of the pixel transistor of the sub-pixel of the pixel in the n1+m1 row and the n2 column, and the third gate driving transistor and the pixel transistor of the sub-pixel of the pixel in the n1+m1 row and the n2 column are respectively located on different sides of the third signal line.

6. The pixel array of claim 1, wherein the gate driving transistors further include a fourth gate driving transistor; the fourth gate driving transistor is disposed next to the pixel transistor of the sub-pixel of the pixel in the n1th row and n2+l2th column; the signal lines further include a fourth signal line; the fourth signal line is electrically connected to the first terminal of the fourth gate driving transistor; in a top view of the pixel array, the fourth signal line is located between the first signal line and the data line electrically connected to the first terminal of the pixel transistor of the sub-pixel of the pixel in the n1th row and n2th column, wherein l2 is a positive integer greater than or equal to 2.

7. The pixel array of claim 6, wherein, in a top view of the pixel array, the fourth gate driving transistor and the pixel transistor of the sub-pixel of the pixel in the n1th row and n2+l2th column are located between the first signal line and the data line electrically connected to the first terminal of the pixel transistor of the sub-pixel of the pixel in the n1th row and n2+l2th column, and the fourth gate driving transistor and the pixel transistor of the sub-pixel of the pixel in the n1th row and n2+l2th column are respectively located on different sides of the fourth signal line.

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