A wide bandgap semiconductor device structure and method of fabrication thereof

Abstract

The application provides a wide band gap semiconductor device structure and a manufacturing method thereof, and belongs to the technical field of semiconductor devices. The device structure comprises a drain, a substrate and an epitaxial layer which are sequentially stacked; a P well region is arranged in the middle of the surface layer of the epitaxial layer away from the substrate, and a JFET region is arranged between two adjacent P well regions; a gate and a source are arranged above the JFET region, and the gate and the source are isolated by an interlayer dielectric layer; a first electric field shielding layer, a second electric field shielding layer and a third electric field shielding layer are sequentially stacked between the gate and the epitaxial layer in the direction from the substrate to the epitaxial layer; gate dielectric layers which are in contact with the surface of the epitaxial layer away from the substrate are arranged on both sides of the first electric field shielding layer; the first electric field shielding layer and the third electric field shielding layer are material layers with a critical electric field strength greater than or equal to 6 MV / cm, and the second electric field shielding layer is a high dielectric constant material layer. The device structure bears voltage and reduces electric field through the three-layer electric field shielding layer, thereby improving the reliability and switching speed of the device.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of semiconductor devices, and particularly relates to a wide-bandgap semiconductor device structure and a manufacturing method thereof. BACKGROUND

[0002] In the use of a conventional planar MOSFET (metal-oxide-semiconductor field effect transistor) device, as the drain-source voltage increases, the electric field in the gate dielectric layer above the JFET (junction field effect transistor) region gradually increases, and the electric field in the middle of the gate dielectric layer is the most concentrated. Therefore, under severe conditions such as avalanche breakdown or short circuit, the gate dielectric layer is prone to damage, which affects the reliability of the device during operation. SUMMARY

[0003] To solve the above problems, the present application provides a wide-bandgap semiconductor device structure. The device structure is mainly used to bear voltage and reduce electric field by constructing an electric field shielding layer on the JFET region, thereby improving the reliability and switching speed of the gate dielectric layer.

[0004] To achieve the above purpose, the present application specifically adopts the following technical solutions:

[0005] A wide-bandgap semiconductor device structure, comprising a drain, a substrate, and an epitaxial layer stacked in sequence; a P-well region is arranged in the middle of the surface layer away from the substrate side of the epitaxial layer, and a JFET region is arranged between two adjacent P-well regions; a gate and a source are arranged above the JFET region, and the gate and the source are isolated by an interlayer dielectric layer; a first electric field shielding layer, a second electric field shielding layer, and a third electric field shielding layer are stacked in sequence between the gate and the epitaxial layer in the direction of the substrate pointing to the epitaxial layer; gate dielectric layers are arranged on both sides of the first electric field shielding layer and in contact with the surface of the epitaxial layer away from the substrate side; the first electric field shielding layer is a material layer with a critical electric field strength of ≥6 MV / cm, the second electric field shielding layer is a high-dielectric-constant material layer, and the third electric field shielding layer is a material layer with a critical electric field strength of ≥6 MV / cm.

[0006] In a preferred embodiment, the first electric field shielding layer is a silicon dioxide layer.

[0007] In a preferred embodiment, the second electric field shielding layer includes at least one of a silicon nitride layer, an aluminum oxide layer, and a polycrystalline silicon layer.

[0008] In a preferred embodiment, the third electric field shielding layer is a silicon dioxide layer.

[0009] In a preferred embodiment, the first electric field shielding layer has n levels of steps, where n is an integer ≥2; and the width of each level of step gradually decreases in the direction from the substrate to the epitaxial layer.

[0010] In a preferred embodiment, the JFET region is provided with an N-type current spreading layer.

[0011] In a preferred embodiment, the P-well region is provided with a source N+ region in the surface layer away from the substrate side, and the source N+ region is electrically connected to the source electrode.

[0012] In a preferred embodiment, the P-well region is provided with a source P+ region in the surface layer away from the substrate side, and the source P+ region is electrically connected to the source electrode.

[0013] In a further preferred embodiment, the P-well region is provided with a source N+ region in the surface layer away from the substrate side, and the epitaxial layer is provided with a source P+ region in the surface layer away from the substrate side, and the source N+ region and the source P+ region are both electrically connected to the source electrode.

[0014] In a preferred embodiment, a plurality of P+ field limiting rings are provided in the surface layer of the epitaxial layer away from the substrate side, away from the P-well region side.

[0015] In a preferred embodiment, the substrate comprises any one of a silicon carbide substrate, a gallium nitride substrate, a gallium oxide substrate, a diamond substrate, an aluminum nitride substrate.

[0016] The present application also provides a method for manufacturing the wide bandgap semiconductor device structure of any one of the above embodiments, comprising the following steps:

[0017] Growing an epitaxial layer on a substrate;

[0018] Forming spaced P-well regions in the epitaxial layer by ion implantation;

[0019] Depositing a material with a critical electric field strength ≥ 6 MV / cm and a high dielectric constant material on the surface of the epitaxial layer away from the substrate side in sequence to obtain a first electric field shielding layer and a second electric field shielding layer respectively; etching the second electric field shielding layer to stop etching on the surface of the first electric field shielding layer;

[0020] Depositing a material with a critical electric field strength ≥ 6 MV / cm on the surface of the obtained device structure away from the substrate side to obtain a third electric field shielding layer; etching the first electric field shielding layer and the third electric field shielding layer by a wet etching method;

[0021] Placing the obtained device structure in an oxidation furnace at 1150-1500°C for 10-150 min, and then annealing in a NO or Ar or N2O atmosphere at 1150-1500°C for 1-2 h to form an oxidation layer on the surface of the epitaxial layer away from the substrate side as a gate dielectric layer;

[0022] Depositing gate material on the surface of the device structure far from the substrate, and etching to obtain a gate; continuing to deposit interlayer dielectric material on the surface of the device structure far from the substrate, and etching to obtain an interlayer dielectric layer surrounding the gate;

[0023] Depositing source metal on the surface of the device structure far from the substrate, and etching to obtain a source; depositing drain metal on the surface of the substrate far from the epitaxial layer to obtain a drain.

[0024] In the preferred embodiment, the preparation method of the first electric field shielding layer and the second electric field shielding layer comprises the following steps:

[0025] Depositing material with a critical electric field strength ≥ 6 MV / cm on the surface of the epitaxial layer far from the substrate, and forming a first level step through photolithography; then forming a second level step through photolithography and plasma etching to obtain a first electric field shielding layer; when the step number n > 2, repeating the step of forming a second level step to obtain more level steps as the first electric field shielding layer; and depositing high dielectric constant material on the exposed surface of the first electric field shielding layer to obtain a second electric field shielding layer.

[0026] In the preferred embodiment, the preparation method of the wide bandgap semiconductor device structure further comprises the following step: forming a source N+ region in the P well region by ion implantation.

[0027] In the preferred embodiment, the preparation method of the wide bandgap semiconductor device structure further comprises the following step: forming a source P+ region and a plurality of P+ field limiting rings in the surface layer of the epitaxial layer far from the substrate by ion implantation.

[0028] In the preferred embodiment, the preparation method of the wide bandgap semiconductor device structure further comprises the following step: forming an N-type current spreading layer in the JFET region formed by the two adjacent P well regions by ion implantation.

[0029] The present application provides another preparation method of the wide bandgap semiconductor device structure, comprising the following steps:

[0030] Growing an epitaxial layer on a substrate;

[0031] Forming spaced P well regions in the epitaxial layer by ion implantation;

[0032] Depositing material with a critical electric field strength ≥ 6 MV / cm and high dielectric constant material on the surface of the epitaxial layer far from the substrate in sequence, etching the obtained material layer, and etching to stop on the surface of the epitaxial layer far from the substrate to obtain a first electric field shielding layer and a second electric field shielding layer, respectively.

[0033] The obtained device structure is placed in an atmosphere of NO or Ar or N2O and annealed at 1150-1500°C for 1-2h; the surface of the second electric field shielding layer away from the surface of the first electric field shielding layer is oxidized to form a third electric field shielding layer; and the surface of the epitaxial layer away from the substrate is oxidized to form an oxide layer as a gate dielectric layer;

[0034] A gate material is deposited on the surface of the obtained device structure away from the substrate, and after etching, a gate is obtained; and an interlayer dielectric material is further deposited on the surface of the device structure away from the substrate, and after etching, an interlayer dielectric layer surrounding the gate is obtained.

[0035] A source metal is deposited on the surface of the obtained device structure away from the substrate, and after etching, a source is obtained; and a drain metal is deposited on the surface of the substrate away from the epitaxial layer, and a drain is obtained.

[0036] In a preferred embodiment, the method for manufacturing the wide-bandgap semiconductor device structure further comprises the following step: forming a source N+ region in the P well region by ion implantation.

[0037] In a preferred embodiment, the method for manufacturing the wide-bandgap semiconductor device structure further comprises the following step: forming a source P+ region and a plurality of P+ field limiting rings in the surface layer of the epitaxial layer away from the substrate by ion implantation.

[0038] In a preferred embodiment, the method for manufacturing the wide-bandgap semiconductor device structure further comprises the following step: forming an N-type current spreading layer in the JFET region formed by the two adjacent P well regions by ion implantation.

[0039] The technical scheme of the present application has the following beneficial effects: the JFET region of the wide-bandgap semiconductor device structure of the present application is constructed with three layers of electric field shielding layers above the JFET region, wherein the materials of the first electric field shielding layer and the third electric field shielding layer are high critical field strength materials, which are mainly used for bearing voltage; and the material of the second electric field shielding layer is a high dielectric constant material, which is mainly used for reducing electric field. Through the design of the structure, not only the electric field in the gate dielectric layer can be reduced to improve the reliability of the device, but also the gate-drain capacitance can be reduced to improve the switching speed of the device. BRIEF DESCRIPTION OF DRAWINGS

[0040] Figure 1 A schematic diagram of a wide-bandgap semiconductor device structure provided for an embodiment of the present application;

[0041] Figure 2 A schematic diagram of another wide-bandgap semiconductor device structure provided for an embodiment of the present application;

[0042] Figure 3 A schematic diagram of the structure obtained in step S2 of the method for manufacturing a wide-bandgap semiconductor device structure according to an embodiment of the present application;

[0043] Figure 4 A schematic diagram of the structure obtained in step S3 of the method for manufacturing a wide-bandgap semiconductor device structure according to an embodiment of the present application;

[0044] Figure 5 A schematic diagram of the structure obtained in step S4 of the method for manufacturing a wide-bandgap semiconductor device structure according to an embodiment of the present application;

[0045] Figure 6 A schematic diagram of the structure obtained in step S5 of the method for manufacturing a wide-bandgap semiconductor device structure according to an embodiment of the present application;

[0046] Figure 7 A schematic diagram of the structure obtained in step S6 of the method for manufacturing a wide-bandgap semiconductor device structure according to an embodiment of the present application;

[0047] Figure 8 A schematic diagram of the structure obtained in step S7 of the method for manufacturing a wide-bandgap semiconductor device structure according to an embodiment of the present application;

[0048] Figure 9 A schematic diagram of the structure obtained in step S8 of the method for manufacturing a wide-bandgap semiconductor device structure according to an embodiment of the present application;

[0049] Figure 10 、 Figure 11 、 Figure 12 A process diagram of manufacturing a first electric field shielding layer in the method for manufacturing a wide-bandgap semiconductor device structure according to another embodiment of the present application;

[0050] Figure 13 A schematic diagram of another wide-bandgap semiconductor device structure according to an embodiment of the present application;

[0051] Figure 14 、 Figure 15 A process diagram of manufacturing a third electric field shielding layer in the method for manufacturing a wide-bandgap semiconductor device structure according to another embodiment of the present application.

[0052] In the figure: 1, substrate; 2, epitaxial layer; 3, first electric field shielding layer; 4, second electric field shielding layer; 5, third electric field shielding layer; 6, gate; 7, interlayer dielectric layer; 8, source; 9, drain; 10, gate dielectric layer; 11, P well region; 12, JFET region; 13, N-type current spreading layer; 14, source N+ region; 15, source P+ region; 16, P+ field limiting ring; 17, mask; 18, first sidewall; 19, window; 20, second sidewall; 21, first photoresist layer; 22, second photoresist layer. DETAILED DESCRIPTION

[0053] The technical solutions of the present application are described below in conjunction with the embodiments, so that those skilled in the art can fully understand the present application. Obviously, the described embodiments are only some preferred embodiments of the present application, not all embodiments. Any equivalent transformation or replacement of the following embodiments made by those skilled in the art without creative labor is within the protection scope of the present application.

[0054] The directional terms mentioned in the present application, such as "upper", "lower", "inner", "outer", "bottom surface", "upper surface", etc., indicate the orientation or positional relationship based on the orientation or positional relationship in the drawings of the specification, or the orientation or positional relationship in which the product of the present application is usually placed during use, and are only for the convenience of describing and understanding the structure of the product of the present application. Therefore, the directional terms cannot be understood as limiting the present application. In the present application, unless otherwise explicitly limited, the expressions such as "on", "above", "upper", and "upper surface" of the first feature to the second feature mean that the first feature and the second feature can be in direct contact or indirect contact through an intermediate medium; can be directly above or obliquely above the second feature, or only means that the first feature is higher than the second feature in horizontal height. The expressions such as "below", "under", "lower", and "lower surface" of the first feature to the second feature mean that the first feature and the second feature can be in direct contact or indirect contact through an intermediate medium; can be directly below or obliquely below the second feature, or only means that the first feature is lower than the second feature in horizontal height. The ordinal numbers used in the present application, such as "first", "second", etc., are only for the purpose of description to distinguish similar objects, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. The high dielectric constant (High-κ) material used in the present application refers to a dielectric material with a relative dielectric constant greater than that of silicon dioxide (κ = 4). The methods not described in detail in the following embodiments are conventional methods well known to those skilled in the art.

[0055] As Figure 1As shown, the embodiment of the present application provides a wide band gap semiconductor device structure, which comprises a drain 9, a substrate 1, an epitaxial layer 2, a first electric field shielding layer 3, a second electric field shielding layer 4, a third electric field shielding layer 5, a gate 6, an interlayer dielectric layer 7 and a source 8 which are sequentially stacked. The first electric field shielding layer 3 is provided with a gate dielectric layer 10 which is in contact with the surface of the epitaxial layer 2 away from the substrate 1 on both sides. The gate dielectric layer 10 and the first electric field shielding layer 3 jointly separate the gate 6 and the epitaxial layer 2. The interlayer dielectric layer 7 is arranged around the gate 6 to insulate and separate the gate 6 from the source 8. The epitaxial layer 2 is provided with P well regions 11 which are arranged in the middle of the surface layer away from the substrate 1, and a JFET region 12 between any two adjacent P well regions 11. The material of the substrate 1 is a wide band gap semiconductor material, for example, any one of silicon carbide substrate, gallium nitride substrate, gallium oxide substrate, diamond substrate, aluminum nitride substrate. The material of the epitaxial layer 2 is any one of silicon carbide, gallium nitride, gallium oxide, diamond, aluminum nitride. The material of the first electric field shielding layer 3 is silicon dioxide. The material of the second electric field shielding layer 4 is a high dielectric constant material, for example, any one of silicon nitride, aluminum oxide, polysilicon. The material of the third electric field shielding layer 5 is silicon dioxide. The material of the gate 6 is polysilicon. The material of the interlayer dielectric layer 7 is silicon dioxide. The material of the source 8 is aluminum metal. The material of the drain 9 is titanium / nickel / silver laminated metal. The doping element of the P well region 11 is Al, and the doping concentration is 1×10 16 cm -3 ~ 3×10 17 cm -3 (for example, the doping concentration of the P well region 11 is 1×10 16 cm -3 , 1.5×10 16 cm -3 , 2×10 16 cm -3 , 2.5×10 16 cm -3 ……2×10 17 cm -3 , 2.6×10 17 cm -3 , 3×10 17 cm -3 ).

[0056] Further, the doping type of the substrate 1 is heavily doped N type (N+ type).

[0057] Further, the doping type of the epitaxial layer 2 is lightly doped N type (N- type).

[0058] Further, continuing to refer to Figure 1 , the surface layer of the P well region 11 away from the substrate 1 is formed with a source N+ region 14 by ion implantation, and the source N+ region 14 is electrically connected with the source 8.

[0059] Further, with reference to Figure 1 , a source P+ region 15 is formed by ion implantation in a surface layer of the epitaxial layer 2 away from the substrate 1 and away from the P-well region 11. The source P+ region 15 is electrically connected to the source 8.

[0060] Further, with reference to Figure 1 , a plurality of P+ field limiting rings 16 are formed by ion implantation in a surface layer of the epitaxial layer 2 away from the substrate 1 and away from the P-well region 11.

[0061] As shown in Figure 12 , in some other embodiments, the first electric field shielding layer 3 has n (n is an integer ≥ 2) levels of steps. The width of each level of steps gradually decreases in the direction of the epitaxial layer 2 away from the substrate 1.

[0062] As shown in Figure 2 , in some other embodiments, the JFET region is formed with an N-type current spreading layer 13 by N-type ion implantation. The N-type doping element is nitrogen element or phosphorus element, and the doping concentration is 1×10 16 cm -3 ~ 3×10 17 cm -3 (For example, the doping concentration is 1×10 16 cm -3 , 1.2×10 16 cm -3 , 2.3×10 16 cm -3 , 2.5×10 16 cm -3 ……1×10 17 cm -3 , 2×10 17 cm -3 , 3×10 17 cm -3 ).

[0063] As shown in Figure 1 and Figures 3-10 , the embodiments of the present application further provide a method for manufacturing a wide-bandgap semiconductor device structure, comprising the following steps:

[0064] S1, growing an epitaxial layer 2 on a substrate 1. The material of the substrate 1 is a wide-bandgap semiconductor material, such as any one of silicon carbide, gallium nitride, gallium oxide, diamond, aluminum nitride. The doping type of the epitaxial layer 2 is N-type. In this embodiment, the substrate 1 is a silicon carbide substrate, and the doping type of the epitaxial layer 2 is N-type.

[0065] S2. Ion implantation is used to form spaced P-well regions 11 in the epitaxial layer 2. The epitaxial layer 2 between two adjacent P-well regions is the JFET region 12. The mask 17 used for ion implantation is a single layer of silicon dioxide or a multilayer structure of silicon dioxide, polysilicon, and silicon dioxide.

[0066] S3. A first dielectric layer is grown on the surface of epitaxial layer 2 facing away from substrate 1. A first sidewall spacer 18 and a window 19 are formed by etching the front surface. The material of first sidewall spacer 18 is at least one of polysilicon, silicon dioxide, and silicon nitride. Ion implantation is used through window 19 to form source N+ region 14 in P-well region 11. First sidewall spacer 18 and the mask are removed.

[0067] S4 , forming a source P+ region 15 and a terminal P+ field limiting ring 16 in the surface layer of the epitaxial layer 2 away from the substrate 1 by ion implantation.

[0068] S5. A material having a critical electric field strength ≥6 MV / cm and a high dielectric constant material are sequentially deposited on the surface of the epitaxial layer 2 away from the substrate 1 to form a first electric field shielding layer 3 and a second electric field shielding layer 4, respectively. The second electric field shielding layer 4 is dry-etched, and the etching stops on the surface of the first electric field shielding layer 3. In this embodiment, the material of the first electric field shielding layer 3 is silicon dioxide, and the material of the second electric field shielding layer 4 is silicon nitride.

[0069] S6. Deposit a material with a critical electric field strength ≥ 6 MV / cm (e.g., silicon dioxide) on the upper surface of the structure obtained in step S5 to form a third electric field shielding layer 5. Wet etching is performed to remove the first electric field shielding layer 3 and the third electric field shielding layer 5. The wet etching process ensures that the surface of the epitaxial layer 2 is not damaged.

[0070] S7. Oxidize the upper surface of the epitaxial layer 2 at 1150°C to 1500°C (for example, the oxidation temperature is 1150°C, 1200°C, 1250°C, 1300°C, 1400°C, 1500°C) for 10 minutes to 150 minutes (for example, the oxidation time is 10 minutes, 20 minutes, 30 minutes, 60 minutes, 80 minutes, 120 minutes, 150 minutes); then anneal at 1150°C to 1500°C (for example, the annealing temperature is 1150°C, 1250°C, 1300°C, 1350°C, 1450°C, 1500°C) in an NO or Ar or N2O atmosphere for 1 to 2 hours (for example, the annealing time is 1 hour, 1.5 hours, 2 hours) to reduce the interface state on the upper surface of the epitaxial layer 2 to form a gate dielectric layer 10.

[0071] S8, depositing a gate material on the top surface of the device structure obtained in step S7, and etching to obtain a gate 6; continue to deposit an interlayer dielectric material (e.g. silicon dioxide) on the top surface of the device structure, and etch to obtain an interlayer dielectric layer 7 surrounding the gate 6; then etch away the excess gate dielectric layer 10.

[0072] S9, depositing a source metal on the top surface of the device structure obtained in step S8, and etching to obtain a source 8; depositing a drain metal on the surface of the substrate 1 away from the epitaxial layer 2 to obtain a drain 9. The final device structure is shown in Figure 1

[0073] As shown in Figures 10-12 , in some other embodiments, the method for preparing the first electric field shielding layer 3 and the second electric field shielding layer 4 in step S5 includes the following steps: depositing a material with a critical electric field strength ≥ 6 MV / cm on the surface of the epitaxial layer 2 away from the substrate 1, then continue to apply a first photoresist layer 21, and etch to form a first level step; apply a second photoresist layer 22 on the first level step, and use oxygen plasma to etch the front surface to form a second sidewall 20, and then etch to form a second level step; repeat the step of forming the second level step to obtain more level steps; remove the first photoresist layer and the second photoresist layer, and the obtained first electric field shielding layer 3 has a structure with multiple level steps (as shown in Figure 12 ), and the width of each level step gradually decreases in the direction from the substrate 1 to the epitaxial layer 2. The other steps are the same as S1-S4 and S6-S9, and the schematic diagram of the final wide bandgap semiconductor device structure is shown in Figure 13

[0074] As shown in Figures 14-15 , in some other embodiments, step S5 includes the following steps: sequentially depositing a material with a critical electric field strength ≥ 6 MV / cm and a high dielectric constant material on the surface of the epitaxial layer 2 away from the substrate 1 to obtain the first electric field shielding layer 3 and the second electric field shielding layer 4, respectively. The material of the first electric field shielding layer 3 is silicon dioxide, and the material of the second electric field shielding layer 4 is polysilicon. The method for preparing the third electric field shielding layer 5 in step S6 and the method for preparing the gate dielectric layer in step S7 include: placing the obtained device structure in an oxidation furnace at 1150°C-1500°C (for example, the oxidation temperature is 1150°C, 1200°C, 1250°C, 1300°C, 1350°C, 1450°C, 1500°C) for 10 min-150 min (for example, the oxidation time is 10 min, 25 min, 35 min, 40 min, 70 min, 110 min, 150 min), so that the upper surface of the second electric field shielding layer 4 is oxidized to form the third electric field shielding layer 5 (as shown in Figure 14 ​​As shown), the surface of the epitaxial layer 2 away from the substrate 1 is oxidized to form an oxide layer as the gate dielectric layer 10 (see Figure 15 ); then, annealing is performed at 1150° C. to 1500° C. (for example, annealing temperatures are 1150° C., 1250° C., 1350° C., 1450° C., or 1500° C.) for 1 to 2 hours (for example, annealing times are 1 hour, 1.5 hours, or 2 hours) in an NO, Ar, or N2O atmosphere to reduce the interface state on the upper surface of the third electric field shielding layer 5. The other steps are the same as S1 to S4 and S8 to S9.

[0075] like Figure 2 As shown, in some other embodiments, step S2 further includes the following steps: forming an N-type current spreading layer 13 in the JFET region 12 by ion implantation. The N-type doping element is nitrogen or phosphorus, and the doping concentration is 1×10 16 cm -3 ~3×10 17 cm -3 (For example, the doping concentration is 1×10 16 cm -3 , 1.5×10 16 cm -3 , 2×10 16 cm -3 , 2.5×10 16 cm -3 , 4×10 16 cm -3 , 5×10 16 cm -3 ,……1×10 17 cm -3 , 2×10 17 cm -3 , 3×10 17 cm -3 ).

[0076] The foregoing description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. It will be apparent to anyone skilled in the art that various modifications and variations of the present invention are possible. Any simple equivalent variations and modifications made in accordance with the scope of protection of the present invention and the contents of the specification are intended to be included within the scope of protection of the present invention.

Claims

1. A method for manufacturing a wide bandgap semiconductor device structure, characterized in that: The following steps are involved: growing an epitaxial layer on a substrate; forming spaced P-well regions in the epitaxial layer by ion implantation; and forming a JFET region between two adjacent P-well regions; Depositing a material with a critical electric field strength of ≥6 MV / cm and a high dielectric constant material on a surface of the epitaxial layer away from the substrate in sequence to obtain a first electric field shielding layer and a second electric field shielding layer respectively; Etching the second electric field shielding layer, and stopping the etching on the surface of the first electric field shielding layer; Depositing a material having a critical electric field strength of ≥6 MV / cm on a surface of the obtained device structure away from the substrate to obtain a third electric field shielding layer; etching the first electric field shielding layer and the third electric field shielding layer by wet etching; The obtained device structure is oxidized at 1150° C. to 1500° C. for 10 min to 150 min, and then annealed at 1150° C. to 1500° C. for 1 h to 2 h in an atmosphere of NO, Ar, or N2O, so that an oxide layer is formed on the surface of the epitaxial layer away from the substrate as a gate dielectric layer; Depositing a gate material on a surface of the obtained device structure away from the substrate, and etching to obtain a gate; Continuing to deposit an interlayer dielectric material on the surface of the device structure away from the substrate, and etching to obtain an interlayer dielectric layer surrounding the gate; Depositing a source metal on a surface of the obtained device structure away from the substrate, and etching to obtain a source electrode; Depositing a drain metal on a surface of the substrate away from the epitaxial layer to obtain a drain; Alternatively, the method for manufacturing the wide bandgap semiconductor device structure comprises the following steps: growing an epitaxial layer on a substrate; forming spaced P-well regions in the epitaxial layer by ion implantation; and forming a JFET region between two adjacent P-well regions; A material having a critical electric field strength of ≥6 MV / cm and a high dielectric constant material are sequentially deposited on a surface of the epitaxial layer away from the substrate, and the resulting material layers are etched, with the etching stopping on the surface of the epitaxial layer away from the substrate, to respectively obtain a first electric field shielding layer and a second electric field shielding layer; the obtained device structure is oxidized at 1150° C. to 1500° C. for 10 to 150 minutes, and then annealed at 1150° C. to 1500° C. for 1 to 2 hours in an atmosphere of NO, Ar, or N2O; the surface of the second electric field shielding layer away from the first electric field shielding layer is oxidized to form a third electric field shielding layer; the oxide layer formed by the oxidation of the surface of the epitaxial layer away from the substrate serves as a gate dielectric layer; Depositing a gate material on a surface of the obtained device structure away from the substrate, and etching to obtain a gate; further depositing an interlayer dielectric material on a surface of the device structure away from the substrate, and etching to obtain an interlayer dielectric layer surrounding the gate; A source metal is deposited on the surface of the obtained device structure away from the substrate, and a source electrode is obtained after etching; a drain metal is deposited on the surface of the substrate away from the epitaxial layer to obtain a drain electrode.

2. The method for manufacturing a wide bandgap semiconductor device structure according to claim 1, wherein: The first electric field shielding layer is a silicon dioxide layer; or / and the second electric field shielding layer includes at least one of a silicon nitride layer, an aluminum oxide layer, and a polysilicon layer; or / and the third electric field shielding layer is a silicon dioxide layer.

3. The method for manufacturing a wide bandgap semiconductor device structure according to claim 1, wherein: The first electric field shielding layer has n steps, where n is an integer ≥ 2; and the width of each step gradually decreases in a direction from the substrate to the epitaxial layer.

4. The method for manufacturing a wide bandgap semiconductor device structure according to claim 1, wherein: A source N+ region is formed by ion implantation in the surface layer of the P-well region away from the substrate, and the source N+ region is electrically connected to the source; or / and a source P+ region is formed by ion implantation in the surface layer of the epitaxial layer away from the substrate, and the source P+ region is electrically connected to the source.

5. The method for manufacturing a wide bandgap semiconductor device structure according to claim 1, wherein: In a surface layer of the epitaxial layer away from the substrate, a plurality of P+ field limiting rings are formed on a side away from the P-well region by ion implantation.

6. The method for manufacturing a wide bandgap semiconductor device structure according to claim 1, wherein: The method for preparing the first electric field shielding layer and the second electric field shielding layer comprises the following steps: A material having a critical electric field strength of ≥6 MV / cm is deposited on the surface of the epitaxial layer away from the substrate, and a first step is formed by photolithography; a second step is then formed by photolithography and plasma etching to obtain a first electric field shielding layer; when the number of steps n is greater than 2, the step of forming the second step is repeated to obtain more steps as the first electric field shielding layer; and a high dielectric constant material is deposited on the exposed surface of the first electric field shielding layer to obtain a second electric field shielding layer.

7. The method for manufacturing a wide bandgap semiconductor device structure according to claim 1, wherein: The following steps are involved: An N-type current spreading layer is formed in the JFET region by ion implantation.

8. A wide bandgap semiconductor device structure prepared by the method according to any one of claims 1 to 7.

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