Display panel and method for driving the same

Abstract

The present application provides a display panel and a method for driving the display panel. The present application sets a switch circuit to output a single cascade control signal output by each shift register unit as a driving cascade signal to drive the pixel unit to display a normal picture, or outputs the single cascade control signal as a black insertion cascade signal to drive the pixel unit to display a black picture to realize black insertion display, so that each shift register unit can realize normal display or black insertion display of the display panel; in addition, by setting two gate driving circuits, the display panel can realize black insertion display in addition to bilateral driving or unilateral driving of each row of pixel units, thereby realizing diversified display modes of the display panel.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a method for driving the display panel. Background Art

[0002] In order to solve the problem of ghosting when the display panel switches dynamic images, it is generally necessary to insert black (AFI technology, Auto Frame Insertion) in the display interval of a frame to complete the initialization before the next frame is displayed, reduce or eliminate the visual residue of the previous frame displayed by the human eye, thereby achieving the purpose of eliminating ghosting, improving dynamic clarity, improving dynamic response, etc., and improving the dynamic display quality of LCD (Liquid Crystal Display).

[0003] At present, in high-resolution, narrow-framed display devices, GOA (Gate on Array, array substrate row drive) technology is generally used to realize in-plane row scanning drive. When non-AFI technology is used, the left and right GOAs are generally used to drive inward at the same time, that is, there are two left and right GOA units in the same row to complete the drive, which is referred to as dual drive. This driving method is complementary on the left and right, has strong driving ability, and uniform picture display. When using AFI technology, the left GOA is generally used for display drive, and the right GOA is used for black insertion drive. Therefore, AFI technology is generally single-drive, and its driving ability is slightly worse than non-AFI technology. Summary of the invention

[0004] The main technical problem solved by the present application is to provide a display panel and a method for driving the display panel, so as to solve the problem in the prior art of how to realize dual drive based on narrow frame by using AFI technology.

[0005] In order to solve the above technical problems, the first technical solution provided by the present application is: to provide a display panel, which includes:

[0006] A plurality of pixel units arranged in an array, each pixel unit comprising a display switch and a black insertion switch;

[0007] Two gate drive circuits, each gate drive circuit includes a plurality of cascaded shift register units;

[0008] A switch circuit is arranged in one-to-one correspondence with the shift register units, and is arranged in correspondence with and electrically connected to at least one row of pixel units; the switch circuit is used to output a single cascade control signal output by the corresponding shift register unit as a driving cascade signal or a black insertion cascade signal;

[0009] The driving cascade signal is used to control the display switch in the corresponding row of pixel units to turn on, so as to drive the pixel units to display normal images; the black insertion cascade signal is used to control the black insertion switch in the corresponding row of pixel units to turn on, so as to drive the pixel units to display black images.

[0010] Among them, the display panel also includes a plurality of gate line groups arranged at intervals, each gate line group is arranged corresponding to and electrically connected to a row of pixel units; the gate line group includes a display gate line and a black insertion gate line arranged at intervals; the display gate line is electrically connected to the control end of the display switch in the pixel unit of the corresponding row to control the opening of the display switch, and the black insertion gate line is electrically connected to the control end of the black insertion switch in the pixel unit of the corresponding row to control the opening of the black insertion switch.

[0011] Among them, the switching circuit is electrically connected between the corresponding shift register unit and the corresponding gate line group; the switching circuit is used to transmit the single cascade control signal output by the corresponding shift register unit as a driving cascade signal to the display gate line in the corresponding gate line group, or the switching circuit is used to transmit the single cascade control signal output by the corresponding shift register unit as a black insertion cascade signal to the black insertion gate line in the corresponding gate line group.

[0012] Among them, each gate drive circuit also includes a first signal line and a second signal line; the switching circuit includes a first switch and a second switch, the input end of the first switch is electrically connected to the output end of the corresponding shift register unit, the output end of the first switch is electrically connected to the corresponding display gate line, and the control end of the first switch is electrically connected to the first signal line; the input end of the second switch is connected to the same output end of the corresponding shift register unit as the input end of the first switch, the output end of the second switch is electrically connected to the corresponding black gate line, and the control end of the second switch is electrically connected to the second signal line.

[0013] Among them, each gate drive circuit also includes a ground power signal line, and the display panel also includes a reset switch, which is set in a one-to-one correspondence with the shift register unit, the input end of the reset switch is electrically connected to the black gate line corresponding to the corresponding shift register unit, the output end of the reset switch is electrically connected to the ground power signal line, and the control end of the reset switch is connected to the output end of the last m-stage shift register unit of the corresponding shift register unit; wherein m is a natural number greater than or equal to 1.

[0014] The cascade control signal outputted from the output end of the same subsequent m-stage shift register unit serves as a reset signal of the current-stage shift register unit and as a control signal received by a reset switch corresponding to the current-stage shift register unit.

[0015] Among them, the display panel also includes multiple data lines; the pixel unit also includes a pixel capacitor, a pixel electrode and a common electrode, the input end of the display switch is electrically connected to the data line, the output end of the display switch is electrically connected to one end of the pixel capacitor via the pixel electrode, and the other end of the pixel capacitor is electrically connected to the common electrode; the input end of the black insertion switch is electrically connected to the pixel electrode, and the output end of the black insertion switch is connected to the common electrode.

[0016] The structures of the two gate driving circuits are the same; the display panel includes a normal display mode and a black insertion display mode;

[0017] When the display panel is in a normal display mode, at least one gate driving circuit is in operation, and the switch circuits corresponding to all the shift register units in the gate driving circuit output the cascade control signals as driving cascade signals;

[0018] When the display panel is in a black insertion display mode, both gate drive circuits work, and the switch circuits corresponding to all the shift register units in one gate drive circuit output the cascade control signals as drive cascade signals, and the switch circuits corresponding to all the shift register units in the other gate drive circuit output the cascade control signals as black insertion cascade signals, wherein within one frame, the drive timings of the two gate drive circuits differ by at least half a frame.

[0019] In order to solve the above technical problem, the second technical solution provided by the present application is: to provide a method for driving a display panel, which is used to drive the above display panel; wherein, it includes:

[0020] Controlling the shift register unit to output a cascade control signal;

[0021] The switch circuit corresponding to the shift register unit is controlled to output the cascade control signal as a driving cascade signal or a black insertion cascade signal.

[0022] Wherein, the display panel includes a normal display mode and a black insertion display mode;

[0023] Controlling the switch circuit corresponding to the shift register unit to output the cascade control signal as a driving cascade signal or a black insertion cascade signal, including:

[0024] When the display panel is in a black insertion display mode, the switch circuits corresponding to all the shift register units in one gate driving circuit are controlled to output all the cascade control signals as driving cascade signals, and the switch circuits corresponding to all the shift register units in another gate driving circuit are controlled to output all the cascade control signals as black insertion cascade signals;

[0025] When the display panel is in a normal display mode, at least one gate driving circuit works, and the control switch circuit outputs all cascade control signals as driving cascade signals.

[0026] Beneficial effects of the present application: Different from the prior art, the present application provides a display panel and a method for driving the display panel, wherein the display panel includes a plurality of pixel units arranged in an array, two gate drive circuits and a switch circuit. Each pixel unit includes a display switch and a black insertion switch. The gate drive circuit includes a plurality of cascaded shift register units. The switch circuit is arranged in a one-to-one correspondence with the shift register unit, and is arranged and electrically connected to at least one row of pixel units. The switch circuit is used to output a single cascade control signal output by the corresponding shift register unit as a drive cascade signal or a black insertion cascade signal. Among them, the drive cascade signal is used to control the display switch in the corresponding row of pixel units to turn on, so as to drive the pixel unit to display a normal picture. The black insertion cascade signal is used to control the black insertion switch in the corresponding row of pixel units to turn on, so as to drive the pixel unit to display a black picture. The present application sets a switch circuit to output a single cascade control signal output by each shift register unit as a driving cascade signal to drive the pixel unit to display a normal picture, or outputs the single cascade control signal as a black insertion cascade signal to drive the pixel unit to display a black picture to achieve black insertion display, so that each shift register unit can achieve normal display or black insertion display of the display panel; in addition, by setting two gate drive circuits, the display panel can achieve black insertion display in addition to bilateral driving or unilateral driving of each row of pixel units, thereby achieving diversified display modes of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0028] Figure 1 is a schematic structural diagram of an embodiment of a display panel provided by the present application;

[0029] Figure 2 is a structural schematic diagram of an embodiment of a pixel unit provided by the present application;

[0030] Figure 3 is a schematic diagram of an equivalent circuit structure of an embodiment of a pixel unit provided by the present application;

[0031] Figure 4 is a schematic diagram of timing differences between two gate drive circuits according to an embodiment of the present application;

[0032] Figure 5 is a schematic diagram of timing differences of another embodiment of two gate driving circuits provided by the present application;

[0033] Figure 6 This is a schematic diagram of mode switching of a display panel provided by the present application;

[0034] Figure 7 It is a flow chart of an implementation of a method for driving a display panel provided in the present application.

[0035] Description of Figure Numbers:

[0036] 10. Pixel unit; 11. Display switch; 12. Black insertion switch; 13. Pixel electrode; 14. Common electrode; C. Pixel capacitor; 20. Gate drive circuit; 21 / SW1 / SW3. First signal line; 22 / SW2 / SW4. Second signal line; VSS. Ground power signal line; STV1 / STV2. Frame start signal; CK. Clock signal line; 20A. First gate drive circuit; 20B. Second gate drive circuit; GOA / Gn / Gn+1 / Gn+m / Gn+1+m. Shift register unit; 30. Gate line group; Gate1. Display gate line; Gate2. Black insertion gate line; 40. Switch circuit; 41 / T1 / T4. First switch; 42 / T2 / T5. Second switch; 50 / T3 / T6. Reset switch; Data. Data line; 101. Display area; 102. Frame area; t1. Display stage; t2. Black insertion stage. DETAILED DESCRIPTION

[0037] The scheme of the embodiment of the present application is described in detail below in conjunction with the drawings of the specification.

[0038] In the following description, for the purpose of explanation rather than limitation, specific details such as specific system structures, interfaces, and technologies are provided to facilitate a thorough understanding of the present application.

[0039] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0040] The terms "first", "second", "third" in this application are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined as "first", "second", "third" can expressly or implicitly include at least one of the features. In the description of this application, the meaning of "multiple" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined. In the embodiments of this application, all directional indications (such as up, down, left, right, front, back...) are only used to explain the relative position relationship, movement, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication also changes accordingly. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device comprising a series of steps or units is not limited to the steps or units listed, but optionally also includes steps or units that are not listed, or optionally also includes other steps or units inherent to these processes, methods, products or devices.

[0041] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0042] See also Figures 1 to 3 , Figure 1 is a schematic structural diagram of an embodiment of a display panel provided by the present application, Figure 2 is a schematic structural diagram of an embodiment of a pixel unit provided by the present application, Figure 3 Schematic diagram of an equivalent circuit structure of an embodiment of a pixel unit provided in the present application.

[0043] The present application provides a display panel, which includes a plurality of pixel units 10 arranged in an array, two gate drive circuits 20 and a switch circuit 40. Each pixel unit 10 includes a display switch 11 and a black insertion switch 12. The gate drive circuit 20 includes a plurality of cascaded shift register units GOA. The switch circuit 40 is arranged in a one-to-one correspondence with the shift register unit GOA, and is arranged and electrically connected to at least one row of pixel units 10. The switch circuit 40 is used to output a single cascade control signal output by the corresponding shift register unit GOA as a drive cascade signal or a black insertion cascade signal. Among them, the drive cascade signal is used to control the display switch 11 in the corresponding row of pixel units 10 to turn on, so as to drive the pixel unit 10 to display a normal picture. The black insertion cascade signal is used to control the black insertion switch 12 in the corresponding row of pixel units 10 to turn on, so as to drive the pixel unit 10 to display a black picture.

[0044] The present application sets a switch circuit 40 to output a single cascade control signal output by each shift register unit GOA as a driving cascade signal to drive the pixel unit 10 to display a normal picture, or outputs the single cascade control signal as a black insertion cascade signal to drive the pixel unit 10 to display a black picture to achieve black insertion display, so that each shift register unit GOA can achieve normal display or black insertion display of the display panel; in addition, by setting two gate drive circuits 20, the display panel can achieve black insertion display in addition to bilateral driving or unilateral driving of each row of pixel units 10, thereby achieving diversified display modes of the display panel.

[0045] The display panel has a display area 101 and a frame area 102 located at the side of the display area 101. In the present application, the display panel is a liquid crystal panel.

[0046] The display panel also includes a plurality of data lines Data. The pixel unit 10 also includes a pixel capacitor C, a pixel electrode 13 and a common electrode 14. The input end of the display switch 11 is electrically connected to the data line Data, the output end of the display switch 11 is electrically connected to one end of the pixel capacitor C via the pixel electrode 13, and the other end of the pixel capacitor C is electrically connected to the common electrode 14. The input end of the black insertion switch 12 is electrically connected to the pixel electrode 13, and the output end of the black insertion switch 12 is electrically connected to the common electrode 14. The input end of the black insertion switch 12 is electrically connected between the pixel capacitor C and the pixel electrode 13.

[0047] Liquid crystal molecules are disposed between each pixel electrode 13 and each common electrode 14. When there is a potential difference between the pixel electrode 13 and the corresponding common electrode 14, an electric field is generated, and the electric field drives the corresponding liquid crystal molecules to deflect, so that the pixel unit 10 displays a normal picture. When the potential between the pixel electrode 13 and the corresponding common electrode 14 is the same, the corresponding liquid crystal molecules do not deflect, and the pixel unit 10 displays a black picture.

[0048] Specifically, when the display switch 11 is turned on and the black insertion switch 12 is turned off, there is a potential difference between the common electrode 14 and the pixel electrode 13, so as to drive the pixel unit 10 to display a normal picture. When the display switch 11 is turned off and the black insertion switch 12 is turned on, the potential between the common electrode 14 and the pixel electrode 13 is the same, so as to drive the pixel unit 10 to display a black picture.

[0049] It should be noted that the display switch 11 and the black insertion switch 12 in each pixel unit 10 cannot be in the on state at the same time, so as to avoid affecting the normal display of the pixel unit 10 .

[0050] The two gate drive circuits 20 are respectively arranged in the border area 102 and on opposite sides of the display area 101. Each gate drive circuit 20 includes a plurality of cascaded shift register units GOA. The specific structure of the shift register unit GOA is not limited here, and is selected according to actual needs. Each shift register unit GOA is correspondingly arranged and coupled to at least one row of pixel units 10 to drive the corresponding row of pixel units 10 to display. In other words, each shift register unit GOA can drive a row of pixel units 10, or a plurality of rows of pixel units 10, which is not limited here and is selected according to actual needs.

[0051] In this embodiment, the two gate driving circuits 20 have the same structure. Each shift register unit GOA drives a row of pixel units 10 .

[0052] In other embodiments, the structures of the two gate driving circuits 20 may be different.

[0053] The display panel further includes a plurality of gate line groups 30 arranged at intervals. Each gate line group 30 is arranged corresponding to and electrically connected to a row of pixel units 10. The gate line group 30 includes a display gate line Gate1 and a black insertion gate line Gate2 arranged at intervals. The display gate line Gate1 is electrically connected to the control end of the display switch 11 in the pixel unit 10 of the corresponding row to control the opening of the display switch 11, and the black insertion gate line Gate2 is electrically connected to the control end of the black insertion switch 12 in the pixel unit 10 of the corresponding row to control the opening of the black insertion switch 12.

[0054] Specifically, the display gate line Gate1 extends in the row direction of the pixel unit 10. The display gate line Gate1 and the black gate line Gate2 in the gate line group 30 are insulated and spaced apart to avoid short circuit connection between the display gate line Gate1 and the black gate line Gate2 to affect the display of the pixel unit 10.

[0055] In this embodiment, the black gate line Gate2 in the gate line group 30 is arranged in parallel with the display gate line Gate1, and the black gate line Gate2 and the display gate line Gate1 are respectively located on opposite sides of the corresponding row of pixel units 10. That is, the extension direction of the gate line group 30 is arranged in parallel with the extension direction of the display gate line Gate1.

[0056] It should be understood that in other embodiments, the black insertion gate line Gate2 and the display gate line Gate1 in the gate line group 30 may be located on the same side of the pixel unit 10 of the corresponding row.

[0057] The two gate driving circuits 20 are respectively located on opposite sides of the gate line group 30 along the extending direction of the display gate line Gate1. One of the two gate driving circuits 20 is coupled to one end of the gate line group 30, and the other is coupled to the other end of the gate line group 30, so that the two gate driving circuits 20 can drive a row of pixel units 10 at the same time.

[0058] The switch circuit 40 is electrically connected between the corresponding shift register unit GOA and the corresponding gate line group 30. That is, one end of the switch circuit 40 is connected to the shift register unit GOA, and the other end is electrically connected to the gate line group 30, so as to transmit the cascade control signal output by the shift register unit GOA to the gate line group 30, thereby driving the pixel unit 10 in the corresponding row to display.

[0059] Further, the switch circuit 40 is used to transmit the single cascade control signal output by the corresponding shift register unit GOA as a driving cascade signal to the display gate line Gate1 in the corresponding gate line group 30, or the switch circuit 40 is used to transmit the single cascade control signal output by the corresponding shift register unit GOA as a black insertion cascade signal to the black insertion gate line Gate2 in the corresponding gate line group 30.

[0060] It can be understood that the switch circuit 40 can conduct between the output end of the shift register unit GOA and the corresponding display gate line Gate1, so that the single cascade control signal output by the shift register unit GOA is transmitted to the display gate line Gate1 as a driving cascade signal to drive the pixel unit 10 connected to the display gate line Gate1 to display a normal picture, or the switch circuit 40 can conduct between the output end of the shift register unit GOA and the corresponding black insertion gate line Gate2, so that the single cascade control signal output by the shift register unit GOA is transmitted to the black insertion gate line Gate2 as a black insertion cascade signal to drive the pixel unit 10 connected to the black insertion gate line Gate2 to display a black picture. That is to say, the cascade control signal output by the shift register unit GOA in the present application is a driving cascade signal or a black insertion cascade signal. A switch circuit 40 cannot output a driving cascade signal and a black insertion cascade signal at the same time, and can only selectively output a single cascade control signal output by a single shift register unit GOA as a driving cascade signal or a black insertion cascade signal.

[0061] It should be noted that in the present application, the switch circuits 40 corresponding to the shift register units GOA in the same gate drive circuit 20 output the same signal type. Specifically, the switch circuits 40 corresponding to the shift register units GOA in the same gate drive circuit 20 all output drive cascade signals or all output black insertion cascade signals.

[0062] Each gate drive circuit 20 also includes a first signal line 21 and a second signal line 22. The switch circuit 40 includes a first switch 41 and a second switch 42, wherein the input end of the first switch 41 is electrically connected to the output end of the corresponding shift register unit GOA, the output end of the first switch 41 is electrically connected to the corresponding display gate line Gate1, and the control end of the first switch 41 is electrically connected to the first signal line 21. The input end of the second switch 42 is connected to the same output end of the corresponding shift register unit GOA as the input end of the first switch 41, the output end of the second switch 42 is electrically connected to the corresponding black insertion gate line Gate2, and the control end of the second switch 42 is electrically connected to the second signal line 22. That is, the first signal line 21 is used to control the opening and closing of the first switch 41, and the second signal line 22 is used to control the opening and closing of the second switch 42. The first switch 41 is used to connect and disconnect the output end of the shift register unit GOA and the display gate line Gate1. The second switch 42 is used to connect and disconnect the output end of the shift register unit GOA and the black insertion gate line Gate2.

[0063] In this embodiment, the first switch 41 and the second switch 42 are both transistors, and the transistor types of the first switch 41 and the second switch 42 are the same, both are N-type transistors.

[0064] In other embodiments, the first switch 41 and the second switch 42 may also be other types of transistors.

[0065] The first signal line 21 and the second signal line 22 are controlled independently. The driving timing of the first signal line 21 and the driving timing of the second signal line 22 do not overlap, so as to avoid the display switch 11 and the black insertion switch 12 being turned on at the same time, which would affect the normal display of the pixel unit 10.

[0066] Each gate driving circuit 20 further includes at least one clock signal line CK. There is no limitation on the number of the clock signal lines CK, which is selected according to the actual structure of the gate driving circuit 20 .

[0067] The display panel includes a normal display mode and a black insertion display mode. When the display panel is in the normal display mode, at least one gate drive circuit 20 works, and the switch circuits 40 corresponding to all the shift register units GOA in the gate drive circuit 20 output the cascade control signals as drive cascade signals. That is to say, when the display panel is in the normal display mode, one gate drive circuit 20 works to drive each row of pixel units 10 on a single side; when two gate drive circuits 20 work at the same time, each row of pixel units 10 is driven on both sides. Compared with unilateral drive, bilateral drive can improve the driving ability of the pixel unit 10, and the picture display is more uniform. At the same time, when the gate drive circuit 20 on one side is abnormal, the gate drive circuit 20 on the other side can be used to work, so as to improve the fault tolerance of the gate drive circuit 20, and improve the yield and service life of the display panel.

[0068] When the display panel is in the black insertion display mode, both gate drive circuits 20 work, and the switch circuit 40 corresponding to all the shift register units GOA in one gate drive circuit 20 outputs the cascade control signal as a drive cascade signal, and the switch circuit 40 corresponding to all the shift register units GOA in the other gate drive circuit 20 outputs the cascade control signal as a black insertion cascade signal, wherein, within a frame, the driving timings of the two gate drive circuits 20 differ by at least half a frame. That is, one gate drive circuit 20 is used to drive each row of pixel units 10 to display a normal picture, and the other gate drive circuit 20 is used as a black insertion circuit to drive each row of pixel units 10 to display a black picture. Within a frame, the driving timings of the frame start signals of the two gate drive circuits 20 differ by at least half a frame.

[0069] Compared with the prior art, the coordinated use of the switch circuit 40 and the gate drive circuit 20 in the present application enables the display panel of the present application to have multiple display modes, which can not only realize single drive and dual drive, but also realize black insertion display, and can switch modes according to customer needs or display requirements to improve customer experience. Secondly, the present application does not increase the number of gate drive circuits 20 while being compatible with the normal display mode and the black insertion display mode, which is suitable for high-resolution display panels to realize the black insertion mode.

[0070] Furthermore, each gate drive circuit 20 further includes a ground power signal line VSS, and the display panel further includes a reset switch 50, which is arranged in one-to-one correspondence with the shift register unit GOA, an input end of the reset switch 50 is electrically connected to the black gate line Gate2 corresponding to the corresponding shift register unit GOA, an output end of the reset switch 50 is electrically connected to the ground power signal line VSS, and a control end of the reset switch 50 is connected to the output end of the next m-stage shift register unit GOA of the corresponding shift register unit GOA. Wherein, m is a natural number greater than or equal to 1.

[0071] The reset switch 50 is used to pull down the potential of the black insertion gate line Gate2 to a low potential after the black insertion display is finished in the black insertion display mode, so as to turn off the black insertion switch 12 connected to the black insertion gate line Gate2, thereby preventing the black insertion switch 12 from being incompletely turned off and affecting the normal display of the pixel unit 10. At the same time, it can also prevent the second switch 42 in the switch circuit 40 from leaking electricity in the normal display mode, causing the potential of the corresponding black insertion gate line Gate2 to be pulled up, causing the black insertion switch 12 to be turned on and affecting the pixel unit 10 to display a normal picture.

[0072] In the present application, in the black insertion display mode, within one frame, the driving timing of the frame start signals of the two gate driving circuits 20 is set to differ by at least half a frame, so that the reset switch 50 and the black insertion switch 12 corresponding to the same row of pixel units 10 will not be turned on at the same time, thereby affecting the pixel unit 10 to display a black picture. Specifically, when the black insertion switch 12 in the pixel unit 10 is turned on, the reset switch 50 corresponding to the row of pixel units 10 is turned on at the same time, which will pull down the potential of the black insertion gate line Gate2 corresponding to the row of pixel units 10, thereby causing the potential of the black insertion gate line Gate2 to be less than the gate threshold voltage of the black insertion switch 12, so that the potential of the black insertion gate line Gate2 is insufficient to turn on the black insertion switch 12, resulting in the pixel unit 10 being unable to display a black picture normally, affecting the black insertion display of the display panel.

[0073] It should be noted that, within a frame, the driving timing of the reset signal of the current shift register unit GOA and the driving timing of the current shift register unit GOA are both located in the first half frame of the current frame. In the black insertion display mode, the driving timing of the frame start signals of the two gate driving circuits 20 is set to differ by at least half a frame, so that the driving timing of the gate driving circuit 20 used as the black insertion circuit is located in the second half frame of the current frame, that is, when the black insertion switch 12 in the pixel unit 10 is turned on, the reset switch 50 corresponding to the pixel unit 10 of the row will not be turned on at the same time.

[0074] The control end of the reset switch 50 is connected to the output end of the corresponding shift register unit GOA of the next m stages, which can be understood as the control end of the reset switch 50 corresponding to the nth stage shift register unit GOA is connected to the output end of the n+mth stage shift register unit GOA, where n is a natural number greater than or equal to 1.

[0075] The cascade control signal output by the next h-stage shift register unit GOA serves as the reset signal of the current-stage shift register unit GOA. Specifically, the cascade control signal output by the n+h-stage shift register unit GOA serves as the reset signal of the n-stage shift register unit GOA. Wherein, h is a natural number greater than or equal to 1. The size relationship between h and m is not limited and is selected according to actual needs.

[0076] In this embodiment, the cascade control signal outputted from the output terminal of the same subsequent m-stage shift register unit GOA serves as the reset signal of the current stage shift register unit GOA and as the control signal received by the reset switch 50 corresponding to the current stage shift register unit GOA.

[0077] It can be understood that the cascade control signal outputted from the output terminal of the n+mth shift register unit GOA serves as the reset signal of the nth shift register unit GOA and as the control signal received by the reset switch 50 corresponding to the nth shift register unit GOA. That is, h is equal to m.

[0078] In this embodiment, the reset signal of a certain stage of shift register unit GOA is multiplexed into the control signal of the reset switch 50 corresponding to the stage of shift register unit GOA, which can reduce the routing of the gate drive circuit 20 and is conducive to the design of a narrow frame.

[0079] It should be noted that the reset signal of the last-stage shift register unit GOA of the present application is a frame start signal.

[0080] In a specific embodiment, the two gate driving circuits 20 are defined as a first gate driving circuit 20A and a second gate driving circuit 20B, respectively. The first gate driving circuit 20A is disposed in the frame area 102 on the left side of the display area 101, and the second gate driving circuit 20B is disposed in the frame area 102 on the right side of the display area 101. The first switch 41 and the second switch 42 corresponding to the shift register unit GOA in the first gate driving circuit 20A are respectively represented as T1 and T2, and the reset switch 50 corresponding to the shift register unit GOA in the first gate driving circuit 20A is represented as T3. The first switch 41 and the second switch 42 corresponding to the shift register unit GOA in the second gate driving circuit 20B are respectively represented as T4 and T5, and the reset switch 50 corresponding to the shift register unit GOA in the second gate driving circuit 20B is represented as T6.

[0081] The first signal line 21 and the second signal line 22 in the first gate drive circuit 20A are represented as SW1 and SW2, respectively, and the first signal line 21 and the second signal line 22 in the second gate drive circuit 20B are represented as SW3 and SW4, respectively. The frame start signal in the first gate drive circuit 20A is represented as STV1, and the frame start signal in the second gate drive circuit 20B is represented as STV2.

[0082] The nth shift register unit GOA is represented as Gn, the n+1th shift register unit GOA is represented as Gn+1, the n+mth shift register unit GOA is represented as Gn+m, and the n+1+mth shift register unit GOA is represented as Gn+1+m.

[0083] Please refer to 1 to Figure 6 , Figure 4 is a timing difference diagram of two gate drive circuits according to an embodiment of the present application. Figure 5 is a timing difference diagram of another embodiment of two gate drive circuits provided by the present application, Figure 6 This is a schematic diagram of mode switching of a display panel provided by the present application.

[0084] Normal display modes include dual-drive mode, left-side single-drive mode, and right-side single-drive mode.

[0085] When the display panel is in dual-drive mode, the first gate drive circuit 20A and the second gate drive circuit 20B work simultaneously, that is, the frame start signal STV1 of the first gate drive circuit 20A and the frame start signal STV2 of the second gate drive circuit 20B have the same drive timing. All switch circuits 40 output drive cascade signals according to the drive timing of the gate drive circuit 20 to control the display switch 11 to turn on. Specifically, when the current stage shift register unit GOA outputs the cascade control signal, SW1 and SW3 both provide a high potential, SW2 and SW4 both provide a low potential, T1 and T4 are turned on, T2 and T5 are turned off, and the current stage shift register unit GOA in the first gate drive circuit 20A and the current stage shift register unit GOA in the second gate drive circuit 20B simultaneously drive the corresponding row pixel unit 10 to display a normal picture. In this mode, the display panel has good driving capability and display uniformity.

[0086] When the display panel is in the left single-drive mode, the first gate drive circuit 20A works and the second gate drive circuit 20B does not work. The switch circuits 40 corresponding to the shift register unit GOA in the first gate drive circuit 20A all output drive cascade signals to control the display switch 11 to turn on. All black insertion switches 12 are closed. Specifically, the current stage shift register unit GOA in the first gate drive circuit 20A outputs a cascade control signal, SW1 provides a high potential, SW2, SW3 and SW4 all provide a low potential, T1 is turned on, T2, T4 and T5 are turned off, and the current stage shift register unit GOA in the first gate drive circuit 20A drives the corresponding row pixel unit 10 to display a normal picture.

[0087] When the display panel is in the right-side single-drive mode, the first gate drive circuit 20A does not work, and the second gate drive circuit 20B works. The switch circuits 40 corresponding to the shift register unit GOA in the second gate drive circuit 20B all output drive cascade signals to control the display switch 11 to turn on. All black insertion switches 12 are closed. Specifically, the current-stage shift register unit GOA in the second gate drive circuit 20B outputs a cascade control signal, SW3 provides a high potential, SW1, SW2, and SW4 all provide a low potential, T4 is turned on, T1, T2, and T5 are turned off, and the current-stage shift register unit GOA in the second gate drive circuit 20B drives the corresponding row pixel unit 10 to display a normal picture.

[0088] The black insertion display mode includes a first black insertion mode and a second black insertion mode. A frame of the picture includes a display phase t1 and a black insertion phase t2 in sequence.

[0089] When the display panel is in the first black insertion mode, both the first gate drive circuit 20A and the second gate drive circuit 20B are working. The switch circuits 40 corresponding to the shift register unit GOA in the first gate drive circuit 20A all output a drive cascade signal to control the display switch 11 to turn on, and the switch circuits 40 corresponding to the shift register unit GOA in the second gate drive circuit 20B all output a black insertion cascade signal to control the black insertion switch 12 to turn on. That is, the first gate drive circuit 20A is used to drive the pixel unit 10 of the corresponding row to display a normal picture, and the second gate drive circuit 20B is used as a black insertion circuit to drive the pixel unit 10 of the corresponding row to display a black picture. Specifically, in the display stage t1 within a frame of the picture, the current stage shift register unit GOA in the first gate drive circuit 20A outputs a cascade control signal, SW1 provides a high potential, SW2, SW3 and SW4 all provide a low potential, T1 is turned on, T2, T4 and T5 are turned off, and the current stage shift register unit GOA in the first gate drive circuit 20A drives the corresponding row of pixel units 10 to display a normal picture. In the black insertion phase t2 in the detection frame, the current stage shift register unit GOA in the second gate driving circuit 20B outputs a cascade control signal, SW4 provides a high potential, SW1, SW2 and SW3 all provide a low potential, T5 is turned on, T1, T2 and T4 are turned off, and the current stage shift register unit GOA in the second gate driving circuit 20B drives the corresponding row pixel unit 10 to display a black frame. In a frame, the driving timing of the second gate driving circuit 20B is delayed by at least half a frame compared to the timing of the first gate driving circuit 20A, that is, Figure 4 As shown, the driving timing of the frame start signal STV2 of the second gate driving circuit 20B is delayed by at least half a frame compared to the driving timing of the frame start signal STV1 of the first gate driving circuit 20A, so that the reset switch 50 corresponding to the same row of pixel units 10 will not be turned on at the same time as the black insertion switch 12, thereby affecting the pixel unit 10 to display a black picture.

[0090] When the display panel is in the second black insertion mode, both the first gate drive circuit 20A and the second gate drive circuit 20B work. The switch circuits 40 corresponding to the shift register unit GOA in the first gate drive circuit 20A output black insertion cascade signals to control the black insertion switch 12 to turn on, and the switch circuits 40 corresponding to the shift register unit GOA in the second gate drive circuit 20B output drive cascade signals to control the display switch 11 to turn on. That is, the first gate drive circuit 20A is used as a black insertion circuit to drive the pixel unit 10 of the corresponding row to display a black screen. The second gate drive circuit 20B is used to drive the pixel unit 10 of the corresponding row to display a normal screen. Specifically, in the display stage t1 within a frame of the screen, the current stage shift register unit GOA in the second gate drive circuit 20B outputs a cascade control signal, SW3 provides a high potential, SW1, SW2 and SW4 all provide a low potential, T4 is turned on, T1, T2 and T5 are turned off, and the current stage shift register unit GOA in the second gate drive circuit 20B drives the corresponding row pixel unit 10 to display a normal screen. In the black insertion phase t2 in the detection frame, the current stage shift register unit GOA in the first gate driving circuit 20A outputs a cascade control signal, SW2 provides a high potential, SW1, SW3 and SW4 all provide a low potential, T2 is turned on, T1, T4 and T5 are turned off, and the current stage shift register unit GOA in the first gate driving circuit 20A drives the corresponding row pixel unit 10 to display a black frame. In a frame, the driving timing of the first gate driving circuit 20A is delayed by at least half a frame compared to the timing of the second gate driving circuit 20B, that is, Figure 5 As shown, the driving timing of the frame start signal STV1 of the first gate driving circuit 20A is delayed by at least half a frame compared to the driving timing of the frame start signal STV2 of the second gate driving circuit 20B, so that the reset switch 50 corresponding to the same row of pixel units 10 will not be turned on at the same time as the black insertion switch 12, thereby affecting the pixel unit 10 to display a black picture.

[0091] See also Figure 7 , Figure 7 It is a flow chart of an implementation of a method for driving a display panel provided in the present application.

[0092] The present application provides a method for driving a display panel. The method for driving a display panel is used to drive the above-mentioned display panel. The method for driving a display panel specifically comprises the following steps:

[0093] Step S10: controlling the shift register unit to output a cascade control signal.

[0094] Specifically, the shift register unit is controlled to output the cascade control signal according to the driving timing of the gate driving circuit.

[0095] In a specific implementation, the step of controlling the shift register unit to output the cascade control signal specifically includes:

[0096] One of the two gate driving circuits is controlled to work, and the corresponding shift register unit is controlled to output a cascade control signal according to the driving timing of the gate driving circuit.

[0097] In another specific implementation, the step of controlling the shift register unit to output the cascade control signal specifically includes:

[0098] The two gate driving circuits are controlled to work simultaneously, and the shift register unit is controlled to output a cascade control signal according to the driving timing of the gate driving circuits.

[0099] Step S20: controlling the switch circuit corresponding to the shift register unit to output the cascade control signal as a driving cascade signal or a black insertion cascade signal.

[0100] Specifically, according to the driving sequence of the shift register units and the mode of the display panel, the switch circuit corresponding to the shift register unit is controlled to output the cascade control signal as a driving cascade signal or a black insertion cascade signal.

[0101] The display panel includes a normal display mode and a black insertion display mode.

[0102] Step S20: controlling the switch circuit corresponding to the shift register unit to output the cascade control signal as a driving cascade signal or a black insertion cascade signal, specifically comprising:

[0103] When the display panel is in a black insertion display mode, the switch circuits corresponding to all the shift register units in one gate driving circuit are controlled to output all the cascade control signals as driving cascade signals, and the switch circuits corresponding to all the shift register units in another gate driving circuit are controlled to output all the cascade control signals as black insertion cascade signals;

[0104] When the display panel is in a normal display mode, at least one gate driving circuit works, and the control switch circuit outputs all cascade control signals as driving cascade signals.

[0105] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0106] The above are only implementation methods of the present application, and are not intended to limit the patent protection scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly used in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A display panel, characterized in that: include: A plurality of pixel units arranged in an array, each of the pixel units comprising a display switch and a black insertion switch; Two gate drive circuits, each of which includes a plurality of cascaded shift register units; A switch circuit is arranged in one-to-one correspondence with the shift register units, and is arranged in correspondence with and electrically connected to at least one row of the pixel units; the switch circuit is used to output a single cascade control signal outputted by the corresponding shift register unit as a driving cascade signal or a black insertion cascade signal; The driving cascade signal is used to control the display switch in the pixel unit of the corresponding row to turn on, so as to drive the pixel unit to display a normal picture; the black insertion cascade signal is used to control the black insertion switch in the pixel unit of the corresponding row to turn on, so as to drive the pixel unit to display a black picture; The display panel further comprises a plurality of gate line groups arranged at intervals, each of the gate line groups being arranged corresponding to and electrically connected to a row of the pixel units; the gate line groups comprising a display gate line and a black insertion gate line arranged at intervals; the display gate line is electrically connected to a control end of a display switch in the pixel units of the corresponding row to control the turning on of the display switch, and the black insertion gate line is electrically connected to a control end of a black insertion switch in the pixel units of the corresponding row to control the turning on of the black insertion switch; The switch circuit is electrically connected between the corresponding shift register unit and the corresponding gate line group; the switch circuit is used to transmit the single cascade control signal output by the corresponding shift register unit as the driving cascade signal to the display gate line in the corresponding gate line group, or the switch circuit is used to transmit the single cascade control signal output by the corresponding shift register unit as the black insertion cascade signal to the black insertion gate line in the corresponding gate line group; Each of the gate drive circuits also includes a first signal line and a second signal line; the switch circuit includes a first switch and a second switch, the input end of the first switch is electrically connected to the output end of the corresponding shift register unit, the output end of the first switch is electrically connected to the corresponding display gate line, and the control end of the first switch is electrically connected to the first signal line; the input end of the second switch is connected to the same output end of the corresponding shift register unit as the input end of the first switch, the output end of the second switch is electrically connected to the corresponding black gate line, and the control end of the second switch is electrically connected to the second signal line.

2. The display panel according to claim 1, characterized in that: Each of the gate drive circuits also includes a ground power signal line, and the display panel also includes a reset switch, which is arranged in a one-to-one correspondence with the shift register unit, an input end of the reset switch is electrically connected to the black gate line corresponding to the corresponding shift register unit, an output end of the reset switch is electrically connected to the ground power signal line, and a control end of the reset switch is connected to the output end of the corresponding shift register unit of the last m stages of the shift register unit; wherein m is a natural number greater than or equal to 1.

3. The display panel according to claim 2, characterized in that: The cascade control signal outputted from the output end of the same subsequent m-stage shift register unit serves as a reset signal of the current-stage shift register unit and as a control signal received by a reset switch corresponding to the current-stage shift register unit.

4. The display panel according to claim 1, characterized in that: The display panel also includes a plurality of data lines; the pixel unit also includes a pixel capacitor, a pixel electrode and a common electrode, the input end of the display switch is electrically connected to the data line, the output end of the display switch is electrically connected to one end of the pixel capacitor via the pixel electrode, and the other end of the pixel capacitor is electrically connected to the common electrode; the input end of the black insertion switch is electrically connected to the pixel electrode, and the output end of the black insertion switch is connected to the common electrode.

5. The display panel according to claim 1, characterized in that: The two gate drive circuits have the same structure; the display panel includes a normal display mode and a black insertion display mode; When the display panel is in the normal display mode, at least one of the gate driving circuits is in operation, and the switch circuits corresponding to all the shift register units in the gate driving circuit output the cascade control signal as the driving cascade signal; When the display panel is in a black insertion display mode, both of the two gate drive circuits are working, and the switch circuit corresponding to all the shift register units in one of the gate drive circuits outputs the cascade control signals as drive cascade signals, and the switch circuit corresponding to all the shift register units in the other gate drive circuit outputs the cascade control signals as black insertion cascade signals, wherein, within one frame, the drive timings of the two gate drive circuits differ by at least half a frame.

6. A method for driving a display panel, for driving the display panel according to any one of claims 1 to 5; characterized in that: include: Controlling the shift register unit to output a cascade control signal; The switch circuit corresponding to the shift register unit is controlled to output the cascade control signal as a driving cascade signal or a black insertion cascade signal.

7. The method for driving a display panel according to claim 6, wherein: The display panel includes a normal display mode and a black insertion display mode; The control of the switch circuit corresponding to the shift register unit to output the cascade control signal as a driving cascade signal or a black insertion cascade signal comprises: When the display panel is in the black insertion display mode, the switch circuits corresponding to all the shift register units in one of the gate driving circuits are controlled to output the cascade control signals as driving cascade signals, and the switch circuits corresponding to all the shift register units in another of the gate driving circuits are controlled to output the cascade control signals as black insertion cascade signals; When the display panel is in the normal display mode, at least one of the gate driving circuits operates to control the switch circuit to output all of the cascade control signals as driving cascade signals.

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