Display panel and display device

Abstract

The application provides a display panel and a display device, wherein the time length of the bias adjustment stage and the time length of the non-emitting stage are set to be non-same ratio change, when the display panel is converted from a first mode to a second mode based on the change requirement of brightness, the time length of the non-emitting stage is in a state of being shortened, at this time, the time length of the bias adjustment stage is adjusted in a W1 / L1W2 / L2 mode, so that the change amplitude of the time length of the bias adjustment stage caused by the mode change of the working state is relatively small; that is, the time length of the bias adjustment stage in the second mode is relatively large, and the phenomenon of flicker of the display panel during the mode adjustment in the second mode is avoided. Therefore, the technical scheme provided by the application improves the flicker problem of the display panel under different brightness modes, and ensures that the display device has good display effect.

Description

[0001] This application is a divisional application of application number 202110905723.6, filed on August 6, 2021, entitled "Display Panel and Display Device". Technical Field

[0002] This application relates to the field of display technology, and more specifically, to a display panel and display device. Background Technology

[0003] Pixel circuits provide the driving current required for the light-emitting elements of a display device and control whether the light-emitting elements enter the light-emitting stage, thus becoming an indispensable component in most display devices. However, with the increase of usage time, the internal characteristics of the driving transistors in the pixel circuits change slowly, causing the threshold voltage of the driving transistors to drift, which affects the driving current they generate. Consequently, the display effect of the display device becomes unsatisfactory, and screen flickering is likely to occur. Summary of the Invention

[0004] In view of this, this application provides a display panel and a display device that effectively solves the technical problems existing in the prior art, improves the flickering problem of the display panel in different brightness modes, and ensures the display effect of the display device.

[0005] To achieve the above objectives, the technical solution provided by the present invention is as follows:

[0006] A display panel, comprising:

[0007] Pixel circuits and light-emitting elements;

[0008] The pixel circuit includes a driving module and a compensation module;

[0009] The driving module is used to provide driving current to the light-emitting element, and the driving module includes a driving transistor;

[0010] The compensation module is used to compensate the threshold voltage of the driving transistor, and the compensation module is connected between the gate and drain of the driving transistor.

[0011] One frame of the display panel includes a non-emissive phase and an emissive phase. The non-emissive phase includes a bias adjustment phase. During the bias adjustment phase, the compensation module is turned off, and the source or drain of the driving transistor receives a bias adjustment signal to adjust the bias state of the driving transistor.

[0012] The pixel circuit operates in a first mode and a second mode. In the first mode, the duration of the non-light-emitting phase is L1, and in the second mode, the duration of the non-light-emitting phase is L2, wherein L1 > L2.

[0013] The operation of the display panel in the first mode includes a first frame, and the operation of the display panel in the second mode includes a second frame, wherein...

[0014] In the first frame, the duration of the bias adjustment phase is W1, and in the second frame, the duration of the bias adjustment phase is W2, wherein W1 / L1 < W2 / L2.

[0015] Accordingly, this application also provides a display device, including the aforementioned display panel.

[0016] Compared with existing technologies, the technical solution provided in this application has at least the following advantages:

[0017] This invention provides a display panel and a display device, wherein the duration of the bias adjustment phase and the duration of the non-emissive phase are set to change non-proportionally. When the display panel switches from a first operating mode to a second operating mode based on brightness changes, the duration of the non-emissive phase shortens. At this time, the duration of the bias adjustment phase is adjusted according to the formula W1 / L1 < W2 / L2, so that the change in the duration of the bias adjustment phase caused by the change in operating mode is relatively small. That is, the duration of the bias adjustment phase is relatively long in the second mode, avoiding flickering during mode adjustment caused by a shorter duration of the bias adjustment phase in the second mode. Therefore, the technical solution provided by this invention improves the flickering problem of the display panel in different brightness modes, ensuring the display effect of the display device. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention;

[0020] Figure 2 A timing diagram of a first mode and a second mode provided for embodiments of the present invention;

[0021] Figure 3 A schematic diagram illustrating the drift of the Id-Vg curve of the driving transistor;

[0022] Figure 4 A timing diagram of another first mode and a second mode provided for embodiments of the present invention;

[0023] Figure 5 A timing diagram for yet another first mode and second mode provided in an embodiment of the present invention;

[0024] Figure 6 A timing diagram for yet another first mode and second mode provided in an embodiment of the present invention;

[0025] Figure 7 A timing diagram for yet another first mode and second mode provided in an embodiment of the present invention;

[0026] Figure 8 A timing diagram for yet another first mode and second mode provided in an embodiment of the present invention;

[0027] Figure 9 A timing diagram for yet another first mode and second mode provided in an embodiment of the present invention;

[0028] Figure 10 A timing diagram for yet another first mode and second mode provided in an embodiment of the present invention;

[0029] Figure 11 A timing diagram for yet another first mode and second mode provided in an embodiment of the present invention;

[0030] Figure 12 A timing diagram for yet another first mode and second mode provided in an embodiment of the present invention;

[0031] Figure 13 A timing diagram for yet another first mode and second mode provided in an embodiment of the present invention;

[0032] Figure 14 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0033] Figure 15 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention;

[0034] Figure 16 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention;

[0035] Figure 17 A timing diagram provided for an embodiment of the present invention;

[0036] Figure 18 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention;

[0037] Figure 19 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention;

[0038] Figure 20This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention;

[0039] Figure 21 Another timing diagram provided for an embodiment of the present invention;

[0040] Figure 22 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention;

[0041] Figure 23 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention;

[0042] Figure 24 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention;

[0043] Figure 25 This is yet another timing diagram provided in an embodiment of the present invention;

[0044] Figure 26 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention;

[0045] Figure 27 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention;

[0046] Figure 28 This is yet another timing diagram provided in an embodiment of the present invention;

[0047] Figure 29 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention;

[0048] Figure 30 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention;

[0049] Figure 31 This is yet another timing diagram provided in an embodiment of the present invention;

[0050] Figure 32 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention;

[0051] Figure 33 This is yet another timing diagram provided in an embodiment of the present invention;

[0052] Figure 34 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention. Detailed Implementation

[0053] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0054] As described in the background section, pixel circuits provide the driving current required for the light-emitting elements of a display device and control whether the light-emitting elements enter the light-emitting stage, thus becoming an indispensable component in most display devices. However, with the increase of usage time, the internal characteristics of the driving transistors in the pixel circuits change slowly, causing the threshold voltage of the driving transistors to drift, thereby affecting the driving current they generate. This results in poor display effects in existing display devices, with frequent screen flickering.

[0055] Based on this, embodiments of the present invention provide a display panel and a display device, which effectively solves the technical problems existing in the prior art, improves the flickering problem of the display panel in different brightness modes, and ensures the display effect of the display device.

[0056] To achieve the above objectives, the technical solutions provided by the embodiments of the present invention are as follows, in detail... Figures 1 to 34 The technical solutions provided in the embodiments of the present invention will be described in detail.

[0057] Combination Figure 1 and Figure 2 As shown, Figure 1 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention. Figure 2 This invention provides a timing diagram of a first mode and a second mode, wherein the display panel provided in this embodiment includes: a pixel circuit 10 and a light-emitting element 20; the pixel circuit 10 includes a driving module 11 and a compensation module 12; the driving module 11 is used to provide driving current to the light-emitting element 20, and the driving module 11 includes a driving transistor T0; the compensation module 12 is used to compensate the threshold voltage of the driving transistor T0, and the compensation module 12 is connected between the gate and drain of the driving transistor T0; one frame of the display panel includes a non-light-emitting stage and a light-emitting stage, the non-light-emitting stage includes a bias adjustment stage, in which the compensation module 12 is turned off, and the source or drain of the driving transistor T0 receives a bias adjustment signal to adjust the bias state of the driving transistor T0.

[0058] The pixel circuit 10 operates in two modes: a first mode (EMIT1) and a second mode (EMIT2). The duration of the non-light-emitting phase in the first mode (EMIT1) is L1, and the duration of the non-light-emitting phase in the second mode (EMIT2) is L2, where L1 > L2. The operation of the display panel in the first mode (EMIT1) includes a first frame, and the operation of the display panel in the second mode (EMIT2) includes a second frame. In the first frame, the duration of the bias adjustment phase is W1, and in the second frame, the duration of the bias adjustment phase is W2, where W1 / L1 < W2 / L2.

[0059] Understandably, in the first mode EMIT1 provided by this embodiment of the invention, the brightness of the light-emitting element is lower than that in the second mode EMIT2. The display panel provided by this embodiment of the invention can adjust the brightness of the light-emitting element. In the first mode EMIT1, the duration L1 of the non-light-emitting phase is greater than the duration L2 of the non-light-emitting phase in the second mode EMIT2. When the total duration of the non-light-emitting and light-emitting phases in a single frame is the same or similar, the duration of the light-emitting phase in the first mode EMIT1 is greater than that in the second mode EMIT2. Correspondingly, the brightness of the light-emitting element is lower in the first mode EMIT1 and higher in the second mode EMIT2. The brightness mode is switched by switching between the first mode EMIT1 and the second mode EMIT2. It should be noted that the brightness in the first mode and the brightness in the second mode refer to the total brightness perceived by the human eye in the final displayed image. Because the duration of the light-emitting phase in the first mode is shorter than that in the second mode, the duration of the light-emitting phase in each frame is longer in the second mode, resulting in a higher total brightness perceived by the human eye in the final image.

[0060] The pixel circuit 10 provided in this embodiment of the invention includes a driving module 11, the output terminal of which is coupled to a light-emitting element 20. The driving module 11 includes a driving transistor T0. When the driving transistor T0 is turned on, the driving module 11 provides a driving current to the light-emitting element 20. Optionally, the source of the driving transistor T0 is the input terminal of the driving module 11, and the drain of the driving transistor T0 is the output terminal of the driving module 12. This invention does not impose specific limitations on this; the design needs to be tailored to the specific conduction type of the driving transistor T0. Furthermore, the pixel circuit 10 includes a compensation module 12, which is used to compensate for the threshold voltage of the driving transistor T0. The compensation module 12 is connected between the gate and drain of the driving transistor T0. When the transmission path of the compensation module 12 is turned on, the transmission path between the gate and drain of the driving transistor T0 is turned on, thereby adjusting the voltage between the gate and output terminal of the driving transistor T0 and compensating for the threshold voltage of the driving transistor T0.

[0061] Generally, in the non-bias adjustment stages such as the light-emitting phase of a pixel circuit, when the driving transistor is a PMOS type, there may be a situation where the gate potential is greater than the drain potential when the driving transistor is turned on; when the driving transistor is an NMOS type, there may be a situation where the gate potential is less than the drain potential when the driving transistor is turned on. Prolonged operation in this state can lead to ion polarization inside the driving transistor, resulting in a built-in electric field and causing the threshold voltage of the driving transistor to continuously increase. Figure 3 The diagram shows the drift of the Id-Vg curve of the driving transistor. The shift in the Id-Vg curve causes a shift in the threshold voltage Vth of the driving transistor, which in turn affects the driving current flowing into the light-emitting element and thus affects the display effect of the panel.

[0062] The pixel circuit 10 provided in this embodiment of the invention adds a bias adjustment stage to its operation. During the bias adjustment stage, the compensation module 12 is turned off, and the source or drain of the driving transistor T0 receives a bias adjustment signal to adjust the bias state of the driving transistor T0. This improves the potential difference between the gate and drain potentials, or between the gate and source potentials, of the driving transistor T0, reduces the degree of ion polarization inside the driving transistor T0, ensures that the Id-Vg curve of the driving transistor T0 does not shift, reduces the threshold voltage shift of the driving transistor T0, and improves the display effect of the panel.

[0063] Furthermore, in this embodiment of the invention, the duration of the bias adjustment phase and the duration of the non-emissive phase are set to be non-symmetrical. When the display panel switches from the first operating mode EMIT1 to the second operating mode EMIT2 based on brightness changes, the duration of the non-emissive phase shortens. At this time, the duration of the bias adjustment phase is adjusted according to the formula W1 / L1 < W2 / L2, so that the change in the duration of the bias adjustment phase caused by the change in operating mode is relatively small. That is, the duration of the bias adjustment phase is relatively long in the second operating mode EMIT2 because the duration of the emissive phase is relatively long, and the bias situation may be more severe, requiring a longer bias adjustment phase to offset the influence of the bias of the driving transistor. Maintaining a longer duration of the bias adjustment phase in the second operating mode EMIT2 avoids the flickering phenomenon that occurs when the display panel adjusts its mode due to a shorter duration of the bias adjustment phase in the second operating mode EMIT2. Therefore, the technical solution provided by this invention improves the flickering problem of the display panel in different brightness modes and ensures the display effect of the display device.

[0064] In one embodiment of the present invention, the relationship between the time length W1 of the offset adjustment phase in the first frame and the time length W2 of the offset adjustment phase in the second frame can be W1 ≤ W2. For example... Figure 4 The diagram shows a timing diagram of another first mode and a second mode provided by an embodiment of the present invention. In this embodiment, the time length W1 of the offset adjustment stage in the first frame can be equal to the time length W2 of the offset adjustment stage in the second frame. That is, the time length of the offset adjustment stage can remain unchanged in different brightness modes, thereby improving the flickering problem of the display panel in different brightness modes.

[0065] Or such as Figure 5The diagram shows a timing diagram of another first mode and second mode provided by an embodiment of the present invention. In this embodiment, the duration W1 of the bias adjustment phase in the first frame can be less than the duration W2 of the bias adjustment phase in the second frame. Furthermore, the duration L1 of the non-light-emitting phase in the first mode EMIT1 is greater than the duration L2 of the non-light-emitting phase in the second mode EMIT2. Therefore, when the duration of a frame is consistent, the duration of the light-emitting phase in the first mode EMIT1 is less than the duration of the light-emitting phase in the second mode EMIT2. Since the threshold voltage shift of the driving transistor T0 is mainly caused during the light-emitting phase, the longer the duration of the light-emitting phase, the more severe the shift. Therefore, adjusting the duration W2 of the bias adjustment phase in the second frame to be greater than the duration W1 of the bias adjustment phase in the first frame balances the threshold voltage of the driving transistor T0 under the first mode EMIT1 and the second mode EMIT2, improving the flickering problem of the display panel under different brightness modes.

[0066] In other embodiments of this application, under the premise that W1 / L1 < W2 / L2, the relationship between W1 and W2 can also be W1 > W2. In this case, when switching from the first mode to the second mode, the duration of the non-emission phase becomes shorter, and the duration of the bias adjustment phase also becomes shorter. For example, when there is a certain requirement for the duration of the non-emission phase of the second mode, the duration of the bias adjustment phase can be appropriately shortened to ensure that the duration of the non-emission phase is shorter.

[0067] In one embodiment of the present invention, the variation relationships of the offset adjustment phase duration W1 in the first frame, the offset adjustment phase duration W2 in the second frame, the non-emissive phase duration L1 of the pixel circuit in the first mode EMIT1, and the non-emissive phase duration L2 of the pixel circuit in the second mode EMIT2 can be W2 / W1 < L1 / L2, where W2 / W1 ≥ 1 and L1 / L2 > 1. The present invention primarily considers that the extension of the non-emissive phase duration in the first mode is greater than the shortening of the offset adjustment phase duration in the first mode, thus avoiding an excessively short offset adjustment phase duration that could lead to incomplete offset adjustment in the first mode.

[0068] In one embodiment of the present invention, the present invention provides the following time lengths: W1 in the first frame, W2 in the second frame, L1 in the non-emissive phase of the pixel circuit in the first mode EMIT1, and L2 in the second mode EMIT2, wherein W1 / L1 < 1 / 2, and / or W2 / L2 < 1 / 2. The present invention optimizes the duration of the offset adjustment phase in the first frame (W1) and the second frame (W2) by limiting the ratio ranges of W1 and L1, and limiting the ratio ranges of W2 and L2, thereby avoiding excessively long offset adjustment phase durations. Generally, during a single frame of display, there are high-brightness and low-brightness light-emitting elements. The gate potential of the driving transistor for the high-brightness element is lower, while the gate potential of the driving transistor for the low-brightness element is relatively higher. However, the bias adjustment signal is the same in some cases. Therefore, if the duration of the bias adjustment phase is set too long, the difference between the bias adjustment results of the driving transistors for the high-brightness and low-brightness elements will further widen, resulting in a poor display effect. Therefore, this embodiment of the invention sets the relevant proportional relationships W1 / L1 < 1 / 2 and / or W2 / L2 < 1 / 2 to ensure that the duration of the bias adjustment phase is within half of the entire non-light-emitting phase, avoiding a situation where the bias adjustment phase is too long and leads to a large difference in the bias adjustment of the driving transistors for light-emitting elements of different brightness, thus improving the display effect of the panel.

[0069] In one embodiment of the present invention, the bias adjustment stage in the first frame includes N1 sub-bias adjustment stages, where N1 ≥ 1, and the bias adjustment stage in the second frame includes N2 sub-bias adjustment stages, where N2 ≥ 1; wherein the duration of at least one sub-bias adjustment stage in the first frame is equal to the duration of at least one sub-bias adjustment stage in the second frame. Specifically, as follows... Figure 6The diagram shows a timing diagram of another first mode and a second mode provided by an embodiment of the present invention. In the first frame provided by the present invention, the time lengths of the N1 sub-bias adjustment stages included in the bias adjustment stage are respectively the time lengths of the first sub-bias adjustment stage W11 to the N1st sub-bias adjustment stage W1n; and in the second frame, the time lengths of the N2 sub-bias adjustment stages included in the bias adjustment stage are respectively the time lengths of the first sub-bias adjustment stage W21 to the N2nd sub-bias adjustment stage W2n. Here, n in W1n and W2n is merely a code to indicate a certain number, and does not mean that the number of bias adjustment stages in W1n and W2n is equal. N1 and N2 may be equal or unequal. The time length of at least one sub-bias adjustment stage in the first frame is equal to the time length of at least one sub-bias adjustment stage in the second frame. As can be seen, the bias adjustment stage provided by the present invention can be composed of at least one sub-bias adjustment stage, and there are at least one sub-bias adjustment stage with equal time length in the first frame and the second frame. That is, the time length of at least one sub-bias adjustment stage does not change with the adjustment of the brightness mode, ensuring that the display panel can avoid flickering problems in different brightness modes.

[0070] like Figure 7 The diagram shows a timing diagram of another first mode and a second mode provided by an embodiment of the present invention. In this embodiment, the time length W1i of the i-th sub-bias adjustment stage in the first frame is equal to the time length W2i of the i-th sub-bias adjustment stage in the second frame, where 1 ≤ i ≤ N0; when N1 ≠ N2, N0 is the smaller of N1 and N2; when N1 = N2, N0 = N1 = N2. This embodiment sets the time lengths of the sub-bias adjustment stages in the first and second frames that have the same sequence starting from the non-light-emitting stage to be the same, making the total time length of the bias adjustment stages in the first and second frames the same. This further ensures that the bias adjustment results are similar under different brightness modes, and ensures that the display panel can avoid flickering problems under different brightness modes.

[0071] Furthermore, in this embodiment, |N1-N2|≥1. When W1<W2, N2-N1≥1. That is, at this time, the bias adjustment stage in the second frame has at least one more sub-bias adjustment stage than the bias adjustment stage in the first frame. The duration of the bias adjustment stage is adjusted by adjusting the number of sub-bias adjustment stages. Because the control signals in the display panel are often pulses of a certain width, adjusting the pulse width often requires adjusting various signals in the circuit elements that generate the pulse, which may result in a large adjustment. However, adjusting the number of pulses often only requires giving a specific instruction. Therefore, in this embodiment, N2-N1≥1 is set so that W1<W2. Similarly, when W1>W2, N1-N2≥1. At this time, the bias adjustment stage in the first frame has at least one more sub-bias adjustment stage than the bias adjustment stage in the second frame. The duration of the bias adjustment stage is adjusted by adjusting the number of sub-bias adjustment stages.

[0072] like Figure 8 The diagram shows a timing diagram of another first mode and a second mode provided by an embodiment of the present invention. In the first frame, the time interval between the start of the non-emission phase and the start of the bias adjustment phase is L3, and in the second frame, the time interval between the start of the non-emission phase and the start of the bias adjustment phase is L4, where L3 > L4. The technical solution provided by this embodiment of the present invention adjusts the duration of the non-emission phase in the first frame and the second frame by adjusting the time interval between the start of the non-emission phase and the start of the bias adjustment phase in the first and second frames. This is mainly because adjusting the duration of the non-emission phase after the start of the bias adjustment phase involves adjusting the time of the bias adjustment phase. Therefore, adjusting L3 and L4 before the start of the bias adjustment phase can effectively avoid the adverse effects on the time of the bias adjustment phase, ensuring the display effect in different modes and avoiding flickering problems.

[0073] like Figure 9 The diagram shown illustrates a timing diagram of another first mode and a second mode provided in an embodiment of the present invention. The non-light-emitting stage further includes a signal adjustment stage. In the signal adjustment stage, the compensation module is activated, and the gate of the driving transistor T0 receives a preset signal to adjust the gate potential of the driving transistor T0. The signal adjustment stage includes M sub-signal adjustment stages. For example, in the first mode EMIT, the signal adjustment stage includes M sub-signal adjustment stages Z11 to Z1m, and in the second mode EMIT2, the signal adjustment stage includes M sub-signal adjustment stages Z21 to Z2m, where M ≥ 1. The activation of the compensation module 12 corresponds to the signal adjustment stage.

[0074] like Figure 10The diagram shows a timing diagram of another first mode and a second mode provided by an embodiment of the present invention. The bias adjustment stage provided by this embodiment is located in the time period from the start of the non-emission stage to the start of the j-th sub-signal adjustment stage, where 1 ≤ j ≤ M. In the first frame, the time length from the start of the non-emission stage to the start of the j-th sub-signal adjustment stage Z1j is L11, and the time length from the start of the j-th sub-signal adjustment stage Z1j to the end of the non-emission stage is L12. In the second frame, the time length from the start of the non-emission stage to the start of the j-th sub-signal adjustment stage Z2j is L21, and the time length from the start of the j-th sub-signal adjustment stage Z2j to the end of the non-emission stage is L22. L11 = L21, and L12 > L22. The bias adjustment stage provided by this embodiment is before the start of the j-th sub-signal adjustment stage, and L11 = L21, and L12 > L22, thereby adjusting the time period from the start of the j-th sub-signal adjustment stage to the end of the non-emission stage, avoiding any impact on the timing of the bias adjustment stage.

[0075] like Figure 11 The diagram shows a timing diagram of another first mode and a second mode provided by an embodiment of the present invention. In this embodiment, L11 = L21, and L12 > L22; furthermore, L12 > L11, and / or L22 > L21. In at least one of the first and second frames provided by this embodiment, the time length of the non-light-emitting phase including the bias adjustment phase is shorter than the time length without the bias adjustment phase. On the one hand, by adjusting the portion of the non-light-emitting phase that does not include the bias adjustment phase, the time of the non-light-emitting phase for different brightness modes is adjusted; on the other hand, this avoids the bias adjustment time being too long, which could lead to uneven display of high and low grayscale areas on the panel.

[0076] like Figure 12This is a timing diagram of another first mode and second mode provided by an embodiment of the present invention. In this embodiment, the bias adjustment stage is located in the time period from the end of the j-th sub-signal adjustment stage to the end of the non-emission stage, 1≤j≤M. In the first frame, the time length from the start of the non-emission stage to the end of the j-th sub-signal adjustment stage Z1j is L13, and the time length from the end of the j-th sub-signal adjustment stage Z1j to the end of the non-emission stage is L14. In the second frame, the time length from the start of the non-emission stage to the end of the j-th sub-signal adjustment stage Z2j is L23, and the time length from the end of the j-th sub-signal adjustment stage Z2j to the end of the non-emission stage is L24. In this case, L13>L23, and L14=L24. The bias adjustment stage provided in this embodiment of the invention is located in the time period between the end of the j-th sub-signal adjustment stage and the end of the non-light emission stage, and L13 > L23 and L14 = L24. Therefore, the time in the non-light emission stage that does not include the bias adjustment stage (i.e., the time between the start of the non-light emission stage and the end of the j-th sub-signal adjustment stage) is adjusted, while the time that includes the bias adjustment stage (i.e., the time between the end of the j-th sub-signal adjustment stage and the end of the non-light emission stage) remains unchanged.

[0077] like Figure 12 In the embodiments of the present invention, L13 > L23 and L14 = L24; and, in the embodiments of the present invention, L13 > L14, and / or, L23 > L24. In at least one of the first and second frames provided in the embodiments of the present invention, the duration of the offset adjustment phase within the non-light-emitting stage is shorter than the duration without the offset adjustment phase. On the one hand, by adjusting the portion of the non-light-emitting stage that does not include the offset adjustment phase, the duration of the non-light-emitting stage for different brightness modes is adjusted; on the other hand, this avoids the situation where the offset adjustment time is too long, leading to uneven display of high grayscale areas and low grayscale areas on the panel.

[0078] like Figure 13 The diagram shown is a timing diagram of another first mode and a second mode provided in an embodiment of the present invention, wherein, in Figure 9Based on the illustrated embodiment, the bias adjustment stage provided in this embodiment of the invention includes N sub-bias adjustment stages. In the first frame, the time lengths of the N sub-bias adjustment stages are from the time length W11 of the first sub-bias adjustment stage to the time length W1n of the Nth sub-bias adjustment stage; and in the second frame, the time lengths of the N sub-bias adjustment stages are from the time length W21 of the first sub-bias adjustment stage to the time length W2n of the Nth sub-bias adjustment stage, where N ≥ 1. At least one sub-bias adjustment stage begins after the end of the first sub-signal adjustment stage. In the first frame, the total time length of the sub-bias adjustment stages beginning after the end of the first sub-signal adjustment stage Z11 is W10; in the second frame, the total time length of the sub-bias adjustment stages beginning after the end of the first sub-signal adjustment stage Z21 is W20, where W10 = W20.

[0079] Further as Figure 13 As shown, in the first frame provided by this embodiment of the invention, all sub-bias adjustment stages can begin after the end of the first sub-signal adjustment stage Z11, that is, W10 can be equal to W1; and in the second frame, all sub-bias adjustment stages can begin after the first sub-signal adjustment stage Z21, that is, W20 can be equal to W2. It should be noted that this invention does not impose a specific limit on the number of sub-bias adjustment stages following the first sub-signal adjustment stage in the first and second frames, and specific design is required based on actual applications.

[0080] The specific structure of the pixel circuit provided in the embodiments of the present invention will be described in more detail below.

[0081] like Figure 14 The diagram shows another pixel circuit structure provided in an embodiment of the present invention. The pixel circuit 10 includes a data writing module 13 and a reset module 14. The data writing module 13 is connected to the source of the driving transistor T0 and is used to provide a data signal Vdata to the driving module 11. The reset module 14 is connected to the gate of the driving transistor T0 and is used to provide a reset signal Vref1 to the gate of the driving transistor T0. M = 1, that is, the signal adjustment stage only includes the first sub-signal adjustment stage, and the preset signal is the data signal Vdata. During the signal adjustment stage, the data writing module 13 is turned on, and the data signal terminal provides the data signal Vdata to the gate of the driving transistor T0 through the data writing module 13, the driving module 11, and the compensation module 12.

[0082] Figure 14In the circuit shown, the data writing module 13 includes a first transistor T1. The first electrode of the first transistor T1 is connected to the data signal Vdata, the second electrode of the first transistor T1 is connected to the source of the driving transistor T0, and the gate of the first transistor T1 is connected to the first scan signal K1. During the bias adjustment stage, the first scan signal K1 controls the first transistor T1 to turn on, so as to transmit the bias adjustment signal to the driving transistor T0. At this time, the bias adjustment signal can be the current data signal on the data line connected to the pixel circuit, the data signal transmitted from the previous frame, or some other signal. The present invention does not impose specific limitations on this.

[0083] Figure 14 In the circuit shown, the compensation module 12 includes a second transistor T2. The first electrode of the second transistor T2 is connected to the drain of the driving transistor T0, and the second electrode of the second transistor T2 is connected to the gate of the driving transistor T0. The gate of the second transistor T2 is connected to the second scan signal K2. Optionally, in this embodiment of the invention, the second transistor T2 can be an oxide semiconductor transistor (OST). OSTs have relatively smaller leakage current, which helps to stabilize the potential of the driving transistor. Similarly, the driving transistor T0 can optionally be an OST, specifically an indium gallium zinc oxide (IGZO) semiconductor transistor. The driving transistor T0 has advantages such as high mobility, low leakage current, good uniformity, transparency, and simple fabrication process.

[0084] Figure 14 In the circuit shown, the reset module 14 includes a reset transistor Tr1. The first electrode of the reset transistor Tr1 is connected to the reset signal Vref1, the second electrode of the reset transistor Tr1 is connected to the gate of the driving transistor T0, and the gate of the reset transistor Tr1 is connected to the reset scan signal Kr1.

[0085] Figure 14 In the circuit shown, the second scan signal K2 is a pulse signal. When the second scan signal K2 outputs a valid pulse, it controls the path between the first electrode and the second electrode of the second transistor T2 to conduct, thereby compensating for the threshold voltage of the driving transistor T0. The pixel circuit 10 provided in this embodiment of the invention includes a bias adjustment stage. In the bias adjustment stage, the second scan signal K2 outputs an invalid pulse to control the second transistor T2 to turn off. Furthermore, the pixel circuit 10 provided in this embodiment of the invention also includes a signal adjustment stage. The second scan signal K2 outputs a valid pulse to control the path between the first electrode and the second electrode of the second transistor T2 to conduct, so that the gate of the driving transistor T0 receives a preset signal. The signal adjustment stage only includes a first sub-signal adjustment stage, where the preset signal received by the gate of the driving transistor T0 is the data signal Vdata.

[0086] In one embodiment of the present invention, the driving transistor T0 provided by the present invention can be a P-type transistor, specifically as follows: Figure 15 As shown, Figure 15 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention. Figure 15 The pixel circuit shown is Figure 14 Based on the circuit shown, it also includes a third transistor T3 and a fourth transistor T4 for controlling light emission. The gates of the third transistor T3 and the fourth transistor T4 are connected to a light emission control signal EM. The first electrode of the third transistor T3 is connected to a first power supply signal PVDD. The second electrode of the third transistor T3 is connected to the source of the driving transistor T0. The first electrode of the fourth transistor T4 is connected to the drain of the driving transistor T0. The second electrode of the fourth transistor T4 is connected to one end of the light-emitting element 20, and the other end of the light-emitting element 20 is connected to a second power supply signal PVEE. The light emission control signal EM is a pulse signal. During a valid pulse, the light emission control signal EM controls the third transistor T3 and the fourth transistor T4 to conduct, and the light-emitting element 20 is in the light-emitting stage. During an invalid pulse, the light emission control signal EM controls the third transistor T3 and the fourth transistor T4 to turn off, and the light-emitting element 20 is in the non-light-emitting stage. It also includes a holding capacitor C for maintaining the node potential. The first end of the holding capacitor C is connected to the first power supply signal PVDD, and the second end of the holding capacitor C is connected to the gate of the driving transistor T0.

[0087] Furthermore, the driving transistor T0 provided in this embodiment of the invention can be an N-type transistor, specifically as follows: Figure 16 As shown, Figure 16 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention. Figure 16 The pixel circuit shown is Figure 14 Based on the circuit shown, it also includes a third transistor T3 and a fourth transistor T4 for controlling light emission. The gates of the third transistor T3 and the fourth transistor T4 are connected to a light emission control signal EM. The first electrode of the third transistor T3 is connected to a first power supply signal PVDD. The second electrode of the third transistor T3 is connected to the drain of the driving transistor T0. The first electrode of the fourth transistor T4 is connected to the source of the driving transistor T0. The second electrode of the fourth transistor T4 is connected to one end of the light-emitting element 20, and the other end of the light-emitting element 20 is connected to a second power supply signal PVEE. The light emission control signal EM is a pulse signal. When the light emission control signal EM is active, the light-emitting element 20 is in the light-emitting stage, and when the light emission control signal EM is inactive, the light-emitting element 20 is in the non-light-emitting stage. It also includes a holding capacitor C for maintaining the node potential. The first end of the holding capacitor C is connected to the source of the driving transistor T0, or the first end of the holding capacitor C is connected to the light-emitting element 20, and the second end of the holding capacitor C is connected to the gate of the driving transistor T0.

[0088] Combination Figure 17 As shown, Figure 15 and Figure 16 The timing diagram of any pixel circuit is shown below. First, the light emission control signal EM outputs an invalid pulse, causing the pixel circuit 10 to control the light emission element 20 to be in a non-light emission stage. The non-light emission stage includes a reset stage, a bias adjustment stage, and a signal adjustment stage. In the reset stage, the reset scan signal Kr1 controls the reset transistor Tr1 to turn on, transmitting the reset signal Vref1 to the gate of the driving transistor T0. In the bias adjustment stage, the second scan signal K2 outputs an invalid pulse to control the second transistor T2 to turn off. Simultaneously, the first scan signal K1 controls the first transistor T1 to turn on, transmitting the bias adjustment signal to the source of the driving transistor T0, and then from the driving transistor T0 to the drain of the driving transistor T0, used to adjust the bias state of the driving transistor T0. The bias adjustment signal can be provided through the port of the data signal Vdata. In the signal adjustment stage, the second scan signal K2 outputs an valid pulse to control the second transistor T2 to turn on. Simultaneously, the first scan signal K1 controls the first transistor T1 to turn on. The data signal Vdata, multiplexed as a preset signal, is transmitted to the gate of the driving transistor T0 through the first transistor T1, the driving transistor T0, and the second transistor T2. Then, the light emission control signal EM outputs a valid pulse, causing the pixel circuit 10 to control the light emission element 20 to be in the light emission stage. It should be noted that the light emission control signal EM provided in this embodiment of the invention can be a single control signal that controls two transistors simultaneously; or, the light emission control signal EM can be divided into two sub-light emission control signals, each controlling its corresponding transistor, and the duration of the invalid pulse output by the two sub-light emission control signals is the length of the non-light emission stage.

[0089] like Figure 18 The diagram shows a schematic of another pixel circuit provided in an embodiment of the present invention. The pixel circuit includes a data writing module 15 and a reset module 16. The data writing module 15 is connected to the source of the driving transistor T0 and is used to provide a data signal Vdata to the driving module T0. The reset module 16 is connected to the drain of the driving transistor T0 and is used to provide a reset signal Vref2 to the gate of the driving transistor T0. M = 2, and in the first sub-signal adjustment stage, the preset signal is the reset signal Vref2, and in the second sub-signal adjustment stage, the preset signal is the data signal Vdata. In the first sub-signal adjustment stage, the reset module 16 is turned on, and the reset signal terminal provides the reset signal Vref2 to the gate of the driving transistor T0 through the reset module 16 and the compensation module 12. In the second sub-signal adjustment stage, the data writing module 15 is turned on, and the data signal terminal provides the data signal Vdata to the gate of the driving transistor T0 through the data writing module 15, the driving module 11, and the compensation module 12.

[0090] Figure 18 In the circuit shown, the data writing module 15 includes a fifth transistor T5. The first electrode of the fifth transistor T5 is connected to the data signal Vdata, the second electrode of the fifth transistor T5 is connected to the source of the driving transistor T0, and the gate of the fifth transistor T5 is connected to the fifth scan signal K5.

[0091] Figure 18 In the circuit shown, the compensation module 12 includes a second transistor T2. The first electrode of the second transistor T2 is connected to the drain of the driving transistor T0, and the second electrode of the second transistor T2 is connected to the gate of the driving transistor T0. The gate of the second transistor T2 is connected to the second scan signal K2. Optionally, in this embodiment of the invention, the second transistor T2 can be an oxide semiconductor transistor (OST). OSTs have relatively smaller leakage current, which helps to stabilize the potential of the driving transistor. Similarly, the driving transistor T0 can optionally be an OST, specifically an indium gallium zinc oxide (IGZO) semiconductor transistor. The driving transistor T0 has advantages such as high mobility, low leakage current, good uniformity, transparency, and simple fabrication process.

[0092] Figure 18 In the circuit shown, the reset module 16 includes a reset transistor Tr2. The first electrode of the reset transistor Tr2 is connected to the reset signal Vref2, the second electrode of the reset transistor Tr2 is connected to the drain of the driving transistor T0, and the gate of the reset transistor Tr2 is connected to the reset scan signal Kr2.

[0093] Figure 18In the circuit shown, the second scan signal K2 is a pulse signal. When the second scan signal K2 outputs a valid pulse, it controls the path between the first electrode and the second electrode of the second transistor T2 to be turned on. The pixel circuit 10 provided in this embodiment of the invention includes a bias adjustment stage. In the bias adjustment stage, the second scan signal K2 outputs an invalid pulse to control the second transistor T2 to be turned off; while the reset transistor Tr2 is turned on according to the control of the reset scan signal Kr2. The reset transistor Tr2 transmits the bias adjustment signal to the drain of the driving transistor T0. The bias adjustment signal is provided by the port of the reset signal Vref2. That is, the reset signal Vref2 is actually a signal with different levels in the reset stage and the bias adjustment stage. For example, when the driving transistor is a PMOS transistor, the Vref2 signal is a low level signal in the reset stage and a high level signal in the bias adjustment stage; when the driving transistor is an NMOS transistor, the Vref2 signal is a high level signal in the reset stage and a low level signal in the bias adjustment stage. Furthermore, the pixel circuit 10 provided in this embodiment of the invention further includes a signal adjustment stage, which includes a first sub-signal adjustment stage and a second sub-signal adjustment stage. In the first sub-signal adjustment stage, the second scan signal K2 outputs an effective pulse to control the path between the first electrode and the second electrode of the second transistor T2 to be turned on. At the same time, the reset transistor Tr2 is controlled to be turned on by the reset scan signal Kr2, and the reset signal Vref2 is transmitted to the gate of the driving transistor T0 through the reset transistor Tr2 and the second transistor T2. In the second sub-signal adjustment stage, the second scan signal K2 outputs an effective pulse to control the path between the first electrode and the second electrode of the second transistor T2 to be turned on. At the same time, the fifth transistor T5 and the driving transistor T0 are turned on, and the data signal Vdata is transmitted to the gate of the driving transistor T0 through the fifth transistor T5, the driving transistor T0 and the second transistor T2. That is, in the first sub-signal adjustment stage, the preset signal connected to the gate of the driving transistor T0 is the reset signal Vref2; while in the second sub-signal adjustment stage, the preset signal connected to the gate of the driving transistor T0 is the data signal Vdata.

[0094] In one embodiment of the present invention, the driving transistor T0 provided by the present invention can be a P-type transistor, specifically as follows: Figure 19 As shown, Figure 19 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention. Figure 19 The pixel circuit shown is Figure 18Based on the circuit shown, it also includes a sixth transistor T6 and a seventh transistor T7 for controlling light emission. The gates of the sixth transistor T6 and the seventh transistor T7 are connected to a light emission control signal EM1. The first electrode of the sixth transistor T6 is connected to a first power supply signal PVDD, and its second electrode is connected to the source of the driving transistor T0. The first electrode of the seventh transistor T7 is connected to the drain of the driving transistor T0, and its second electrode is connected to one end of the light-emitting element 20. The other end of the light-emitting element 20 is connected to a second power supply signal PVEE. The light emission control signal EM1 is a pulse signal. When the light emission control signal EM1 is active, the light-emitting element 20 is in the light-emitting stage; when the light emission control signal EM1 is inactive, the light-emitting element 20 is in the non-light-emitting stage. It also includes a holding capacitor C for maintaining the node potential. The first end of the holding capacitor C is connected to the first power supply signal PVDD, and the second end of the holding capacitor C is connected to the gate of the driving transistor T0.

[0095] Furthermore, the driving transistor T0 provided in this embodiment of the invention can be an N-type transistor, specifically as follows: Figure 20 As shown, Figure 20 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention. Figure 20 The pixel circuit shown is Figure 18 Based on the circuit shown, it also includes a sixth transistor T6 and a seventh transistor T7 for controlling light emission. The gates of the sixth transistor T6 and the seventh transistor T7 are connected to a light emission control signal EM1. The first electrode of the sixth transistor T6 is connected to a first power supply signal PVDD, and the second electrode of the sixth transistor T6 is connected to the drain of the driving transistor T0. The first electrode of the seventh transistor T7 is connected to the source of the driving transistor T0, and the second electrode of the seventh transistor T7 is connected to one end of the light-emitting element 20. The other end of the light-emitting element 20 is connected to a second power supply signal PVEE. The light emission control signal EM1 is a pulse signal. During a valid pulse, the light emission control signal EM1 controls the sixth transistor T6 and the seventh transistor T7 to conduct, and the light-emitting element 20 is in the light-emitting stage. During an invalid pulse, the light emission control signal EM1 controls the sixth transistor T6 and the seventh transistor T7 to turn off, and the light-emitting element 20 is in the non-light-emitting stage. It also includes a holding capacitor C for maintaining the node potential. The first end of the holding capacitor C is connected to the source of the driving transistor T0, or the first end of the holding capacitor C is connected to the light-emitting element, and the second end of the holding capacitor C is connected to the gate of the driving transistor T0.

[0096] Combination Figure 21 As shown, Figure 19 and Figure 20The timing diagram of any pixel circuit is shown below. First, the light emission control signal EM1 outputs an invalid pulse, causing the pixel circuit 10 to control the light emission element 20 to be in a non-light emission stage. The non-light emission stage includes a reset stage (i.e., the first sub-signal adjustment stage), a bias adjustment stage, and a second sub-signal adjustment stage. In the reset stage (i.e., the first sub-signal adjustment stage), the reset scan signal Kr2 controls the reset transistor Tr2 to turn on, and at the same time, the second scan signal K2 outputs an valid pulse to control the second transistor T2 to turn on. The reset signal Vref2 is transmitted to the gate of the driving transistor T0 through the reset transistor Tr2 and the second transistor T2. During the bias adjustment phase, the second scan signal K2 outputs an invalid pulse to turn off the second transistor T2. Simultaneously, the reset scan signal Kr2 turns on the reset transistor Tr2, transmitting the bias adjustment signal to the drain of the driving transistor T0 to adjust its bias state. The bias adjustment signal can be provided through the port of the reset signal Vref2 (e.g., when the driving transistor T0 is an N-type transistor, the reset signal Vref2 is high during the reset phase and low during the bias adjustment phase; or, when T0 is a P-type transistor, the reset signal Vref2 is low during the reset phase and high during the bias adjustment phase). In the second sub-signal adjustment phase, the second scan signal K2 outputs an valid pulse to turn on the second transistor T2. Simultaneously, the fifth scan signal K5 turns on the fifth transistor T5. The data signal Vdata, multiplexed as a preset signal, is transmitted to the gate of the driving transistor T0 through the fifth transistor T5, the driving transistor T0, and the second transistor T2. Then, the light emission control signal EM1 outputs a valid pulse, causing the pixel circuit 10 to control the light-emitting element 20 to be in the light-emitting phase. It should be noted that the light emission control signal EM provided in the embodiments of the present invention can be a single control signal that controls two transistors simultaneously; or, the light emission control signal EM can be divided into two sub-light emission control signals, which control their respective transistors respectively, and the duration of the longer invalid pulse output in the two sub-light emission control signals is the duration of the non-light emission phase.

[0097] like Figure 22 The diagram shows another pixel circuit provided in an embodiment of the present invention. The pixel circuit 10 includes a data writing module 17. The data writing module 17 is connected to the source of the driving transistor T0 and is used to provide a data signal Vdata to the driving module 11. During the bias adjustment phase, the data writing module 17 is turned on and the compensation module 12 is turned off. The data writing module 17 writes a bias adjustment signal Vobs to the source of the driving transistor T0. The bias adjustment signal Vobs is transmitted to the drain of the driving transistor T0 through the driving transistor T0.

[0098] Figure 22In the circuit shown, the data writing module 17 includes an eighth transistor T8. The first electrode of the eighth transistor T8 is connected to the data signal Vdata, the second electrode of the eighth transistor T8 is connected to the source of the driving transistor T0, and the gate of the eighth transistor T8 is connected to the eighth scan signal K8.

[0099] Figure 22 In the circuit shown, the compensation module 12 includes a second transistor T2. The first electrode of the second transistor T2 is connected to the drain of the driving transistor T0, and the second electrode of the second transistor T2 is connected to the gate of the driving transistor T0. The gate of the second transistor T2 is connected to the second scan signal K2. Optionally, in this embodiment of the invention, the second transistor T2 can be an oxide semiconductor transistor (OST). OSTs have relatively smaller leakage current, which helps to stabilize the potential of the driving transistor. Similarly, the driving transistor T0 can optionally be an OST, specifically an indium gallium zinc oxide (IGZO) semiconductor transistor. The driving transistor T0 has advantages such as high mobility, low leakage current, good uniformity, transparency, and simple fabrication process.

[0100] Figure 22 In the circuit shown, the second scan signal K2 is a pulse signal. When the second scan signal K2 outputs a valid pulse, it controls the path between the first and second electrodes of the second transistor T2 to be turned on, thereby compensating for the threshold voltage of the driving transistor T0. The pixel circuit 10 provided in this embodiment of the invention includes a bias adjustment stage. In the bias adjustment stage, the second scan signal K2 outputs an invalid pulse to control the second transistor T2 to be turned off; while the eighth scan signal K8 controls the eighth transistor T8 to be turned on, transmitting the bias adjustment signal Vobs to the source of the driving transistor T0, and transmitting the bias adjustment signal Vobs to the drain of the driving transistor T0 because the driving transistor T0 is turned on.

[0101] In one embodiment of the present invention, the driving transistor T0 provided by the present invention can be a P-type transistor, specifically as follows: Figure 23 As shown, Figure 23 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention. Figure 23 The pixel circuit shown is Figure 22Based on the circuit shown, it also includes a ninth transistor T9 and a tenth transistor T10 for controlling light emission. The gates of the ninth transistor T9 and the tenth transistor T10 are connected to a light emission control signal EM2. The first electrode of the ninth transistor T9 is connected to a first power supply signal PVDD, and its second electrode is connected to the source of a driving transistor T0. The first electrode of the tenth transistor T10 is connected to the drain of the driving transistor T0, and its second electrode is connected to one end of a light-emitting element 20. The other end of the light-emitting element 20 is connected to a second power supply signal PVEE. The light emission control signal EM2 is a pulse signal. During a valid pulse, EM2 controls the ninth transistor T9 and the tenth transistor T10 to conduct, and the light-emitting element 20 is in the light-emitting stage. During an invalid pulse, EM2 controls the ninth transistor T9 and the tenth transistor T10 to turn off, and the light-emitting element 20 is in the non-light-emitting stage. A holding capacitor C is also included to maintain the node potential. The first end of the holding capacitor C is connected to the first power supply signal PVDD, and the second end of the holding capacitor C is connected to the gate of the driving transistor T0.

[0102] Furthermore, the driving transistor T0 provided in this embodiment of the invention can be an N-type transistor, specifically as follows: Figure 24 As shown, Figure 24 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention. Figure 24 The pixel circuit shown is Figure 22 Based on the circuit shown, it also includes a ninth transistor T9 and a tenth transistor T10 for controlling light emission. The gates of both transistors T9 and T10 are connected to a light emission control signal EM2. The first electrode of the ninth transistor T9 is connected to a first power supply signal PVDD, and its second electrode is connected to the drain of a driving transistor T0. The first electrode of the tenth transistor T10 is connected to the source of the driving transistor T0, and its second electrode is connected to one end of a light-emitting element 20. The other end of the light-emitting element 20 is connected to a second power supply signal PVEE. The light emission control signal EM2 is a pulse signal. When the light emission control signal EM2 is active, the light-emitting element 20 is in the light-emitting stage; when the light emission control signal EM2 is inactive, the light-emitting element 20 is in the non-light-emitting stage. A holding capacitor C is also included to maintain the node potential. The first end of the holding capacitor C is connected to the source of the driving transistor T0, and the second end of the holding capacitor C is connected to the gate of the driving transistor T0.

[0103] Combination Figure 25 As shown, Figure 23 and Figure 24The timing diagram of any pixel circuit is shown below. First, the light emission control signal EM2 outputs an invalid pulse, causing the pixel circuit 10 to control the light-emitting element 20 to be in a non-light-emitting stage. The non-light-emitting stage includes a bias adjustment stage and a signal adjustment stage. In the bias adjustment stage, the second scan signal K2 outputs an invalid pulse to control the second transistor T2 to turn off. Simultaneously, the eighth scan signal K8 controls the eighth transistor T8 to turn on, transmitting the bias adjustment signal Vobs to the source of the driving transistor T0. The bias adjustment signal Vobs is also transmitted through the driving transistor T0 to the drain of the driving transistor T0 to adjust the bias state of the driving transistor T0. The bias adjustment signal Vobs can be provided through the port of the data signal Vdata. In the signal adjustment stage, the second scan signal K2 outputs a valid pulse to control the second transistor T2 to turn on. Simultaneously, the eighth scan signal K8 controls the eighth transistor T8 to turn on. The data signal Vdata, multiplexed as a preset signal, is transmitted through the eighth transistor T8, the driving transistor T0, and the second transistor T2 to the gate of the driving transistor T0. Then, the light emission control signal EM outputs a valid pulse, causing the pixel circuit 10 to control the light-emitting element 20 to be in the light-emitting stage. It should be noted that the light emission control signal EM provided in the embodiments of the present invention can be a single control signal that controls two transistors simultaneously; or, the light emission control signal EM can be divided into two sub-light emission control signals, which control their respective transistors respectively, and the duration of the longer invalid pulse output in the two sub-light emission control signals is the duration of the non-light emission phase.

[0104] In one embodiment of the present invention, the operation of the pixel circuit provided by the present invention includes a bias adjustment stage. A separate bias adjustment module can be provided in the pixel circuit to provide a bias adjustment signal to the driving transistor during the bias adjustment stage, thus eliminating the need to reuse other modules in the pixel circuit to provide bias adjustment signals to the driving transistor during the bias adjustment stage. Figure 26 The diagram shown is a schematic representation of another pixel circuit provided in an embodiment of the present invention, wherein... Figure 26 The pixel circuit 10 shown can be used as Figure 18 The circuit shown is an improvement based on the circuit shown (this invention does not specifically limit the scope of the invention). Figure 18 (This is merely one of many circuits that can be improved by this invention), the pixel circuit also includes a bias adjustment module 18, which is connected to the drain of the driving transistor T0; wherein, during the bias adjustment phase, the bias adjustment module 18 is turned on, the compensation module 12 is turned off, and the bias adjustment module 18 writes a bias adjustment signal Vobs to the drain of the driving transistor T0. The bias adjustment module 18 includes a bias adjustment transistor Tb, the first electrode of the bias adjustment transistor Tb is connected to the bias adjustment signal Vobs, the second electrode of the bias adjustment transistor Tb is connected to the drain of the driving transistor T0, and the gate of the bias adjustment transistor Tb is connected to the bias adjustment scan signal Kb.

[0105] Specifically, such as Figure 27 As shown, Figure 27 The pixel circuit 10 shown is Figure 20 The circuit shown is an improvement based on the present invention, wherein the present invention provides Figure 27 The pixel circuit shown also includes a bias adjustment module 18, which includes a bias adjustment transistor Tb. The first electrode of the bias adjustment transistor Tb is connected to the bias adjustment signal Vobs, the second electrode of the bias adjustment transistor Tb is connected to the drain of the driving transistor T0, and the gate of the bias adjustment transistor Tb is connected to the bias adjustment scan signal Kb. Combined with... Figure 28 The corresponding provided Figure 27 As shown in the timing diagram of the pixel circuit, the light emission control signal EM1 first outputs an invalid pulse, causing the pixel circuit 10 to control the light emission element 20 to be in a non-light emission stage. The non-light emission stage includes a reset stage (i.e., the first sub-signal adjustment stage), a bias adjustment stage, and a second sub-signal adjustment stage. In the reset stage (i.e., the first sub-signal adjustment stage), the reset scan signal Kr2 controls the reset transistor Tr2 to turn on, and at the same time, the second scan signal K2 outputs an valid pulse to control the second transistor T2 to turn on. The reset signal Vref2 is transmitted to the gate of the driving transistor T0 through the reset transistor Tr2 and the second transistor T2. During the bias adjustment phase, the second scan signal K2 outputs an invalid pulse to control the second transistor T2 to turn off. Simultaneously, the fifth scan signal K5 maintains control over the fifth transistor T5 to turn off. Meanwhile, the bias adjustment scan signal Kb controls the bias adjustment transistor Tb to turn on, transmitting the bias adjustment signal Vobs to the drain of the driving transistor T0 to adjust its bias state. The bias adjustment signal Vobs is a fixed-level signal; when the driving transistor T0 is a P-type transistor, Vobs is a high-level signal, and when the driving transistor T0 is an N-type transistor, Vobs is a low-level signal. In the second sub-signal adjustment phase, the second scan signal K2 outputs an valid pulse to control the second transistor T2 to turn on. Simultaneously, the fifth scan signal K5 controls the fifth transistor T5 to turn on. The data signal Vdata, multiplexed as a preset signal, is transmitted to the gate of the driving transistor T0 through the fifth transistor T5, the driving transistor T0, and the second transistor T2. Then, the light emission control signal EM1 outputs a valid pulse, causing the pixel circuit 10 to control the light-emitting element 20 to be in the light-emitting phase. It should be noted that the light emission control signal EM provided in the embodiments of the present invention can be a single control signal that controls two transistors simultaneously; or, the light emission control signal EM can be divided into two sub-light emission control signals, which control their respective transistors respectively, and the duration of the longer invalid pulse output in each sub-light emission control signal is the duration of the non-light emission phase.

[0106] In one embodiment of the present invention, the pixel circuit provided by the present invention further includes a light-emitting control module, which is used to selectively allow the light-emitting element to enter the light-emitting stage. The light-emitting control module includes a first light-emitting control module and a second light-emitting control module. The control terminal of the first light-emitting control module receives a first light-emitting control signal, and the control terminal of the second light-emitting control module receives a second light-emitting control signal. In the non-light-emitting stage, the invalid pulse duration of the first light-emitting control signal is S1, the invalid pulse duration of the second light-emitting control signal is S2, and the duration of the non-light-emitting stage is the larger of S1 and S2. Specifically, as follows... Figure 29 As shown, Figure 29 The pixel circuit 10 shown can be used as Figure 14 The circuit shown is an improvement based on the circuit shown (this invention does not specifically limit the scope of the invention). Figure 14 (This is merely one of many circuits that can be improved by the present invention), the pixel circuit 10 includes a first light-emitting control module 191 and a second light-emitting control module 192. One end of the first light-emitting control module 191 is connected to a first power supply signal PVDD, and the other end of the first light-emitting control module 191 is connected to the first electrode of the driving transistor T0 (wherein, when the driving transistor T0 is a P-type transistor, the first electrode of the driving transistor T0 is the source and the second electrode is the drain; and when the driving transistor T0 is an N-type transistor, the first electrode of the driving transistor T0 is the drain and the second electrode is the source), and the control terminal of the first light-emitting control module 191 is connected to a first light-emitting control signal EM11. One end of the second light-emitting control module 192 is connected to the second electrode of the driving transistor T0, and the other end of the second light-emitting control module 192 is connected to one end of the light-emitting element 20, the control terminal of the second light-emitting control module 192 is connected to a second light-emitting control signal EM12, and the other end of the light-emitting element 20 is connected to a second power supply signal PVEE. Specifically, a valid pulse of the first light-emitting control signal EM11 controls the first light-emitting control module 191 to turn on, while an invalid pulse of the first light-emitting control signal EM11 controls the first light-emitting control module 191 to turn off; a valid pulse of the second light-emitting control signal EM12 controls the second light-emitting control module 192 to turn on, while an invalid pulse of the second light-emitting control signal EM12 controls the second light-emitting control module 192 to turn off, thereby turning on or off the transmission path between the driving transistor T0 and the light-emitting element 20.

[0107] Further as Figure 30 As shown, Figure 30 The pixel circuit 10 shown can be used as Figure 15 The circuit shown is an improvement based on the circuit shown (this invention does not specifically limit the scope of the invention). Figure 15 This is merely one of many circuits that can be improved upon in this invention. One end of the first light-emitting control module 191 is connected to either the source or drain of the driving transistor T0. Figure 30 The driving transistor T0 shown is a P-type transistor. One end of the first light-emitting module 191 is connected to the source of the driving transistor T0, and the other end is connected to the first power signal terminal to receive the first power signal PVDD. One end of the second light-emitting control module 192 is connected to the other of the source and drain of the driving transistor T0. Figure 30 The driving transistor T0 shown is a P-type transistor. One end of the second light-emitting module 192 is connected to the drain of the driving transistor T0, and the other end is coupled to the initialization signal terminal to receive the initialization signal VAR. The driving transistor T0 is a PMOS type transistor. The first light-emitting module 191 includes a third transistor T3. The first electrode of the third transistor T3 is connected to the first power supply signal PVDD, the second electrode of the third transistor T3 is connected to the source of the driving transistor T0, and the gate of the third transistor T3 is connected to the first light-emitting control signal EM11. The second light-emitting control module 192 includes a fourth transistor T4. The fourth transistor T4 can be coupled to the initialization signal VAR through the initialization transistor Tv. The first electrode of the fourth transistor T4 is connected to the drain of the driving transistor T0, the second electrode of the fourth transistor T4 is connected to one end of the light-emitting element 20 and the first electrode of the initialization transistor Tv, the gate of the fourth transistor T4 is connected to the second light-emitting control signal EM12, the second electrode of the initialization transistor Tv is connected to the initialization signal VAR, and the gate of the initialization transistor Tv is connected to the control signal Kv. Figure 31 The timing diagram shown illustrates that during the bias adjustment phase, the first light-emitting control module 191 is turned on, and the second light-emitting control module 192 is turned off. The first power supply signal PVDD serves as the bias adjustment signal, which is input to the source of the driving transistor T0 through the first light-emitting control module 191 and transmitted to the drain of the driving transistor T0. Specifically, the initialization transistor Tv provided in this embodiment is turned on when the fourth transistor T4 is turned off, initializing the light-emitting element 20 in a dark state during the non-light-emitting phase.

[0108] Or, such as Figure 32 As shown, Figure 32 The pixel circuit 10 shown can be used as Figure 16 The circuit shown is an improvement based on the circuit shown (this invention does not specifically limit the scope of the invention). Figure 16 This is merely one of many circuits that can be improved upon in this invention. One end of the first light-emitting control module 191 is connected to either the source or drain of the driving transistor T0. Figure 32The driving transistor T0 shown is an N-type transistor. One end of the first light-emitting module 191 is connected to the drain of the driving transistor T0, and the other end is connected to the first power signal terminal to receive the first power signal PVDD. One end of the second light-emitting control module 192 is connected to the other of the source and drain of the driving transistor T0. Figure 32 The driving transistor T0 shown is an N-type transistor. One end of the second light-emitting module 192 is connected to the source of the driving transistor T0, and the other end is coupled to the initialization signal terminal to receive the initialization signal VAR. The driving transistor T0 is an NMOS transistor. During the bias adjustment phase, the second light-emitting control module 192 is turned on, and the first light-emitting control module 191 is turned off. The initialization signal VAR is a bias adjustment signal, which is input to the source of the driving transistor T0 through the initialization transistor Tv and the second light-emitting control module 192, and then transmitted to the drain of the driving transistor T0.

[0109] In any of the above embodiments of the present invention, in the same mode, when the frame refresh frequency of the display panel is F1, the duration of the non-light-emitting phase is A1, and the duration of the bias adjustment phase is B1; when the frame refresh frequency of the display panel is F2, the duration of the non-light-emitting phase is A2, and the duration of the bias adjustment phase is B2; wherein, F1 < F2; B1 / A1 > B2 / A2. In this embodiment, when the frame refresh frequency is F1, the refresh frequency is relatively low, and the time of one refresh cycle is relatively long. For example, when F1 is 1Hz, one refresh cycle is 1s, and the light-emitting phase lasts for a long time. When the frame refresh frequency is F2, the refresh frequency is relatively high, and the time of one refresh cycle is relatively short. For example, when F2 is 60Hz, one refresh cycle is 1 / 60s, and the light-emitting phase lasts for a short time. Relatively speaking, when the light-emitting phase lasts for a long time, the bias phenomenon of the driving transistor is more obvious. Therefore, a relatively long bias adjustment phase is needed to compensate for it. When the light-emitting phase lasts for a short time, the required bias adjustment phase time is also relatively short. Therefore, in this embodiment, it is set that B1 / A1 > B2 / A2, that is, when the frame refresh frequency is a lower frequency F1, the proportion of the light-emitting phase time occupied by the bias adjustment phase is larger; when the frame refresh frequency is a higher frequency F2, the proportion of the light-emitting phase time occupied by the bias adjustment phase is smaller.

[0110] Furthermore, in this embodiment, B1 is set to be greater than B2. When F1 is less than F2, the bias adjustment phase is longer when the frame refresh frequency is low and shorter when the frame refresh frequency is high. This allows the bias state of the driving transistor to be better adjusted under both high and low frame refresh frequencies.

[0111] Accordingly, embodiments of the present invention also provide a display device, including the display panel provided in any of the above embodiments.

[0112] like Figure 34 The diagram shown is a structural schematic of a display device provided in an embodiment of the present invention, wherein the display device 1000 provided in the embodiment of the present invention can be a mobile terminal device.

[0113] In other embodiments of the present invention, the display device provided by the present invention may also be an electronic display device such as a mobile phone, computer, or vehicle terminal, and the present invention does not impose specific limitations on it.

[0114] This invention provides a display panel and a display device, wherein the duration of the bias adjustment phase and the duration of the non-emissive phase are set to be non-symmetrical. When the display panel switches from a first operating mode to a second operating mode based on brightness changes, the duration of the non-emissive phase shortens. At this time, the duration of the bias adjustment phase is adjusted according to the formula W1 / L1 < W2 / L2, so that the variation in the duration of the bias adjustment phase caused by the change in operating mode is relatively small. That is, the duration of the bias adjustment phase is relatively long in the second mode, avoiding flickering during mode adjustment caused by a shorter duration of the bias adjustment phase in the second mode. Therefore, the technical solution provided by this invention improves the flickering problem of the display panel in different brightness modes, ensuring high display performance of the display device.

[0115] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A display panel, characterized in that, include: Pixel circuits and light-emitting elements; The pixel circuit includes a driving module, a data writing module, a bias adjustment module, and a compensation module; The driving module includes a driving transistor; The data writing module provides data signals to the driving transistor; The bias adjustment module provides a bias adjustment signal to the driving transistor; The compensation module is connected between the gate and drain of the driving transistor; One frame of the display panel includes a non-light-emitting phase and a light-emitting phase. The non-light-emitting phase includes a bias adjustment phase. In the bias adjustment phase, the source and / or drain of the driving transistor receives the bias adjustment signal. The operating states of the pixel circuit include a first mode and a second mode. In the first mode, the duration of the non-light-emitting phase is L1, and in the second mode, the duration of the non-light-emitting phase is L2, where L1 > L2. The operation of the display panel in the first mode includes a first frame, and the operation of the display panel in the second mode includes a second frame; The non-light-emitting stage further includes a signal adjustment stage, in which the compensation module is activated, the gate of the driving transistor receives a preset signal, and the signal adjustment stage includes M sub-signal adjustment stages, where M≥1; wherein... In the first frame, the bias adjustment phase includes N1 sub-bias adjustment phases, where N1 ≥ 1, wherein at least one of the sub-bias adjustment phases begins after the end of the first sub-signal adjustment phase, and the total duration of the sub-bias adjustment phases beginning after the end of the first sub-signal adjustment phase is W10. In the second frame, the bias adjustment phase includes N2 sub-bias adjustment phases, where N2 ≥ 1, wherein at least one sub-bias adjustment phase begins after the end of the first sub-signal adjustment phase, and the total duration of the sub-bias adjustment phases beginning after the end of the first sub-signal adjustment phase is W20; wherein, W10 = W20.

2. The display panel according to claim 1, characterized in that, In the first frame, each of the N1 sub-bias adjustment phases begins after the end of the first sub-signal adjustment phase; and / or, In the second frame, all N2 sub-bias adjustment stages begin after the end of the first sub-signal adjustment stage.

3. The display panel according to claim 1, characterized in that, The brightness of the light-emitting element in the first mode is lower than that in the second mode.

4. The display panel according to claim 1, characterized in that, The bias adjustment phase is located in the time period from the start of the non-luminescent phase to the start of the j-th sub-signal adjustment phase, where 1≤j≤M; In the first frame, the time length from the start of the non-light-emitting phase to the start of the j-th sub-signal adjustment phase is L11, and the time length from the start of the j-th sub-signal adjustment phase to the end of the non-light-emitting phase is L12. In the second frame, the time length from the start of the non-light-emitting phase to the start of the j-th sub-signal adjustment phase is L21, and the time length from the start of the j-th sub-signal adjustment phase to the end of the non-light-emitting phase is L22; wherein... L12 > L22.

5. The display panel according to claim 4, characterized in that, L11 = L21.

6. The display panel according to claim 4, characterized in that, L12 > L11, and / or, L22 > L21.

7. The display panel according to claim 1, characterized in that, The bias adjustment phase is located in the time period from the end of the j-th sub-signal adjustment phase to the end of the non-luminous phase, 1≤j≤M; In the first frame, the time length from the start of the non-light-emitting phase to the end of the j-th sub-signal adjustment phase is L13, and the time length from the end of the j-th sub-signal adjustment phase to the end of the non-light-emitting phase is L14. In the second frame, the time length from the start of the non-light-emitting phase to the end of the j-th sub-signal adjustment phase is L23, and the time length from the end of the j-th sub-signal adjustment phase to the end of the non-light-emitting phase is L24; wherein... L13 > L23.

8. The display panel according to claim 7, characterized in that, L14 = L24.

9. The display panel according to claim 7, characterized in that, L13 > L14, and / or, L23 > L24.

10. The display panel according to claim 1, characterized in that, The pixel circuit includes a reset module; The data writing module is connected to the source of the driving transistor and is used to provide data signals to the driving module; The reset module is connected to the gate of the driving transistor and is used to provide a reset signal to the gate of the driving transistor; wherein, M=1, and the preset signal is a data signal; During the signal adjustment phase, the data writing module is activated, and the data signal terminal provides a data signal to the gate of the driving transistor through the data writing module, the driving module, and the compensation module.

11. The display panel according to claim 1, characterized in that, The pixel circuit includes a reset module; The data writing module is connected to the source of the driving transistor and is used to provide data signals to the driving module; The reset module is connected to the drain of the driving transistor and is used to provide a reset signal to the gate of the driving transistor; wherein, M=2, in the first sub-signal adjustment stage, the preset signal is a reset signal, and in the second sub-signal adjustment stage, the preset signal is a data signal; In the first sub-signal adjustment stage, the reset module is turned on, and the reset signal terminal provides a reset signal to the gate of the driving transistor through the reset module and the compensation module; In the second sub-signal adjustment stage, the data writing module is activated, and the data signal terminal provides a data signal to the gate of the driving transistor through the data writing module, the driving module, and the compensation module.

12. The display panel according to claim 1, characterized in that, During the bias adjustment phase, the bias adjustment module is activated, and the bias adjustment module writes the bias adjustment signal to the source and / or drain of the driving transistor.

13. A display panel, characterized in that, include: Pixel circuits and light-emitting elements; The pixel circuit includes a driving module, a data writing module, a bias adjustment module, and a compensation module; The driving module includes a driving transistor; The data writing module provides data signals to the driving transistor; The bias adjustment module provides a bias adjustment signal to the driving transistor; The compensation module is connected between the gate and drain of the driving transistor; The display panel's frame time includes a non-light-emitting phase and a light-emitting phase. The non-light-emitting phase includes a bias adjustment phase. During the bias adjustment phase, the compensation module is turned off, and the source and / or drain of the driving transistor receives the bias adjustment signal. The operating states of the pixel circuit include a first mode and a second mode. In the first mode, the duration of the non-light-emitting phase is L1, and in the second mode, the duration of the non-light-emitting phase is L2, where L1 > L2. The operation of the display panel in the first mode includes a first frame, and the operation of the display panel in the second mode includes a second frame; The non-light-emitting stage further includes a signal adjustment stage, in which the compensation module is activated, the gate of the driving transistor receives a preset signal, and the signal adjustment stage includes M sub-signal adjustment stages, where M≥1; wherein... In the first frame, the bias adjustment phase includes N1 sub-bias adjustment phases, where N1 ≥ 1, wherein at least one of the sub-bias adjustment phases begins after the end of the first sub-signal adjustment phase, and the total duration of the sub-bias adjustment phases beginning after the end of the first sub-signal adjustment phase is W10. In the second frame, the bias adjustment phase includes N2 sub-bias adjustment phases, where N2 ≥ 1, wherein at least one sub-bias adjustment phase begins after the end of the first sub-signal adjustment phase, and the total duration of the sub-bias adjustment phases beginning after the end of the first sub-signal adjustment phase is W20; wherein, W10 = W20.

14. The display panel according to claim 13, characterized in that, In the first frame, each of the N1 sub-bias adjustment phases begins after the end of the first sub-signal adjustment phase; and / or, In the second frame, all N2 sub-bias adjustment stages begin after the end of the first sub-signal adjustment stage.

15. The display panel according to claim 13, characterized in that, The brightness of the light-emitting element in the first mode is lower than that in the second mode.

16. The display panel according to claim 13, characterized in that, The bias adjustment phase is located in the time period from the start of the non-luminescent phase to the start of the j-th sub-signal adjustment phase, where 1≤j≤M; In the first frame, the time length from the start of the non-light-emitting phase to the start of the j-th sub-signal adjustment phase is L11, and the time length from the start of the j-th sub-signal adjustment phase to the end of the non-light-emitting phase is L12. In the second frame, the time length from the start of the non-light-emitting phase to the start of the j-th sub-signal adjustment phase is L21, and the time length from the start of the j-th sub-signal adjustment phase to the end of the non-light-emitting phase is L22; wherein... L12 > L22.

17. The display panel according to claim 16, characterized in that, L11 = L21.

18. The display panel according to claim 16, characterized in that, L12 > L11, and / or, L22 > L21.

19. The display panel according to claim 13, characterized in that, The bias adjustment phase is located in the time period from the end of the j-th sub-signal adjustment phase to the end of the non-luminous phase, 1≤j≤M; In the first frame, the time length from the start of the non-light-emitting phase to the end of the j-th sub-signal adjustment phase is L13, and the time length from the end of the j-th sub-signal adjustment phase to the end of the non-light-emitting phase is L14. In the second frame, the time length from the start of the non-light-emitting phase to the end of the j-th sub-signal adjustment phase is L23, and the time length from the end of the j-th sub-signal adjustment phase to the end of the non-light-emitting phase is L24; wherein... L13 > L23.

20. The display panel according to claim 19, characterized in that, L14 = L24.

21. The display panel according to claim 19, characterized in that, L13 > L14, and / or, L23 > L24.

22. The display panel according to claim 13, characterized in that, The pixel circuit includes a reset module; The data writing module is connected to the source of the driving transistor and is used to provide data signals to the driving module; The reset module is connected to the gate of the driving transistor and is used to provide a reset signal to the gate of the driving transistor; wherein, M=1, and the preset signal is a data signal; During the signal adjustment phase, the data writing module is activated, and the data signal terminal provides a data signal to the gate of the driving transistor through the data writing module, the driving module, and the compensation module.

23. The display panel according to claim 13, characterized in that, The pixel circuit includes a reset module; The data writing module is connected to the source of the driving transistor and is used to provide data signals to the driving module; The reset module is connected to the drain of the driving transistor and is used to provide a reset signal to the gate of the driving transistor; wherein, M=2, in the first sub-signal adjustment stage, the preset signal is a reset signal, and in the second sub-signal adjustment stage, the preset signal is a data signal; In the first sub-signal adjustment stage, the reset module is turned on, and the reset signal terminal provides a reset signal to the gate of the driving transistor through the reset module and the compensation module; In the second sub-signal adjustment stage, the data writing module is activated, and the data signal terminal provides a data signal to the gate of the driving transistor through the data writing module, the driving module, and the compensation module.

24. The display panel according to claim 13, characterized in that, During the bias adjustment phase, the bias adjustment module is activated, and the bias adjustment module writes the bias adjustment signal to the source and / or drain of the driving transistor.

25. A display panel, characterized in that, include: Pixel circuits and light-emitting elements; The pixel circuit includes a driving module, a bias adjustment module, and a compensation module; The driving module includes a driving transistor; The bias adjustment module provides a bias adjustment signal to the driving transistor; The compensation module is connected between the gate and drain of the driving transistor; One frame of the display panel includes a non-light-emitting phase and a light-emitting phase. The non-light-emitting phase includes a bias adjustment phase. In the bias adjustment phase, the source and / or drain of the driving transistor receives the bias adjustment signal. The operating states of the pixel circuit include a first mode and a second mode. In the first mode, the duration of the non-light-emitting phase is L1, and in the second mode, the duration of the non-light-emitting phase is L2, where L1 > L2. The operation of the display panel in the first mode includes a first frame, and the operation of the display panel in the second mode includes a second frame; The non-light-emitting stage further includes a signal adjustment stage, in which the compensation module is activated, the gate of the driving transistor receives a preset signal, and the signal adjustment stage includes M sub-signal adjustment stages, where M≥1; wherein... In the first frame, the bias adjustment phase includes N1 sub-bias adjustment phases, where N1 ≥ 1, wherein at least one of the sub-bias adjustment phases begins after the end of the first sub-signal adjustment phase, and the total duration of the sub-bias adjustment phases beginning after the end of the first sub-signal adjustment phase is W10. In the second frame, the bias adjustment phase includes N2 sub-bias adjustment phases, where N2 ≥ 1, wherein at least one sub-bias adjustment phase begins after the end of the first sub-signal adjustment phase, and the total duration of the sub-bias adjustment phases beginning after the end of the first sub-signal adjustment phase is W20; wherein, W10 = W20.

26. The display panel according to claim 25, characterized in that, In the first frame, each of the N1 sub-bias adjustment phases begins after the end of the first sub-signal adjustment phase; and / or, In the second frame, all N2 sub-bias adjustment stages begin after the end of the first sub-signal adjustment stage.

27. The display panel according to claim 25, characterized in that, The brightness of the light-emitting element in the first mode is lower than that in the second mode.

28. The display panel according to claim 25, characterized in that, The bias adjustment phase is located in the time period from the start of the non-luminescent phase to the start of the j-th sub-signal adjustment phase, where 1≤j≤M; In the first frame, the time length from the start of the non-light-emitting phase to the start of the j-th sub-signal adjustment phase is L11, and the time length from the start of the j-th sub-signal adjustment phase to the end of the non-light-emitting phase is L12. In the second frame, the time length from the start of the non-light-emitting phase to the start of the j-th sub-signal adjustment phase is L21, and the time length from the start of the j-th sub-signal adjustment phase to the end of the non-light-emitting phase is L22; wherein... L12 > L22.

29. The display panel according to claim 28, characterized in that, L11 = L21.

30. The display panel according to claim 28, characterized in that, L12 > L11, and / or, L22 > L21.

31. The display panel according to claim 25, characterized in that, The bias adjustment phase is located in the time period from the end of the j-th sub-signal adjustment phase to the end of the non-luminous phase, 1≤j≤M; In the first frame, the time length from the start of the non-light-emitting phase to the end of the j-th sub-signal adjustment phase is L13, and the time length from the end of the j-th sub-signal adjustment phase to the end of the non-light-emitting phase is L14. In the second frame, the time length from the start of the non-light-emitting phase to the end of the j-th sub-signal adjustment phase is L23, and the time length from the end of the j-th sub-signal adjustment phase to the end of the non-light-emitting phase is L24; wherein... L13 > L23.

32. The display panel according to claim 31, characterized in that, L14 = L24.

33. The display panel according to claim 31, characterized in that, L13 > L14, and / or, L23 > L24.

34. The display panel according to claim 25, characterized in that, The pixel circuit includes a data writing module and a reset module; The data writing module is connected to the source of the driving transistor and is used to provide data signals to the driving module; The reset module is connected to the gate of the driving transistor and is used to provide a reset signal to the gate of the driving transistor; wherein, M=1, and the preset signal is a data signal; During the signal adjustment phase, the data writing module is activated, and the data signal terminal provides a data signal to the gate of the driving transistor through the data writing module, the driving module, and the compensation module.

35. The display panel according to claim 25, characterized in that, The pixel circuit includes a data writing module and a reset module; The data writing module is connected to the source of the driving transistor and is used to provide data signals to the driving module; The reset module is connected to the drain of the driving transistor and is used to provide a reset signal to the gate of the driving transistor; wherein, M=2, in the first sub-signal adjustment stage, the preset signal is a reset signal, and in the second sub-signal adjustment stage, the preset signal is a data signal; In the first sub-signal adjustment stage, the reset module is turned on, and the reset signal terminal provides a reset signal to the gate of the driving transistor through the reset module and the compensation module; In the second sub-signal adjustment stage, the data writing module is activated, and the data signal terminal provides a data signal to the gate of the driving transistor through the data writing module, the driving module, and the compensation module.

36. The display panel according to claim 25, characterized in that, During the bias adjustment phase, the bias adjustment module is activated, and the bias adjustment module writes the bias adjustment signal to the source and / or drain of the driving transistor.

37. The display panel according to claim 25, characterized in that, The pixel circuit further includes a data writing module connected to the source of the driving transistor, used to provide the driving transistor with a data signal or the bias adjustment signal; wherein... The data writing module is multiplexed as the bias adjustment module. During the bias adjustment phase, the data writing module is turned on and writes the bias adjustment signal to the source and / or drain of the driving transistor.

38. A display panel, characterized in that, include: Pixel circuits and light-emitting elements; The pixel circuit includes a driving module, a bias adjustment module, and a compensation module; The driving module includes a driving transistor; The bias adjustment module provides a bias adjustment signal to the driving transistor; The compensation module is connected between the gate and drain of the driving transistor; The display panel's frame time includes a non-light-emitting phase and a light-emitting phase. The non-light-emitting phase includes a bias adjustment phase. During the bias adjustment phase, the compensation module is turned off, and the source and / or drain of the driving transistor receives the bias adjustment signal. The operating states of the pixel circuit include a first mode and a second mode. In the first mode, the duration of the non-light-emitting phase is L1, and in the second mode, the duration of the non-light-emitting phase is L2, where L1 > L2. The operation of the display panel in the first mode includes a first frame, and the operation of the display panel in the second mode includes a second frame; The non-light-emitting stage further includes a signal adjustment stage, in which the compensation module is activated, the gate of the driving transistor receives a preset signal, and the signal adjustment stage includes M sub-signal adjustment stages, where M≥1; wherein... In the first frame, the bias adjustment phase includes N1 sub-bias adjustment phases, where N1 ≥ 1, wherein at least one of the sub-bias adjustment phases begins after the end of the first sub-signal adjustment phase, and the total duration of the sub-bias adjustment phases beginning after the end of the first sub-signal adjustment phase is W10. In the second frame, the bias adjustment phase includes N2 sub-bias adjustment phases, where N2 ≥ 1, wherein at least one sub-bias adjustment phase begins after the end of the first sub-signal adjustment phase, and the total duration of the sub-bias adjustment phases beginning after the end of the first sub-signal adjustment phase is W20; wherein, W10 = W20.

39. The display panel according to claim 38, characterized in that, In the first frame, each of the N1 sub-bias adjustment phases begins after the end of the first sub-signal adjustment phase; and / or, In the second frame, all N2 sub-bias adjustment stages begin after the end of the first sub-signal adjustment stage.

40. The display panel according to claim 38, characterized in that, The brightness of the light-emitting element in the first mode is lower than that in the second mode.

41. The display panel according to claim 38, characterized in that, The bias adjustment phase is located in the time period from the start of the non-luminescent phase to the start of the j-th sub-signal adjustment phase, where 1≤j≤M; In the first frame, the time length from the start of the non-light-emitting phase to the start of the j-th sub-signal adjustment phase is L11, and the time length from the start of the j-th sub-signal adjustment phase to the end of the non-light-emitting phase is L12. In the second frame, the time length from the start of the non-light-emitting phase to the start of the j-th sub-signal adjustment phase is L21, and the time length from the start of the j-th sub-signal adjustment phase to the end of the non-light-emitting phase is L22; wherein... L12 > L22.

42. The display panel according to claim 41, characterized in that, L11 = L21.

43. The display panel according to claim 41, characterized in that, L12 > L11, and / or, L22 > L21.

44. The display panel according to claim 38, characterized in that, The bias adjustment phase is located in the time period from the end of the j-th sub-signal adjustment phase to the end of the non-luminous phase, 1≤j≤M; In the first frame, the time length from the start of the non-light-emitting phase to the end of the j-th sub-signal adjustment phase is L13, and the time length from the end of the j-th sub-signal adjustment phase to the end of the non-light-emitting phase is L14. In the second frame, the time length from the start of the non-light-emitting phase to the end of the j-th sub-signal adjustment phase is L23, and the time length from the end of the j-th sub-signal adjustment phase to the end of the non-light-emitting phase is L24; wherein... L13 > L23.

45. The display panel according to claim 44, characterized in that, L14 = L24.

46. ​​The display panel according to claim 44, characterized in that, L13 > L14, and / or, L23 > L24.

47. The display panel according to claim 38, characterized in that, The pixel circuit includes a data writing module and a reset module; The data writing module is connected to the source of the driving transistor and is used to provide data signals to the driving module; The reset module is connected to the gate of the driving transistor and is used to provide a reset signal to the gate of the driving transistor; wherein, M=1, and the preset signal is a data signal; During the signal adjustment phase, the data writing module is activated, and the data signal terminal provides a data signal to the gate of the driving transistor through the data writing module, the driving module, and the compensation module.

48. The display panel according to claim 38, characterized in that, The pixel circuit includes a data writing module and a reset module; The data writing module is connected to the source of the driving transistor and is used to provide data signals to the driving module; The reset module is connected to the drain of the driving transistor and is used to provide a reset signal to the gate of the driving transistor; wherein, M=2, in the first sub-signal adjustment stage, the preset signal is a reset signal, and in the second sub-signal adjustment stage, the preset signal is a data signal; In the first sub-signal adjustment stage, the reset module is turned on, and the reset signal terminal provides a reset signal to the gate of the driving transistor through the reset module and the compensation module; In the second sub-signal adjustment stage, the data writing module is activated, and the data signal terminal provides a data signal to the gate of the driving transistor through the data writing module, the driving module, and the compensation module.

49. The display panel according to claim 38, characterized in that, During the bias adjustment phase, the bias adjustment module is activated, and the bias adjustment module writes the bias adjustment signal to the source and / or drain of the driving transistor.

50. The display panel according to claim 38, characterized in that, The pixel circuit further includes a data writing module connected to the source of the driving transistor, used to provide the driving transistor with a data signal or the bias adjustment signal; wherein... The data writing module is multiplexed as the bias adjustment module. During the bias adjustment phase, the data writing module is turned on and writes the bias adjustment signal to the source and / or drain of the driving transistor.

51. A display device, characterized in that, Includes the display panel as described in any one of claims 1-50.

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