Array substrate, control method thereof, and display panel

Abstract

The present disclosure provides an array substrate, a display panel and a control method thereof, and relates to the technical field of display. In the array substrate, a first control circuit is electrically connected with a data signal end, a first node and a storage circuit, and is configured to write and store a signal of the data signal end in the storage circuit under the signal control of the first node; the first node is electrically connected with an output end of a multiplexer; a second control circuit is electrically connected with the storage circuit, a second control end and a pixel electrode, and is configured to write a signal of the storage circuit in the pixel electrode under the signal control of the second control end; the second control end is electrically connected with an output end of a shift register; and a third control circuit is electrically connected with a first voltage end, the first node and the third control end, and is configured to write a signal of the first voltage end in the first node under the signal control of the third control end.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular, to an array substrate and a control method thereof, and a display panel. BACKGROUND

[0002] In some display devices (e.g., mobile phones), a display panel uses a liquid crystal display panel (LCD). It is found in practical applications that the LCD display panel is prone to jitter in a low-frequency display mode. SUMMARY

[0003] Embodiments of the present disclosure provide an array substrate and a control method thereof, and a display panel, which improve the jitter problem in a low-frequency mode.

[0004] To achieve the above object, the embodiments of the present disclosure adopt the following technical solutions:

[0005] In one aspect, an array substrate is provided, comprising a shift register, a multiplexer, and a controller, the controller comprising a first control circuit, a storage circuit, a second control circuit, and a third control circuit,

[0006] The first control circuit is electrically connected with a data signal terminal, a first node, and the storage circuit, and is configured to write and store a signal of the data signal terminal in the storage circuit under the control of a signal of the first node; the first node is electrically connected with an output terminal of the multiplexer;

[0007] The second control circuit is electrically connected with the storage circuit, a second control terminal, and a pixel electrode, and is configured to write a signal of the storage circuit into the pixel electrode under the control of a signal of the second control terminal; the second control terminal is electrically connected with an output terminal of the shift register;

[0008] The third control circuit is electrically connected with a first voltage terminal, the first node, and the third control terminal, and is configured to write a signal of the first voltage terminal into the first node under the control of a signal of the third control terminal.

[0009] In some embodiments, the shift register comprises:

[0010] The first output circuit is electrically connected with a second clock signal terminal, an output terminal, and a pull-up node, and is configured to write a signal of the second clock signal terminal into the output terminal under the control of a signal of the pull-up node;

[0011] The second output circuit is electrically connected with a second voltage terminal, the output terminal and a pull-down node, and is configured to write a signal of the second voltage terminal into the output terminal under the control of a signal of the pull-down node.

[0012] The third output circuit is electrically connected with a third voltage terminal, the output terminal and a third clock signal terminal, and is configured to write a signal of the third voltage terminal into the output terminal under the control of a signal of the third clock signal terminal.

[0013] In some embodiments, the third control circuit includes a sixteenth transistor, a first electrode of the sixteenth transistor being electrically connected with the first voltage terminal, a second electrode of the sixteenth transistor being electrically connected with the first node, and a gate of the sixteenth transistor being electrically connected with the third control terminal.

[0014] In some embodiments, the third output circuit includes a thirteenth transistor, a first electrode of the thirteenth transistor being electrically connected with the third voltage terminal, a second electrode of the thirteenth transistor being electrically connected with the output terminal, and a gate of the thirteenth transistor being electrically connected with the third clock signal terminal.

[0015] In some embodiments, the third control terminal and the third clock signal terminal are electrically connected.

[0016] In some embodiments, the first voltage terminal and the third voltage terminal are electrically connected.

[0017] In another aspect, a control method of an array substrate is provided, the array substrate including a shift register, a multiplexer and a controller, the controller including a first control circuit, a storage circuit, a second control circuit and a third control circuit,

[0018] The first control circuit is electrically connected with a data signal terminal, a first node and the storage circuit, and is configured to write and store a signal of the data signal terminal in the storage circuit under the control of a signal of the first node; the first node is electrically connected with an output terminal of the multiplexer.

[0019] The second control circuit is electrically connected with the storage circuit, a second control terminal and a pixel electrode, and is configured to write a signal of the storage circuit into the pixel electrode under the control of a signal of the second control terminal; the second control terminal is electrically connected with an output terminal of the shift register.

[0020] The third control circuit is electrically connected with the first voltage terminal, the first node and the third control terminal, and is configured to write a signal of the first voltage terminal into the first node under the control of a signal of the third control terminal.

[0021] One image frame includes a light-emitting stage and a holding stage, the holding stage includes a charging stage, and the control method includes:

[0022] In the charging stage, the third control circuit is controlled to write a signal of the first voltage terminal into the first node, so that the first control circuit writes a signal of the data signal terminal into the storage circuit under the control of a signal of the first node.

[0023] In the charging stage, the second control circuit is controlled to write a signal of the storage circuit into the pixel electrode.

[0024] In some embodiments, the shift register includes:

[0025] The first output circuit is electrically connected with a second clock signal terminal, an output terminal and a pull-up node, and is configured to write a signal of the second clock signal terminal into the output terminal under the control of a signal of the pull-up node.

[0026] The second output circuit is electrically connected with a second voltage terminal, the output terminal and a pull-down node, and is configured to write a signal of the second voltage terminal into the output terminal under the control of a signal of the pull-down node.

[0027] The third output circuit is electrically connected with a third voltage terminal, the output terminal and a third clock signal terminal, and is configured to write a signal of the third voltage terminal into the output terminal under the control of a signal of the third clock signal terminal.

[0028] The control of the second control circuit to write a signal of the storage circuit into the pixel electrode includes:

[0029] The third output circuit is controlled to write a signal of the third voltage terminal into the second control terminal, so that the second control circuit writes a signal of the storage circuit into the pixel electrode under the control of a signal of the second control terminal.

[0030] In some embodiments, the holding stage further includes a discharging stage after the charging stage, and the control method further includes:

[0031] In the discharging stage, the third control circuit is controlled to write a signal of the first voltage terminal into the first node, so that the first control circuit is turned on under the control of a signal of the first node.

[0032] In the discharging phase, the third output circuit is controlled to write the signal of the third voltage terminal to the second control terminal, so that the second control circuit is turned on;

[0033] In the discharging phase, the signal of the data signal terminal is a low-level signal, so that the pixel electrode is discharged through the second control circuit, the storage circuit and the first control circuit.

[0034] In another aspect, a display panel is provided, comprising an array substrate, a color film substrate and a liquid crystal layer, the array substrate and the color film substrate are arranged in a box, and the liquid crystal layer is located between the array substrate and the color film substrate.

[0035] The array substrate comprises a shift register, a multiplexer and a controller, the controller comprises a first control circuit, a storage circuit, a second control circuit and a third control circuit,

[0036] The first control circuit is electrically connected with a data signal terminal, a first node and the storage circuit, and is configured to write and store the signal of the data signal terminal in the storage circuit under the control of the signal of the first node; the first node is electrically connected with an output terminal of the multiplexer;

[0037] The second control circuit is electrically connected with the storage circuit, a second control terminal and a pixel electrode, and is configured to write the signal of the storage circuit to the pixel electrode under the control of the signal of the second control terminal; the second control terminal is electrically connected with an output terminal of the shift register;

[0038] The third control circuit is electrically connected with a first voltage terminal, the first node and the third control terminal, and is configured to write the signal of the first voltage terminal to the first node under the control of the signal of the third control terminal.

[0039] The array substrate and the control method thereof, and the display panel provided by the embodiments of the present disclosure, the controller additionally comprises a third control circuit, when the pixel electrode is in a level holding phase, the signal of the first voltage terminal is written to the first node through the third control circuit, so as to control the first control circuit to be turned on, so that the signal of the data signal terminal is written to the pixel electrode through the first control circuit and the second control circuit, and the voltage between the pixel electrode and the common electrode is kept stable, thereby improving the product jitter. BRIEF DESCRIPTION OF DRAWINGS

[0040] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0041] Figure 1 This is an application scenario diagram of a display panel provided in an embodiment of the present disclosure;

[0042] Figure 2 A cross-sectional view of a display panel provided in an embodiment of this disclosure;

[0043] Figure 3 A partial circuit block diagram of an array substrate provided in an embodiment of this disclosure;

[0044] Figure 4 This is a circuit schematic diagram of a controller in related technologies;

[0045] Figure 5 This is a partial circuit schematic of a shift register in related technologies;

[0046] Figure 6 This is a timing diagram of the STV and CKB signals in the high-frequency mode of the display panel.

[0047] Figure 7 The timing diagram shows the STV and CKB signals in low-frequency mode of the display panel.

[0048] Figure 8 This is a signal timing diagram in related technologies;

[0049] Figure 9 A circuit block diagram of a controller provided in an embodiment of this disclosure;

[0050] Figure 10 This is a circuit schematic diagram of a controller according to an embodiment of the present disclosure;

[0051] Figure 11 A partial structural block diagram of a shift register provided in an embodiment of this disclosure;

[0052] Figure 12 A partial circuit schematic diagram of a shift register provided in an embodiment of this disclosure;

[0053] Figure 13 for Figure 12 The diagram shows the signal timing of some signal terminals of the shift register during the light emission stage.

[0054] Figure 14 for Figure 12A signal timing diagram of part of the shift register shown;

[0055] Figure 15 A control method of an array substrate provided by an embodiment of the present disclosure is shown in a step block diagram.

[0056] Figure 16 Another control method of an array substrate provided by an embodiment of the present disclosure is shown in a step block diagram. DETAILED DESCRIPTION

[0057] The technical solutions in the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the scope of protection of the present disclosure.

[0058] In the embodiments of the present disclosure, the terms “first”, “second”, “third”, “fourth” and the like are used to distinguish the same items or similar items with basically the same functions and effects, only for the purpose of clearly describing the technical solutions in the embodiments of the present disclosure, and cannot be understood as indicating or implying the relative importance of the indicated technical features or implying the number of the indicated technical features.

[0059] In the embodiments of the present disclosure, the term “multiple” means two or more, and the term “at least one” means one or more, unless otherwise explicitly and specifically limited.

[0060] In the embodiments of the present disclosure, the terms “upper”, “lower” and the like indicate the orientation or position relationship shown in the drawings, only for the purpose of facilitating the description of the present disclosure and simplifying the description, and are not intended to indicate or imply that the indicated devices or elements must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present disclosure.

[0061] Embodiments of the present disclosure provide a display panel, which can be applied to various devices and apparatuses with display functions, for displaying graphics. For example, the display panel can be applied to a mobile phone, a wireless device, a personal data assistant (PDA), a handheld or portable computer, a GPS receiver / navigator, a camera, an MP4 video player, a video camera, a game console, a watch, a clock, a calculator, a television monitor, a flat panel display, a computer monitor, an automobile display (e.g., an odometer display, etc.), a navigator, a cockpit controller and / or display, a display of a camera view (e.g., a display of a rearview camera in a vehicle), an electronic photo, an electronic billboard or sign, a projector, a building structure, a packaging and aesthetic structure (e.g., a display of an image of a piece of jewelry), and the like. Figure 1An application scenario diagram of a display panel 100 provided by an embodiment of the present disclosure is shown in FIG. 1. Figure 1 The display panel 100 is taken as an example of being applied to a mobile phone.

[0062] The display panel 100 can be a liquid crystal display (LCD). When the display panel 100 is an LCD, the display panel 100 can be a horizontal electric field type LCD or a vertical electric field type LCD. When the display panel 100 is a horizontal electric field type LCD, the display panel 100 can be an in-plane switching (IPS) LCD or an advanced super dimension switch (ADS) LCD.

[0063] Figure 2 A cross-sectional view of a display panel provided by an embodiment of the present disclosure is shown in FIG. 2. Figure 2 When the display panel 100 is an LCD, the display panel 100 includes an array substrate 110, a color filter (CF) substrate 130, and a liquid crystal layer 120. The array substrate 110 and the CF substrate 130 are arranged in a sandwich manner, and the liquid crystal layer 120 is located between the array substrate 110 and the CF substrate 130. The side of the array substrate 110 away from the CF substrate 130 is further provided with a backlight assembly, which is used to provide a light source.

[0064] The display panel includes a pixel electrode and a common electrode. When a voltage is applied between the pixel electrode and the common electrode, an electric field is formed between the pixel electrode and the common electrode, which can drive the liquid crystal to move. When the LCD is a horizontal electric field type LCD, the pixel electrode and the common electrode can be both arranged on the array substrate. When the LCD is a vertical electric field type LCD, the pixel electrode can be arranged on the array substrate, and the common electrode can be arranged on the CF substrate.

[0065] The array substrate is provided with a data signal line, which is electrically connected to the pixel electrode, so that the data signal in the data signal line can be written into the pixel electrode. One data signal line can be electrically connected to multiple pixel electrodes at the same time, so as to reduce the number of data signal lines.

[0066] Figure 3 A partial circuit block diagram of an array substrate provided by an embodiment of the present disclosure is shown in FIG. 3. Figure 3As shown, the array substrate comprises a plurality of selectors and a controller, the plurality of selectors are electrically connected with a plurality of selection lines, the pixel electrode of each sub-pixel is connected with the controller, and the controller is electrically connected with the data signal line and the selection line. The controller can be turned on under the signal control of the selection line, so that the signal of the data signal line is written into the pixel electrode.

[0067] For example, continuing to refer to Figure 3 For example, taking two adjacent pixels as an example, each of the two pixels comprises a red sub-pixel R, a green sub-pixel G and a blue sub-pixel B. The data signal line DATA1 is electrically connected with the red sub-pixel R, the blue sub-pixel B of one of the two pixels and the green sub-pixel G of the other pixel. The data signal line DATA2 is electrically connected with the green sub-pixel G of one of the two pixels and the red sub-pixel R and the blue sub-pixel B of the other pixel. The plurality of selection lines comprises a red selection line MUXR, a green selection line MUXG and a blue selection line MUXB. The red selection line MUXR is electrically connected with the controllers of the two red sub-pixels R. The green selection line MUXG is electrically connected with the controllers of the two green sub-pixels G. The blue selection line MUXB is electrically connected with the controllers of the two blue sub-pixels B.

[0068] The array substrate further comprises a scan driving circuit, the scan driving circuit comprises a plurality of cascaded shift registers, the shift register comprises an output end, and the shift register outputs a scan signal through the output end. The output end of the shift register is electrically connected with the controller, so that the shift register cooperates with the selector to jointly control the controller. Figure 5 For the circuit schematic diagram of the shift register in the related art, when a plurality of shift registers are cascaded, the output end of the previous shift register is electrically connected with the input end of the next shift register. The input end of the first shift register inputs the STV signal.

[0069] Figure 4 For the circuit schematic diagram of the controller in the related art, the OUT end in the shift register is electrically connected with the OUT end in the controller.

[0070] The working mode of the display panel comprises a low-frequency mode and a high-frequency mode, Figure 6 For the timing diagram of the STV signal and the CKB signal in the high-frequency mode of the display panel, Figure 7 For the timing diagram of the STV signal and the CKB signal in the low-frequency mode of the display panel. For example, Figure 6 As shown, the frequency is 120Hz, then Figure 7 As shown, the frequency is 40Hz.

[0071] For example, Figure 4 to Figure 7As shown, the low-frequency mode is realized by inserting a porch on the basis of the high-frequency mode timing signal. That is, compared with the high-frequency mode, the low-frequency mode includes a light-emitting stage and a holding stage in one frame range, and in the holding stage, the STV signal and the CKB signal are both low-level signals, so that the output end of the shift register outputs a low-level signal, and the data signal at the DATA end cannot be written into the pixel electrode, so that the pixel electrode is in the level holding stage. However, when the pixel electrode is in the level holding stage, the leakage occurs, so that the voltage between the pixel electrode and the common electrode continuously changes, resulting in the continuous generation of DC in the liquid crystal display panel, and the dB value of L127 and FLK drifts, thereby causing the generation of the jitter.

[0072] Figure 8 For a signal timing diagram in the related art, the dashed line in the figure is the level of the common electrode, and the curve is the level of the pixel electrode. As shown in Figure 8 Due to the leakage phenomenon, the level of the pixel electrode continuously changes in one image frame range, resulting in the continuous change of the voltage between the pixel electrode and the common electrode, and the voltage between the pixel electrode and the common electrode in adjacent two image frames is different, thereby causing the jitter phenomenon.

[0073] In view of this, in the embodiment of the present disclosure, the pixel electrode is charged at least once in the holding stage, so that the level of the pixel electrode in one image frame range is more stable, and the jitter phenomenon is improved.

[0074] Figure 9 A circuit block diagram of a controller provided in the embodiment of the present disclosure is shown in Figure 9 As shown, the controller includes a first control circuit, a storage circuit, a second control circuit, and a third control circuit.

[0075] The first control circuit is electrically connected with the data signal end DATA, the first node N1, and the storage circuit source. The first control circuit is configured to write and store the signal of the data signal end DATA in the storage circuit source under the control of the signal of the first node N1. For example, when the signal of the first node N1 is a high-level signal, the first control circuit is turned on, and the signal of the data signal end DATA is written into the storage circuit source.

[0076] The first node N1 is electrically connected with the output end OUT of the multiplexer. For example, the first node N1 is electrically connected with the red selection line MUXR, or the first node N1 is electrically connected with the green selection line MUXG, or the first node N1 is electrically connected with the blue selection line MUXB.

[0077] The second control circuit is electrically connected to the storage circuit source, the second control terminal S2, and the pixel electrode. The second control circuit is configured to write the signal from the storage circuit source to the pixel electrode under the control of the signal from the second control terminal S2. For example, when the signal from the second control terminal S2 is a high-level signal, the second control circuit is turned on, and the signal from the storage circuit source is written to the pixel electrode, thereby creating an electric field between the pixel electrode and the common electrode. Exemplarily, the second voltage terminal V2 is electrically connected to the VGL line, and a constant low-level signal can be passed through the VGL line.

[0078] The third control circuit is electrically connected to the first voltage terminal V1, the first node N1, and the third control terminal S3. The third control circuit is configured to write the signal of the first voltage terminal V1 into the first node N1 under the signal control of the third control terminal S3. For example, when the signal of the third control terminal S3 is a high-level signal, the third control circuit is turned on, and the signal of the first voltage terminal V1 is written into the first node N1.

[0079] For example, the first voltage terminal V1 is electrically connected to the VGH line, and a constant high-level signal can be passed through the VGH line.

[0080] In this embodiment, the controller additionally provides a third control circuit. When the pixel electrode is in the level holding stage, the signal of the first voltage terminal V1 is written to the first node N1 through the third control circuit, thereby controlling the first control circuit to be turned on. This allows the signal of the data signal terminal DATA to be written to the pixel electrode through the first control circuit and the second control circuit, so that the voltage between the pixel electrode and the common electrode remains stable, thereby improving the product's jitter.

[0081] Figure 10 This is a circuit schematic diagram of a controller according to an embodiment of this disclosure. Figure 10 As shown, the first control circuit includes a fourteenth transistor T14. The first terminal of the fourteenth transistor T14 is electrically connected to the data signal terminal DATA, the second terminal of the fourteenth transistor T14 is electrically connected to the storage circuit source, and the gate of the fourteenth transistor T14 is electrically connected to the first node N1. The second control circuit includes a fifteenth transistor T15. The first terminal of the fifteenth transistor T15 is electrically connected to the storage circuit source, the second terminal of the fifteenth transistor T15 is electrically connected to the pixel electrode, and the gate of the fifteenth transistor T15 is electrically connected to the second control terminal S2. The third control circuit includes a sixteenth transistor T16. The first terminal of the sixteenth transistor T16 is electrically connected to the first voltage terminal V1, the second terminal of the sixteenth transistor T16 is electrically connected to the first node N1, and the gate of the sixteenth transistor T16 is electrically connected to the third control terminal S3.

[0082] It should be noted that the diagram only illustrates the case where the fourteenth transistor T14, the fifteenth transistor T15, and the sixteenth transistor T16 are all N-type transistors. In actual applications, they can also be P-type transistors.

[0083] For example, a capacitor is connected between the first terminal of the fourteenth transistor T14 and the second terminal of the fifteenth transistor T15 and ground.

[0084] For example, during the holding phase, the second control terminal S2 and the third control terminal S3 are high-level signals, the high-level signal of the first voltage terminal V1 is written to the first node N1, the fourteenth transistor T14 is turned on under the control of the high-level signal of the first node N1, the data signal of the data signal terminal DATA is written to the storage circuit source, the fifteenth transistor T15 is turned on under the control of the high-level signal of the second control terminal S2, and the data signal stored in the storage circuit source is written to the pixel electrode.

[0085] During the holding phase, the data signal can be written to the pixel electrode once or multiple times.

[0086] Figure 11 This is a partial structural block diagram of a shift register provided in an embodiment of this disclosure. For example... Figure 11 As shown, the shift register includes a first output circuit, a second output circuit, and a third output circuit.

[0087] The first output circuit is electrically connected to the second clock signal terminal CKB, the output terminal OUT, and the pull-up node PU. The first output circuit is configured to write the signal of the second clock signal terminal CKB to the output terminal OUT under the signal control of the pull-up node PU. For example, when the pull-up node PU is a high-level signal, the signal of the second clock signal terminal CKB is written to the output terminal OUT.

[0088] The second output circuit is electrically connected to the second voltage terminal V2, the output terminal OUT, and the pull-down node PD. The second output circuit is configured to write the signal from the second voltage terminal V2 to the output terminal OUT under the signal control of the pull-down node PD. For example, when the signal from the pull-down node PD is a high-level signal, the signal from the second voltage terminal V2 is written to the output terminal OUT. The second control terminal S2 is electrically connected to the output terminal OUT of the shift register.

[0089] The third output circuit is electrically connected to the third voltage terminal V3, the output terminal OUT, and the third clock signal terminal CLB. The third output circuit is configured to write the signal from the third voltage terminal V3 to the output terminal OUT under the signal control of the third clock signal terminal CLB. For example, when the third clock signal terminal CLB is a high-level signal, the signal from the third voltage terminal V3 is written to the output terminal OUT.

[0090] For example, the third voltage terminal V3 is electrically connected to the VGH line.

[0091] The third output circuit is used to output a level through the output terminal OUT during the holding phase to control the second control circuit to conduct, thereby writing the data signal of the storage circuit source into the pixel electrode.

[0092] Figure 12 This is a circuit schematic diagram of a shift register provided for an embodiment of this disclosure. Figure 12 As shown, the first output circuit includes a third transistor T3. The first terminal of the third transistor T3 is electrically connected to the second clock signal terminal CKB, the second terminal of the third transistor T3 is electrically connected to the output terminal OUT, and the gate of the third transistor T3 is electrically connected to the pull-up node PU. The second output circuit includes a fourth transistor T4. The first terminal of the fourth transistor T4 is electrically connected to the output terminal OUT, the second terminal of the fourth transistor T4 is electrically connected to the second voltage terminal V2, and the gate of the fourth transistor T4 is electrically connected to the pull-down node PD. The third output circuit includes a thirteenth transistor T13. The first terminal of the thirteenth transistor T13 is electrically connected to the third voltage terminal V3, the second terminal of the thirteenth transistor T13 is electrically connected to the output terminal OUT, and the gate of the thirteenth transistor T13 is electrically connected to the second clock signal terminal CKB.

[0093] For example, continue to refer to Figure 12 The shift register also includes transistors T1, T2, T3, T5, T6, T7, T8, T9, T10, T11, capacitor C1, and capacitor C2.

[0094] To reduce the number of signal lines within the array substrate, the third control terminal S3 can be electrically connected to the third clock signal terminal CLB.

[0095] Figure 13 for Figure 12 The diagram shows the signal timing of a portion of the shift register during the light-emitting phase. For example, as shown... Figure 13As shown, the light-emitting stage includes t1, t2, t3, t4 and t5 periods. In the t1 period, the input end IN inputs a high level, T1 is opened, C1 is charged, the pull-up node PU is at a high level, T3 is opened, and the second clock signal end CKB is at a low level, so the output end OUT outputs a low level. In the t2 period, the input end IN is at a high level, T1 is opened, C1 is charged, the pull-up node PU is at a high level, T3 is opened, and the second clock signal end CKB is at a high level, so the output end OUT outputs a high level. Due to the bootstrap effect of C1, the voltage of the pull-up node PU is further increased, ensuring that the output voltage of the output end OUT is high. In the t3 period, the input end IN is at a low level, T1 is closed, C1 has no loop, so the pull-up node PU remains at a high level, T3 is opened, and the second clock signal end CKB is at a low level, so the output end OUT outputs a low level. In the t4 period, the input end IN becomes a high level, T7 is opened, the pull-down node PD becomes a high level, T4 and T5 are opened, C1 forms a loop and is discharged, the pull-up node PU becomes a low level, T3 is closed, so the output end OUT outputs a low level; at the same time, due to the high level of the pull-down node PD, C2 is charged. In the t5 period, C2 has no loop, so the pull-down node PD remains at a high level, T4 and T5 are opened, and the output end OUT outputs a low level.

[0096] Figure 14 For Figure 12 The signal timing diagram of part of the signal ends of the shift register is shown. As shown in Figure 10 , Figure 12 and Figure 14 , in the holding stage: the second clock signal end CKB is pulled high from a low level to a high level, at this time T13 is opened, and the output end OUT outputs a high level. Because the second clock signal end CKB is electrically connected with the third control end S3, the third control end S3 is at a high level, T16 is turned on, the N1 node is at a high level, T14 is opened, and the DATA end starts to charge the source. Moreover, S2 and the output end OUT of the shift register are at a high level, and the source charges the pixel electrode. When the second clock signal end CKB changes from a high level to a low level, at this time T13 and T16 are both closed, the N1 node is at a low level, and the DATA end is at a low level, so the pixel electrode enters the level holding stage.

[0097] Therefore, in the embodiment of the present disclosure, the pixel electrode can be charged in the holding stage, so that the level of the pixel electrode remains relatively stable, thereby improving the jitter phenomenon. The charging of the pixel electrode in the holding stage can be one time or multiple times, Figure 14 for example, six times of charging are taken as an example for illustration.

[0098] Continuing to refer to Figure 14 , the holding stage can include a charging stage and a discharging stage.

[0099] Figure 15 A control method of an array substrate is provided for the embodiments of the present disclosure. As shown in Figure 15 the control method comprises the following steps.

[0100] S100, in the charging phase, the third control circuit is controlled to write the signal of the first voltage terminal to the first node, so that the first control circuit writes the signal of the data signal terminal to the storage circuit under the control of the signal of the first node.

[0101] For example, in the charging phase, a high-level signal is written to the third control terminal S3, the third control circuit is turned on, and the high-level signal of the first voltage terminal V1 is written to the first node N1. The first control circuit is turned on under the control of the high-level signal of the first node N1, and the signal of the data signal terminal DATA is written to the storage circuit source.

[0102] S200, in the charging phase, the second control circuit is controlled to write the signal of the storage circuit to the pixel electrode.

[0103] For example, in the charging phase, a high-level signal is written to the second control terminal S2, the second control circuit is turned on, and the data signal in the storage circuit source is written to the pixel electrode, thereby realizing the charging of the pixel electrode.

[0104] The control method of the array substrate provided by the embodiments of the present disclosure additionally provides a third control circuit. When the pixel electrode is in the level holding phase, the signal of the first voltage terminal V1 is written to the first node N1 through the third control circuit, thereby controlling the first control circuit to be turned on, so that the signal of the data signal terminal DATA is written to the pixel electrode through the first control circuit and the second control circuit, and the voltage between the pixel electrode and the common electrode is kept stable, thereby improving the jitter of the product.

[0105] In some embodiments, the second control circuit is controlled to write the signal of the storage circuit source to the pixel electrode, comprising:

[0106] S210, the third output circuit is controlled to write the signal of the third voltage terminal to the second control terminal, so that the second control circuit writes the signal of the storage circuit to the pixel electrode under the control of the signal of the second control terminal.

[0107] For example, a high-level signal is written to the second clock signal terminal CKB, the third output circuit is turned on, the high-level signal of the third voltage terminal V3 is written to the output terminal OUT, the high-level signal of the output terminal OUT is written to the second control terminal S2, the second control circuit is turned on under the control of the high-level signal of the second control terminal S2, and the signal of the storage circuit source is written to the pixel electrode, thereby realizing the charging of the pixel electrode.

[0108] Figure 16Another control method of the array substrate is provided for the embodiments of the present disclosure. As shown in Figure 16 The control method further includes the following steps.

[0109] S300, in the discharging stage, the third control circuit is controlled to write the signal of the first voltage terminal to the first node, so that the first control circuit is turned on under the control of the signal of the first node.

[0110] For example, a high-level signal is written to the third control terminal S3, the third control circuit is turned on, a high-level signal of the first voltage terminal V1 is written to the first node N1, the first control circuit is turned on under the control of the high-level signal of the first node N1, and a low-level signal of the data signal terminal DATA is written to the storage circuit source.

[0111] S400, in the discharging stage, the third output circuit is controlled to write the signal of the third voltage terminal to the second control terminal, so that the second control circuit is turned on.

[0112] For example, a high-level signal is written to the second clock signal terminal CKB, so that the third output circuit is turned on, a high-level signal of the third voltage terminal V3 is written to the output terminal OUT, a high-level signal of the output terminal OUT is written to the second control terminal S2, the second control circuit is turned on under the control of the high-level signal of the second control terminal S2, and a low-level signal of the storage circuit source is written to the pixel electrode, so as to realize the discharging of the pixel electrode.

[0113] In the discharging stage, the signal of the data signal terminal DATA is a low-level signal, so as to discharge the pixel electrode through the second control circuit, the storage circuit source and the first control circuit.

[0114] Exemplarily, continuing to refer to Figure 10 , Figure 12 and Figure 14 , at the last pull-up moment of the third clock signal terminal CLB, T13 and T16 are still open, but the level of the data signal terminal DATA is low at this time, at this time, the pixel electrode enters the discharging state, and a frame ends, so as to prepare for the next frame.

[0115] The above merely provides the specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited to this. Any person skilled in the art can easily think of the changes or replacements within the technical range disclosed by the present disclosure, which should be covered in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. An array substrate, characterized in that, It includes a shift register, a multiplexer, and a controller, wherein the controller includes a first control circuit, a storage circuit, a second control circuit, and a third control circuit. The first control circuit is electrically connected to the data signal terminal, the first node, and the storage circuit. The first control circuit is configured to write the signal from the data signal terminal and store it in the storage circuit under the signal control of the first node. The first node is electrically connected to the output terminal of the multiplexer. The second control circuit is electrically connected to the storage circuit, the second control terminal, and the pixel electrode. The second control circuit is configured to write the signal of the storage circuit to the pixel electrode under the signal control of the second control terminal. The second control terminal is electrically connected to the output terminal of the shift register; The third control circuit is electrically connected to the first voltage terminal, the first node, and the third control terminal. The third control circuit is configured to write the signal from the first voltage terminal into the first node under the signal control of the third control terminal.

2. The array substrate according to claim 1, characterized in that, The shift register includes: The first output circuit is electrically connected to the second clock signal terminal, the output terminal, and the pull-up node. The first output circuit is configured to write the signal of the second clock signal terminal to the output terminal under the signal control of the pull-up node. The second output circuit is electrically connected to the second voltage terminal, the output terminal, and the pull-down node. The second output circuit is configured to write the signal of the second voltage terminal to the output terminal under the signal control of the pull-down node. The third output circuit is electrically connected to the third voltage terminal, the output terminal, and the third clock signal terminal. The third output circuit is configured to write the signal from the third voltage terminal to the output terminal under the signal control of the third clock signal terminal.

3. The array substrate according to claim 1 or 2, characterized in that, The third control circuit includes a sixteenth transistor, the first terminal of which is electrically connected to the first voltage terminal, the second terminal of which is electrically connected to the first node, and the gate of which is electrically connected to the third control terminal.

4. The array substrate according to claim 2, characterized in that, The third output circuit includes a thirteenth transistor, the first terminal of which is electrically connected to the third voltage terminal, the second terminal of which is electrically connected to the output terminal, and the gate of which is electrically connected to the third clock signal terminal.

5. The array substrate according to claim 2, characterized in that, The third control terminal and the third clock signal terminal are electrically connected.

6. The array substrate according to claim 2, characterized in that, The first voltage terminal is electrically connected to the third voltage terminal.

7. A method for controlling an array substrate, characterized in that, The array substrate includes a shift register, a multiplexer, and a controller. The controller includes a first control circuit, a storage circuit, a second control circuit, and a third control circuit. The first control circuit is electrically connected to the data signal terminal, the first node, and the storage circuit. The first control circuit is configured to write the signal from the data signal terminal and store it in the storage circuit under the signal control of the first node. The first node is electrically connected to the output terminal of the multiplexer. The second control circuit is electrically connected to the storage circuit, the second control terminal, and the pixel electrode. The second control circuit is configured to write the signal of the storage circuit to the pixel electrode under the signal control of the second control terminal. The second control terminal is electrically connected to the output terminal of the shift register; The third control circuit is electrically connected to the first voltage terminal, the first node, and the third control terminal. The third control circuit is configured to write the signal of the first voltage terminal into the first node under the signal control of the third control terminal. An image frame includes an emission phase and a holding phase, the holding phase including a charging phase, and the control method includes: During the charging phase, the third control circuit is controlled to write the signal at the first voltage terminal to the first node, so that the first control circuit writes the signal at the data signal terminal to the storage circuit under the signal control of the first node. During the charging phase, the second control circuit is controlled to write the signal from the storage circuit into the pixel electrode.

8. The control method according to claim 7, characterized in that, The shift register includes: The first output circuit is electrically connected to the second clock signal terminal, the output terminal, and the pull-up node. The first output circuit is configured to write the signal of the second clock signal terminal to the output terminal under the signal control of the pull-up node. The second output circuit is electrically connected to the second voltage terminal, the output terminal, and the pull-down node. The second output circuit is configured to write the signal of the second voltage terminal to the output terminal under the signal control of the pull-down node. The third output circuit is electrically connected to the third voltage terminal, the output terminal, and the third clock signal terminal. The third output circuit is configured to write the signal from the third voltage terminal to the output terminal under the signal control of the third clock signal terminal. The control of the second control circuit to write the signal of the storage circuit to the pixel electrode includes: The third output circuit is controlled to write the signal from the third voltage terminal to the second control terminal, so that the second control circuit writes the signal from the storage circuit to the pixel electrode under the control of the signal from the second control terminal.

9. The control method according to claim 8, characterized in that, The holding phase further includes a discharging phase following the charging phase, and the control method further includes: During the discharge phase, the third control circuit is controlled to write the signal at the first voltage terminal into the first node, so that the first control circuit is turned on under the signal control of the first node. During the discharge phase, the third output circuit is controlled to write the signal at the third voltage terminal to the second control terminal, thereby turning on the second control circuit. During the discharge phase, the signal at the data signal terminal is a low-level signal, so that the pixel electrode discharges through the second control circuit, the storage circuit, and the first control circuit.

10. A display panel, characterized in that, It includes an array substrate, a color filter substrate, and a liquid crystal layer, wherein the array substrate and the color filter substrate are disposed in a cell, and the liquid crystal layer is located between the array substrate and the color filter substrate; The array substrate includes a shift register, a multiplexer, and a controller. The controller includes a first control circuit, a storage circuit, a second control circuit, and a third control circuit. The first control circuit is electrically connected to the data signal terminal, the first node, and the storage circuit. The first control circuit is configured to write the signal from the data signal terminal and store it in the storage circuit under the signal control of the first node. The first node is electrically connected to the output terminal of the multiplexer. The second control circuit is electrically connected to the storage circuit, the second control terminal, and the pixel electrode. The second control circuit is configured to write the signal of the storage circuit to the pixel electrode under the signal control of the second control terminal. The second control terminal is electrically connected to the output terminal of the shift register; The third control circuit is electrically connected to the first voltage terminal, the first node, and the third control terminal. The third control circuit is configured to write the signal from the first voltage terminal into the first node under the signal control of the third control terminal.

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