Dynamic Voltage Adjustment Method and Circuit

Abstract

The embodiments of this specification provide a dynamic voltage adjustment method and circuit. Among them, the Buck module is used to step down the input voltage to the output voltage and generate a sampling voltage based on the output voltage; the charge and discharge enable signal generation module is used to compare the sampling voltage with a first threshold voltage to generate a discharge enable signal, and compare the sampling voltage with a second threshold voltage to generate a charge enable signal; the charge and discharge signal generation module is used to generate start signals for charging the upper transistor and discharging the lower transistor under the action of the charge and discharge control signal generation module; the charge and discharge control signal generation module is used to generate control signals for charging the upper transistor and discharging the lower transistor to control the maximum current of charging and discharging. When the output voltage changes instantaneously, the Buck module can ensure a fast dynamic response and finally achieve a stable output.

Description

Technical Field

[0001] The embodiments of this specification relate to the field of circuit technologies, and particularly to a dynamic voltage adjustment method and circuit. Background Art

[0002] With the increasing requirements for larger screen sizes of electronic products and the increasing applications of always-on displays, new challenges are posed to the battery life of electronic products. Currently, there are two commonly used power-saving modes. One is envelope tracking (ET), and the other is average power tracking (APT). The basic function of both is to make the power supply of the power amplifier change with the input signal.

[0003] Currently, the Buck DC / DC buck topology is mostly used in the power supply for the power amplifier (PA). The input signal of the PA is collected by the MIPI interface, and the output signal of the MIPI interface finally controls and adjusts the output voltage of the Buck circuit to ensure that the voltage output by the Buck can change with the change of the PA input signal. To improve the efficiency and stability of the circuit, the Buck circuit needs to have an adaptive dynamic voltage adjustment function to make the output voltage of the Buck closely follow the change of the PA input.

[0004] The principle of the existing common Buck voltage control mode is to collect the input signal of the PA by the MIPI and control and adjust the output voltage Vout of the Buck circuit. Specifically, for the output voltage Vout of the Buck circuit, the voltage of FB is obtained through the voltage-dividing resistors R1 and R2. This voltage is error-amplified with the reference voltage Vref1 to obtain the output V of the error amplifier EA . Output V EA is connected to the positive input terminal of the comparator COMP. The negative input terminal of the comparator COMP is the inductor current collected. Through the comparison and inversion of the comparator COMP, a pulsed signal of the output VC is obtained. The high and low levels of this pulsed signal control the conduction of the upper transistor MP and the lower transistor MN of the Buck circuit through the drive logic. This feedback network belongs to a negative feedback network. When the output voltage Vout decreases, the collected FB voltage value increases, so that the V EA voltage becomes smaller. Through the comparison and inversion of the comparator COMP, the duty cycle of the output VC becomes larger. Through the drive logic circuit, the conduction time of the lower transistor MN becomes longer, and the conduction time of the upper transistor MP becomes shorter, resulting in an increase in the Vout voltage; when the output voltage Vout increases, the collected FB voltage value decreases, so that the V EAWhen the voltage increases, after comparison by the comparator COMP and inversion, the duty cycle of the output VC becomes smaller. Through the driving logic circuit, the conduction time of the upper transistor MP becomes longer and the conduction time of the lower transistor MN becomes shorter, resulting in a decrease in the Vout voltage. The stability of the output voltage is achieved through this negative feedback network. When the Vout voltage suddenly increases a lot, due to the sudden large increase in the Vout voltage, under the action of the load capacitor CL, a positive (in the same direction as the inductor current) pulsed charging current will be generated. This current flows from the left side to the right side of the inductor and, through the driving logic circuit, causes the upper transistor MP to conduct at this time, and the upper transistor MP is in the charging mode. Without the control of the charging circuit, the charging current of the upper transistor can reach a very high level, often exceeding the normal operating current, thus causing damage to the upper transistor. For example, when the normal power supply voltage VDD = 5V and the output voltage V OUT rises from 0.7V to 4.5V and the load RL = 3Ω, without the control of the charging circuit, the charging current of the upper transistor can reach about 9A, completely exceeding the maximum output current capacity of 1.2A.

[0005] Similarly, when the Vout voltage suddenly decreases a lot, due to the sudden large decrease in the Vout voltage, under the action of the load capacitor CL, a negative (opposite to the inductor current) pulsed discharging current will be generated. This current flows from the right side to the left side of the inductor and, through the driving logic circuit, causes the lower transistor MN to conduct at this time, and the lower transistor MN is in the discharging mode. Without the control of the discharging circuit, the discharging current of the lower transistor can reach a very high level, often exceeding the normal operating current, thus causing damage to the lower transistor.

[0006] In the existing technology, when the output voltage changes transiently a lot, due to the generation of large pulsed charging / discharging currents, it will cause the upper / lower transistors to burn out, resulting in the system being unable to work properly. Therefore, there is an urgent need for a better solution. Summary of the Invention

[0007] In view of this, the embodiments of this specification provide a dynamic voltage adjustment method. One or more embodiments of this specification also relate to a dynamic voltage adjustment circuit to solve the technical defects existing in the prior art.

[0008] According to the first aspect of the embodiments of this specification, a dynamic voltage adjustment method is provided, including:

[0009] Obtain a sampled voltage, compare the sampled voltage with a threshold voltage, and determine an enable signal;

[0010] Based on the level state of the enable signal and the level state of the control signal, trigger the rising edge or falling edge of the control signal;

[0011] Based on the rising edge or falling edge of the control signal, determine the corresponding start signal output to the Buck module to control the output voltage of the Buck module.

[0012] In a possible implementation, the threshold voltage includes a first threshold voltage and a second threshold voltage; the enable signal includes a discharge enable signal and a charge enable signal;

[0013] Correspondingly, comparing the sampled voltage with the threshold voltage to determine the enable signal includes:

[0014] When the sampled voltage is greater than the first threshold voltage, control the discharge enable signal to be set to a high level;

[0015] When the sampled voltage is less than the second threshold voltage, control the charge enable signal to be set to a high level.

[0016] In a possible implementation, the start signal includes a discharge start signal and a charge start signal; the control signal includes a discharge control signal and a charge control signal;

[0017] Correspondingly, based on the level state of the enable signal and the level state of the control signal, trigger the rising edge or falling edge of the control signal. Based on the rising edge or falling edge of the control signal, determine the corresponding start signal output to the Buck module, including:

[0018] When the discharge enable signal is set to a high level and the discharge control signal is at a high level, trigger the falling edge of the discharge control signal after a first delay;

[0019] When there is a falling edge of the discharge control signal, trigger the rising edge of the discharge start signal after a second delay to start discharging. When there is a falling edge of the discharge start signal, trigger the rising edge of the discharge control signal to end discharging and limit the discharge current of the lower transistor;

[0020] When the charge enable signal is set to a high level and the charge control signal is at a high level, trigger the falling edge of the charge control signal after a third delay;

[0021] When there is a falling edge of the charge control signal, trigger the falling edge of the charge start signal after a fourth delay to start charging. When there is a rising edge of the charge start signal, trigger the rising edge of the charge control signal to end charging and limit the charging current of the upper transistor.

[0022] According to the second aspect of the embodiments of this specification, a dynamic voltage adjustment circuit is provided, including a Buck module, a charge and discharge enable signal generation module, a charge and discharge control signal generation module, and a charge and discharge signal generation module;

[0023] The input end of the Buck module is electrically connected to the output end of the charge and discharge signal generation module, and the output end of the Buck module is electrically connected to the input end of the charge and discharge enable signal generation module;

[0024] The output end of the charge and discharge enable signal generation module is electrically connected to the input end of the charge and discharge signal generation module;

[0025] The input and output ends of the charge and discharge signal generation module are electrically connected to the input and output ends of the charge and discharge control signal generation module;

[0026] The Buck module is used to step down the input voltage to the output voltage and generate a sampling voltage based on the output voltage;

[0027] The charge and discharge enable signal generation module is used to compare the sampling voltage with the first threshold voltage and the second threshold voltage. When the sampling voltage is greater than the first threshold voltage, a high-level discharge enable signal is generated to allow the lower transistor to discharge. When the sampling voltage is less than the second threshold voltage, a low-level charge enable signal is generated to allow the upper transistor to charge;

[0028] The charge and discharge control signal generation module is used to generate a charge control signal and a discharge control signal to control the maximum current of charging and discharging;

[0029] The charge and discharge signal generation module is used to correspondingly generate a charge start signal or a discharge start signal under the combined action of the charge and discharge enable signal and the charge and discharge control signal.

[0030] In a possible implementation manner, the charge and discharge enable signal generation module includes a first enable unit and a second enable unit; the threshold voltage includes a first threshold voltage and a second threshold voltage; the enable signal includes a discharge enable signal and a charge enable signal;

[0031] The first input end of the first enable unit is electrically connected to the output end of the Buck module, and the second input end of the first enable unit is adapted to be connected to the first threshold voltage;

[0032] The first input end of the second enable unit is electrically connected to the output end of the Buck module, and the second input end of the second enable unit is adapted to be connected to the second threshold voltage;

[0033] The first enable unit is used to compare the sampling voltage with the first threshold voltage to determine the discharge enable signal;

[0034] The second enable unit is used to compare the sampling voltage with the second threshold voltage to determine the charge enable signal;

[0035] In a possible implementation manner, the charge and discharge signal generation module includes a gate circuit unit, a MOS transistor unit, and a comparator unit;

[0036] The input terminal of the gate circuit unit is electrically connected to the output terminal of the charge and discharge enable signal generation module, and the output terminal of the gate circuit unit is electrically connected to the input terminal of the MOS transistor unit;

[0037] The output terminal of the MOS transistor unit is electrically connected to the input terminal of the comparator unit, and the output terminal of the comparator unit is electrically connected to the input / output terminal of the charge and discharge control signal generation module and the input terminal of the Buck module;

[0038] The gate circuit unit is used to determine the states of the discharge enable signal and the charge enable signal;

[0039] The MOS transistor unit is used to determine whether to output a first output voltage or a second output voltage according to the states of the enable signal and the control signal;

[0040] The comparator unit is used to compare the output voltage of the MOS transistor unit with a reference voltage to determine the states of the charge start signal and the discharge start signal.

[0041] In a possible implementation manner, when the first output voltage output by the MOS transistor unit is greater than the reference voltage, the comparator unit outputs a high-level discharge start signal to start discharging. When the second output voltage output by the MOS transistor unit is greater than the reference voltage, the comparator unit outputs a low-level charge start signal to start charging.

[0042] In a possible implementation manner, the MOS transistor unit includes a mirror current source, a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor, a first capacitor, and a second capacitor;

[0043] The input terminal of the mirror current source is electrically connected to the power supply, and the output terminal is respectively connected to the drain of the fourth MOS transistor, the drain of the fifth MOS transistor, and the drain of the sixth MOS transistor. One end of the first capacitor is connected to the drain of the fifth MOS transistor, and one end of the second capacitor is connected to the drain of the sixth MOS transistor. The gates of the fifth MOS transistor and the sixth MOS transistor are both connected to the output terminal of the charge and discharge control signal generation module. The drains of the fifth MOS transistor and the sixth MOS transistor are both connected to the input terminal of the comparator unit. The sources of the fourth MOS transistor, the fifth MOS transistor, and the sixth MOS transistor, and the other ends of the first capacitor and the second capacitor are connected to the ground terminal.

[0044] In a possible implementation manner, the charge and discharge control signal generation module includes a first control unit and a second control unit;

[0045] The first control unit is used to trigger the rising edge of the discharge control signal again to end the discharge after timing a preset discharge time at the rising edge of the discharge start signal. The input terminal and the output terminal of the first control unit are electrically connected to the input / output terminal of the charge and discharge signal generation module;

[0046] The second control unit is used to trigger the rising edge of the charging control signal to end the charging again after timing a preset charging time at the falling edge of the charging start signal. The input end and the output end of the second control unit are electrically connected to the input and output ends of the charge and discharge signal generation module.

[0047] In a possible implementation manner, the first control unit includes a second NOR gate, a third NOR gate, a first timer, and a fourth NOT gate;

[0048] The second control unit includes a first NAND gate, a second NAND gate, and a second timer;

[0049] The first input end of the second NOR gate is adapted to be electrically connected to a high level. The second input end of the second NOR gate is electrically connected to the output end of the third NOR gate. The output end of the second NOR gate is electrically connected to the first input end of the third NOR gate;

[0050] The second input end of the third NOR gate is electrically connected to the input and output ends of the charge and discharge signal generation module. The output end of the third NOR gate is electrically connected to the input end of the first timer;

[0051] The output end of the first timer is electrically connected to the input end of the fourth NOT gate. The output end of the fourth NOT gate is electrically connected to the input and output ends of the charge and discharge signal generation module;

[0052] The first input end of the first NAND gate is adapted to be electrically connected to the ground terminal. The second input end of the first NAND gate is electrically connected to the output end of the second NAND gate. The output end of the first NAND gate is electrically connected to the first input end of the second NAND gate;

[0053] The second input end of the second NAND gate is electrically connected to the input and output ends of the charge and discharge signal generation module. The output end of the second NAND gate is electrically connected to the input end of the second timer;

[0054] The output terminal of the second timer is electrically connected to the input / output terminal of the charge / discharge signal generation module. An embodiment of this specification provides a dynamic voltage adjustment method and circuit. The Buck module is used to step down the input voltage to an output voltage and generate a sampling voltage based on the output voltage; the charge / discharge enable signal generation module is used to compare the sampling voltage with a first threshold voltage to generate a discharge enable signal, and compare the sampling voltage with a second threshold voltage to generate a charge enable signal; the charge / discharge signal generation module is used to generate a start signal for charging the upper transistor and discharging the lower transistor under the action of the charge / discharge control signal generation module. When the output voltage decreases by a first target value within a first period of time, a high-level lower transistor discharge signal is generated. When the output voltage increases by a second target value within a second period of time, a low-level upper transistor charge signal is generated; the charge / discharge control signal generation module is used to generate a control signal for charging the upper transistor and discharging the lower transistor to control the target current for charging and discharging. It is realized that when the output voltage of the Buck module changes instantaneously, a fast dynamic response can be ensured and a stable output can be finally achieved. Description of the Drawings

[0055] Figure 1a is a flowchart of a dynamic voltage adjustment method provided by an embodiment of this specification;

[0056] Figure 1b is a circuit diagram of a dynamic voltage adjustment circuit provided by an embodiment of this specification;

[0057] Figure 2 is a circuit diagram of the charge / discharge enable signal generation module of a dynamic voltage adjustment circuit provided by an embodiment of this specification;

[0058] Figure 3 is a circuit diagram of the charge / discharge signal generation module of a dynamic voltage adjustment circuit provided by an embodiment of this specification;

[0059] Figure 4 is a timing diagram of the lower transistor discharge of a dynamic voltage adjustment circuit provided by an embodiment of this specification;

[0060] Figure 5 is a timing diagram of the upper transistor charge of a dynamic voltage adjustment circuit provided by an embodiment of this specification;

[0061] Figure 6 is a circuit diagram of the charge / discharge control signal generation module of a dynamic voltage adjustment circuit provided by an embodiment of this specification;

[0062] Figure 7 is a dynamic voltage adjustment output waveform diagram of a dynamic voltage adjustment circuit provided by an embodiment of this specification. Detailed Embodiments

[0063] In the following description, numerous specific details are set forth in order to provide a thorough understanding of this specification. However, this specification can be implemented in many other ways different from those described herein, and those skilled in the art can make similar generalizations without departing from the spirit of this specification. Therefore, this specification is not limited by the specific implementations disclosed below.

[0064] The terms used in one or more embodiments of this specification are for the purpose of describing specific embodiments only and are not intended to limit one or more embodiments of this specification. The singular forms "a" and "the" used in one or more embodiments of this specification and the appended claims are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the term "and / or" used in one or more embodiments of this specification refers to and encompasses any and all possible combinations of one or more of the associated listed items.

[0065] It should be understood that although the terms first, second, etc. may be used in one or more embodiments of this specification to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from each other. For example, without departing from the scope of one or more embodiments of this specification, the first may also be referred to as the second, and similarly, the second may also be referred to as the first. Depending on the context, the word "if" as used herein can be interpreted as "when" or "while" or "in response to determining".

[0066] First, the noun terms related to one or more embodiments of this specification are explained.

[0067] DVS: dynamic voltage scaling, dynamic voltage adjustment.

[0068] The Buck circuit is a DC-DC converter based on the principle of inductive energy storage, which can convert high-voltage input into low-voltage output to meet the power supply requirements of different circuits.

[0069] In view of this, the embodiments of this specification provide a dynamic voltage adjustment method. One or more embodiments of this specification are also related to a dynamic voltage adjustment circuit, which will be described in detail one by one in the following embodiments.

[0070] See Figure 1a , Figure 1a shows a flowchart of a dynamic voltage adjustment method provided according to an embodiment of this specification. Specifically, the method includes:

[0071] S1001: Obtain a sampled voltage, compare the sampled voltage with a threshold voltage, and determine an enable signal;

[0072] S1002: Trigger the rising edge or falling edge of the control signal based on the level state of the enabling signal and the level state of the control signal;

[0073] S1003: Determine to output an electrical signal to the Buck module based on the rising edge or falling edge of the control signal to control the output voltage of the Buck module.

[0074] Hereinafter, the embodiments of this specification will combine the dynamic voltage adjustment method with the dynamic voltage adjustment circuit for description. For details, refer to the following embodiments.

[0075] See Figure 1b , Figure 1b shows a circuit diagram of a dynamic voltage adjustment circuit 100 provided according to an embodiment of this specification. The dynamic voltage adjustment circuit 100 includes a Buck module 101, a charge / discharge enabling signal generation module 102, a charge / discharge control signal generation module 103, and a charge / discharge signal generation module 104; the input end of the Buck module 101 is electrically connected to the output end of the charge / discharge signal generation module 104, and the output end of the Buck module 101 is electrically connected to the input end of the charge / discharge enabling signal generation module 102; the output end of the charge / discharge enabling signal generation module 102 is electrically connected to the input end of the charge / discharge signal generation module 104; the input / output end of the charge / discharge signal generation module 104 is electrically connected to the input / output end of the charge / discharge control signal generation module 103; the Buck module 101 is configured to step down the input voltage to an output voltage and generate a sampling voltage based on the output voltage; the charge / discharge enabling signal generation module 102 is configured to compare the sampling voltage with a first threshold voltage and a second threshold voltage. When the sampling voltage is greater than the first threshold voltage, a high-level discharge enabling signal is generated to allow the lower transistor to discharge. When the sampling voltage is less than the second threshold voltage, a low-level charge enabling signal is generated to allow the upper transistor to charge; the charge / discharge control signal generation module 103 is configured to generate a charge control signal and a discharge control signal to control the maximum current of charging and discharging; the charge / discharge signal generation module 104 is configured to correspondingly generate a charge start signal or a discharge start signal under the combined action of the charge / discharge enabling signal and the charge / discharge control signal.

[0076] Among them, the Buck module 101 can be a Buck circuit. The sampling voltage can be an FB signal. The output voltage can be Vout. The threshold voltages can be Vref_A and Vref_B, the enabling signals can be EN_A and EN_B signals, the electrical signals can be ontime_A and ontime_B signals. The control signals can be X70_YA and X70_YB signals. The upper transistor can be understood as the circuit where MP is located, and the lower transistor can be understood as the circuit where MN is located.

[0077] In practical applications, see Figure 1b, the charge / discharge enable signal generation module 102 is used to compare the sampled voltage value of FB with the threshold voltages (Vref_A and Vref_B), and generate the enable signals for the upper transistor charging and the lower transistor discharging; the comparator compares the magnitude of the FB voltage with the voltages Vref_A and Vref_B, and after delaying a preset time, generates the enable signal EN_A for controlling charging and the discharge EN_B signal. The input of the charge / discharge enable signal generation module 102 is the FB signal, Vref_A and Vref_B signals, and the output is the EN_A and EN_B signals. The EN_A signal is used to control the charging of the upper transistor, and the EN_B signal is used to control the discharging of the lower transistor. The output terminal serves as the input terminal of the charge / discharge enable signal generation module 102.

[0078] Further, refer to Figure 1b , the charge / discharge control signal generation module 103 is used to generate the upper transistor charging control signal X70_YB and the lower transistor discharging control signal X70_YA. Its input is the ontime_A and ontime_B signals, and the output is the X70_YA and X70_YB signals.

[0079] Further, refer to Figure 1b , the charge / discharge signal generation module 104 is used to generate the start signals for controlling the upper transistor charging and the lower transistor discharging. When the upper transistor charging enable signal EN_B is at a high level, under the control of the upper transistor charging control signal X70_YB signal, it generates the upper transistor charging signal ontime_B. When the lower transistor discharging enable signal EN_A is at a high level, under the control of the lower transistor discharging control signal X70_YA signal, it generates the lower transistor discharging signal ontime_A. Its input terminal is connected to the output terminals of the charge / discharge enable signal generation module 102 and the charge / discharge control signal generation module 103, and the output terminals are respectively connected to the upper transistor and the lower transistor.

[0080] In a possible implementation manner, the charge / discharge enable signal generation module 102 includes a first enable unit 1021 and a second enable unit 1022; the threshold voltages include a first threshold voltage and a second threshold voltage; the enable signals include a discharge enable signal and a charge enable signal; the first input terminal of the first enable unit 1021 is electrically connected to the output terminal of the Buck module 101, and the second input terminal of the first enable unit 1021 is the preset first threshold voltage; the first input terminal of the second enable unit 1022 is electrically connected to the output terminal of the Buck module 101, and the second input terminal of the second enable unit 1022 is the preset second threshold voltage; the first enable unit 1021 is used to compare the sampled voltage with the first threshold voltage to determine the discharge enable signal; the second enable unit 1022 is used to compare the sampled voltage with the second threshold voltage to determine the charge enable signal.

[0081] Among them, the first threshold voltage can be Vref_A, and the second threshold voltage can be Vref_B. The discharge enable signal can be the EN_A signal, and the discharge enable signal can be the EN_B signal.

[0082] Furthermore, the first enabling unit 1021 includes a first comparator COMP_A1, a first delay element, and a first inverter; the second enabling unit 1022 includes a second comparator COMP_B1, a second delay element, and a second inverter; a first input terminal of the first comparator COMP_A1 is electrically connected to an output terminal of the Buck module 101, and a second input terminal of the first comparator COMP_A1 is adapted to be connected to the first threshold voltage; an input terminal of the first delay element is electrically connected to an output terminal of the first comparator COMP_A1; an input terminal of the first inverter is electrically connected to an output terminal of the first delay element; a first input terminal of the second comparator COMP_B1 is electrically connected to an output terminal of the Buck module 101, and a second input terminal of the second comparator COMP_B1 is adapted to be connected to the second threshold voltage; an input terminal of the second delay element is electrically connected to an output terminal of the second comparator COMP_B1; an input terminal of the second inverter is electrically connected to an output terminal of the second delay element. When the sampled voltage is greater than the first threshold voltage, the discharge enable signal is controlled to be set to a high level; when the sampled voltage is less than the second threshold voltage, the charge enable signal is controlled to be set to a high level.

[0083] Specifically, refer to Figure 2 , Figure 2 which shows a circuit diagram of the charge / discharge enable signal generation module 102. Among them, the charging is the charging of the upper transistor MP, and the discharging is the discharging of the lower transistor MN.

[0084] During normal operation, in Figure 1b , Vref1 = 0.6V. When the Vout voltage changes suddenly by a large amount, the enable signals for triggering the charging of the upper transistor and the discharging of the lower transistor are generated. In Figure 2 , Vref_A = 0.7V, Vref_B = 0.5V. That is, when the FB voltage is between 0.5V and 0.7V, it operates according to the normal Buck circuit voltage control mode; when the FB voltage is greater than 0.7V, the discharge enable signal EN_A of the lower transistor is triggered, and at this time EN_A is at a high level, enabling the lower transistor to discharge; when the FB voltage is less than 0.5V, the charge enable signal EN_B of the upper transistor is triggered, and at this time EN_B is at a high level, enabling the upper transistor to charge. The FB voltage is a partial voltage of the output voltage of the Buck circuit, and the transient trend of the output voltage is opposite to that of the FB voltage. When the output voltage increases, the FB voltage decreases instantaneously, and when the output voltage decreases instantaneously, the FB voltage increases instantaneously.

[0085] When the Vout voltage suddenly decreases by a large amount, the FB voltage after the resistor voltage division of the sampling will have a very high overshoot voltage, and the FB voltage far exceedsFigure 1b Vref1 in it. When judging the enabling signal for the lower transistor to discharge, Vref_A is used as the comparison point. When the voltage value of FB exceeds Vref_A, after being compared by the comparator COMP_A1, a low level of VA is output. After a delay of the first preset time (1.4 us) and being inverted, the enabling signal EN_A for the lower transistor to discharge is obtained. At this time, EN_A is at a high level. The 1.4 us delay ensures the enabling signal EN_A for the lower transistor to discharge caused by the mis-triggering of FB.

[0086] When the Vout voltage suddenly increases a lot, there will be a very low overshoot voltage for the FB voltage after the sampling resistor voltage division. The FB voltage is much lower than Figure 1b Vref1 in it. When judging the enabling signal for the upper transistor to charge, Vref_B is used as the comparison point. When the voltage value of FB is lower than Vref_B, after being compared by the comparator COMP_B1, a low level of VB is output. After a delay of the second preset time (1 us) and being inverted, the enabling signal EN_B for the upper transistor to charge is obtained. At this time, EN_B is at a high level. The 1 us delay ensures the enabling signal EN_B for the upper transistor to charge caused by the mis-triggering of FB.

[0087] The charge / discharge enabling signal generation module 102 includes: comparators COMP_A1 and COMP_B1. The non-inverting input terminal of the comparator COMP_A1 is connected to Vref_A, the inverting input terminal is connected to FB. The non-inverting input terminal of the comparator COMP_B1 is connected to FB, and the inverting input terminal is connected to Vref_B. The output terminal of the comparator COMP_A1 passes through a delay element and a NOT gate to obtain the enabling signal EN_A for triggering the lower transistor. The output terminal of the comparator COMP_B1 passes through a delay element and a NOT gate to obtain the enabling signal EN_B for the upper transistor.

[0088] In a possible implementation, the charge / discharge signal generation module 104 includes a gate circuit unit 1041, a MOS transistor unit 1042, and a comparator unit 1043. The input terminal of the gate circuit unit 1041 is electrically connected to the output terminal of the charge / discharge enabling signal generation module 102. The output terminal of the gate circuit unit 1041 is electrically connected to the input terminal of the MOS transistor unit 1042. The output terminal of the MOS transistor unit 1042 is electrically connected to the input terminal of the comparator unit 1043. The output terminal of the comparator unit 1043 is electrically connected to the input / output terminal of the charge / discharge control signal generation module 103 and the input terminal of the Buck module 101.

[0089] Further, the gate circuit unit 1041 includes a first NOR gate and a first NOT gate; a first input terminal of the first NOR gate is electrically connected to an output terminal of the charge and discharge enabling signal generation module 102, and a second input terminal of the first NOR gate is electrically connected to the output terminal of the charge and discharge enabling signal generation module 102; an output terminal of the first NOR gate is electrically connected to an input terminal of the first NOT gate; an output terminal of the first NOT gate is electrically connected to an input terminal of the MOS transistor unit 1042.

[0090] Further, when the first output voltage output by the MOS transistor unit is greater than the reference voltage, the comparator unit outputs a high-level discharge start signal to start discharging, and when the second output voltage output by the MOS transistor unit is greater than the reference voltage, the comparator unit outputs a low-level charge start signal to start charging. The MOS transistor unit includes a mirror current source, a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor, a first capacitor, and a second capacitor; an input terminal of the mirror current source is electrically connected to a power supply, and output terminals are respectively connected to a drain of the fourth MOS transistor, a drain of the fifth MOS transistor, and a drain of the sixth MOS transistor. One end of the first capacitor is connected to the drain of the fifth MOS transistor, and one end of the second capacitor is connected to the drain of the sixth MOS transistor. Gates of the fifth MOS transistor and the sixth MOS transistor are both connected to an output terminal of the charge and discharge control signal generation module. Drains of the fifth MOS transistor and the sixth MOS transistor are both connected to an input terminal of the comparator unit. Sources of the fourth MOS transistor, the fifth MOS transistor, and the sixth MOS transistor, and the other ends of the first capacitor and the second capacitor are connected to a ground terminal.

[0091] Among them, the first capacitor may be C_A, and the second capacitor may be C_B. The mirror current source includes a resistor R, MOS transistors M1, M2, and M3.

[0092] Further, the comparator unit 1043 includes a third comparator COMP_A2, a fourth comparator COMP_B2, a second NOT gate, and a third NOT gate; a first input terminal of the third comparator COMP_A2 is electrically connected to a drain of the fifth MOS transistor, a second input terminal of the third comparator COMP_A2 is adapted to be connected to a reference voltage, and an output terminal of the third comparator COMP_A2 is electrically connected to an input terminal of the second NOT gate; a first input terminal of the fourth comparator COMP_B2 is electrically connected to a drain of the sixth MOS transistor, a second input terminal of the fourth comparator COMP_B2 is adapted to be connected to a reference voltage, and an output terminal of the fourth comparator COMP_B2 is electrically connected to an input terminal of the third NOT gate; output terminals of the second NOT gate and the third NOT gate are both connected to an input / output terminal of the charge and discharge control signal generation module 103 and an input terminal of the Buck module 101.

[0093] Specifically, refer to Figure 3, the charge / discharge signal generation module 104 includes MOS transistors M1 - M6, resistor R, first capacitor C_A and second capacitor C_B, comparators COMP_A2 and COMP_B2. The enable signals EN_A and EN_B are connected to a NAND gate after passing through a first NOR gate. The output terminal of the NOR gate is connected to the gate of M4. The sources of M1, M2, and M3 are all connected to the VDD terminal. The drain of M1 is connected to the drain of M4 through resistor R. The gate and drain of M1 are short - circuited and then connected to the gates of M2 and M3. The drain of M2 is connected to the drain of M5. The drain of M3 is connected to the drain of M6. The sources of M4, M5, and M6 are all connected to GND. The inverting input terminal of comparator COMP_A2 is connected to the drain of M5, and the non - inverting input terminal is connected to the reference voltage (0.6 * Vout). The output terminal of COMP_A2 outputs the ontime_A signal after passing through a NOR gate. The non - inverting input terminal of comparator COMP_B2 is connected to the drain of M6, and the inverting input terminal is connected to the reference voltage (0.6 * Vout). The output terminal of COMP_B2 outputs the ontime_B signal after passing through a NOR gate. A first capacitor C_A is connected between the inverting input terminal of COMP_A2 and GND, and a second capacitor C_B is connected between the non - inverting input terminal of COMP_B2 and GND.

[0094] In a possible implementation, the electrical signal includes a discharge start signal and a charge start signal; the control signal includes a discharge control signal and a charge control signal; when the discharge enable signal is set to high level and the discharge control signal is high level, the falling edge of the discharge control signal is triggered after a first delay; when there is a falling edge of the discharge control signal, the rising edge of the discharge start signal is triggered after a second delay to start discharging. When there is a falling edge of the discharge start signal, the rising edge of the discharge control signal is triggered to end discharging, thereby limiting the discharge current of the lower transistor;

[0095] When the charge enable signal is set to high level and the charge control signal is high level, the falling edge of the charge control signal is triggered after a third delay; when there is a falling edge of the charge control signal, the falling edge of the charge start signal is triggered after a fourth delay to start charging. When there is a rising edge of the charge start signal, the rising edge of the charge control signal is triggered to end charging, thereby limiting the charging current of the upper transistor.

[0096] Among them, the discharge start signal can be the ontime_A signal, and the charge start signal can be the ontime_B signal. The discharge control signal can be the X70_YA signal, and the charge control signal can be the X70_YB signal. The second delay can be T_A2, and the fourth delay can be T_B2. The second delay T_A2 is to prevent mis - triggering of starting discharge, and the fourth delay T_B2 is to prevent mis - triggering of starting charging.

[0097] In Figure 3When the lower transistor discharge enable signal EN_A is at a high level, the NMOS transistor M4 conducts, generating a mirror current source I = VDD / R. Through the mirroring of current mirrors M1 and M2, the current in M2 is I = VDD / R. Under the control of the lower transistor discharge control signal X70_YA signal, the lower transistor discharge signal ontime_A is controlled. When ontime_A is at a high level, the lower transistor starts to discharge; when X70_YA is at a high level, Vtime_A is cleared, and at this time ontime_A is at a low level, turning off the lower transistor discharge. The falling edge of X70_YA triggers Vtime_A to start timing and charging. When the voltage of vtime_A exceeds k*Vout, it triggers the rising edge of ontime_A, and the charging time T_A2 = C_A*k*Vout / I. The high-level time of ontime_A is the lower transistor discharge time. The rising edge of ontime_A, after delaying the lower transistor discharge time, triggers the rising edge of X70_YA. The timing diagram of the lower transistor discharge is as Figure 4 shown. The low-level time of X70_YA is T_A1, and the lower transistor discharge time is T_A3 = T_A1 - T_A2.

[0098] In Figure 3 When the upper transistor charge enable signal EN_B is at a high level, the NMOS transistor M4 conducts, generating a mirror current source I = VDD / R. Through the mirroring of current mirrors M1 and M3, the current in M3 is I = VDD / R. Under the control of the upper transistor charge control signal X70_YB signal, the upper transistor charge signal ontime_B is controlled. When ontime_B is at a low level, the upper transistor starts to charge; when X70_YB is at a high level, Vtime_B is cleared, and at this time ontime_B is at a high level, turning off the upper transistor charge. The falling edge of X70_YB triggers Vtime_B to start timing and charging. When the voltage of Vtime_B exceeds k*Vout, it triggers the falling edge of ontime_B, and the charging time T_B2 = C_B*k*Vout / I. The low-level time of ontime_B is the upper transistor charge time. The falling edge of ontime_B, after delaying the upper transistor charge time, triggers the rising edge of X70_YB. The timing diagram of the upper transistor charge is as Figure 5 shown. The low-level time of X70_YB is T_B1, and the upper transistor charge time is T_B3 = T_B1 - T_B2. The value of k is a parameter used to dynamically collect the output voltage change. The maximum charging and discharging currents can be controlled by adjusting the value of k. When the charging and discharging currents are too large, the value of k is reduced. k is a value greater than 0.2 and less than 0.8, preferably 0.6.

[0099] Furthermore, the generation circuit of the detailed lower transistor discharge control signal X70_YA is as Figure 6 shown. The generation circuit of the detailed upper transistor charge control signal X70_YB is asFigure 6 as shown

[0100] In a possible implementation, the charge and discharge control signal generation module 103 includes a first control unit 1031 and a second control unit 1032; the input end and the output end of the first control unit 1031 are electrically connected to the input and output ends of the charge and discharge signal generation module 104; the input end and the output end of the second control unit 1032 are electrically connected to the input and output ends of the charge and discharge signal generation module 104. The first control unit 1031 is configured to trigger the rising edge of the discharge control signal to end the discharge after timing a preset discharge time at the rising edge of the discharge start signal. The input end and the output end of the first control unit 1031 are electrically connected to the input and output ends of the charge and discharge signal generation module. The second control unit 1032 is configured to trigger the rising edge of the charge control signal to end the charge after timing a preset charge time at the falling edge of the charge start signal. The input end and the output end of the second control unit 1032 are electrically connected to the input and output ends of the charge and discharge signal generation module.

[0101] Further, the first control unit 1031 includes a second NOR gate, a third NOR gate, a first timer T_A3, and a fourth NOT gate; the second control unit 1032 includes a first NAND gate, a second NAND gate, and a second timer T_B3; the first input end of the second NOR gate is adapted to be connected to a high level, the second input end of the second NOR gate is electrically connected to the output end of the third NOR gate, and the output end of the second NOR gate is electrically connected to the first input end of the third NOR gate; the second input end of the third NOR gate is electrically connected to the input and output ends of the charge and discharge signal generation module 104, and the output end of the third NOR gate is electrically connected to the input end of the first timer T_A3; the output end of the first timer T_A3 is electrically connected to the input end of the fourth NOT gate, and the output end of the fourth NOT gate is electrically connected to the input and output ends of the charge and discharge signal generation module 104; the first input end of the first NAND gate is adapted to be electrically connected to a ground terminal, the second input end of the first NAND gate is electrically connected to the output end of the second NAND gate, and the output end of the first NAND gate is electrically connected to the first input end of the second NAND gate; the second input end of the second NAND gate is electrically connected to the input and output ends of the charge and discharge signal generation module 104, and the output end of the second NAND gate is electrically connected to the input end of the second timer T_B3; the output end of the second timer T_B3 is electrically connected to the input and output ends of the charge and discharge signal generation module 104.

[0102] Specifically, the charge / discharge control signal generation circuit is as Figure 6As shown, the charge / discharge control signal generation module 103 includes a NOR-NAND gate, a NOT gate, and a delay element. One input terminal of the second NOR gate is constantly at a high level, and the other input terminal is connected to the output of the third NOR gate. One input terminal of the third NOR gate is connected to the ontime_A signal, and the other input terminal is connected to the output terminal of the second NOR gate. The output signal of the third NOR gate is connected to the NOT gate after a preset time of timing to output the X70_YA signal. One input terminal of the first NAND gate is constantly at a low level, and the other input terminal is connected to the output of the second NAND gate. One input terminal of the second NAND gate is connected to the ontime_B signal, and the other input terminal is connected to the output of the first NAND gate. The output signal of the second NAND gate is output as the X70_YB signal after a preset time of timing.

[0103] In Figure 3 the charge / discharge signal generation circuit, the rising edge of ontime_A is controlled by the falling edge of the lower transistor discharge control signal X70_YA and the delay T_A2. In Figure 6 the rising edge of the lower transistor discharge control signal X70_YA is controlled by the rising edge of ontime_A and the delay T_A3. The rising edge of ontime_A triggers the falling edge of VA2, and after the lower transistor discharge time T_A3, it triggers the rising edge of X70_YA.

[0104] In Figure 3 the charge / discharge signal generation circuit, the falling edge of ontime_B is controlled by the falling edge of the upper transistor charge control signal X70_YB and the delay T_B2. In Figure 6 the rising edge of the upper transistor charge control signal X70_YB is controlled by the falling edge of ontime_B and the delay T_B3. The falling edge of ontime_B triggers the rising edge of VB2, and after the upper transistor charge time T_B3, it triggers the rising edge of X70_YB.

[0105] The embodiments of this specification provide a dynamic voltage adjustment method and circuit. The Buck module is used to step down the input voltage to the output voltage and generate a sampling voltage based on the output voltage. The charge and discharge enable signal generation module is used to compare the sampling voltage with a first threshold voltage to generate a discharge enable signal, and compare the sampling voltage with a second threshold voltage to generate a charge enable signal. The charge and discharge signal generation module is used to generate start signals for charging the upper transistor and discharging the lower transistor under the action of the charge and discharge control signal generation module. When the output voltage decreases by a first target value within a first period of time, a high-level lower transistor discharge signal is generated. When the output voltage increases by a second target value within a second period of time, a low-level upper transistor charge signal is generated. The charge and discharge control signal generation module is used to generate control signals for controlling the upper transistor charge control signal and the lower transistor discharge control signal to control the target current of charging and discharging. It is realized that when the output voltage of the Buck module changes instantaneously, a fast dynamic response can be ensured and a stable output can be finally achieved.

[0106] Furthermore, the embodiments of this specification set two threshold voltages. When the output voltage changes greatly, the sampled voltage value of FB is compared with the threshold voltages respectively, and finally the corresponding upper transistor charge enable signal and lower transistor discharge enable signal are generated. When the output voltage decreases greatly, the lower transistor discharge enable signal EN_A is generated. When the output voltage increases greatly, the upper transistor charge enable signal EN_B is generated. The charging of the upper transistor and the discharging of the lower transistor are controlled by the enable signals.

[0107] The embodiments of this specification generate start signals for controlling the charging of the upper transistor and the discharging of the lower transistor through the charge / discharge signal generation module 104. When the output voltage instantaneously decreases greatly, a high-level lower transistor discharge signal ontime_A is generated to discharge the lower transistor to increase the output voltage. When the output voltage instantaneously increases greatly, a low-level upper transistor charge signal ontime_B is generated to turn on the upper transistor to lower the output voltage. Through the start signals for charging the upper transistor and discharging the lower transistor generated by the charge / discharge signal generation module 104, the on-time of the upper transistor and the lower transistor can be adjusted in a timely manner when the output voltage changes instantaneously, so that the output voltage is stable.

[0108] The embodiments of this specification generate a lower transistor discharge control signal X70_YA through the charge / discharge control signal generation module 103 when the output voltage instantaneously decreases greatly, and generate an upper transistor charge control signal X70_YB when the output voltage instantaneously increases greatly. The charge / discharge control signal limits the maximum current of charging the upper transistor and discharging the lower transistor to ensure the safe operation of the upper / lower transistors.

[0109] In the embodiments of this specification, the charging time of the upper transistor and the discharging time of the lower transistor can be adjusted arbitrarily according to system requirements. By changing the delay time through a delay device, on the basis of ensuring system stability, the output voltage can be quickly stabilized.

[0110] It should be noted that for a dynamic voltage adjustment circuit 100 of the present disclosure, the output waveform of the dynamic voltage adjustment that can be achieved is as follows Figure 7 shown. In the figure, the horizontal axis represents time, and the vertical axis from top to bottom represents the voltage waveforms of the MIPI interface, FB, EN_A, X70_YA, ontime_A, EN_B, X70_YB, and ontime_B respectively. When the output voltage controlled by MIPI drops significantly instantaneously, the voltage value of FB will exceed Vref_A, thereby triggering the lower transistor discharge enable signal EN_A to be at a high level. When the lower transistor discharge enable signal is at a high level, the final output lower transistor discharge signal ontime_A is controlled by the lower transistor discharge control signal X70_YA. When ontime_A is at a high level, the lower transistor MN is triggered to discharge; when the output voltage controlled by MIPI rises significantly instantaneously, the voltage value of FB will be lower than Vref_B, thereby triggering the upper transistor charge enable signal EN_B to be at a high level. When the upper transistor charge enable signal EN_B is at a high level, the final output upper transistor charge signal ontime_B is controlled by the upper transistor charge control signal X70_YB. When ontime_B is at a low level, the upper transistor MP is triggered to charge. The time of the lower transistor discharge and the time of the upper transistor charge can be adjusted arbitrarily according to requirements, so as to quickly and stably stabilize the final output voltage on the basis of meeting the system stability and improve the efficiency of the system.

[0111] It should be noted that for the foregoing circuit embodiments, for the sake of simplicity of description, they are all expressed as a series of action combinations. However, those skilled in the art should know that the embodiments of this specification are not limited by the described action sequence, because according to the embodiments of this specification, certain steps can be performed in other sequences or simultaneously. Secondly, those skilled in the art should also know that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily essential for the embodiments of this specification.

[0112] In the above embodiments, the descriptions of the respective embodiments have their own emphases. For the parts not detailed in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0113] The preferred embodiments of this specification disclosed above are only used to help explain this specification. The alternative embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, according to the content of the embodiments of this specification, many modifications and changes can be made. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the embodiments of this specification, so that those skilled in the art can understand and utilize this specification well. This specification is only limited by the claims and their full scope and equivalents.

Claims

1. A dynamic voltage adjustment circuit, characterized in that: It includes a Buck module, a charge and discharge enable signal generating module, a charge and discharge control signal generating module and a charge and discharge signal generating module; The input end of the Buck module is electrically connected to the output end of the charge and discharge signal generating module, and the output end of the Buck module is electrically connected to the input end of the charge and discharge enable signal generating module; The output end of the charge and discharge enable signal generating module is electrically connected to the input end of the charge and discharge signal generating module; The input and output ends of the charge and discharge signal generating module are electrically connected to the input and output ends of the charge and discharge control signal generating module; The Buck module is used to step down the input voltage into an output voltage, and generate a sampling voltage based on the output voltage; The charge and discharge enable signal generating module is used to compare the sampled voltage with a first threshold voltage and a second threshold voltage, and when the sampled voltage is greater than the first threshold voltage, generate a high-level discharge enable signal to allow the lower tube to discharge, and when the sampled voltage is less than the second threshold voltage, generate a low-level charge enable signal to allow the upper tube to charge; The charge and discharge control signal generating module is used to generate a charge control signal and a discharge control signal to control the maximum current of charging and discharging; The charge and discharge signal generating module is used to generate a charge start signal or a discharge start signal correspondingly under the joint action of the charge and discharge enable signal and the charge and discharge control signal; The charge and discharge signal generating module includes a gate circuit unit, a MOS tube unit and a comparator unit; The input end of the gate circuit unit is electrically connected to the output end of the charge and discharge enable signal generating module, and the output end of the gate circuit unit is electrically connected to the input end of the MOS tube unit; The output end of the MOS tube unit is electrically connected to the input end of the comparator unit, and the output end of the comparator unit is electrically connected to the input and output ends of the charge and discharge control signal generating module and the input end of the Buck module; The gate circuit unit is used to determine the states of the discharge enable signal and the charge enable signal; The MOS tube unit is used to determine the output of the first output voltage or the second output voltage according to the state of the enable signal and the control signal; The comparator unit is used to compare the output voltage of the MOS tube unit with a reference voltage to determine the states of the charge start signal and the discharge start signal.

2. The dynamic voltage adjustment circuit according to claim 1, characterized in that: The charge and discharge enable signal generating module includes a first enable unit and a second enable unit; the threshold voltage includes a first threshold voltage and a second threshold voltage; the enable signal includes a discharge enable signal and a charge enable signal; The first input end of the first enabling unit is electrically connected to the output end of the Buck module, and the second input end of the first enabling unit is suitable for connecting to a first threshold voltage; The first input terminal of the second enabling unit is electrically connected to the output terminal of the Buck module, and the second input terminal of the second enabling unit is suitable for connecting to a second threshold voltage; The first enabling unit is used to compare the sampled voltage with the first threshold voltage to determine a discharge enabling signal; The second enabling unit is used to compare the sampled voltage with the second threshold voltage to determine a charging enabling signal.

3. The dynamic voltage adjustment circuit according to claim 1, characterized in that: When the first output voltage output by the MOS tube unit is greater than the reference voltage, the comparator unit outputs the discharge start signal of a high level to start discharging; when the second output voltage output by the MOS tube unit is greater than the reference voltage, the comparator unit outputs the charge start signal of a low level to start charging.

4. The dynamic voltage adjustment circuit according to claim 3, characterized in that: The MOS tube unit includes a mirror current source, a fourth MOS tube, a fifth MOS tube, a sixth MOS tube, a first capacitor and a second capacitor; The input end of the mirror current source is electrically connected to the power supply, and the output end is respectively connected to the drain of the fourth MOS tube, the drain of the fifth MOS tube, and the drain of the sixth MOS tube, one end of the first capacitor is connected to the drain of the fifth MOS tube, one end of the second capacitor is connected to the drain of the sixth MOS tube, the gate of the fifth MOS tube and the gate of the sixth MOS tube are both connected to the output end of the charge and discharge control signal generating module, the drain of the fifth MOS tube and the drain of the sixth MOS tube are both connected to the input end of the comparator unit, and the source of the fourth MOS tube, the fifth MOS tube, the sixth MOS tube, the first capacitor, and the other end of the second capacitor are connected to the ground end.

5. The dynamic voltage adjustment circuit according to claim 1, characterized in that: The charge and discharge control signal generating module includes a first control unit and a second control unit; The first control unit is used to trigger the rising edge of the discharge control signal again to end the discharge after the rising edge of the discharge start signal times the preset discharge time, and the input and output ends of the first control unit are electrically connected to the input and output ends of the charge and discharge signal generating module; The second control unit is used to trigger the rising edge of the charging control signal again to end charging after the falling edge of the charging start signal times a preset charging time, and the input and output ends of the second control unit are electrically connected to the input and output ends of the charging and discharging signal generating module.

6. The dynamic voltage adjustment circuit according to claim 5, characterized in that: The first control unit includes a second NOR gate, a third NOR gate, a first timer and a fourth NOR gate; The second control unit includes a first NAND gate, a second NAND gate and a second timer; The first input terminal of the second NOR gate is suitable for being electrically connected to a high level, the second input terminal of the second NOR gate is electrically connected to the output terminal of the third NOR gate, and the output terminal of the second NOR gate is electrically connected to the first input terminal of the third NOR gate; The second input end of the third NOR gate is electrically connected to the input and output ends of the charge and discharge signal generating module, and the output end of the third NOR gate is electrically connected to the input end of the first timer; The output end of the first timer is electrically connected to the input end of the fourth NOT gate, and the output end of the fourth NOT gate is electrically connected to the input and output ends of the charge and discharge signal generating module; The first input terminal of the first NAND gate is suitable for being electrically connected to the ground terminal, the second input terminal of the first NAND gate is electrically connected to the output terminal of the second NAND gate, and the output terminal of the first NAND gate is electrically connected to the first input terminal of the second NAND gate; The second input end of the second NAND gate is electrically connected to the input and output ends of the charge and discharge signal generating module, and the output end of the second NAND gate is electrically connected to the input end of the second timer; The output end of the second timer is electrically connected to the input and output ends of the charge and discharge signal generating module.

7. A dynamic voltage adjustment method, characterized in that: Applied to the dynamic voltage adjustment circuit according to any one of claims 1 to 6, the method comprising: Acquire a sampled voltage, compare the sampled voltage with a threshold voltage, and determine an enable signal; Based on the level state of the enable signal and the level state of the control signal, triggering the rising edge or the falling edge of the control signal; Based on the rising edge or the falling edge of the control signal, it is determined to output a corresponding start signal to the Buck module to control the output voltage of the Buck module.

8. The method according to claim 7, characterized in that The threshold voltage includes a first threshold voltage and a second threshold voltage; the enable signal includes a discharge enable signal and a charge enable signal; Accordingly, comparing the sampled voltage with the threshold voltage to determine the enable signal includes: When the sampling voltage is greater than the first threshold voltage, controlling the discharge enable signal to be set to a high level; When the sampling voltage is less than the second threshold voltage, the charging enable signal is controlled to be set to a high level.

9. The method according to claim 8, characterized in that The start signal includes a discharge start signal and a charge start signal; the control signal includes a discharge control signal and a charge control signal; Correspondingly, the triggering of the rising edge or falling edge of the control signal based on the level state of the enable signal and the level state of the control signal, and determining to output a corresponding start signal to the Buck module based on the rising edge or falling edge of the control signal, includes: When the discharge enable signal is set to a high level and the discharge control signal is at a high level, a falling edge of the discharge control signal is triggered after a first delay; When the discharge control signal has a falling edge, the rising edge of the discharge start signal is triggered after the second delay to start the discharge, and when the discharge start signal has a falling edge, the rising edge of the discharge control signal is triggered to end the discharge, thereby limiting the discharge current of the lower tube; When the charging enable signal is set to a high level and the charging control signal is at a high level, triggering a falling edge of the charging control signal after a third delay; When the charging control signal has a falling edge, the falling edge of the charging start signal is triggered after the fourth delay to start charging. When the charging start signal has a rising edge, the rising edge of the charging control signal is triggered to end charging, thereby limiting the charging current of the upper tube.

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