Hybrid Serial Receiver Circuit

Abstract

The hybrid receiver circuitry included in a computer system may include both analog and ADC-based receiver circuitry. The front-end circuitry generates different equalization signals based on a received signal encoding a serial data stream including a plurality of data symbols. Depending on the baud rate of the serial data stream, either the digital receive circuitry or the analog receiver circuitry is activated to provide desired performance and power consumption over a range of possible baud rates. The ADC-based receiver circuitry may include a plurality of analog-to-digital converter circuits having different resolutions that may be selected for different baud rates.

Description

Background Art Technical Field

[0002] The present disclosure relates to the field of high-speed communication interface design, and more particularly to the use of receiver circuits based on hybrid analog / digital converters (ADCs).

[0003] Description of Related Technologies

[0004] Computing systems typically include multiple interconnected integrated circuits. In some cases, integrated circuits may communicate by transmitting and receiving data bits over a communication channel or link. The communication channel may support parallel communication for transmitting multiple data bits in parallel, or serial communication for transmitting data bits one at a time in a serial fashion.

[0005] Data transmitted between integrated circuits may be encoded to facilitate transmission. For example, in the case of serial communication, data may be encoded to provide transitions between logical states sufficient to allow clock and data recovery circuitry to operate. Alternatively, in the case of parallel communication, data may be encoded to reduce switching noise or improve signal integrity.

[0006] During data transmission, the physical characteristics of the communication channel may attenuate the transmitted signal associated with a particular data bit. For example, the impedance of the wiring included in the communication channel or link may attenuate certain frequency ranges of the transmitted signal. Additionally, an impedance mismatch between the wiring included in the communication channel and the devices coupled to the communication channel may cause reflections of the transmitted signal, which may degrade subsequent transmitted signals corresponding to other data bits. Summary of the Invention

[0007] Various embodiments for processing a serial data stream are disclosed. Broadly, a hybrid receiver circuit includes a front-end circuit, an ADC-based receiver circuit, an analog receiver circuit, and a clock circuit. The front-end circuit may be configured to generate an equalization signal using at least one signal encoding a serial data stream including a plurality of data symbols. The ADC-based receiver circuit may include at least one analog-to-digital converter circuit and may be configured to generate a first plurality of recovered data symbols based on the baud rate of the serial data stream, using a first equalization signal and a plurality of first clock signals. The analog receiver circuit may be configured to generate a second plurality of recovered data symbols based on the baud rate of the serial data stream, using a second equalization signal and a plurality of second clock signals. The clock circuit may be configured to generate a plurality of first clock signals using first control information determined during generation of the first plurality of recovered data symbols, and to generate a plurality of second clock signals using second control information determined during generation of the second plurality of recovered data symbols. Brief Description of the Drawings

[0008] Figure 1It is a block diagram of an embodiment of a hybrid receiver circuit for a computer system.

[0009] Figure 2 It is a block diagram of an embodiment of an analog front-end circuit.

[0010] Figure 3 It is a block diagram of an embodiment of an ADC-based receiver circuit for a hybrid receiver circuit.

[0011] Figure 4 It is a block diagram of an embodiment of an analog receiver circuit for a hybrid receiver circuit.

[0012] Figure 5 It is a block diagram of an embodiment of a sampling circuit for an ADC-based receiver circuit.

[0013] Figure 6 It is a block diagram of an embodiment of a clock circuit for a hybrid receiver circuit.

[0014] Figure 7 It is a block diagram of a computer system including a transmitter circuit and a receiver circuit.

[0015] Figure 8 It is a flowchart of an embodiment of a method for operating a hybrid receiver circuit.

[0016] Figure 9 It is a block diagram of an embodiment of a system-on-chip including a receiver circuit.

[0017] Figure 10 It is a block diagram of various embodiments of a computer system that may include a receiver circuit.

[0018] Figure 11 An example of a non-transitory computer-readable storage medium storing circuit design information is shown. Detailed Description

[0019] A computing system may include one or more integrated circuits, such as a central processing unit (CPU) and a memory. Each of the integrated circuits in the computing system may communicate via a serial or parallel interface. In a parallel interface, multiple data bits are transmitted simultaneously, while in a serial interface, data is transmitted as a series of sequential single data bits. When a serial interface is employed to transmit data between two devices included in the computing system, the data may be transmitted according to different protocols. For example, data may be transmitted using return-to-zero (RZ), non-return-to-zero (NRZ), pulse amplitude modulation (PAM), or any suitable combination thereof.

[0020] Serial data streams are often transmitted without an accompanying clock signal. In such cases, the clock signal is recovered from the serial data stream (in a process known as "clock recovery") and is used to sample the serial data stream to determine the value of the included data symbols (in a process known as "data recovery"). Various techniques can be employed to recover both the data and the clock signal. For example, a receiver circuit can generate a clock signal having a frequency approximately the same as the frequency of the clock signal used to create the data stream. A phase-locked loop circuit can then be used to align the phase of the clock signal with transitions in the serial data stream. Alternatively, the serial data stream can be oversampled, i.e., sampled at a frequency higher than the frequency of the clock signal used to generate the serial data stream.

[0021] Receiver circuits for serial data streams can be analog-based, or they can employ analog-to-digital converter (ADC) circuits. ADC-based receiver circuits convert an equalized version of the input data signal into bits in the digital domain, thereby allowing additional processing (e.g., feed-forward equalization) to be performed as digital signal processing operations.

[0022] In new interconnect standards, receiver circuits are required to support a wide range of baud rates. As used and defined herein, the baud rate (or "symbol rate") is the rate at which information is transmitted over a communication channel. For example, in PCIE, the data rate can vary from 2.5 Gbaudps to 32 Gbaudps. At the lower end of such a range, analog-based receiving circuits can provide a power-efficient solution for sampling the signals transmitted over the communication channel. However, as the baud rate of the signal increases, analog-based receiver circuits may not provide the performance required to consistently recover the data. At high baud rates, ADC-based receiver circuits can provide the performance required to sample the signals, but are power-inefficient at lower baud rates. No single receiver circuit topology covers the required data rate range without sacrificing performance or power.

[0023] The embodiments shown in the figures and described below can provide techniques for sampling signals of an encoded serial data stream using a hybrid receiver circuit that includes both an analog-based receiver circuit and an ADC-based receiver circuit. Under certain conditions (e.g., low baud rate, low-loss communication channel, etc.), the analog-based receiver circuit can be enabled to sample the signals in a power-efficient manner. In response to a change in conditions (e.g., an increase in the baud rate of the received data stream), the analog-based receiver circuit can be disabled, and the ADC-based receiver circuit is enabled to provide the required performance under the new conditions.

[0024] Figure 1A block diagram depicting an embodiment of a hybrid receiver circuit is shown. As shown, the hybrid receiver circuit 100 includes a front-end circuit 101, an ADC-based receiver circuit 102, an analog receiver circuit 103, a clock circuit 104, and a multiplexing circuit 105.

[0025] The front-end circuit 101 is configured to generate an equalized signal 108 using a signal 106. In various embodiments, the signal 106 encodes a serial data stream including data symbols 107. Although the front-end circuit 101 is depicted as generating a single equalized signal used by both the ADC-based receiver circuit 102 and the analog receiver circuit 103, in other embodiments, the front-end circuit 101 may be configured to generate different equalized signals for each of the ADC-based receiver circuit 102 and the analog receiver circuit 103.

[0026] In some embodiments, the signal 106 may encode the data symbol 107 according to one of various symbol encodings. For example, the signal 106 may be transmitted according to RZ, NRZ, PAM3, or any other suitable symbol encoding. Note that although a single signal is depicted as encoding the data symbol 107, in other embodiments, multiple signals may be employed to encode the data symbol 107. For example, in some cases, when using a differential signaling standard, two signals may be employed to encode the data symbol 107.

[0027] The ADC-based receiver circuit 102 includes an analog-to-digital converter circuit 116 and is configured to generate a recovered data symbol 110 using a clock signal 114 and an equalized signal 108 based on the baud rate of a serial data stream including data symbols 107. As described below, the ADC-based receiver circuit 102 may include multiple analog-to-digital converter circuits that sample the equalized signal 108 at different resolutions. In various embodiments, different analog-to-digital converter circuits among the multiple analog-to-digital converter circuits may be employed based on the baud rate of a serial data stream including data symbols 107.

[0028] The analog receiver circuit 103 is configured to generate a recovered data symbol 111 using a clock signal 115 and an equalized signal 108 based on the baud rate of a serial data stream including data symbols 107. As described below, the analog receiver circuit 103 may be implemented primarily using analog circuits that perform various functions (e.g., decision feedback equalization) in the analog domain. Note that at baud rates less than a threshold, the power consumption of the analog receiver circuit 103 may be less than the power consumption of the ADC-based receiver circuit 102. Although only a single analog receiver circuit is depicted in the Figure 1 embodiment, additional analog receiver circuits may be employed in other embodiments, each configured to be activated under a corresponding set of conditions (e.g., input data stream baud rate, channel conditions, etc.).

[0029] The clock circuit 104 is configured to generate a clock signal 114 using control information 112 and a clock signal 115 using control information 113. In some embodiments, the clock circuit 104 may be configured to generate the clock signal 114 or the clock signal 115 based on a mode signal 120. For example, the clock circuit 104 may be configured to generate the clock signal 114 in response to determining that the mode signal 120 is a particular value. Alternatively, the clock circuit 104 may be configured to generate the clock signal 115 in response to determining that the mode signal 120 is a different value. Although the clock signal 114 and the clock signal 115 are depicted as a single line, in various embodiments, the clock signal 114 and the clock signal 115 may include multiple clock signals having respective phases. Note that the value of the mode signal 104 may correspond to a particular set of conditions (e.g., input data stream baud rate, channel conditions, etc.). A change in one or more of these conditions may result in a different value of the mode signal 104.

[0030] The clock circuit 104 may be configured to generate the clock signal 114 in response to determining that the baud rate of the serial data stream is equal to a particular baud rate value and otherwise generate the clock signal 115. In various embodiments, the determination of the baud rate may be performed during an initialization process associated with the communication channel to which the hybrid receiver circuit 100 is coupled.

[0031] In various embodiments, the ADC-based receiver circuit 102 is configured to determine control information 112 during generation of the recovered data symbol 110. In a similar manner, the analog receiver circuit 103 is also configured to determine control information 113 during generation of the recovered data symbol 111. The control information 112 may include information indicating a phase error detected during generation of the recovered data symbol 110, and the control information 113 may include information indicating a phase error detected during generation of the recovered data symbol 111.

[0032] In various embodiments, the multiplexing circuit 105 is configured to generate an output data symbol 121 by selecting the recovered data symbol 110 or the recovered data symbol 111 using the mode signal 120. The multiplexing circuit 105 may be implemented using a plurality of logic gates, a plurality of pass gate circuits coupled together in a wired-OR fashion, or any other suitable circuit configured to select between the two sets of recovered data symbols. Note that the multiplexing circuit 105 may be optional, as in some embodiments, the load circuit may directly receive the recovered data symbol 110 and the recovered data symbol 111.

[0033] Go to Figure 2, a block diagram depicting an implementation of the front-end circuit 101 is shown. As shown, the front-end circuit 101 includes a filter circuit 201 and an automatic gain control circuit 202A. Although the front-end circuit 101 is depicted as generating a single equalized signal, in other implementations, the front-end circuit 101 may be configured to generate any suitable number of equalized signals using the signal 106.

[0034] The filter circuit 201 is configured to generate a filtered signal 203 using the signal 106. In various implementations, to generate the filtered signal 203, the filter circuit 201 may also be configured to attenuate high-frequency noise in the signal 106. In some cases, the filter circuit 201 may also be configured to attenuate low-frequency components at or near the DC level of the signal 106.

[0035] The automatic gain control circuit 202 is configured to generate an equalized signal 108 using the filtered signal 203. In various implementations, the automatic gain control circuit 202 may be implemented as a closed-loop control circuit that uses feedback derived from the equalized signal 108 to maintain the amplitude of the data symbols at an optimal level for sampling. In various implementations, the automatic gain control circuit 202 may include any suitable combination of attenuator and amplifier circuits that can be dynamically activated or deactivated to maintain the amplitude of the data symbols.

[0036] Although a single automatic gain circuit is described in the Figure 2 implementation, additional automatic gain control circuits may be employed in other implementations that require multiple equalized signals. In such cases, the additional automatic gain circuits may apply different amounts of gain and / or attenuation to their respective equalized signals.

[0037] Turning to Figure 3 , a block diagram depicting an implementation of the ADC-based receiver circuit 102 is shown. As shown, the ADC-based receiver circuit 102 includes a sampling circuit 301 and a recovery circuit 302.

[0038] The sampling circuit 301 is configured to generate a sample 303 using the equalized signal 108 and a clock signal 114. As described below, in various implementations, the sampling circuit 301 may include multiple analog-to-digital converter circuits. In such cases, the sampling circuit 301 may also be configured to make a selection based on the baud rate of the serial data stream including the data symbols 107 to select a first analog-to-digital converter circuit from the multiple analog-to-digital converter circuits. The first analog-to-digital converter circuit may be configured to sample the equalized signal 108 using the clock signal 114 to generate the sample 303.

[0039] The sampling circuit 301 may also be configured to select the second analog-to-digital converter circuit among the plurality of analog-to-digital converter circuits based on the baud rate of the serial data stream including the data symbol 107. The second analog-to-digital converter circuit is configured to sample the equalized signal 108 using the clock signal 114 to generate a sampling signal 303. Note that the sampling signal 303 may include a plurality of sampled streams. In various embodiments, the resolution of the second analog-to-digital converter circuit is greater than the resolution of the first analog-to-digital converter circuit. As used and described herein, the resolution of an analog-to-digital converter circuit refers to the minimum incremental voltage that causes the digital output of the analog-to-digital converter circuit to change. In some cases, a sampling circuit such as the sampling circuit 301 may include multiple sets of analog-to-digital circuits (referred to as "sub-analog-to-digital converter circuits" or "sub-ADCs") coupled in parallel and activated in a sequential manner to increase the resolution.

[0040] The recovery circuit 302 is configured to generate a recovered data symbol 110 and control information 112 using the sampling 303. To generate the recovered data symbol 110 and control information 112, the recovery circuit 302 may be configured to perform equalization operations such as feed-forward equalization (FFE) and decision feedback equalization (DFE). In other embodiments, the recovery circuit 302 may also be configured to correct mismatches in the sampling 303 and multiply the sampling 303 by a gain factor. In various embodiments, the recovery circuit 302 may be implemented as a digital signal processor (DSP) or other suitable processing circuit.

[0041] Go to Figure 4 , a block diagram of an embodiment of the analog receiver circuit 103 is depicted. As shown, the analog receiver circuit 103 includes a splitter circuit 401 and a recovery circuit 402.

[0042] The splitter circuit 401 is configured to generate a sampling using the equalized signal 109 and the clock signal 115. In various embodiments, the splitter circuit 401 is configured to compare the equalized signal 109 with a plurality of thresholds. Such thresholds may correspond to voltage levels associated with leading or trailing effects. In various embodiments, the splitter circuit 401 may also be configured to generate one or more error signals that may be included in the control information 113. In some embodiments, the splitter circuit 401 may also be configured to perform equalization, such as decision feedback equalization (DFE).

[0043] The recovery circuit 402 is configured to generate a recovered data symbol 111 and control information 113 using a sampling signal 403. Note that the sampling signal 403 may include a sampling stream generated by the splitter circuit 401. To generate the control information 113, the recovery circuit 402 may be configured to perform phase detection. For example, in various embodiments, the recovery circuit 402 may be configured to perform Mueller-Muller phase detection or Alexander phase detection. In various embodiments, the recovery circuit 402 may be configured to perform such phase detection in the analog domain.

[0044] Turning Figure 5 , an embodiment of the sampling circuit 301 is depicted. As shown, the sampling circuit 301 includes sampling buffers 501A - 501D, sub-analog-to-digital converter circuits (referred to as "sub-ADCs 502A - 502D"), switches 503A - 503D, and a clock generation circuit 504. Note that although four sampling buffers, four switches, and four sub-ADCs are depicted in the Figure 5 embodiment, different numbers of sampling buffers, switches, and sub-ADCs may be employed in other embodiments.

[0045] The switches 503A - 503D are configured to couple the equalization signal 108 to the corresponding ones of the sampling buffers 501A - 501D using a buffer clock 505. In various embodiments, each of the buffer clocks 505 may be phase-shifted relative to each other such that only one of the switches 503A - 503D is closed at any given time. In various embodiments, the respective frequencies of the buffer clocks 505 may be based on the frequency of the recovery clock signal 512 and the number of sampling buffers and sub-ADCs included in the sampling circuit 301.

[0046] In various embodiments, the switches 503A - 503D may be implemented using one or more switched metal-oxide-semiconductor field-effect transistors (MOSFETs), fin field-effect transistors (FinFETs), gate-all-around field-effect transistors (GAAFETs), or any other suitable switching device.

[0047] Each of the sampling buffers 501A - 501D is configured to buffer the equalization signal 108 and drive the analog-to-digital converter circuits included in the corresponding ones of the sub-ADCs 502A - 502D. In various embodiments, the sampling buffers 501A - 501D may be implemented as unity-gain amplifier circuits, or any other suitable circuit configured to buffer an analog signal and provide additional drive to allow driving multiple analog-to-digital converter circuits.

[0048] Each of the sub-ADCs 502A-502D includes a plurality of analog-to-digital converter circuits, which are coupled to a corresponding one of the sample buffers 501A-501D and are configured to generate sample signals 507A-507D based on the voltage levels of the outputs of the corresponding ones of the sample buffers 501A-501D. In various embodiments, each of the sample signals 507A-507D includes a corresponding sample stream generated by the corresponding one of the sub-ADCs 502A-502D. The analog-to-digital circuits included in a given one of the sub-ADCs 502A-502D are sequentially activated by the ADC clocks 506A and 506B. In various embodiments, the number of analog-to-digital converter circuits included in a sub-ADC determines the interleaving factor of the sub-ADC.

[0049] As described above, the sub-ADCs 502A-502D can be sequentially activated. Once a particular one of the sub-ADCs 502A-502D has been activated, the included analog-to-digital converter circuits can then be sequentially activated. In such a case, the samples generated by the sub-ADCs 502A-502D can be interleaved with each other. A recovery circuit (e.g., recovery circuit 302) can be configured to correctly align the samples and retime the data to a different and possibly slower clock domain.

[0050] When a given analog-to-digital converter circuit is activated, it samples the output of its corresponding sample buffer. Once the output has been sampled, there can be a period of time (referred to as the "resolution period" or "resolving period") for the analog-to-digital converter circuit to generate a plurality of bits whose combined value corresponds to the voltage level of the sampled output. The duration of the resolution period and the number of bits generated vary depending on the type of analog-to-digital circuit employed. In various embodiments, the sum of the sampling period and the resolution period of the analog-to-digital converter circuits included in a given sub-ADC can be less than or equal to the active time of the corresponding one of the buffer clocks 505.

[0051] The individual analog-to-digital converter circuits included in the sub-ADCs 502A-502D can be implemented as flash ADCs, successive approximation ADCs, or any other suitable type of analog-to-digital converter circuit. Although only four ADCs are depicted as being included in the sub-ADCs 502A-502D, any suitable number of analog-to-digital converter circuits can be employed in other embodiments. In such a case, the clock generator circuit 504 will be configured to generate the required number of ADC clock signals.

[0052] The clock generator circuit 504 is configured to generate the buffer clocks 505 and the ADC clocks 506A and 506B. In various embodiments, the clock generator circuit 504 can be implemented using a phase-locked loop circuit, a delay-locked loop circuit, a delay circuit, or any other type of circuit suitable for generating a plurality of clock signals having different phases.

[0053] Go to Figure 6 which depicts a block diagram of an implementation of the clock circuit 104. As shown, the clock circuit 104 includes a multiplexing circuit 601, a multiplexing circuit 602, an oscillator circuit 603, an oscillator circuit 604, a logic circuit 605, a logic circuit 606, a buffer circuit 607, a multiplexing circuit 608, a clock generator circuit 609, and a buffer circuit 610.

[0054] The multiplexing circuit 601 is configured to select one of the control information 112 or the control information 113 to generate a tuning signal on the node 612. In various implementations, the multiplexing circuit 601 can be configured to use the mode signal 120 to select the one of the control information 112 or the control information 113. In a similar manner, the multiplexing circuit 602 is configured to select one of the control information 112 or the control information 113 to generate a tuning signal on the node 613.

[0055] In various implementations, the multiplexing circuits 601 and 602 can be implemented using a plurality of logic gates. In other implementations, the multiplexing circuits 601 and 602 can be implemented using a plurality of pass gate circuits coupled together in a wired-OR fashion.

[0056] The oscillator circuit 603 is configured to generate one or more clock phases on the node 614 using the tuning signal on the node 612. In various implementations, the oscillator circuit 603 can be an inductor-capacitor oscillator circuit (referred to as an “LC oscillator circuit”). In a similar manner, the oscillator circuit 604 is configured to generate one or more clock phases on the node 615 using the tuning signal on the node 613. In various implementations, the oscillator circuit 604 can be implemented as a ring oscillator circuit.

[0057] The logic circuit 605 is configured to generate one or more clock phases on the nodes 616 and 621 using the clock phase on the node 614 and the test clock 620. In various implementations, the logic circuit 605 can be configured to use the test clock 620 instead of the clock phase on the node 614 during the test mode. To generate the clock phases on the nodes 621 and 616, the logic circuit 605 can also be configured to adjust the skew of the clock phase and buffer the clock phase.

[0058] The logic circuit 606 is configured to generate the clock phase at node 618 using the clock phase at node 615 and the test clock 620. To generate the clock phase at node 618, the logic circuit 606 may also be configured to perform frequency division using at least one of the clock phases at node 615. In other embodiments, the logic circuit 606 may be configured to delay one or more of the clock phases at node 615 to generate the clock phase at node 618.

[0059] The multiplexing circuit 608 is configured to select the clock phase from node 621, node 616, or node 618 to generate the clock phase at node 619. In various embodiments, the multiplexing circuit 608 may be configured to select using the mode signal 120 or based on the baud rate of the serial data stream including the data symbol 107. In various embodiments, the multiplexing circuit 608 may be implemented using multiple logic gates, multiple pass gate circuits coupled together in a wired-OR manner, or any other suitable circuit.

[0060] The clock generator circuit 609 is configured to generate the clock signal 114 using the clock phase at node 619. In various embodiments, the number of clock signals included in the clock signal 114 may be greater than the number of clock phases at node 619. In such a case, the clock generator circuit 609 may also be configured to delay different clock phases at node 619 to generate the clock signal 114 such that the individual clock signals in the clock signal 114 have respective phase shifts.

[0061] The multiplexing circuit 610 is configured to select the clock phase from node 616 or node 618 to generate the clock signal 115. In various embodiments, the multiplexing circuit 610 may be configured to select using the mode signal 120 or based on the baud rate of the serial data stream including the data symbol 107. In various embodiments, the multiplexing circuit 610 may be implemented using multiple logic gates, multiple pass gate circuits coupled together in a wired-OR manner, or any other suitable circuit.

[0062] As described above, a receiver circuit, such as the hybrid receiver circuit 100, may be employed in a computer system. Figure 7 A block diagram of an embodiment of such a computer system is depicted. As shown, the computer system 700 includes devices 701 and 702 coupled by a communication bus 707.

[0063] Device 701 includes circuit block 703 and transmitter circuit 704. In various embodiments, device 701 can be a processor circuit, a processor core, a memory circuit, or any other suitable circuit block on an integrated circuit that can be included in a computer system. Note that although device 701 depicts only a single circuit block and a single transmitter circuit, in other embodiments, additional circuit blocks and additional transmitter circuits can be employed.

[0064] Transmitter circuit 704 is configured to serially transmit a signal corresponding to data received from circuit block 703 via communication bus 707. Such a signal can differentially encode one or more bits such that at a particular point in time, the difference between the corresponding voltage levels of lines 708A and 708B corresponds to a particular bit value. In some cases, generation of the signal can include encoding the bits prior to transmission. Note that although communication bus 707 is depicted as including two lines, any appropriate number of lines can be employed in other embodiments.

[0065] Device 702 includes receiver circuit 705 and circuit block 706. Similar to device 701, device 702 can be a processor circuit, a processor core, a memory circuit, or any other suitable circuit block configured to receive data from transmitter circuit 704. In various embodiments, receiver circuit 705 can correspond to hybrid receiver circuit 100 as Figure 1 depicted.

[0066] In some embodiments, devices 701 and 702 can be fabricated on a common integrated circuit. In other embodiments, devices 701 and 702 can be located on different integrated circuits mounted on a common substrate or circuit board. In such cases, communication bus 707 can include metal or other conductive traces on the substrate or circuit board. Although only two devices are depicted in computer system 700, any suitable number of devices can be employed in other embodiments.

[0067] Turning to Figure 8 , a flowchart depicting an embodiment of a method for operating a hybrid receiver circuit is shown. The method, which can be applied to various hybrid receiver circuits such as hybrid receiver circuit 100, begins at block 801.

[0068] The method includes generating an equalization signal (block 802) using at least one signal that encodes a serial data stream including a plurality of data symbols. In some embodiments, generating the equalization signal includes filtering the plurality of signals to generate a filtered signal. In such cases, the method can include buffering the filtered signal with a gain factor to generate the equalization signal. In various embodiments, the method can also include generating a plurality of equalization signals using the at least one signal.

[0069] The method further includes activating a particular receiver circuit among a plurality of receiver circuits based on an operating condition, where the particular receiver circuit includes at least one analog-to-digital converter circuit (block 803). In various embodiments, the plurality of receiver circuits includes a plurality of ADC-based receiver circuits and a plurality of analog receiver circuits that are activated in response to detecting a corresponding operating condition. As used and defined herein, an operating condition refers to a set of physical and electrical parameters that affect the transmission of a signal encoding a serial data stream and the characteristics of the signal itself. For example, a particular operating condition may include the baud rate of the serial data stream and the electrical characteristics (e.g., impedance) of the channel through which the serial data stream is transmitted. In various embodiments, activating a particular receiver circuit based on the baud rate of the serial data stream includes performing a comparison of the baud rate of the serial data stream with a threshold and activating the particular receiver circuit in response to determining that the baud rate of the serial data stream is greater than the threshold.

[0070] In some embodiments, the method further includes activating a different receiver circuit among the plurality of receiver circuits including an analog receiver circuit in response to detecting a different operating condition. In such a case, the method may further include: generating a second plurality of recovered data symbols by the different receiver circuit using a second equalization signal and a different set of clock signals, and generating the different set of clock signals by a clock circuit using different control information determined during the generation of the second plurality of recovered data symbols.

[0071] In other embodiments, activating includes receiving baud rate information of the serial data stream by the different receiver circuit in response to detecting the different operating condition. In various embodiments, the different receiver circuit may receive the baud rate information during an initialization or startup process associated with the communication channel. In such a case, the method may further include deactivating the particular receiver circuit in response to detecting the different operating condition.

[0072] The method further includes generating a first plurality of recovered data symbols (block 804) by the particular receiver circuit using a first equalization signal and a particular set of clock signals. In some embodiments, the particular receiver circuit includes a plurality of analog-to-digital converter circuits. In such a case, generating a first plurality of recovered data symbols by the particular receiver circuit includes: selecting a first analog-to-digital converter circuit among the plurality of analog-to-digital converter circuits based on the baud rate of the serial data stream, and sampling the first equalization signal by the first analog-to-digital converter circuit using the particular set of clock signals to generate a plurality of samples. The method may further include generating the first plurality of recovered data symbols using the plurality of samples.

[0073] In other embodiments, the method may further include selecting the second analog-to-digital converter circuit among the plurality of analog-to-digital converter circuits based on the baud rate of the serial data stream. In various embodiments, the resolution of the second analog-to-digital converter circuit is greater than the resolution of the first analog-to-digital converter circuit. In such a case, the method further includes sampling the first equalized signal by the second analog-to-digital converter circuit using the specific set of clock signals to generate a plurality of interleaved samples, and generating a first plurality of recovered data symbols using the plurality of interleaved samples.

[0074] The method further includes generating the specific set of clock signals by a clock circuit using specific control information determined during the generation of the first plurality of recovered data symbols (block 805). In some embodiments, the clock circuit may include a plurality of oscillator circuits. In such a case, generating the specific set of clock signals includes adjusting the frequency of at least one of the plurality of oscillator circuits using the specific control information. The method ends at block 806.

[0075] In Figure 9 FIG. shows a block diagram of a system-on-chip (SoC). In the illustrated embodiment, the SoC 900 includes a processor circuit 901, a memory circuit 902, an analog / mixed-signal circuit 903, and an input / output circuit 904, each of which is coupled to a communication bus 905. In various embodiments, the SoC 900 may be configured for use in a desktop computer, a server, or in a mobile computing application such as, for example, a tablet computer, a laptop computer, or a wearable computing device.

[0076] In various embodiments, the processor circuit 901 may represent a general-purpose processor that performs computing operations. For example, the processor circuit 901 may be a central processing unit (CPU) such as a microprocessor, a microcontroller, an application-specific integrated circuit (ASIC), or a field-programmable gate array (FPGA).

[0077] In various embodiments, the memory circuit 902 may include any suitable type of memory, such as, for example, dynamic random access memory (DRAM), static random access memory (SRAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), or non-volatile memory. Note that although a single memory circuit is shown in Figure 9 FIG., any suitable number of memory circuits may be employed in other embodiments.

[0078] The analog / mixed-signal circuit 903 may include a crystal oscillator circuit, a phase-locked loop (PLL) circuit, an analog-to-digital converter (ADC) circuit, and a digital-to-analog converter (DAC) circuit (all not shown). In other embodiments, the analog / mixed-signal circuit 903 may be configured to perform power management tasks by including on-chip power supplies and voltage regulators.

[0079] The input / output circuit 904 may be configured to coordinate data transfer between the SoC 900 and one or more peripheral devices. Such peripheral devices may include, but are not limited to, storage devices (e.g., storage devices based on magnetic or optical media, including hard disk drives, tape drives, CD drives, DVD drives, etc.), audio processing subsystems, or any other suitable type of peripheral device. In some embodiments, the input / output circuit 904 may be configured to implement the Universal Serial Bus (USB) protocol or a version of the IEEE 1394( ) protocol and include the hybrid receiver circuit 100 as described in the embodiments such as Figure 1 . In this case, the input / output circuit 904 may also include a mode control circuit 906 configured to generate a mode signal 120. In some cases, the mode control circuit 906 may be configured to set the value of the mode signal 120 based on the rate at which the hybrid receiver circuit 100 receives data. In other cases, the mode control circuit 906 may be configured to set the value of the mode signal 120 during initialization or boot-up operations of the SoC 900.

[0080] The input / output circuit 904 may also be configured to coordinate data transfer between the SoC 900 and one or more devices (e.g., other computing systems or integrated circuits) coupled to the SoC 900 via a network. In one embodiment, the input / output circuit 904 may be configured to perform the data processing required to implement Ethernet (IEEE 802.3) networking standards such as, for example, Gigabit Ethernet or 10 Gigabit Ethernet, although any suitable networking standard is contemplated. In some embodiments, the input / output circuit 904 may be configured to implement multiple discrete network interface ports.

[0081] Turning now to Figure 10 , various types of systems are shown that may include any of the circuits, devices, or systems described above. Systems or devices 1000 that may incorporate or otherwise utilize one or more of the techniques described herein may be used in a wide range of fields. For example, the system or device 1000 may be used as part of the hardware of a system such as a desktop computer 1010, a laptop computer 1020, a tablet computer 1030, a cellular or mobile phone 1040, or a television 1050 (or a set-top box coupled to a television).

[0082] Similarly, the disclosed components can be used in wearable device 1060, such as a smartwatch or a health monitoring device. In many embodiments, a smartwatch can implement a variety of different functions—for example, access to email, cellular service, calendar, health monitoring, etc. Wearable devices can also be designed to perform only health monitoring functions, such as monitoring a user's vital signs, performing epidemiological functions such as contact tracing, providing communication to emergency medical services, etc. Other types of devices are also envisioned, including devices worn around the neck, devices implantable in the human body, glasses or helmets designed to provide computer-generated reality experiences, such as those based on augmented reality and / or virtual reality, etc.

[0083] System or device 1000 can also be used in a variety of other environments. For example, system or device 1000 can be used in the context of a server computer system (such as a dedicated server) or on shared hardware implementing cloud-based service 1070. Further still, system or device 1000 can be implemented in a wide range of dedicated everyday devices, including devices 1080 commonly found in the home, such as refrigerators, thermostats, security cameras, etc. The interconnection of such devices is often referred to as the "Internet of Things" (IoT). The components can also be implemented in various modes of transportation. For example, system or device 1000 can be used in control systems, guidance systems, entertainment systems, etc. of various types of vehicles 1090.

[0084] Figure 10 The applications shown are merely exemplary and are not intended to limit the potential future applications of the disclosed system or device. Other exemplary applications include, but are not limited to: portable gaming devices, music players, data storage devices, unmanned aerial vehicles, etc.

[0085] Figure 11 is a block diagram showing an example of a non-transitory computer-readable storage medium storing design information of a storage circuit design. In the illustrated embodiment, semiconductor manufacturing system 1120 is configured to process design information 1115 stored on non-transitory computer-readable storage medium 1110 and manufacture integrated circuit 1130 based on the design information 1115.

[0086] The non-transitory computer-readable storage medium 1110 may include any one of various suitable types of memory devices or storage devices. The non-transitory computer-readable storage medium 1110 may be an installation medium, such as a CD-ROM, floppy disk, or magnetic tape device; computer system memory or random access memory such as DRAM, DDR RAM, SRAM, EDO RAM, Rambus RAM, etc.; non-volatile memory such as flash memory, magnetic media, e.g., a hard disk drive or optical storage device; registers, or other similar types of memory elements, etc. The non-transitory computer-readable storage medium 1110 may include other types of non-transitory memory or combinations thereof. The non-transitory computer-readable storage medium 1110 may include two or more memory media that may reside in different locations, e.g., in different computer systems connected by a network.

[0087] The design information 1115 may be specified using any of a variety of suitable computer languages, including hardware description languages such as, but not limited to: VHDL, Verilog, SystemC, SystemVerilog, RHDL, M, MyHDL, etc. The design information 1115 may be capable of being used by the semiconductor manufacturing system 1120 to fabricate at least a portion of the integrated circuit 1130. The format of the design information 1115 may be recognized by at least one semiconductor manufacturing system, such as, for example, the semiconductor manufacturing system 1120. In some embodiments, the design information 1115 may include a netlist that specifies elements of a cell library and their connectivity. One or more cell libraries used during the logic synthesis of the circuits included in the integrated circuit 1130 may also be included in the design information 1115. Such cell libraries may include information indicating device or transistor-level netlists, mask design data, characterization data, etc. of the cells included in the cell library.

[0088] In various embodiments, the integrated circuit 1130 may include one or more custom macro cells, such as memories, analog or mixed-signal circuits, etc. In such cases, the design information 1115 may include information related to the included macro cells. Such information may include, but is not limited to, a schematic capture database, mask design data, behavioral models, and device or transistor-level netlists. As used herein, the mask design data may be formatted according to the Graphic Data System (GDSII) or any other suitable format.

[0089] The semiconductor manufacturing system 1120 may include any of a variety of suitable elements configured to manufacture integrated circuits. This may include, for example, elements for depositing semiconductor materials (e.g., on a wafer that may include a mask), removing materials, shaping the deposited materials, modifying the materials (e.g., by doping materials or using ultraviolet treatment to modify the dielectric constant), etc. The semiconductor manufacturing system 1120 may also be configured to perform various tests on the manufactured circuits for proper operation.

[0090] In various embodiments, the integrated circuit 1130 is configured to operate according to a circuit design specified by the design information 1115, which may include performing any of the functions described herein. For example, the integrated circuit 1130 may include any of the various elements shown or described herein. Additionally, the integrated circuit 1130 may be configured to perform various functions described herein in connection with other components. Additionally, the functionality described herein may be performed by multiple connected integrated circuits.

[0091] As used herein, a phrase of the form "design information specifying a design of a circuit configured to..." does not imply that the circuit in question must be manufactured in order to meet the element. Instead, the phrase indicates that the design information describes a circuit that, when manufactured, will be configured to perform the indicated actions or will include the specified components.

[0092] ***

[0093] This disclosure includes references to "embodiments," which are non-limiting specific implementations of the disclosed concepts. References to "an embodiment," "one embodiment," "a particular embodiment," "some embodiments," "various embodiments," etc., do not necessarily refer to the same embodiment. A large number of possible embodiments are contemplated, including the specific embodiments detailed, as well as modified or alternative forms that fall within the spirit or scope of this disclosure. Not all of these embodiments will necessarily exhibit any or all of the potential advantages described herein.

[0094] Unless otherwise indicated, specific embodiments are not intended to limit the scope of the claims drafted based on the disclosure of the present form, even in cases where only a single example is described for a particular feature. Thus, the disclosed embodiments are intended to be illustrative rather than restrictive, without any contrary statement. This patent application is intended to cover such alternative forms, modified forms, and equivalent forms, which will be apparent to those skilled in the art who benefit from this disclosure.

[0095] Specific features, structures, or characteristics may be combined in any suitable manner consistent with this disclosure. Accordingly, this disclosure is intended to cover any feature or combination of these features (explicitly or implicitly) disclosed herein, or any generalization thereof. Thus, new claims may be made during the prosecution of this patent application (or a patent application claiming priority therefrom) directed to any such combination of features. Specifically, referring to the appended claims, the features of a dependent claim may be combined with the features of an independent claim, and features from corresponding independent claims may be combined in any appropriate manner other than only by the specific combinations recited in the appended claims.

[0096] For example, while the appended dependent claims are drafted such that each dependent claim depends from a single other claim, additional dependencies are also contemplated. In appropriate cases, it is also contemplated that a claim drafted in one statutory type (e.g., apparatus) can inspire a corresponding claim in another statutory type (e.g., method).

[0097] ***

[0098] Since this disclosure is a legal document, various terms and phrases are subject to regulatory and judicial interpretation. Notice is hereby given that the following paragraphs, as well as the definitions provided throughout this disclosure, will be used to determine how claims drafted based on this disclosure are to be interpreted.

[0099] References to singular forms such as "a," "an," and "the" are intended to mean "one or more" unless the context clearly dictates otherwise. Thus, a reference to "an item" in a claim does not exclude additional instances of that item.

[0100] The word "may" is used herein in an allowable sense (i.e., having the potential to be able to), rather than in a mandatory sense (i.e., must).

[0101] The terms "comprising" and "including" and their forms are open-ended and mean "including but not limited to."

[0102] When the term "or" is used in this disclosure with respect to a list of options, it will generally be understood to be used in an inclusive sense unless the context otherwise provides. Thus, the statement "x or y" is equivalent to "x or y, or both," covering x but not y, y but not x, and both x and y. On the other hand, phrases such as "either x or y, but not both" make it clear that "or" is used in an exclusive sense.

[0103] The phrase “w, x, y, or z, or any combination thereof” or “...at least one of w, x, y, and z” is intended to cover all possibilities of a single element up to the total number of elements in the set. For example, given the set [w, x, y, z], these phrases cover any single element in the set (e.g., w but not x, y, or z), any two elements (e.g., w and x but not y or z), any three elements (e.g., w, x, and y but not z), and all four elements. Thus, the phrase “...at least one of w, x, y, and z” refers to at least one element of the elements in the set [w, x, y, z], thereby covering all possible combinations in the list of options. This phrase should not be construed as requiring the existence of at least one instance of w, at least one instance of x, at least one instance of y, and at least one instance of z.

[0104] In the present disclosure, various “labels” may precede a noun. Unless the context otherwise provides, different labels for features (e.g., “first circuit,” “second circuit,” “specific circuit,” “given circuit,” etc.) refer to different instances of the feature. Unless otherwise specified, the labels “first,” “second,” and “third” do not imply any type of ordering (e.g., spatial, temporal, logical, etc.) when applied to a particular feature.

[0105] Within the present disclosure, different entities (which may be variously referred to as “units,” “circuits,” other components, etc.) may be described or claimed as “configured to” perform one or more tasks or operations. This expression—[entity] configured to [perform one or more tasks]—is used herein to refer to a structure (i.e., a physical thing). More specifically, this expression is used to indicate that this structure is arranged to perform one or more tasks during operation. A structure may be said to be “configured to” perform a certain task even if the structure is not currently being operated. Thus, an entity described or stated as “configured to” perform a certain task refers to a physical thing for implementing that task, such as a device, a circuit, a memory storing executable program instructions, and the like. This phrase is not used herein to refer to intangible things.

[0106] The term “configured to” is not intended to mean “configurable to.” For example, an unprogrammed FPGA would not be considered “configured to” perform a particular function. However, the unprogrammed FPGA can be “configurable to” perform that function.

[0107] The expression structure “configured to” perform one or more tasks in the appended claims is specifically intended not to invoke 35 U.S.C. § 112(f) for that claim element. If the applicant wishes to invoke part 112(f) during the application process, it will use the “means for [performing a function]” structure to phrase the claim element.

[0108] The phrase "based on" is used to describe one or more factors that influence a determination. This term does not exclude the possibility that there may be additional factors that can influence the determination. That is, the determination can be based solely on the specified factors or on the specified factors and other unspecified factors. Consider the phrase "determine A based on B". This phrase specifies that B is a factor used to determine A or that B influences the determination of A. This phrase does not exclude the possibility that the determination of A can also be based on some other factor such as C. This phrase is also intended to cover embodiments where A is determined solely based on B. As used herein, the phrase "based on" is synonymous with the phrase "at least partially based on".

[0109] The phrase "responsive to" describes one or more factors that trigger an effect. This phrase does not exclude the possibility that additional factors may influence or otherwise trigger the effect. That is, the effect can be responsive solely to these factors, or it can be responsive to the specified factors and other unspecified factors. Consider the phrase "perform A responsive to B". This phrase specifies that B is a factor that triggers the performance of A. This phrase does not exclude the possibility that the performance of A may also be responsive to some other factor, such as C. This phrase is also intended to cover embodiments where A is performed solely responsive to B.

Claims

1. A data processing apparatus, comprising: A front-end circuit configured to generate an equalization signal using at least one signal encoding a serial data stream including a plurality of data symbols; An ADC-based receiver circuit including at least one analog-to-digital converter circuit, wherein the ADC-based receiver circuit is configured to: based on the baud rate of the serial data stream, generate a first plurality of recovered data symbols using the equalization signal and a plurality of first clock signals; A first analog receiver circuit configured to: based on the baud rate of the serial data stream, generate a second plurality of recovered data symbols using the equalization signal and a plurality of second clock signals; And A clock circuit configured to: Generate the plurality of first clock signals using first control information determined during the generation of the first plurality of recovered data symbols; And Generate the plurality of second clock signals using second control information determined during the generation of the second plurality of recovered data symbols.

2. The apparatus according to claim 1, further comprising a multiplexing circuit configured to: based on the baud rate of the serial data stream, select the first plurality of recovered data symbols or the second plurality of recovered data symbols to generate a plurality of output data symbols.

3. The apparatus according to claim 1, wherein the clock circuit is further configured to: Receive baud rate information of the serial data stream; and In response to determining that the baud rate information matches a specific value, generate the plurality of first clock signals using the first control information determined during the generation of the first plurality of recovered data symbols, otherwise generate the plurality of second clock signals using the second control information determined during the generation of the second plurality of recovered data symbols.

4. The apparatus according to claim 1, wherein the ADC-based receiver circuit includes a plurality of analog-to-digital converter circuits, and wherein, to generate the first plurality of recovered data symbols, the ADC-based receiver circuit is further configured to: based on the baud rate of the serial data stream, select a first analog-to-digital converter circuit from the plurality of analog-to-digital converter circuits; Wherein the first analog-to-digital converter circuit is configured to sample the equalization signal using the plurality of first clock signals to generate a first plurality of samples; And Wherein the ADC-based receiver circuit is further configured to generate a first portion of the first plurality of recovered data symbols using the first plurality of samples.

5. The apparatus according to claim 4, wherein the ADC-based receiver circuit is further configured to: based on the baud rate of the serial data stream, select a second analog-to-digital converter circuit from the plurality of analog-to-digital converter circuits, wherein a second resolution of the second analog-to-digital converter circuit is greater than a first resolution of the first analog-to-digital converter circuit; Wherein the second analog-to-digital converter circuit is further configured to sample the equalization signal using the plurality of first clock signals to generate a second plurality of samples; and Wherein the ADC-based receiver circuit is further configured to generate a second portion of the first plurality of recovered data symbols using the second plurality of samplings.

6. The apparatus according to claim 1, further comprising a second analog receiver circuit configured to: generate a third plurality of recovered data symbols based on the baud rate of the serial data stream, using the equalization signal and a plurality of third clock signals.

7. A method for data processing, comprising: generating an equalization signal using at least one signal encoding a serial data stream including a plurality of data symbols; activating a particular receiver circuit among a plurality of receiver circuits based on an operating condition, wherein the particular receiver circuit includes at least one analog-to-digital converter circuit; generating, by the particular receiver circuit, a first plurality of recovered data symbols using the equalization signal and a particular set of clock signals; and generating, by a clock circuit, the particular set of clock signals using particular control information determined during the generation of the first plurality of recovered data symbols.

8. The method according to claim 7, wherein activating the specific receiver circuit based on the operating conditions comprises: Activating the particular receiver circuit in response to determining that the operating condition matches a particular value.

9. The method according to claim 8, further comprising: activating a different receiver circuit among a subset of the plurality of receiver circuits including a corresponding analog receiver circuit in response to determining that the operating condition has changed; generating, by the different receiver circuit, a second plurality of recovered data symbols using the equalization signal and a different set of clock signals; and generating, by the clock circuit, the different set of clock signals using different control information determined during the generation of the second plurality of recovered data symbols.

10. The method according to claim 9, wherein the operating condition includes the baud rate of the serial data stream, and wherein activating the different receiver circuit based on the operating condition includes: receiving information indicating the baud rate of the serial data stream; in response to determining that the baud rate of the serial data stream matches a given baud rate value: activating the different receiver circuit; and deactivating the particular receiver circuit.

11. The method according to claim 7, wherein the particular receiver circuit includes a plurality of analog-to-digital converter circuits, and wherein generating the first plurality of recovered data symbols by the particular receiver circuit includes: selecting a first analog-to-digital converter circuit among the plurality of analog-to-digital converter circuits based on the baud rate of the serial data stream; sampling, by the first analog-to-digital converter circuit, the equalization signal using the particular set of clock signals to generate a first plurality of samplings; and generating a first portion of the first plurality of recovered data symbols using the first plurality of samplings.

12. The method according to claim 11, further comprising: selecting a second analog-to-digital converter circuit among the plurality of analog-to-digital converter circuits based on the baud rate of the serial data stream, wherein a second resolution of the second analog-to-digital converter circuit is greater than a first resolution of the first analog-to-digital converter circuit; sampling, by the second analog-to-digital converter circuit, the equalization signal using the particular set of clock signals to generate a second plurality of samplings; and Generate a second portion of the first plurality of recovered data symbols using the second plurality of samples.

13. The method of claim 7, wherein the clock circuit includes a plurality of oscillator circuits, and wherein generating the particular set of clock signals includes adjusting a frequency of at least one of the plurality of oscillator circuits using the particular control information.

14. A data processing apparatus, comprising: A first device, the first device including a first functional circuit block, wherein the first device is configured to: Receive a serial data stream including a plurality of data symbols from the first functional circuit block; Generate a plurality of signals encoding the serial data stream; And Transmit the plurality of signals via a communication channel; And A second device, the second device including a plurality of receiver circuits, wherein the second device is configured to: Receive the plurality of signals via the communication channel; Generate an equalization signal using the plurality of signals; Activate a particular receiver circuit of the plurality of receiver circuits based on a baud rate of the serial data stream, wherein the particular receiver circuit includes at least one analog-to-digital converter circuit; Generate a first plurality of recovered data symbols by the particular receiver circuit using the equalization signal and a particular set of clock signals; And Generate the particular set of clock signals using particular control information determined during generation of the first plurality of recovered data symbols.

15. The apparatus of claim 14, wherein to activate the particular receiver circuit, the second device is further configured to activate the particular receiver circuit in response to determining that the baud rate of the serial data stream matches a given baud rate value.

16. The apparatus of claim 15, wherein the second device is further configured to: Activate a different receiver circuit of a subset of the plurality of receiver circuits including corresponding analog receiver circuits based on the baud rate of the serial data stream; Generate a second plurality of recovered data symbols by the different receiver circuit using the equalization signal and a different set of clock signals; and Generate the different set of clock signals using different control information determined during generation of the second plurality of recovered data symbols.

17. The apparatus of claim 16, wherein to activate the different receiver circuit, the second device is further configured to: in response to determining that the baud rate of the serial data stream matches a different baud rate value: Activate the different receiver circuit; and Deactivate the particular receiver circuit.

18. The apparatus of claim 17, wherein the particular receiver circuit includes a plurality of analog-to-digital converter circuits, and wherein to generate the first plurality of recovered data symbols, the particular receiver circuit is further configured to: Select a first analog-to-digital converter circuit of the plurality of analog-to-digital converter circuits based on the baud rate of the serial data stream; and Wherein the first analog-to-digital converter circuit is configured to sample the equalization signal using the particular set of clock signals to generate a first plurality of samples; and The specific receiver circuit is further configured to generate a first portion of the first plurality of recovered data symbols using the first plurality of samples.

19. The apparatus of claim 18, wherein the specific receiver circuit is further configured to select a second analog-to-digital converter circuit from the plurality of analog-to-digital converter circuits based on the baud rate of the serial data stream, wherein a second resolution of the second analog-to-digital converter circuit is greater than a first resolution of the first analog-to-digital converter circuit; and wherein the second analog-to-digital converter circuit is configured to sample the equalized signal using the specific set of clock signals to generate a second plurality of samples; and wherein the specific receiver circuit is further configured to generate a second portion of the first plurality of recovered data symbols using the second plurality of samples.

20. The apparatus of claim 14, wherein the second device includes a plurality of oscillator circuits, and wherein, in order to generate the specific set of clock signals, the second device is further configured to adjust the frequency of at least one oscillator circuit of the plurality of oscillator circuits using the specific control information.

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