Display panel and display device

Abstract

The present invention discloses a display panel and a display device, wherein the display panel includes: a plurality of pixels arranged in an array and a driving circuit; the driving circuit includes a plurality of cascaded shift register units and a plurality of switch modules electrically connected to the shift register units of each stage; each switch module includes N switch units; the switch units of the same switch module are turned on in a time-sharing manner; in the first N stages of shift register units, the signal input end of the Mth stage shift register unit is electrically connected to the start control signal end through the Mth switch unit to the Nth switch unit, and the signal input end of the Mth stage shift register unit is electrically connected to the signal output end of at least one of the first stage shift register unit to the M-1th stage shift register unit through the first switch unit to the M-1th switch unit; the signal input end of the I+Nth stage shift register unit is electrically connected to the signal output end of at least one of the Ith stage shift register unit to the I+N-1th stage shift register unit through each switch unit.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the development of display technology, people's requirements for display devices are becoming increasingly higher. For example, low power consumption, low cost, and high display quality have gradually become important factors in evaluating display device performance. Since the core of a display device is the display panel, controlling the display quality, cost, and power consumption of the display panel is key to improving display device performance.

[0003] A display panel is typically provided with a plurality of pixels arranged in an array and a driving circuit for driving the pixels to display and emit light. The driving circuit includes a plurality of cascaded shift register units. By providing a start control signal to the first-stage shift register unit, the shift register units at each stage can sequentially output the effective level of the gate drive signal, thereby scanning each row of pixels row by row, and providing data signals to each row of pixels in turn, so that each row of pixels can display and emit light according to the data signals it receives.

[0004] However, in some application scenarios, the display resolution requirements of the images presented in different display areas of the display panel are different, and the existing driving circuit cannot meet the differentiated display needs of the display panel, resulting in the display panel being unable to have the performance of low power consumption, low cost and high display quality. Summary of the Invention

[0005] Embodiments of the present invention provide a display panel and a display device, so that a driving circuit in the display panel can meet diversified display requirements, and the display panel can have the performance of low power consumption, low cost and high display quality.

[0006] In a first aspect, an embodiment of the present invention provides a display panel, the display panel comprising: a plurality of pixels arranged in an array and a driving circuit;

[0007] The driving circuit includes a plurality of cascaded shift register units and a plurality of switch modules electrically connected to the shift register units at each level; the signal output end of the shift register unit at each level is respectively connected to the pixels in each row;

[0008] Each of the switch modules includes N switch units; the N switch units are respectively a first switch unit, ..., an Nth switch unit; the switch units of the same switch module are turned on in a time-sharing manner; N is a positive integer greater than or equal to 2;

[0009] The signal input end of the first-stage shift register unit is electrically connected to the start control signal end; the signal input end of each stage of the shift register unit starting from the second-stage shift register unit is electrically connected to the switch output end of each switch unit of the same switch module;

[0010] Among the first N stages of the shift register units, a signal input terminal of the M-th stage of the shift register unit is electrically connected to the start control signal terminal through the M-th switch unit to the N-th switch unit, and a signal input terminal of the M-th stage of the shift register unit is electrically connected to a signal output terminal of at least one of the first-stage to the M-1-th shift register units through the first switch unit to the M-1-th switch unit; M is a positive integer greater than 1 and less than or equal to N;

[0011] The signal input end of the I+Nth stage shift register unit is electrically connected to the signal output end of at least one of the shift register units from the Ith stage to the I+N-1th stage through each of the switch units; I is a positive integer greater than 1.

[0012] In a second aspect, an embodiment of the present invention further provides a display device, which includes the display panel described in the first aspect.

[0013] The technical solution of the present invention is to provide a switch module corresponding to each stage of the shift register unit in the driving circuit, and each switch module includes N switch units, so that the signal input ends of the shift register units of the other stages except the first stage are electrically connected to the switch units of the same switch module, and in the first N stages of the shift register units, the signal input end of the Mth stage shift register unit is electrically connected to the start control signal end through the Mth switch unit to the Nth switch unit, and the signal input end of the Mth stage shift register unit is electrically connected to the signal output end of at least one of the first stage shift register unit to the M-1th stage shift register unit through the first switch unit to the M-1th switch unit, and the signal input end of the I+Nth stage shift register unit is electrically connected to the signal output end of at least one of the first stage shift register unit to the M-1th stage shift register unit. The signal input end is electrically connected to the signal output end of at least one of the shift register units from the first stage to the I+N-1 stage through each switching unit; in this way, the signal input ends of the shift register units at all stages except the first stage can receive at least one input signal, and by controlling the state of the switching units electrically connected to the shift register units at all stages, the input signal received by the signal input ends of the shift register units at all stages can be selectively controlled to control the effective level time of the gate drive signal output by the signal output ends of the shift register units at all stages, so that the drive circuit can meet diversified drive requirements, and thus the display panel can have the performance of low power consumption, low cost and high display quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 It is a structural schematic diagram of a display device in related technology;

[0015] Figure 2 is a structural schematic diagram of a display panel provided by an embodiment of the present invention;

[0016] Figure 3 This is a driving timing diagram of a display panel provided by an embodiment of the present invention;

[0017] Figure 4 is another driving timing diagram of a display panel provided by an embodiment of the present invention;

[0018] Figure 5 This is another driving timing diagram of a display panel provided by an embodiment of the present invention;

[0019] Figure 6 is a structural diagram of another display panel provided by an embodiment of the present invention;

[0020] Figure 7 is a structural diagram of another display panel provided by an embodiment of the present invention;

[0021] Figure 8 is a schematic structural diagram of a driving circuit provided by an embodiment of the present invention;

[0022] Figure 9 is a structural diagram of another driving circuit provided by an embodiment of the present invention;

[0023] Figure 10 is a structural diagram of another driving circuit provided by an embodiment of the present invention;

[0024] Figure 11 This is another driving timing diagram of a display panel provided by an embodiment of the present invention;

[0025] Figure 12 This is another driving timing diagram of a display panel provided by an embodiment of the present invention;

[0026] Figure 13 This is another driving timing diagram of a display panel provided by an embodiment of the present invention;

[0027] Figure 14 This is another driving timing diagram of a display panel provided by an embodiment of the present invention;

[0028] Figure 15 This is another driving timing diagram of a display panel provided by an embodiment of the present invention;

[0029] Figure 16 This is another driving timing diagram of a display panel provided by an embodiment of the present invention;

[0030] Figure 17 This is another driving timing diagram of a display panel provided by an embodiment of the present invention;

[0031] Figure 18 1 is a structural diagram of a shift register unit provided by an embodiment of the present invention;

[0032] Figure 19 1 is a schematic diagram of a film structure of a display panel provided by an embodiment of the present invention;

[0033] Figure 20 It is a structural schematic diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0034] In order to make the purpose, technical solutions and advantages of the present invention clearer, the technical solutions of the present invention will be fully described below in conjunction with the drawings in the embodiments of the present invention through specific implementation methods. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all the embodiments. Various modifications and changes can be made in the present invention without departing from the spirit or scope of the present invention, which is obvious to those skilled in the art. Therefore, the present invention is intended to cover modifications and changes of the present invention that fall within the scope of the corresponding claims (technical solutions for protection) and their equivalents.

[0035] Furthermore, the words “first”, “second” and similar terms used in the embodiments of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as “one”, “an” or “the” do not indicate a quantity limitation, but rather indicate the existence of at least one. Words such as “include” or “comprise” mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as “connect” or “connected” are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. “Up”, “down”, “left”, “right” and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly. In addition, descriptions such as “same” and “equal” involved in the embodiments of the present disclosure do not mean that the two objects are exactly the same in size or shape. Approximately the same or approximately equal within a certain error range is allowed.

[0036] It should be noted that the implementation methods provided in the embodiments of the present invention can be combined with each other if there is no contradiction.

[0037] Figure 1 It is a structural diagram of a display device of related technology, such as Figure 1As shown, the display device 002 may include a display panel 001 and a display driver chip 003 arranged in the display panel 001. The display panel 001 may include a driving circuit 011 and a plurality of pixels 012 arranged in an array. The display driver chip 003 provides corresponding control signals to the driving circuit 011 to drive each row of pixels 012 through each level of shift register units 0111 of the driving circuit 011, so that the data signals provided by the display driver chip 003 can be written into each row of pixels 012, and each row of pixels 012 can be controlled to display and emit light, so that the display panel 001 can present a corresponding display screen.

[0038] When the display device is a VR / AR display device, viewpoint rendering technology is typically applied to improve the dizziness caused by the use of the VR / AR display device. Specifically, by simulating the user's vision, a high-resolution display area and a low-resolution or medium-low-resolution display area are determined based on the area where the user's eyes are focused. The display driver chip 003 controls the data signals provided to each row of pixels 012, thereby achieving control of the display resolution of different display areas. Thus, the viewpoint rendering technology in the prior art relies entirely on the display driver chip 003 for implementation, which requires a complex circuit structure and complex logical computing capabilities within the display driver chip 003. This results in a large size and high power consumption of the display driver chip 003, which is not conducive to the low power consumption and low cost of the display device.

[0039] In addition, when the display panel 001 displays an image, the shift register units 0111 of each level of the driving circuit 011 in the display panel 001 will output the effective level of the gate driving signal in sequence to scan each row of pixels 012 row by row; this scanning method cannot meet the requirement of different display areas having different display resolutions in the viewpoint rendering technology, which is not conducive to low power consumption and low cost of the display panel.

[0040] To solve the above technical problems, an embodiment of the present invention provides a display panel, which includes: a plurality of pixels arranged in an array and a driving circuit; the driving circuit includes a plurality of cascaded shift register units and a plurality of switch modules electrically connected to the shift register units at each level; the signal output end of the shift register unit at each level is respectively connected to the pixels in each row; each switch module includes N switch units; the N switch units are respectively a first switch unit, ..., an Nth switch unit; the switch units in the same switch module are turned on in a time-sharing manner; N is a positive integer greater than or equal to 2; the signal input end of the first-stage shift register unit is electrically connected to the start control signal end; the signal input ends of the shift register units at each level starting from the second-stage shift register unit are respectively connected to the start control signal end. It is electrically connected to the switch output end of each switch unit of the same switch module; wherein, in the first N stages of shift register units, the signal input end of the M-th stage shift register unit is electrically connected to the start control signal end through the M-th switch unit to the N-th switch unit, and the signal input end of the M-th stage shift register unit is electrically connected to the signal output end of at least one of the first-stage shift register unit to the M-1-th stage shift register unit through the first switch unit to the M-1-th switch unit; M is a positive integer greater than 1 and less than or equal to N; the signal input end of the I+N-th stage shift register unit is electrically connected to the signal output end of at least one of the I-th stage shift register unit to the I+N-1-th stage shift register unit through each switch unit; I is a positive integer greater than 1.

[0041] By adopting the above technical solution, by setting switch modules corresponding to the shift register units of each stage in the driving circuit, and each switch module includes N switch units, the signal input ends of the shift register units of the other stages except the first stage are electrically connected to the switch units of the same switch module, and in the first N stages of shift register units, the signal input end of the Mth stage shift register unit is electrically connected to the start control signal end through the Mth switch unit to the Nth switch unit, and the signal input end of the Mth stage shift register unit is electrically connected to the signal output end of at least one of the first stage shift register unit to the M-1th stage shift register unit through the first switch unit to the M-1th switch unit, and the signal input end of the I+Nth stage shift register unit is electrically connected to the signal output end of at least one of the first stage shift register unit to the M-1th stage shift register unit. The signal input end is electrically connected to the signal output end of at least one of the shift register units from the first stage to the I+N-1 stage through each switching unit; in this way, the signal input ends of the shift register units at all stages except the first stage can receive at least one input signal, and by controlling the state of the switching units electrically connected to the shift register units at all stages, the input signal received by the signal input ends of the shift register units at all stages can be selectively controlled to control the effective level time of the gate drive signal output by the signal output ends of the shift register units at all stages, so that the drive circuit can meet diversified drive requirements, and thus the display panel can have the performance of low power consumption, low cost and high display quality.

[0042] The above is the core concept of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present invention. The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings.

[0043] Figure 2 is a structural diagram of a display panel provided by an embodiment of the present invention, such as Figure 2 As shown, the display panel 100 includes a driving circuit 10 and a plurality of pixels 20 arranged in an array; the driving circuit 10 includes a plurality of cascaded shift register units G; the signal output terminals OUT of the shift register units G at each level are respectively connected to the pixels 20 in each row.

[0044] Among them, the pixel 20 may include a pixel circuit P and a light-emitting element D; the pixel circuit P may be composed of active devices and / or passive devices, active devices may include transistors, etc., and passive devices may include resistors, capacitors, inductors, etc. For the convenience of description, the embodiment of the present invention takes a transistor replacing the pixel circuit P as an example to exemplify the technical solution of the embodiment of the present invention.

[0045] The signal output ends of the shift register units G at each level in the driving circuit 10 are electrically connected to the corresponding rows of pixels 20 to provide gate driving signals to the pixels 20 in each row to control the transistors of the pixel circuits P in each row of pixels 20 to be turned on or off. When the transistors in the pixel circuits P are turned on, the data signals can be controlled to be written into the pixel circuits P, so that the pixel circuits P can drive the light-emitting elements D to display light according to the written data signals, and the display light brightness of the light-emitting elements D is related to the voltage of the data signal. The light emitted by the light-emitting elements D with different display light brightness and / or colors can be combined to present a colorful picture.

[0046] It is understood that the manner in which the signal output terminals OUT of the shift register units G at each level in the drive circuit 10 are electrically connected to the pixels 20 in each row can be configured according to actual needs, and the embodiments of the present invention do not specifically limit this. In an optional embodiment, the display panel 100 may further include multiple scan lines 32 and multiple data lines 31, and at least some of the pixels 20 in the same row can be electrically connected to the same scan line 32, and at least some of the pixels 20 in the same column can be electrically connected to the same data line 31. The signal output terminal of each level of the shift register unit G can be electrically connected to a scan line 32, so that the gate drive signal output by the signal output terminal OUT of each level of the shift register unit G can be transmitted to the pixels 20 in each row through each scan line 32, so that the data signal transmitted by each data line 31 can be written into each pixel 20 accordingly.

[0047] Continue to refer Figure 2 The driving circuit 10 may also include a plurality of switch modules 11 electrically connected to the respective shift register units G; each switch module 11 includes N switch units Q; the N switch units Q are respectively the first switch unit Q1, ..., the Nth switch unit QN; the switch units Q of the same switch module 11 are turned on in time-sharing manner; N is a positive integer greater than or equal to 2. The signal input terminal IN of the first-stage shift register unit G1 is electrically connected to the start control signal terminal STV; the signal input terminals IN of the shift register units G of each stage starting from the second-stage shift register unit G2 are electrically connected to the switch output terminals of the switch units Q of the same switch module 11, and in the first N stages of shift register units G, the signal input terminal IN of the Mth stage shift register unit GM is electrically connected to the start control signal terminal STV through the Mth switch unit QM to the Nth switch unit QN, and the signal input terminal IN of the Mth stage shift register unit GM is electrically connected to the start control signal terminal STV. The terminal IN is electrically connected to the signal output terminal OUT of at least one of the first-stage shift register unit G1 to the M-1-stage shift register unit GM-1 through the first switch unit Q1 to the M-1-th switch unit QM-1; the signal input terminal IN of the I+N-th stage shift register unit GI+N is electrically connected to the signal output terminal OUT of at least one of the I-stage shift register unit GI to the I+N-1-th stage shift register unit GI+N-1 through each switch unit Q; M is a positive integer greater than 1 and less than or equal to N; I is a positive integer greater than 1.

[0048] Specifically, the shift register unit G may include a signal input terminal IN and a signal output terminal OUT, the switch unit Q may include a switch input terminal and a switch output terminal, the switch output terminal of the switch unit Q may be electrically connected to the signal input terminal IN of the I-th stage shift register unit GI, and the switch input terminal of the switch unit Q may be electrically connected to the start control signal terminal STV or the signal output terminal OUT of one of the first shift register unit G1 to the I-1-th stage shift register unit G, so that when the switch unit Q is turned on, the start control signal stv of the start control signal terminal STV or the gate drive signal Gout outputted from the signal output terminal OUT of one of the first shift register unit G1 to the I-1-th stage shift register unit G can be transmitted to the signal input terminal IN of the I-th stage shift register unit GI as the input signal of the I-th stage shift register unit GI, controlling the time when the signal output terminal OUT of the I-th stage shift register unit GI outputs the effective level of the gate drive signal GoutI.

[0049] For example, Figure 2As shown, taking N=2 as an example, the signal input terminal IN of the first-stage shift register unit G1 is electrically connected to the start control signal terminal STV, so that the first-stage shift register unit G1 can receive the start control signal stv of the start control signal terminal STV, and output the corresponding gate drive signal Gout1 under the control of the start control signal stv; in the switch module 11 correspondingly connected to the second-stage shift register unit G2, the switch input terminal of the first switch unit Q1 is electrically connected to the signal output terminal OUT of the first-stage shift register unit G1, and the switch output terminal of the first switch unit Q1 is electrically connected to the signal output terminal OUT of the second-stage shift register unit G2. The signal input terminal IN of the shift register unit G2 is electrically connected, the switch input terminal of the second switch unit Q2 is electrically connected to the start control signal terminal STV, and the switch output terminal of the second switch unit Q2 is electrically connected to the signal input terminal IN of the second-stage shift register unit G2. At this time, when the first switch unit Q1 is turned on, the gate drive signal Gout1 output by the first-stage shift register unit G1 can be used as the input signal of the second-stage shift register unit G2, and when the second switch unit Q2 is turned on, the start control signal stv of the start control terminal STV can be used as the input signal of the second-stage shift register unit G2.

[0050] Correspondingly, in the switch module 11 correspondingly connected to the third-stage shift register unit G3, the switch input terminal of the first switch unit Q1 and the switch input terminal of the second switch unit Q2 are both electrically connected to the signal output terminal OUT of the second-stage shift register unit G2, and the switch output terminal of the first switch unit Q1 and the switch output terminal of the second switch unit Q2 are both electrically connected to the signal input terminal IN of the third-stage shift register unit G3, so that when the first switch unit Q1 or the second switch unit Q2 is turned on, the gate drive signal Gout2 outputted from the signal output terminal OUT of the second-stage shift register unit G2 can be used as the gate drive signal of the third-stage shift register unit G3. Input signal; In the switch module 11 corresponding to the fourth-stage shift register unit G4, the switch input terminal of the first switch unit Q1 is electrically connected to the signal output terminal OUT of the third-stage shift register unit G3, the switch output terminal of the first switch unit Q1 is electrically connected to the signal input terminal IN of the fourth-stage shift register unit G4, the switch input terminal of the second switch unit Q2 is electrically connected to the signal output terminal OUT of the second-stage shift register unit G2, and the switch output terminal of the second switch unit Q2 is electrically connected to the signal input terminal IN of the fourth-stage shift register unit G4. At this time, when the first switch unit Q1 is turned on, the gate output of the third-stage shift register unit G3 is electrically connected. The gate drive signal Gout3 can be used as the input signal of the fourth-stage shift register unit G4, and when the second switch unit Q2 is turned on, the gate drive signal Gout2 output by the second-stage shift register unit G2 can be used as the input signal of the fourth-stage shift register unit G4; and so on, in the switch module 11 corresponding to the I+2-stage shift register unit GI+2, the switch input end of the first switch unit Q1 is electrically connected to the signal output end OUT of the I+1-stage shift register unit GI+1, the switch output end of the first switch unit Q1 is electrically connected to the signal input end IN of the I+2-stage shift register unit GI+2, and the second The switch input terminal of the switch unit Q2 is electrically connected to the signal output terminal OUT of the first-stage shift register unit GI, and the switch output terminal of the second switch unit Q2 is electrically connected to the signal input terminal IN of the (I+2)-stage shift register unit GI+2. In this case, when the first switch unit Q1 is turned on, the gate drive signal GoutI+1 output by the (I+1)-stage shift register unit GI+1 can be used as the input signal of the (I+2)-stage shift register unit GI+2, and when the second switch unit Q2 is turned on, the gate drive signal GoutI output by the first-stage shift register unit GI can be used as the input signal of the (I+2)-stage shift register unit GI+2. In this way, by controlling the state of each switch unit Q electrically connected to the signal input terminal IN of each stage of the shift register unit G, the input signal received by the signal input terminal IN of each stage of the shift register unit G can be controlled, thereby controlling the effective level time of the gate drive signal Gout output by each stage of the shift register unit G.

[0051] In an exemplary embodiment, Figure 3This is a driving timing diagram of a display panel provided by an embodiment of the present invention, combined with reference Figure 2 and Figure 3 As shown, when the first switch unit Q1 electrically connected to each stage of the shift register unit G is in the on state, the signal input terminal IN of each stage of the shift register unit G starting from the second stage shift register unit G2 can receive the gate drive signal Gout1 output by the first stage shift register unit G1 through the first switch unit Q1 electrically connected to its signal input terminal IN, the third stage shift register unit G3 receives the gate drive signal Gout2 output by the second stage shift register unit G2 through the first switch unit Q1 electrically connected to its signal input terminal IN, the fourth stage shift register unit G4 receives the gate drive signal Gout3 output by the third stage shift register unit G3 through the first switch unit Q1 electrically connected to its signal input terminal IN; ...; the (I+2) stage shift register unit G2 receives the gate drive signal Gout1 output by the first stage shift register unit G1 through the first switch unit Q1 electrically connected to its signal input terminal IN. The connected first switch unit Q1 receives the gate drive signal GoutI+1 output by the I+1th stage shift register unit GI+1, so that the effective levels of the gate drive signals Gout (Gout1, Gout2, Gout3, Gout4, ..., GoutI, GoutI+1, GoutI+2, ...) output by the shift register units G at each stage can be shifted in sequence, so that each row of pixels 20 can be scanned row by row, so that the data signal can be written into each row of pixels 20 accordingly, and since each pixel 20 electrically connected to the same data line 31 receives the effective level of the gate drive signal in a time-sharing manner, the data line 31 can transmit the data signal of each pixel 20 in a time-sharing manner, and write the data signal of each pixel 20 into each pixel 10 in a time-sharing manner, so that different data signals can be written into each pixel 20, so that the display panel 100 can present a display screen with a higher resolution.

[0052] In another exemplary embodiment, Figure 4 This is another driving timing diagram of a display panel provided by an embodiment of the present invention, with reference to Figure 2 and Figure 4When the second switch unit Q2 electrically connected to each stage of the shift register unit G is in the on state, the signal input terminals IN of the first-stage shift register unit G1 and the second-stage shift register unit G2 both receive the start control signal stv of the start control signal terminal STV, so that the first-stage shift register unit G1 and the second-stage shift register unit G2 can both output gate drive signals under the control of the start control signal stv. At this time, the gate drive signal Gout1 output by the first-stage shift register unit G1 is the same as the gate drive signal Gout2 output by the second-stage shift register unit G2. Similarly, the signal input terminals IN of the third-stage shift register unit G3 and the fourth-stage shift register unit G4 both receive the gate drive signal Gout2 output by the second-stage shift register unit G2, so that the gate drive signal Gout3 output by the third-stage shift register unit G3 is the same as the gate drive signal Gout4 output by the fourth-stage shift register unit G4. Similarly, the (I+1)th and (I+2)th shift register units G1+1 and G2+4 are both in the on state. The signal input terminals IN of the first-stage shift register unit GI+2 all receive the gate drive signal GoutI output by the first-stage shift register unit GI, so that the gate drive signal GoutI+1 output by the first-stage shift register unit GI+1 is the same as the gate drive signal GoutI+2 output by the first-stage shift register unit GI+2. In this way, the gate drive signals received by two adjacent rows of pixels 20 are the same, so that data signals can be provided to the two rows of pixels 20 at the same time, so that the two rows of pixels 20 receive the same data signal, which is beneficial to shortening the time for writing data signals to each pixel 20 in the display panel 100. At the same time, the data signals of the two adjacent rows of pixels 20 are the same, so that the display luminescence brightness of the two rows of pixels 20 is the same, thereby reducing the display resolution of the display panel 100 to a certain extent. However, since there is no need to provide data signals for each row of pixels 20, it is beneficial to simplify the driving method of the display panel 100, reduce the driving power consumption of the display panel 100, and contribute to low power consumption of the display panel 100.

[0053] In yet another exemplary embodiment, Figure 5 This is another driving timing diagram of a display panel provided by an embodiment of the present invention, combined with reference to Figure 2 and Figure 5, the display panel 100 may include a high-resolution display area and a low-resolution display area. When providing the effective level of the gate drive signal Gout to each pixel 20 in the low-resolution display area, the second switch unit Q2 can be controlled to be in a conductive state, so that two adjacent shift register units G in each stage of the shift register units G (G1, G2, G3, G4, ...) electrically connected to each pixel 20 in the low-resolution display area can simultaneously output the effective level of the gate drive signal Gout (Gout1 and Gout2, or Gout3 and Gout4, ...), thereby simultaneously writing data signals to two adjacent rows of pixels 20; and when providing the effective level of the gate drive signal Gout to each pixel 20 in the high-resolution display area, the first switch unit Q1 can be controlled to be in a conductive state, so that the shift register units G (GI, GI+1, GI+2, ...) electrically connected to each pixel 20 in the high-resolution display area can sequentially output the effective level of the gate drive signal Gout (GoutI, GoutI+1, GoutI+2, ...), thereby respectively providing different data signals to each pixel 20. In this way, by controlling the on-time of the first switch unit Q1 and the second switch unit Q2, it is possible to control the time of the effective level of the gate drive signal Gout output by each level of the shift register unit G, so that the display panel 100 can include display areas with different resolutions. In addition, there is no need to set up a complex circuit structure and complex logical operation capabilities in the display driver chip used to drive the display panel 100, and the viewpoint rendering technology can be realized. This is beneficial to reducing the size of the display driver chip, simplifying the operation logic of the display driver chip, reducing the cost of the display driver chip, and thus reducing the driving cost of the display panel 100. On the premise of ensuring that the display panel 100 has high display quality, it is beneficial to low power consumption and low cost of the display panel 100.

[0054] It is understandable that the above is only an example of N=2 to illustrate the technical solution of the embodiment of the present invention. In the embodiment of the present invention, N can be equal to 3 (such as Figure 6 As shown), 4 (as Figure 7 (as shown) or any integer greater than 4. The present invention does not impose any specific restrictions on this, provided that the core invention of the present invention can be achieved. For ease of description, the present invention uses N=4 as an example to illustrate the technical solutions of the present invention.

[0055] In this embodiment, a switch module corresponding to each stage of the shift register unit is provided in the driving circuit, and each switch module includes N switch units, so that the signal input ends of the shift register units of the other stages except the first stage are electrically connected to the switch units of the same switch module, and in the first N stages of the shift register unit, the signal input end of the M-th stage shift register unit is electrically connected to the start control signal end through the M-th switch unit to the N-th switch unit, and the signal input end of the M-th stage shift register unit is electrically connected to the signal output end of at least one of the first stage shift register unit to the M-1-th stage shift register unit through the first switch unit to the M-1-th switch unit, and the signal input end of the I+N-th stage shift register unit is electrically connected to the signal output end of at least one of the first stage shift register unit to the M-1-th stage shift register unit. The end is electrically connected to the signal output end of at least one of the shift register units from the first stage to the I+N-1 stage through each switching unit; in this way, the signal input ends of the shift register units at all stages except the first stage can receive at least one input signal, and by controlling the state of the switching units electrically connected to the shift register units at all stages, the input signal received by the signal input ends of the shift register units at all stages can be selectively controlled to control the effective level time of the gate drive signal output by the signal output ends of the shift register units at all stages, so that the drive circuit can meet diversified drive requirements, and thus the display panel can have the performance of low power consumption, low cost and high display quality.

[0056] Optionally, the signal input end of the J-th shift register unit is electrically connected to the signal output end of the S-th shift register unit through the K-th switch unit; wherein, J, K and S are all positive integers, J>S, J>K, K≤N; wherein, when J / K≠[J / K], S=[J / K]*K; or, when J / K=[J / K], S=(J / K-1)*K.

[0057] For example, Figure 7As shown, taking N=4 as an example, when J=2, K can be equal to 1, S=1, that is, the signal input terminal IN of the second-stage shift register unit G2 can be electrically connected to the signal output terminal OUT of the first-stage shift register unit G1 through the first switch unit Q1; when J=3, K can be equal to 1 or 2, S=2, that is, the signal input terminal IN of the third-stage shift register unit G3 is electrically connected to the signal output terminal OUT of the second-stage shift register unit G2 through the first switch unit Q1, and the signal input terminal IN of the third-stage shift register unit G3 is also electrically connected to the signal output terminal OUT of the second-stage shift register unit G2 through the second switch unit Q2; when J=4, K can be equal to 1, 2 and 3, and S=3 when K=1 or 3, and S=2 when K=2, that is, The signal input terminal IN of the fourth-stage shift register unit G4 is electrically connected to the signal output terminal OUT of the third-stage shift register unit G3 through the first switch unit Q1 and the third switch unit Q3, and the signal input terminal IN of the fourth-stage shift register unit G4 is also electrically connected to the signal output terminal OUT of the second-stage shift register unit G2 through the second switch unit Q2; when J=5, K can be equal to 1, 2, 3, and 4, and when K=1, 2, or 4, S=4, and when K=3, S=3, that is, the signal input terminal IN of the fifth-stage shift register unit G5 is electrically connected to the signal output terminal OUT of the fourth-stage shift register unit G4 through the first switch unit Q1, the second switch unit Q2, and the fourth switch unit Q4, and the signal input terminal IN of the fifth-stage shift register unit G5 is electrically connected to the signal output terminal OUT of the fourth-stage shift register unit G4. The signal input terminal IN of the sixth-stage shift register unit G6 is electrically connected to the signal output terminal OUT of the fifth-stage shift register unit G5 through the first switch unit Q1, and the signal input terminal IN of the sixth-stage shift register unit G6 is also electrically connected to the signal output terminal OUT of the fourth-stage shift register unit G4 through the second switch unit Q2 and the fourth switch unit Q4. The signal input terminal IN of the sixth-stage shift register unit G6 is also electrically connected to the signal output terminal OUT of the third-stage shift register unit G3 through the third switch unit Q3. The output end OUT is electrically connected; by analogy, when J is less than or equal to N, except for the first-stage shift register unit G1, the signal input ends IN of the other stages of the shift register unit G can receive at least two input signals through different switch units Q; when J is greater than or equal to N, the signal input end IN of each stage of the shift register unit G can receive one, two, three or more input signals through different switch units Q; at this time, the gate drive signal Gout output by the shift register unit G at each stage can be controlled by controlling the state of the switch unit electrically connected to the shift register unit G at each stage, so that the display panel 100 meets the display requirements of different display resolutions while ensuring that the display panel 100 has lower power consumption and cost.

[0058] In an alternative embodiment, continue to refer to Figure 7 , each K-th switch unit QK electrically connected to the signal output terminal OUT of the same shift register unit G is connected to the signal output terminal OUT of the shift register unit G in parallel.

[0059] For example, taking K=4 as an example, the signal output terminal OUT of the fourth-stage shift register unit G4 is electrically connected to four fourth switch units Q4, and the four fourth switch units Q4 are respectively the first fourth switch unit Q41, the second fourth switch unit Q42, the third fourth switch unit Q43 and the fourth fourth switch unit Q44. At this time, the switch input terminal of the first fourth switch unit Q41, the switch input terminal of the second fourth switch unit Q42, the switch input terminal of the third fourth switch unit Q43 and the switch input terminal of the fourth fourth switch unit Q44 are respectively electrically connected to the signal output terminal OUT of the fourth-stage shift register unit G4 through different connecting lines, the switch output terminal of the first fourth switch unit Q41 is electrically connected to the signal input terminal IN of the fifth-stage shift register unit G5, the switch output terminal of the second fourth switch unit Q42 is electrically connected to the signal input terminal IN of the first fourth switch unit Q41, and the switch output terminal of the second fourth switch unit Q42 is electrically connected to the signal input terminal IN of the first fourth switch unit Q41. The signal input terminal IN of the sixth-stage shift register unit G6 is electrically connected, the switch output terminal of the third and fourth switch units Q43 is electrically connected to the signal input terminal IN of the seventh-stage shift register unit G7, and the switch output terminal of the fourth and fourth switch units Q44 is electrically connected to the signal input terminal IN of the eighth-stage shift register unit G8; in this way, when the fourth switch unit Q4 is in the on state, the input signals received by the signal input terminals IN of the fifth-stage shift register unit G5, the sixth-stage shift register unit G6, the seventh-stage shift register unit G7 and the eighth-stage shift register unit G8 do not interfere with each other, and each connecting line has a smaller load, which is beneficial to the accuracy of signal transmission, thereby facilitating the improvement of the accuracy of the signals output by the shift register units G at each stage in the driving circuit 10, and further facilitating the improvement of the picture display accuracy of the display panel 100.

[0060] In another alternative embodiment, Figure 8 FIG. 1 is a schematic diagram of a driving circuit provided by an embodiment of the present invention. Figure 8 As shown, each K-th switch unit QK electrically connected to the signal output terminal OUT of the same shift register unit G is connected in series to the signal output terminal OUT of the shift register unit G in sequence.

[0061] Exemplarily, taking K=4 as an example, the four fourth switch units Q4 electrically connected to the signal output terminal OUT of the fourth-stage shift register unit G4 are respectively the first fourth switch unit Q41, the second fourth switch unit Q42, the third fourth switch unit Q43 and the fourth fourth switch unit Q44. Among them, the switch input terminal of the first to fourth switch unit Q41 is electrically connected to the signal output terminal OUT of the fourth-stage shift register unit G4, the switch output terminal of the first to fourth switch unit Q41 is electrically connected to the switch input terminal of the second to fourth switch unit Q42 and the signal input terminal IN of the fifth-stage shift register unit G5, the switch output terminal of the second to fourth switch unit Q42 is electrically connected to the switch input terminal of the third to fourth switch unit Q43 and the signal input terminal IN of the sixth-stage shift register unit G6, the switch output terminal of the third to fourth switch unit Q43 is electrically connected to the switch input terminal of the fourth to fourth switch unit Q44 and the signal input terminal IN of the seventh-stage shift register unit G7, and the switch output terminal of the fourth to fourth switch unit Q44 is electrically connected to the signal input terminal IN of the eighth-stage shift register unit G8; when each of the fourth switch units Q4 is in the on state, the fifth-stage shift register The register unit G5 can receive the gate drive signal Gout4 output by the fourth-stage shift register unit G4 through the first-fourth switch unit Q41, the sixth-stage shift register unit G6 can receive the gate drive signal Gout4 output by the fourth-stage shift register unit G4 through the second-fourth switch unit Q42 and the first-fourth switch unit Q41 in sequence, the seventh-stage shift register unit G7 can receive the gate drive signal Gout4 output by the fourth-stage shift register unit G4 through the third-fourth switch unit Q43, the second-fourth switch unit Q42 and the first-fourth switch unit Q41 in sequence, and the eighth-stage shift register unit G8 can receive the gate drive signal Gout4 output by the fourth-stage shift register unit G4 through the fourth-fourth switch unit Q44, the third-fourth switch unit Q43, the second-fourth switch unit Q42 and the first-fourth switch unit Q41 in sequence. This arrangement can reduce the number of connection lines used to connect the fourth switch unit Q4 and the signal output terminal OUT of the fourth shift register unit G4, so that the fourth switch units Q4 can be arranged sequentially along the first direction Y. This helps to reduce the size occupied by the switch unit Q in the second direction X, thereby contributing to a narrow frame of the display panel. The first direction X intersects with the second direction Y.

[0062] Optional, Figure 9 is a schematic structural diagram of another driving circuit provided by an embodiment of the present invention, Figure 10 This is a schematic diagram of the structure of another driving circuit provided by an embodiment of the present invention, referring to Figure 9 or Figure 10The switching unit Q may include a switching transistor; the first pole of the switching transistor is the switching input end of the switching unit Q, the second pole of the switching transistor is the switching output end of the switching unit Q, and the gate of the switching transistor receives a switching control signal SW; each switching transistor of the same switching module 11 receives a different switching control signal SW.

[0063] For example, Figure 9 As shown, taking each switch module 11 including four switch units as an example, among the four switch units electrically connected to the signal input terminal IN of the fifth-stage shift register unit G5, the first electrode of the switching transistor of the first switch unit Q1, the first electrode of the switching transistor of the second switch unit Q2, and the first electrode of the switching transistor of the fourth switch unit Q4 are all electrically connected to the signal output terminal Gout of the fourth-stage shift register unit G4, the first electrode of the switching transistor of the third switch unit Q3 is electrically connected to the signal output terminal Gout of the third-stage shift register unit G3, the second electrode of the switching transistor of the first switch unit Q1, the second electrode of the switching transistor of the second switch unit Q2, the second electrode of the switching transistor of the third switch unit Q3, and the second electrode of the switching transistor of the fourth switch unit Q4 are all electrically connected to the signal input terminal IN of the fifth-stage shift register unit G5, the gate of the switching transistor of the first switch unit Q1 receives the first switching control signal SW1, and the gate of the switching transistor of the second switch unit Q1 receives the first switching control signal SW1. The gate of the switching transistor of the switching unit Q2 receives the second switching control signal SW2, the gate of the switching transistor of the third switching unit Q3 receives the third switching control signal SW3, and the gate of the switching transistor of the fourth switching unit Q4 receives the fourth switching control signal SW4; at this time, the first switching control signal SW1 can control the switching transistor of the first switching unit Q1 to be turned on or off; the second switching control signal SW2 can control the switching transistor of the second switching unit Q2 to be turned on or off; the third switching control signal SW3 can control the switching transistor of the third switching unit Q3 to be turned on or off; the fourth switching control signal SW4 can control the switching transistor of the first switching unit Q4 to be turned on or off; in this way, different switching control signals SW are used to control the switching transistors of different switching units in the same switching module 11 to be turned on or off, so that each switching transistor can be turned on in a time-sharing manner, so that the display resolution of the display panel can be selected as needed.

[0064] Optional, continue to Figure 9 or Figure 10 The display panel may further include N switch signal transmission lines 40; the switch signal transmission lines 40 are used to transmit the switch control signal SW; the gates of the switch transistors of each switch unit Q of the same switch module 11 are electrically connected to different switch signal transmission lines 40; the gates of the switch transistors of the Kth switch unit QK electrically connected to each level of the shift register unit G are electrically connected to the same switch signal transmission line; K≤N, and K is a positive integer.

[0065] Among them, the gates of the switching transistors of the K-th switching unit QK electrically connected to the shift register units G of each stage are electrically connected to the same switching signal transmission line, which can be understood as follows: the gates of the switching transistors of the first switching unit Q1 electrically connected to the second-stage shift register unit G2, the gates of the switching transistors of the first switching unit Q1 electrically connected to the third-stage shift register unit G3, ..., the gates of the switching transistors of the first switching unit Q1 electrically connected to the I+N-stage shift register unit GI+N, ... are all electrically connected to the first switching control signal line 41 to be turned on or off under the control of the first switching control signal SW1 transmitted by the first switching control signal line 41; the gates of the switching transistors of the second switching unit Q2 electrically connected to the second-stage shift register unit G2, the gates of the switching transistors of the second switching unit Q2 electrically connected to the third-stage shift register unit G3, ..., the gates of the switching transistors of the second switching unit Q2 electrically connected to the I+N-stage shift register unit GI+N, ... are all electrically connected to the second switching control signal line 42 to be turned on or off under the control of the first switching control signal SW1 transmitted by the first switching control signal line 41. The first and second switching registers G1 and G2 are electrically connected to the first and second shift registers G2, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3, G3

[0066] In this arrangement, the gates of the transistors of the Kth switch unit QK electrically connected to each level of the shift register unit G are electrically connected to the same switch signal transmission line 40, so that the transistors of each Kth switch unit QK can be turned on or off at the same time; at the same time, when the gates of the switching transistors of each switch unit Q of the same switch module 11 are respectively electrically connected to different switch signal transmission lines 40, the types of the switching transistors of each switch unit Q in the same switch module 11 can be the same or different, so that the switching control signals SW transmitted by each switch signal transmission line 40 can be respectively provided to the gates of the switching transistors of different switch units Q, so that the states of the switching transistors of each switch unit Q do not interfere with each other, and the states of the switching transistors in each switch unit Q can be accurately controlled, thereby improving the accuracy of the gate drive signal Gout output by each level of the shift register unit G in the drive circuit 10.

[0067] It can be understood that when the switch control signal SW transmitted by the switch signal transmission line 40 is at a valid level, the switch transistor in the switch unit Q can be controlled to be turned on, and when the switch control signal SW transmitted by the switch signal transmission line 40 is at an invalid level, the switch transistor in the switch unit Q can be controlled to be turned off; wherein, one of the valid level and the invalid level can be a high level, and the other can be a low level; for example, when the switch transistor in the switch unit Q is an N-type transistor, the valid level of the switch control signal is a high level, and the invalid level is a low level; and when the switch transistor in the switch unit Q is a P-type transistor, the valid level of the switch control signal is a low level, and the invalid level is a high level. In the embodiment of the present invention, the type of the switch transistor can be set according to actual needs, and the embodiment of the present invention does not specifically limit this. For ease of description, the embodiment of the present invention takes the switch transistor as a P-type transistor as an example to illustrate the technical solution of the embodiment of the present invention.

[0068] In an optional embodiment, the display mode of the display panel includes a first mode; during the display time of one frame of the image in the first mode, one of the first to Nth switch units is controlled to be in an on state.

[0069] It can be understood that the display time of a frame of picture can be equal to the time period between the moment when the first row of pixels starts writing data signals and the moment when the first row of pixels starts writing data signals next time. During this time period, data signals need to be written to each row of pixels. Therefore, within the display time of a frame of picture, each level of shift register unit will output the effective level of the gate drive signal to refresh the data signal of each row of pixels.

[0070] Specifically, when the display panel is displaying an image, a data signal refresh mode for each row of pixels can be selected as needed. For example, the data signal of each row of pixels can be refreshed row by row. At this time, the effective level of the gate drive signal needs to be provided to each row of pixels in turn. Therefore, the first switch unit electrically connected to each shift register unit can be controlled to be in a conductive state, such as Figure 11 As shown, during the one-frame picture display time of the first mode, the first switch control signal SW1 received by the switch transistor of the first switch unit is at a valid level, and the switch control signals (SW2, SW3, and SW4) received by the switch transistors of the other switch units are at an invalid level, so that the first switch unit is in an on state, and the gate drive signal output by the previous shift register unit in the two adjacent shift register units can be used as the input signal received by the next shift register unit, and the shift register units of each stage in the driving circuit sequentially output the valid levels of the gate drive signals (Gout1, Gout2, Gout3, Gout4, ..., GoutI, GoutI+1, GoutI+2, GoutI+3, GoutI+4, ...) to realize row-by-row scanning of each row of pixels, so that the data signals of each row of pixels are refreshed sequentially.

[0071] In other exemplary embodiments, when the display panel is displaying an image, the data signals of two adjacent rows of pixels may be refreshed at the same time. Figure 12 As shown, the second switch control signal SW2 can be controlled to be at an effective level, and the switch control signals (SW1, SW3 and SW4) received by the switch transistors of the other switch units are at an ineffective level, so that the second switch unit is in a conducting state. The two adjacent shift register units can receive the same input signal. In the driving circuit, each two adjacent shift register units can constitute a shift register unit group. The gate drive signals output by the shift register units of each level in the same shift register unit group are the same. For example, the first-stage shift register unit and the second-stage shift register unit constitute a shift register unit group, and the third-stage shift register unit and the fourth-stage shift register unit constitute a shift register unit group. The bit register units constitute a shift register unit group, so that the gate drive signal Gout1 output by the first-stage shift register unit is the same as the gate drive signal Gout2 output by the second-stage shift register unit, and the gate drive signal Gout1 output by the third-stage shift register unit is the same as the gate drive signal Gout2 output by the fourth-stage shift register unit. At the same time, the effective levels of the gate drive signals (Gout1, Gout3, ..., GoutI, GoutI+1, GoutI+3, ...) output by each stage of the shift register unit group are shifted in sequence, so that the data signals of two adjacent rows of pixels are refreshed simultaneously.

[0072] It should be noted that the above is only an example of the technical solution of the embodiment of the present invention, which is exemplarily described by taking the data signals of each pixel in the display panel being refreshed row by row and the data signals of two adjacent rows of pixels being refreshed simultaneously. In the embodiment of the present invention, Figure 13 As shown, the data signals of three rows of pixels can also be refreshed at the same time, or, as shown Figure 14 As shown, the data signals of four rows of pixels are refreshed at the same time. The specific principle can be referred to the above description and will not be repeated here.

[0073] Optionally, the display mode of the display panel may also include a second mode; the display time of a frame of picture in the second mode includes at least one first stage and at least one second stage; in each of the first stage and the second stage, one of the first to Nth switch units is controlled to be turned on, and the switch unit turned on in the first stage is different from the switch unit turned on in the second stage.

[0074] It can be understood that the display time of one frame of picture in the second mode includes at least one first stage and at least one second stage, that is, the number of first stages can be one, two or more, and similarly, the data of the second stage can also be one, two or more, and the number of first stages and the number of second stages can be the same or different, and the embodiment of the present invention does not make specific limitations on this; at the same time, the first stage and the second stage can be performed alternately, or the first stage and the second stage can also exist in other forms, and the embodiment of the present invention does not make specific limitations on this.

[0075] For example, Figure 9 Take the driving circuit shown as an example, Figure 15 This is another driving timing diagram of a driving circuit provided by an embodiment of the present invention, combined with reference to Figure 9 and Figure 15In the second mode, the display time of one frame of the display panel includes a first stage t11 and a second stage t12. In the first stage t11, the fourth switch control signal SW4 is at an effective level, which can control the fourth switch unit Q4 to be in a conductive state, so that the adjacent four-stage shift register unit can simultaneously output the effective level of the gate drive signal; until the first-stage shift register unit GI outputs the effective level of the gate drive signal GoutI, the second stage t12 is entered, and the fourth switch control signal SW4 can be controlled to be inactive, and the first switch control signal SW1 is changed to an effective level, so that the first switch unit Q1 is turned on, and starting from the I+1-stage shift register unit GI+1, each stage of the shift register unit G can sequentially output the effective level of the gate drive signal (GoutI+1, GoutI+2, GoutI+3, GoutI+4, ...); at this time, the display panel may include two display areas with different driving modes, wherein, in the display area where the pixels electrically connected to the first-stage shift register unit G1 to the first-stage shift register unit GI are located, the adjacent four rows of pixels can be simultaneously The refresh of the data signal makes the data signals written into the four adjacent rows of pixels in the same column the same, so that the picture displayed in the display area has a lower resolution; and in the display area where the pixels electrically connected to the I+1-th level shift register unit GI+1 to the last level shift register unit are located, the data signals of the pixels can be refreshed row by row, so that the data signals written into each pixel can be different, thereby making the picture displayed in the display area have a higher resolution; in this way, in the second mode, the picture displayed by the display panel can be composed of a high-resolution display picture and a low-resolution display picture. At this time, the area where the higher-resolution display picture is located can be the area where the human eye focuses, and the area where the lower-resolution display picture is located can be other areas outside the area where the human eye focuses, so that by controlling the conduction state of each switch unit at different stages, the display panel can realize viewpoint rendering technology, and thus, on the premise of being able to improve the display effect of the display panel, it is beneficial to low power consumption and low cost of the display panel.

[0076] Optionally, the display mode of the display panel includes an Xth mode; the display time of a frame of picture in the Xth mode includes at least one first stage, at least one second stage,..., at least one Xth stage; in each stage from the first stage to the Xth stage, one switch unit from the first switch unit to the Nth switch unit is controlled to be in an on state, and the switch units that are turned on in each stage from the first stage to the Xth stage are different; X is a positive integer greater than or equal to 3.

[0077] In an exemplary embodiment, in conjunction with reference Figure 9 and Figure 16As shown, taking X=3 as an example, in the third mode, the display time of one frame of the display panel may include a first stage t21, a second stage t22 and a third stage t23.In the first phase t21, the fourth switch control signal SW4 is at an active level, which can control the fourth switch unit Q4 to be in a conducting state, so that the four adjacent shift register units can simultaneously output the active level of the gate drive signal. After the first-stage shift register unit GI outputs the active level of the gate drive signal GoutI, the second phase t22 is entered, in which the fourth switch control signal SW4 can be controlled to be at an inactive level, and the first switch control signal SW1 is at an active level, so that the first switch unit Q1 is turned on, and the (I+1)-stage shift register unit GI+1 to the (S)-stage shift register unit GS can sequentially output the gate drive signals (GoutI+1, GoutI+2, GoutI+3, GoutI+4, ... , GoutS); after the S-th stage shift register unit GS outputs the effective level of the gate drive signal GoutS, the third stage t23 can be entered, and the first switch control signal SW1 can be controlled to become an invalid level, and the third switch control signal SW3 can be controlled to become an effective level, so that the third switch unit Q3 is turned on, so that in the shift register units G starting from the S+1-th stage shift register unit GS+1, the adjacent three-stage shift register units G can simultaneously output gate drive signals, for example, the gate drive signals GoutS+1, GoutS+2 and GoutS+3 are the same; at this time, the display panel may include three display areas with different driving modes, wherein the first stage shift register unit G1 to the I-th stage shift register unit G1 are respectively In the display area where the pixels electrically connected to the bit register unit GI are located, the data signals of four adjacent rows of pixels can be refreshed at the same time, so that the data signals written into the four adjacent rows of pixels in the same column are the same, so that the picture displayed in the display area has a lower resolution; and in the display area where the pixels electrically connected to the I+1-th shift register unit GI+1 to the S-th shift register unit GS are located, the data signals of the pixels can be refreshed row by row, so that the data signals written into each pixel can be different, thereby making the picture displayed in the display area have a higher resolution; in the display area where the pixels electrically connected to the S+1-th shift register unit GS+1 to the last shift register unit are located, the data signals of three adjacent rows of pixels can be refreshed at the same time , so that the data signals of three adjacent pixels located in the same column can be the same, so that the picture displayed in the display area has medium and low resolution; like this, in the third mode, the picture displayed by the display panel can be composed of a high-resolution display picture, a medium-low resolution display picture and a low-resolution display picture. At this time, the area where the high-resolution display picture is located can be the area where the human eye focuses, and the areas where the medium-low resolution display picture and the low-resolution display picture are located can be other areas outside the area where the human eye focuses. Therefore, by controlling the conduction state of each switch unit at different stages, the display panel can realize viewpoint rendering technology, and thus, on the premise of being able to improve the display effect of the display panel, it is beneficial to low power consumption and low cost of the display panel.

[0078] In another exemplary embodiment, in conjunction with reference Figure 9 and Figure 17As shown, taking X=4 as an example, in the fourth mode, the display time of one frame of the display panel may include the first stage t31, the second stage t32, the third stage t33 and the fourth stage t34. In the first stage t31, the fourth switch control signal SW4 is at an effective level, which can control the fourth switch unit Q4 to be in a conductive state, so that the adjacent four-stage shift register unit can simultaneously output the effective level of the gate drive signal; until the I-stage shift register unit GI outputs the effective level of the gate drive signal GoutI, it enters the second stage t32, which can control the fourth switch control signal SW4 to be at an inactive level, and the first switch control signal SW1 to be at an effective level, so that the first switch unit Q1 is conductive, and the I+1-stage shift register unit GI+1 to the S-stage shift register unit GS can output the gate drive signals (GoutI+1, GoutI+2, GooutI+3) in sequence. After the S-th shift register unit GS outputs the effective level of the gate drive signal GoutS, the third stage t33 can be entered, and the first switch control signal SW1 can be controlled to become an invalid level, and the third switch control signal SW3 can be controlled to become an effective level, so that the third switch unit Q3 is turned on, so that the three adjacent shift register units G in the S+1-th to J-th shift register units GJ can output gate drive signals at the same time, for example, the gate drive signals GoutS+1, GoutS+2 and GoutS+3 are the same, and the gate drive signals GoutS-2, The effective levels of GoutS+1 and GoutS+4 are shifted in sequence; after the J-th shift register unit GJ outputs the effective level of the gate drive signal GoutJ, the fourth stage t34 can be entered, and the third switch control signal SW3 can be controlled to become an invalid level, and the second switch control signal SW2 can be controlled to become an effective level, so that the second switch unit Q2 is turned on, so that in each level of shift register unit starting from the J+1-th level shift register unit GS+1, the adjacent two-level shift register unit G can output the gate drive signal at the same time, for example, the gate drive signal GoutJ+1 is the same as GoutJ+2, and the gate drive signal GoutJ+3 is the same as GoutS+4; this When the display panel is configured as shown in FIG5 , the display panel may include four display areas with different driving modes. In the display area where the pixels electrically connected to the first-stage shift register unit G1 to the first-stage shift register unit GI are located, the data signals of four adjacent rows of pixels can be refreshed simultaneously, so that the data signals written into the four adjacent rows of pixels in the same column are the same, so that the image displayed in the display area has a lower resolution. In the display area where the pixels electrically connected to the first-stage shift register unit GI+1 to the third-stage shift register unit GS are located, the data signals of the pixels can be refreshed row by row, so that the data signals written into each pixel can be different, so that the image displayed in the display area has a higher resolution.In the display area where the pixels electrically connected to the S+1th-stage shift register unit GS+1 to the Jth-stage shift register unit GJ are located, the data signals of three adjacent rows of pixels can be refreshed simultaneously, so that the data signals of three adjacent pixels in the same column can be the same, thereby making the image displayed in this display area have a medium-low resolution; in the display area where the pixels electrically connected to the J+1th-stage shift register unit GJ+1 to the last-stage shift register unit are located, the data signals of two adjacent rows of pixels can be refreshed simultaneously, so that the data signals of two adjacent pixels in the same column can be the same, thereby making the image displayed in this display area have a medium-high resolution; Thus, in the fourth mode, the images displayed by the display panel can be composed of a high-resolution display image, a medium-high-resolution display image, a medium-low-resolution display image, and a low-resolution display image. In this case, the area where the high-resolution display image is located can be the area where the human eye focuses, while the areas where the medium-high-resolution display image, the medium-low-resolution display image, and the low-resolution display image are located can be areas other than the area where the human eye focuses. Therefore, by controlling the conduction state of each switching unit at different stages, the display panel can implement viewpoint rendering technology, thereby improving the display quality of the display panel while facilitating low power consumption and low cost of the display panel.

[0079] It should be noted that the above description only exemplarily illustrates the technical solution of the embodiment of the present invention by taking X=3 and 4 as examples. In the embodiment of the present invention, X can also be any other positive integer greater than 3 and less than or equal to N, and the embodiment of the present invention does not make any specific limitation on this.

[0080] It should also be noted that the above description is only exemplified by taking the example that the display time of one frame of picture includes a first stage, a second stage, a third stage and a fourth stage. In the embodiment of the present invention, no matter which display mode the display panel adopts, the number of the same stages can be set to one, two or more according to actual needs, and the number of each stage can be the same or different. The embodiment of the present invention will not list them one by one here. On the premise that the core invention point of the embodiment of the present invention can be achieved, the embodiment of the present invention does not make specific limitations on this.

[0081] It can be understood that the above is only an illustrative description of the display mode of the display panel of the embodiment of the present invention. In the embodiment of the present invention, the corresponding conductive switch units in each stage under different display modes of the display panel can be set according to actual needs, and they can be combined in any way. For example, in the second mode, the conductive switch units in the first stage and the second stage can be the first switch unit and the second switch unit respectively, or the conductive switch units in the first stage and the second stage can be the second switch unit and the third switch unit respectively, or the conductive switch units in the first stage and the second stage can be the third switch unit and the fourth switch unit respectively. On the premise that the core invention point of the embodiment of the present invention can be achieved, the embodiment of the present invention does not make specific limitations on this.

[0082] It can also be understood that the specific structure of the shift register units at each level in the embodiment of the present invention can be set according to actual needs. On the premise that the shift register units at each level can control the gate drive signal output by their signal output ends according to the input signal received by their signal input ends, the embodiment of the present invention does not make specific limitations on this.

[0083] In an optional embodiment, Figure 18 : is a structural diagram of a shift register unit provided by an embodiment of the present invention, such as Figure 18 As shown, the shift register unit G includes a signal input module 101 and a signal output module 102; in the same shift register unit G: the signal input module 101 controls the gate drive signal provided to the signal output module 102 in response to at least the input signal of the signal input terminal IN; the signal output module 102 is used to adjust the polarity and / or amplitude of the gate drive signal, and provide the adjusted gate drive signal to the signal output terminal OUT.

[0084] Specifically, the signal input module 101 can be electrically connected to the signal input terminal IN and the signal output module 102 respectively, so that the signal input module 101 can latch the input signal of the signal input terminal IN, and shift the input signal of the signal input terminal IN and provide it to the signal output module 102 as a gate drive signal; the signal output module 102 can also be electrically connected to the signal output terminal OUT, so that the signal output module 102 can simultaneously adjust the amplitude and polarity of the gate drive signal it receives, or only adjust one of the polarity and amplitude of the gate drive signal it receives and then output the gate drive signal to the signal output terminal OUT, so that the gate drive signal can control the transistor in the pixel to accurately turn on or off.

[0085] Among them, the polarity of the gate drive signal output by the signal output terminal OUT is related to the size and type of the transistor in the pixel. For the case where the transistor in the pixel is N-type, the gate drive signal output by the signal output terminal OUT is positive polarity, that is, when the gate drive signal is at a valid level, it can control the transistor in the pixel to be turned on; the gate drive signal output by the signal output terminal OUT is negative polarity, that is, when the gate drive signal is at an invalid level, it can control the transistor in the pixel to be turned off; conversely, for the case where the transistor in the pixel is P-type, the gate drive signal output by the signal output terminal OUT is negative polarity, which can control the transistor in the pixel to be turned on; the gate drive signal output by the signal output terminal OUT is positive polarity, which can control the transistor in the pixel to be turned off.

[0086] In an exemplary embodiment, the signal input module 101 may include a latch, the input end of the latch may be electrically connected to the signal input end IN, the clock end of the latch may be electrically connected to the clock signal end CK, and the output end of the latch may be electrically connected to the signal output module 102; in this way, the latch may latch the input signal of the signal input end IN according to the clock signal of the clock signal end CK, and output the gate drive signal to the signal output module 102 after shifting the latch signal.

[0087] The latch of the signal input module 101 can be composed of a first inverter U11, a second inverter U12, a first tri-state gate U13 and a second tri-state gate U14; wherein the input end of the first inverter U11 is electrically connected to the clock signal end CK, the input end of the first inverter U11 is also electrically connected to the negative signal control end of the first tri-state gate U13 and the positive signal control end of the second tri-state gate U14, and the output end of the first inverter U11 is electrically connected to the positive signal control end of the first tri-state gate U13. The positive signal control terminal of the first tri-state gate U13 is electrically connected to the negative signal control terminal of the second tri-state gate U14; the input terminal of the first tri-state gate U13 is electrically connected to the signal input terminal IN, and the output terminal of the first tri-state gate U13 is electrically connected to the input terminal of the second inverter U12; the output terminal of the second inverter U12 is electrically connected to the input terminal of the second tri-state gate U14, and the output terminal of the second tri-state gate U14 is electrically connected to the input terminal of the second inverter U12; wherein the output terminal of the second inverter U12 is the output terminal of the latch. In this way, the inverter and tri-state gate constitute the signal input module 101, so that the signal input module 101 can output the gate drive signal to the signal output module 102 in response to the input signal of the signal input terminal IN and the clock signal of the clock signal terminal CK.

[0088] Optionally, taking the example that the signal output module 102 can simultaneously adjust the polarity and amplitude of the gate drive signal, as shown in FIG. Figure 18As shown, the signal output module 102 may include a level conversion unit 1021 and a polarity conversion unit 1022. The level conversion unit 1021 may perform level conversion on the gate drive signal output by the signal input module 101 to adjust the amplitude of the gate drive signal; the gate drive signal after level conversion by the level conversion unit 1021 may be provided to the polarity conversion unit 1022, so that the polarity conversion unit 1022 can adjust the polarity of the gate drive signal after level conversion by the level conversion unit 1021; the gate drive signal after polarity adjustment by the polarity conversion unit 1022 may be output by the signal output terminal OUT to control whether the transistor in the pixel is turned on or off.

[0089] It should be noted that the above description is only an exemplary description of the structure of the signal output module 102. In the embodiment of the present invention, the signal output module 102 may also only include a level conversion unit or a polarity conversion unit. On the premise that the core invention point of the embodiment of the present invention can be achieved, the embodiment of the present invention does not make specific limitations on this.

[0090] In an optional embodiment, when the signal output module 102 includes the polarity conversion unit 1022, the polarity conversion unit 1022 may include a buffer, which may be composed of one or more inverters. The number of inverters in the buffer may be set according to actual needs and is not specifically limited in this embodiment of the present invention.

[0091] Based on the above embodiments, Figure 19 Schematic diagram of a film structure of a display panel provided by an embodiment of the present invention, such as Figure 19 As shown, the display panel 100 further includes: a silicon-based substrate Sub; in this case, the driving circuit 10 and the pixels 20 are both disposed on the silicon-based substrate Sub.

[0092] Among them, the silicon-based substrate Sub of the display panel 100 may include multiple substrate areas for setting circuit structures with different carrying capacities. For example, when the transmission signals of each device in the driving circuit 10 are different from the signals transmitted by each device in the pixel 20, the substrate area used to set each device in the driving circuit 10 can be a different substrate area from the substrate area used to set each device in the pixel 20, so that the display panel 100 has a lower cost while meeting the carrying capacity requirements of each device.

[0093] It should be noted that both the pixel and the driver circuit can be composed of active and / or passive devices, and this is not specifically limited in the embodiments of the present invention. For ease of illustration in the drawings, the embodiments of the present invention only exemplarily use a transistor to represent the structure of the pixel and the driver circuit, respectively. The actual structure of the driver circuit and pixel is not limited to this and can be designed according to actual needs.

[0094] In an optional embodiment, the transistors in the driving circuit can be manufactured in the same process as the transistors in the pixels, so as to simplify the manufacturing process steps of the display panel, improve the productivity of the display panel, and reduce the manufacturing cost of the display panel.

[0095] Based on the same inventive concept, an embodiment of the present invention further provides a display device, which includes the display panel provided by any embodiment of the present invention. Therefore, the display device provided by an embodiment of the present invention includes the technical features of the display panel provided by any embodiment of the present invention, and can achieve the beneficial effects of the display panel provided by any embodiment of the present invention. The similarities can be referred to the above description of the display panel provided by the embodiment of the present invention, and will not be repeated here.

[0096] Optional, Figure 20 is a structural diagram of a display device provided by an embodiment of the present invention, such as Figure 20 As shown, the display device may be a near-eye display device 200. The near-eye display device 200 may be smart glasses based on VR or AR, capable of creating a virtual image in a monocular or binocular field of view, and rendering light field information to the human eye through a display panel placed within the non-photopic distance of the human eye, thereby creating a virtual scene in front of the human eye.

[0097] Note that the above are only preferred embodiments of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments, and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments and may include many other equivalent embodiments without departing from the concept of the present invention. The scope of the present invention is determined by the scope of the appended claims.

Claims

1. A display panel, characterized in that: include: A plurality of pixels and a driving circuit arranged in an array; The driving circuit includes a plurality of cascaded shift register units and a plurality of switch modules electrically connected to the shift register units at each level; The signal output terminals of the shift register units at each level are respectively connected to the pixels in each row; Each of the switch modules includes N switch units; the N switch units are respectively a first switch unit, ..., an Nth switch unit; the switch units of the same switch module are turned on in a time-sharing manner; N is a positive integer greater than or equal to 2; The signal input end of the first-stage shift register unit is electrically connected to the start control signal end; the signal input end of each stage of the shift register unit starting from the second-stage shift register unit is electrically connected to the switch output end of each switch unit of the same switch module; Among the first N stages of the shift register units, a signal input terminal of the M-th stage of the shift register unit is electrically connected to the start control signal terminal through the M-th switch unit to the N-th switch unit, and a signal input terminal of the M-th stage of the shift register unit is electrically connected to a signal output terminal of at least one of the first-stage to the M-1-th shift register units through the first switch unit to the M-1-th switch unit; M is a positive integer greater than 1 and less than or equal to N; The signal input end of the shift register unit of the I+Nth stage is electrically connected to the signal output end of at least one of the shift register units of the Ith stage to the I+N-1th stage through each of the switch units; I is a positive integer greater than 1; The signal input terminal of the J-th shift register unit is electrically connected to the signal output terminal of the S-th shift register unit through the K-th switch unit; wherein J, K, and S are all positive integers, J>S, J>K, and K≤N; wherein, when J / K≠[J / K], S=[J / K]*K; or, when J / K=[J / K], S=(J / K-1)*K; The shift register unit includes a signal input module and a signal output module; in the same shift register unit, the signal input module controls the gate drive signal provided to the signal output module in response to at least the input signal of the signal input end; the signal output module is used to adjust the polarity and / or amplitude of the gate drive signal and provide the adjusted gate drive signal to the signal output end.

2. The display panel according to claim 1, wherein: Each of the K-th switch units electrically connected to the signal output end of the same shift register unit is connected in parallel to the signal output end of the shift register unit.

3. The display panel according to claim 1, wherein: Each of the K-th switch units electrically connected to the signal output end of the same shift register unit is sequentially connected in series to the signal output end of the shift register unit.

4. The display panel according to claim 1, wherein: The switching unit includes a switching transistor; The first pole of the switch transistor is the switch input end of the switch unit, the second pole of the switch transistor is the switch output end of the switch unit, and the gate of the switch transistor receives a switch control signal; The switching transistors of the same switching module receive different switching control signals.

5. The display panel according to claim 4, wherein: Also includes: N switch signal transmission lines; the switch signal transmission lines are used to transmit the switch control signal; The gates of the switching transistors of the switching units of the same switching module are electrically connected to different switching signal transmission lines respectively; The gates of the switch transistors of the Kth switch unit electrically connected to the shift register units of each stage are electrically connected to the same switch signal transmission line; K≤N, and K is a positive integer.

6. The display panel according to claim 1, wherein: The display mode of the display panel includes a first mode; During the display time of one frame in the first mode, one of the first to Nth switch units is controlled to be in a conducting state.

7. The display panel according to claim 1, wherein: The display mode of the display panel includes a second mode; The display time of a frame of picture in the second mode includes at least one first stage and at least one second stage; in each of the first stage and the second stage, one of the first to Nth switch units is controlled to be turned on, and the switch unit turned on in the first stage is different from the switch unit turned on in the second stage.

8. The display panel according to claim 1, wherein: The display mode of the display panel includes an Xth mode; The display time of a frame of image in the Xth mode includes at least one first stage, at least one second stage, ..., at least one Xth stage; in each stage from the first stage to the Xth stage, one of the first to Nth switch units is controlled to be in an on state, and the switch units turned on in each stage from the first stage to the Xth stage are different; X is a positive integer greater than or equal to 3.

9. The display panel according to claim 1, wherein: Also includes: Silicon-based substrate; The driving circuit and the pixels are both arranged on the silicon-based substrate.

10. A display device, characterized in that: include: The display panel according to any one of claims 1 to 9.

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