Pixel circuit and display panel

Abstract

This application discloses a pixel circuit and a display panel. The pixel circuit includes a compensation transistor, a first initialization transistor, a first light-emitting control transistor connected in series between a first power line and a second power line, a driving transistor, and a second light-emitting control transistor. By controlling the second light-emitting control transistor to be turned off during a time period of a frame, while the first light-emitting control transistor, the driving transistor, and the compensation transistor are all turned on, and then controlling the first initialization transistor to be turned on after the time period, the electrode potentials of the driving transistors at different gray levels can be reset to the same potential, and then the gate potential of the driving transistor can be reset. This ensures that the gate-source voltage difference and gate-drain voltage difference of the driving transistor remain consistent between frames, thereby reducing the brightness difference at different gray levels and improving the flicker phenomenon.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a pixel circuit and a display panel. Background Technology

[0002] As display products continue to develop in the consumer market, people have increasingly higher requirements for optical performance. Flicker, as an important indicator for evaluating optical performance, is subject to increasingly stringent specifications; at the same time, the introduction of low-frequency displays has exacerbated flicker.

[0003] Therefore, there is an urgent need to provide a pixel circuit and display panel to alleviate the flickering phenomenon. Summary of the Invention

[0004] This application provides a pixel circuit and a display panel to alleviate the technical problem of large brightness differences at different gray levels.

[0005] In a first aspect, this application provides a pixel circuit, which includes a compensation transistor, a first initialization transistor, a first light-emitting control transistor connected in series between a first power line and a second power line, a driving transistor, and a second light-emitting control transistor; the compensation transistor is connected between the gate of the driving transistor and the source or drain of the driving transistor; the first initialization transistor is connected between the gate of the driving transistor and the first initialization line; wherein, during a period of time in a frame, the second light-emitting control transistor is turned off, and the first light-emitting control transistor, the driving transistor, and the compensation transistor are all turned on; and the first initialization transistor is turned on after the period of time.

[0006] In some embodiments, the gate of the first light-emitting control transistor is connected to a first light-emitting control signal, which is the (n+1)th level gate drive signal, and the gate of the second light-emitting control transistor is connected to a second light-emitting control signal, which is the nth level gate drive signal.

[0007] In some embodiments, the first terminal of the first light-emitting control transistor is connected to a first power supply line, the gate of the first light-emitting control transistor is connected to a first light-emitting control line, and the second terminal of the first light-emitting control transistor is connected to the first terminal of the driving transistor; the first terminal of the second light-emitting control transistor is connected to the second terminal of the driving transistor, the second terminal of the second light-emitting control transistor is connected to a second power supply line, and the gate of the second light-emitting control transistor is connected to a second light-emitting control line; wherein the channel type of the first light-emitting control transistor is the same as that of the second light-emitting control transistor; the first light-emitting control line transmits a first light-emitting control signal, the second light-emitting control line transmits a second light-emitting control signal, the pulse width of the first light-emitting control signal is the same as that of the second light-emitting control signal, and the phase of the first light-emitting control signal is different from that of the second light-emitting control signal.

[0008] In some embodiments, the gate of the compensation transistor is connected to a first gate drive signal, which has a first pulse and a second pulse in a frame; the gate of the first initialization transistor is connected to a second gate drive signal, which has a third pulse in a frame; the third pulse is located between the first pulse and the second pulse in timing, and the third pulse and the second pulse at least partially overlap.

[0009] In some implementations, the operation phase of the pixel circuit in a frame includes a first phase in which the second light-emitting control transistor is turned off, and the first light-emitting control transistor, the driving transistor, and the compensation transistor are all turned on.

[0010] In some implementations, the operation phase of the pixel circuit in a frame further includes a second phase following the first phase, in which the first initialization transistor is turned on, and the first light-emitting control transistor, the second light-emitting control transistor, and the compensation transistor are all turned off.

[0011] In some embodiments, the pixel circuit further includes a light-emitting device and a second initialization transistor, the light-emitting device being connected between the second light-emitting control transistor and the second power supply line; the second initialization transistor being connected between the anode of the light-emitting device and the second initialization line; the operation phase of the pixel circuit in a frame further includes a third phase after the second phase, in which the first initialization transistor changes from being turned on to being turned off, the second initialization transistor and the compensation transistor are both turned on, and the second initialization transistor is turned on at least once again after the third phase.

[0012] In some embodiments, the pixel circuit further includes a write transistor connected between the first terminal of the driving transistor and the data line; the operation phase of the pixel circuit in a frame also includes a fourth phase after the third phase, in which the write transistor and the compensation transistor are both turned on, and the first initialization transistor, the second initialization transistor, the first light-emitting control transistor, and the second light-emitting control transistor are all turned off.

[0013] In some implementations, the operation phase of the pixel circuit in a frame also includes a fifth phase located between the fourth phase and the light emission phase, in which the write transistor is turned on.

[0014] In some implementations, the second initialization transistor is turned on again between the fourth and fifth stages.

[0015] Secondly, this application provides a display panel that includes the pixel circuit described above.

[0016] The pixel circuit and display panel provided in this application control the second light-emitting control transistor to be turned off during a time period of a frame, while the first light-emitting control transistor, the driving transistor, and the compensation transistor are all turned on. Then, the first initialization transistor is turned on after the time period. This can reset the electrode potentials of the driving transistors at different gray levels to the same potential, and then reset the gate potential of the driving transistors. This can keep the gate-source voltage difference and gate-drain voltage difference of the driving transistors consistent between frames, thereby reducing the brightness difference at different gray levels and improving the flicker phenomenon. Attached Figure Description

[0017] The technical solution and other beneficial effects of this application will become apparent from the following detailed description of specific embodiments in conjunction with the accompanying drawings.

[0018] Figure 1 This is a schematic diagram of the pixel circuit structure in related technologies.

[0019] Figure 2 for Figure 1 The timing diagram of the pixel circuit is shown.

[0020] Figure 3 This is a schematic diagram of the pixel circuit provided in an embodiment of this application.

[0021] Figure 4 for Figure 3 The timing diagram of the pixel circuit is shown. Detailed Implementation

[0022] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0023] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Features thus defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of this invention, "a plurality of" means two or more unless otherwise explicitly specified.

[0024] Figure 1This is a schematic diagram of a pixel circuit in the related technology. The pixel circuit includes at least one of the following: a driving transistor T1, a writing transistor T2, a compensation transistor T3, a first light-emitting control transistor T5, a second light-emitting control transistor T6, a first initialization transistor T4, a second initialization transistor T7, a bootstrap capacitor Cboost, a storage capacitor Cst, and a light-emitting device D1.

[0025] The first power line is connected to the first terminal of the first light-emitting control transistor T5 and one end of the storage capacitor Cst. The second terminal of the first light-emitting control transistor T5 is connected to the first terminal of the driving transistor T1 and the first terminal of the writing transistor T2. The gate of the driving transistor T1 is connected to the other end of the storage capacitor Cst, the first terminal of the compensation transistor T3, the first terminal of the first initialization transistor T4, and one end of the bootstrap capacitor Cboost. The second terminal of the driving transistor T1 is connected to the second terminal of the compensation transistor T3 and the first terminal of the second light-emitting control transistor T6. The second terminal of the second light-emitting control transistor T6 is connected to the anode of the light-emitting device D1 and the first terminal of the second initialization transistor T7. One electrode connection is made: the cathode of the light-emitting device D1 is connected to the second power supply line; the second electrode of the write transistor T2 is connected to the data line; the gate of the write transistor T2 is connected to the scan line and the other end of the bootstrap capacitor Cboost; the light-emitting control line is connected to the gate of the first light-emitting control transistor T5 and the gate of the second light-emitting control transistor T6; the gate of the compensation transistor T3 is connected to the first gate drive line; the second electrode of the first initialization transistor T4 is connected to the first initialization line; the gate of the first initialization transistor T4 is connected to the second gate drive line; the second electrode of the second initialization transistor T7 is connected to the second initialization line; and the gate of the second initialization transistor T7 is connected to the scan line.

[0026] Among them, the light-emitting device D1 can be an organic light-emitting diode, a mini light-emitting diode, a micro light-emitting diode, or a quantum dot light-emitting diode.

[0027] Each of the above transistors can be an N-channel transistor or a P-channel transistor.

[0028] In this configuration, the first electrode can be either the source or the drain, and the second electrode can be either the source or the drain. For example, if the first electrode is the source, the second electrode is the drain; or if the first electrode is the drain, the second electrode is the source.

[0029] In this design, the first electrode of the driving transistor T1 is the first node A. The second electrode of the driving transistor T1 is the second node B. The anode of the light-emitting device D1 is the third node C. The gate of the driving transistor T1 is the fourth node Q.

[0030] The system includes the following components: a first power line for transmitting the positive power signal ELVDD, a second power line for transmitting the negative power signal ELVSS, and a data line for transmitting the data signal DS. A light-emitting control line for transmitting the light-emitting control signal EM(n). A first initialization line for transmitting the first initialization signal Vi2. A second initialization line for transmitting the second initialization signal Vi1. A scan line for transmitting the scan signal Pscan(n). A first gate drive line for transmitting the first gate drive signal Nscan(n+10). A second gate drive line for transmitting the second gate drive signal Nscan(n).

[0031] Figure 2 for Figure 1 The timing diagram of the pixel circuit is shown. Taking an example where compensation transistor T3 and the first initialization transistor T4 are both N-channel transistors, and the other transistors are all P-channel transistors,... Figure 1 The pixel circuit shown in the diagram operates through the following stages in one frame:

[0032] In the first stage M1: when the scan signal Pscan(n) is high, the write transistor T2 and the second initialization transistor T7 are turned off; when the first gate drive signal Nscan(n+10) is low, the compensation transistor T3 is turned off; when the light emission control signal EM(n) is high, the first light emission control transistor T5 and the second light emission control transistor T6 are turned off; when the second gate drive signal Nscan(n) is high, the first initialization transistor T4 is turned on, and only the gate of the drive transistor T1, i.e., the fourth node Q, is reset.

[0033] In the second stage M2: when the light emission control signal EM(n) is high, the first light emission control transistor T5 and the second light emission control transistor T6 are turned off; when the second gate drive signal Nscan(n) is low, the first initialization transistor T4 is turned off; when the scan signal Pscan(n) is low, the write transistor T2 and the second initialization transistor T7 are turned on; when the first gate drive signal Nscan(n+10) is high, the compensation transistor T3 is turned on; the data signal DS is written to the gate of the drive transistor T1 via the write transistor T2, the drive transistor T1 and the compensation transistor T3; and the second initialization signal Vi1 resets the third node C via the second initialization transistor T7.

[0034] In the third stage M3: when the scan signal Pscan(n) is high, the write transistor T2 and the second initialization transistor T7 are turned off; when the second gate drive signal Nscan(n) is low, the first initialization transistor T4 is turned off; when the first gate drive signal Nscan(n+10) is low, the compensation transistor T3 is turned off; when the light emission control signal EM(n) is low, the first light emission control transistor T5 and the second light emission control transistor T6 are turned on, and the light emission device D1 starts to emit light.

[0035] However, when the first initialization transistor T4 is turned on, the fourth node Q has different potentials at different gray levels, resulting in differences in the reset effect of the fourth node Q at different gray levels. Moreover, when the first initialization transistor T4 resets the gate of the driving transistor T1, the potentials of the first node A and the second node B at different gray levels are different, which causes the gate-source voltage difference (Vgs) and gate-drain voltage difference (Vgd) of the driving transistor T1 to be different at different gray levels, resulting in significant differences in brightness between high and low gray levels.

[0036] Some pixel circuits with eight transistors can also solve the flickering problem of the pixel circuits with seven transistors, but an additional transistor is required.

[0037] In view of this, this embodiment provides a pixel circuit, such as Figure 3 , Figure 4 As shown, the pixel circuit includes a compensation transistor T3, a first initialization transistor T4, a first light-emitting control transistor T5 connected in series between a first power line and a second power line, a driving transistor T1, and a second light-emitting control transistor T6; the compensation transistor T3 is connected between the gate of the driving transistor T1 and the source or drain of the driving transistor T1; the first initialization transistor T4 is connected between the gate of the driving transistor T1 and the first initialization line; wherein, during a period of time in a frame, the second light-emitting control transistor T6 is turned off, and the first light-emitting control transistor T5, the driving transistor T1, and the compensation transistor T3 are all turned on; and the first initialization transistor T4 is turned on after this period of time.

[0038] It is understood that the pixel circuit provided in this embodiment, by controlling the second light-emitting control transistor T6 to be turned off during a period of time in a frame, while the first light-emitting control transistor T5, the driving transistor T1, and the compensation transistor T3 are all turned on during that period, and then controlling the first initialization transistor T4 to be turned on after that period, can reset the electrode potentials of the driving transistor T1 at different gray levels to the same potential, and then reset the gate potential of the driving transistor T1. This can ensure that the gate-source voltage difference and gate-drain voltage difference of the driving transistor T1 remain consistent between frames, thereby reducing the brightness difference at different gray levels and improving the flicker phenomenon.

[0039] Furthermore, compared to a pixel circuit with eight transistors, the pixel circuit of this application uses fewer transistors to improve the existing flickering phenomenon.

[0040] In one embodiment, the first terminal of the first light-emitting control transistor T5 is connected to the first power supply line, the gate of the first light-emitting control transistor T5 is connected to the first light-emitting control line, and the second terminal of the first light-emitting control transistor T5 is connected to the first terminal of the driving transistor T1; the first terminal of the second light-emitting control transistor T6 is connected to the second terminal of the driving transistor T1, the second terminal of the second light-emitting control transistor T6 is connected to the second power supply line, and the gate of the second light-emitting control transistor T6 is connected to the second light-emitting control line.

[0041] The first light-emitting control transistor T5 has the same channel type as the second light-emitting control transistor T6; the first light-emitting control line transmits the first light-emitting control signal EM(n+1), and the second light-emitting control line transmits the second light-emitting control signal EM(n). The pulse width of the first light-emitting control signal EM(n+1) is the same as the pulse width of the second light-emitting control signal EM(n), and the phase of the first light-emitting control signal EM(n+1) is different from the phase of the second light-emitting control signal EM(n).

[0042] It should be noted that this embodiment can not only synchronously reset the first node A, the second node B, and the fourth node Q through the first light-emitting control transistor T5 and the compensation transistor T3 before the first initialization transistor T4 is turned on, but also the first light-emitting control signal EM(n+1) and the second light-emitting control signal EM(n) can be generated through the same gate driving circuit, which reduces the number of gate driving circuits required in the display panel.

[0043] Wherein, the first light emission control signal EM(n+1) is the gate drive signal of the (n+1)th stage, and the second light emission control signal EM(n) is the gate drive signal of the nth stage.

[0044] In one embodiment, the first terminal of the compensation transistor T3 is connected to the second terminal of the driving transistor T1, the second terminal of the compensation transistor T3 is connected to the gate of the driving transistor T1, and the gate of the compensation transistor T3 is connected to the first gate driving line.

[0045] In one embodiment, the first terminal of the first initialization transistor T4 is connected to the gate of the driving transistor T1, the second terminal of the first initialization transistor T4 is connected to the first initialization line, and the gate of the first initialization transistor T4 is connected to the second gate driving line.

[0046] In one embodiment, the pixel circuit further includes a light-emitting device D1 and a second initialization transistor T7. The light-emitting device D1 is connected between the second light-emitting control transistor T6 and the second power supply line. The second initialization transistor T7 is connected between the anode of the light-emitting device D1 and the second initialization line, and the gate of the second initialization transistor T7 is connected to the third gate drive line.

[0047] In one embodiment, the pixel circuit further includes a write transistor T2, which is connected between the first electrode of the drive transistor T1 and the data line, and the gate of the write transistor T2 is connected to the scan line.

[0048] In one embodiment, the pixel circuit further includes a storage capacitor Cst, one end of which is connected to the gate of the driving transistor T1, and the other end of which is connected to a first power supply line.

[0049] In one embodiment, the pixel circuit further includes a bootstrap capacitor Cboost, one end of which is connected to the gate of the driving transistor T1, and the other end of which is connected to the gate of the writing transistor T2.

[0050] The system includes the following power lines: First power line for transmitting the positive power signal ELVDD; second power line for transmitting the negative power signal ELVSS; and a data line for transmitting the data signal DS. First light-emitting control line for transmitting the first light-emitting control signal EM(n+1). Second light-emitting control line for transmitting the second light-emitting control signal EM(n). First initialization line for transmitting the first initialization signal Vi2. Second initialization line for transmitting the second initialization signal Vi1. Scan line for transmitting the scan signal Pscan(n). First gate drive line for transmitting the first gate drive signal Nscan2. Second gate drive line for transmitting the second gate drive signal Nscan1. Third gate drive line for transmitting the third gate drive signal Pscan(n-1).

[0051] Each of the above transistors can be an N-channel transistor or a P-channel transistor. Figure 3 Taking compensation transistor T3 and first initialization transistor T4 as examples, both of which are N-channel transistors, and all other transistors as P-channel transistors, Figure 4 The pixel circuit shown in the diagram operates through the following stages in one frame:

[0052] Phase 1 P1: The first gate drive signal Nscan2 is high, and the compensation transistor T3 is turned on; the second gate drive signal Nscan1 is low, and the first initialization transistor T4 is turned off; the scan signal Pscan(n) is high, and the write transistor T2 is turned off; the third gate drive signal Pscan(n-1) is high, and the second initialization transistor T7 is turned off; the first light emission control signal EM(n+1) is low, and the first light emission control transistor T5 is turned on; the second light emission control signal EM(n) is high, and the second light emission control transistor T6 is turned off.

[0053] Since the first light-emitting control transistor T5 and the compensation transistor T3 are turned on in this stage, the positive power supply signal ELVDD can reset the first node A, the second node B, and the fourth node Q to the same potential through the first light-emitting control transistor T5, the driving transistor T1, and the compensation transistor T3. This ensures that the fourth node Q has the same initial potential at different gray levels in different frames; at the same time, it ensures that the gate-source voltage difference and gate-drain voltage difference of the driving transistor T1 are fixed when entering the second stage P2 described below, thereby improving the brightness difference between high and low gray levels.

[0054] Phase 2 P2: When the first gate drive signal Nscan2 is low, the compensation transistor T3 is off; when the second gate drive signal Nscan1 is high, the first initialization transistor T4 is on; when the scan signal Pscan(n) is high, the write transistor T2 is off; when the third gate drive signal Pscan(n-1) is high, the second initialization transistor T7 is off; when the first light emission control signal EM(n+1) is high, the first light emission control transistor T5 is off; when the second light emission control signal EM(n) is high, the second light emission control transistor T6 is off.

[0055] The first initialization signal Vi2 resets the gate of the driving transistor T1 through the first initialization transistor T4.

[0056] In the third stage P3: the first gate drive signal Nscan2 is at a high potential, and the compensation transistor T3 is turned on; the second gate drive signal Nscan1 switches from a high potential to a low potential, and the first initialization transistor T4 is turned on and then turned off; the scan signal Pscan(n) is at a high potential, and the write transistor T2 is turned off; the third gate drive signal Pscan(n-1) is at a low potential, and the second initialization transistor T7 is turned on; the first light emission control signal EM(n+1) is at a high potential, and the first light emission control transistor T5 is turned off; the second light emission control signal EM(n) is at a high potential, and the second light emission control transistor T6 is turned off.

[0057] The second initialization signal Vi1 resets the anode of the light-emitting device D1 through the second initialization transistor T7. The first initialization signal Vi2 resets the first node A, the second node B, and the fourth node Q through the first initialization transistor T4, the compensation transistor T3, and the driving transistor T1.

[0058] Phase 4 P4: The first gate drive signal Nscan2 is high, and the compensation transistor T3 is turned on; the second gate drive signal Nscan1 is low, and the first initialization transistor T4 is turned off; the scan signal Pscan(n) is low, and the write transistor T2 is turned on; the third gate drive signal Pscan(n-1) is high, and the second initialization transistor T7 is turned off; the first light emission control signal EM(n+1) is high, and the first light emission control transistor T5 is turned off; the second light emission control signal EM(n) is high, and the second light emission control transistor T6 is turned off.

[0059] The data signal DS is written to the gate of the drive transistor T1 via the write transistor T2, the drive transistor T1, and the compensation transistor T3.

[0060] Phase 5 (P5): When the first gate drive signal Nscan2 is low, the compensation transistor T3 is off; when the second gate drive signal Nscan1 is low, the first initialization transistor T4 is off; when the scan signal Pscan(n) is low, the write transistor T2 is on; when the third gate drive signal Pscan(n-1) is high, the second initialization transistor T7 is off; when the first light emission control signal EM(n+1) is high, the first light emission control transistor T5 is off; when the second light emission control signal EM(n) is high, the second light emission control transistor T6 is off.

[0061] The data signal DS is written to the first node A and / or the second node B via the writing transistor T2 and the driving transistor T1.

[0062] During the light-emitting stage: when the first gate drive signal Nscan2 is low, the compensation transistor T3 is off; when the second gate drive signal Nscan1 is low, the first initialization transistor T4 is off; when the scan signal Pscan(n) is high, the write transistor T2 is off; when the third gate drive signal Pscan(n-1) is high, the second initialization transistor T7 is off; when the first light-emitting control signal EM(n+1) is low, the first light-emitting control transistor T5 is on; when the second light-emitting control signal EM(n) is low, the second light-emitting control transistor T6 is on.

[0063] When the luminous current flows through the light-emitting device D1, the light-emitting device D1 starts to emit light.

[0064] Among them, such as Figure 4As shown, the first gate drive signal Nscan2 has a first pulse and a second pulse in a frame; the second gate drive signal Nscan1 has a third pulse in a frame; the third pulse is located between the first pulse and the second pulse in time, and the third pulse and the second pulse at least partially overlap.

[0065] It should be noted that the third gate drive signal Pscan(n-1) can have multiple pulses in one frame, so as to reset the anode of the light-emitting device D1 multiple times in the third stage P3 to the fifth stage P5, which can reduce the brightness difference between frames and further improve the flickering phenomenon.

[0066] For example, the second initialization transistor T7 is turned on once in the third stage P3, and then, exemplarily, turned on again between the fourth stage P4 and the fifth stage P5 after the third stage P3.

[0067] In one embodiment, this embodiment provides a display panel that includes the pixel circuit described above.

[0068] It is understood that, since the display panel provided in this embodiment includes the aforementioned pixel circuit, it is also possible to control the second light-emitting control transistor T6 to be turned off during a period of time in a frame, while the first light-emitting control transistor T5, the driving transistor T1, and the compensation transistor T3 are all turned on. Then, the first initialization transistor T4 is turned on after this period of time. This can reset the electrode potentials of the driving transistor T1 to the same potential under different gray levels, and then reset the gate potential of the driving transistor T1. This can make the gate-source voltage difference and gate-drain voltage difference of the driving transistor T1 consistent under different gray levels, thereby reducing the brightness difference under different gray levels and improving the flicker phenomenon.

[0069] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0070] The pixel circuit and display panel provided in the embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A pixel circuit, characterized in that, The pixel circuit includes: A first light-emitting control transistor, a driving transistor, and a second light-emitting control transistor are connected in series between the first power line and the second power line; A compensation transistor, wherein the compensation transistor is connected between the gate of the driving transistor and the source or drain of the driving transistor; A first initialization transistor is connected between the gate of the driving transistor and a first initialization line; A light-emitting device, wherein the light-emitting device is connected between the second light-emitting control transistor and the second power line; The second initialization transistor is connected between the anode of the light-emitting device and the second initialization line; During a certain period of a frame, the second light-emitting control transistor is turned off, while the first light-emitting control transistor, the driving transistor, and the compensation transistor are all turned on; and the first initialization transistor is turned on after the period. The operation of the pixel circuit in a frame includes a first stage, a second stage, and a third stage. In the third stage, the first initialization transistor changes from being turned on to being turned off, while the second initialization transistor and the compensation transistor are both turned on, and the second initialization transistor turns on at least once after the third stage.

2. The pixel circuit according to claim 1, characterized in that, The gate of the first light-emitting control transistor is connected to a first light-emitting control signal, which is the (n+1)th level gate drive signal. The gate of the second light-emitting control transistor is connected to a second light-emitting control signal, which is the nth level gate drive signal.

3. The pixel circuit according to claim 2, characterized in that, The first terminal of the first light-emitting control transistor is connected to the first power line, the gate of the first light-emitting control transistor is connected to the first light-emitting control line, and the second terminal of the first light-emitting control transistor is connected to the first terminal of the driving transistor. The first terminal of the second light-emitting control transistor is connected to the second terminal of the driving transistor, the second terminal of the second light-emitting control transistor is connected to the second power supply line, and the gate of the second light-emitting control transistor is connected to the second light-emitting control line. Wherein, the channel type of the first light-emitting control transistor is the same as that of the second light-emitting control transistor; the first light-emitting control line transmits the first light-emitting control signal, the second light-emitting control line transmits the second light-emitting control signal, the pulse width of the first light-emitting control signal is the same as that of the second light-emitting control signal, and the phase of the first light-emitting control signal is different from that of the second light-emitting control signal.

4. The pixel circuit according to claim 3, characterized in that, The gate of the compensation transistor is connected to a first gate drive signal, and the first gate drive signal has a first pulse and a second pulse in sequence within a frame; The gate of the first initialization transistor is connected to a second gate drive signal, and the second gate drive signal has a third pulse in one frame; The third pulse is located between the first pulse and the second pulse in timing, and the third pulse and the second pulse at least partially overlap.

5. The pixel circuit according to claim 4, characterized in that, In the first stage, the second light-emitting control transistor is turned off, and the first light-emitting control transistor, the driving transistor, and the compensation transistor are all turned on.

6. The pixel circuit according to claim 5, characterized in that, In the second stage, the first initialization transistor is turned on, and the first light-emitting control transistor, the second light-emitting control transistor, and the compensation transistor are all turned off.

7. The pixel circuit according to claim 1, characterized in that, The pixel circuit further includes a write transistor, which is connected between the first electrode of the drive transistor and the data line; The operation phase of the pixel circuit in a frame also includes a fourth phase after the third phase, in which the write transistor and the compensation transistor are both turned on, and the first initialization transistor, the second initialization transistor, the first light-emitting control transistor, and the second light-emitting control transistor are all turned off.

8. The pixel circuit according to claim 7, characterized in that, The operation phase of the pixel circuit in a frame also includes a fifth phase located between the fourth phase and the light emission phase, in which the write transistor is turned on.

9. The pixel circuit according to claim 8, characterized in that, The second initialization transistor is turned on again between the fourth and fifth stages.

10. A display panel, characterized in that, The display panel includes the pixel circuitry as described in any one of claims 1-9.

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