Semiconductor device, method of manufacturing the same, power conversion circuit, and vehicle

Abstract

The application discloses a semiconductor device, a preparation method thereof, a power conversion circuit and a vehicle, which comprise an N-type semiconductor substrate, an epitaxial layer, a trench structure, a gate, an interlayer dielectric layer, a source and a drain. The trench structure is arranged in the epitaxial layer, and the trench structure comprises a plurality of first trenches and a second trench. The first trenches extend along a first direction and are arranged at intervals along a second direction. The second trench extends along the second direction, is arranged in cross with each of the first trenches and is mutually conductive. The gate is filled in the trench structure through a gate dielectric layer. The interlayer dielectric layer covers the gate and has a contact hole extending along the second direction. The source is arranged on the interlayer dielectric layer and contacts the epitaxial layer through the contact hole. The drain is arranged on a side of the semiconductor substrate away from the epitaxial layer. In this way, the total on-resistance of the device is reduced.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor device, its fabrication method, a power conversion circuit, and a vehicle. Background Technology

[0002] Silicon carbide (SiC) offers advantages over silicon (Si) such as a wider bandgap, higher critical breakdown electric field, higher thermal conductivity, and higher electron saturation drift velocity. Metal-oxide-semiconductor field-effect transistors (MOSFETs) made from SiC exhibit higher breakdown voltage and lower on-state voltage drop compared to insulated-gate bipolar transistors (IGBTs) made from Si. Furthermore, the unipolar conductivity of SiC MOSFETs results in faster switching speeds, lower conduction losses, and lower switching losses compared to Si IGBTs. Therefore, SiC MOSFETs have already replaced Si IGBTs in some applications, such as automotive microcontroller units (MCUs) and on-board battery chargers (OBCs).

[0003] Compared to devices with ordinary planar gate structures, SiC MOSFET devices with trench gate structures embed the gate into the SiC body, turning the conductive channel of the device from the planar direction to the vertical direction. This significantly reduces the cell size of the device and greatly increases the conductive channel density, thereby significantly reducing the on-resistance of the chip and improving the current carrying capacity. Trench gate structure has become the mainstream technology direction for future devices.

[0004] However, in SiC MOSFET devices with trench gate structures, there is a significant contradiction between the channel resistance and the junction field-effect transistor (JFET) resistance: (Refer to...) Figure 1 The horizontal axis represents the cell size, and the vertical axis represents the resistance. Figure 1 It is known that by reducing the spacing of the trench gate structure in SiC MOSFET devices, the cell size of SiC MOSFET devices can be reduced, the conductive channel density can be increased, and the channel resistance can be reduced. However, at the same time, the current-carrying width of the JFET region will also decrease, resulting in an increase in the resistance of the JFET region. Consequently, the overall on-resistance of the SiC MOSFET device will increase, reducing device performance and increasing chip losses. Summary of the Invention

[0005] This application provides a semiconductor device, its fabrication method, a power conversion circuit, and a vehicle, which are used to reduce the total on-resistance of the device, improve device performance, and reduce device losses.

[0006] In a first aspect, this application provides a semiconductor device, comprising: an N-type semiconductor substrate, an epitaxial layer, a trench structure, a gate, an interlayer dielectric layer, a source, and a drain. The trench structure is disposed in the epitaxial layer, specifically including a plurality of first trenches and a second trench. Each of the plurality of first trenches extends along a first direction parallel to the plane of the semiconductor substrate and is spaced apart along a second direction parallel to the plane of the semiconductor substrate. The second trench extends along the second direction and is intersected with each of the plurality of first trenches and is interconnected. The main function of the second trench is to connect the first trenches. By disposing of the first trenches and the second trench in the epitaxial layer, a closely spaced trench structure can be formed. The gate is filled within the trench structure through a gate dielectric layer. The portions of the gate disposed in the plurality of first trenches extend along the first direction, and the portions of the gate disposed in the second trench extend along the second direction and are used to connect the portions of the gate extending along the first direction. Exemplarily, the epitaxial layer may include: a first N-type semiconductor region, a second N-type semiconductor region, a first P-type semiconductor region, and a source region sequentially disposed on a semiconductor substrate; a trench structure may extend into the first N-type semiconductor region in a third direction perpendicular to the plane of the semiconductor substrate. The first direction, the second direction, and the third direction are intersecting each other, for example, they are perpendicular to each other. The presence of the trench structure allows the gate to be embedded within the epitaxial layer of the material. The gate, together with the first P-type semiconductor region through the gate dielectric layer, forms the trench gate structure of the SiC MOSFET device, making the semiconductor device provided in this embodiment a trench gate structure SiC MOSFET. An interlayer dielectric layer is disposed on and covers the gate. The source is disposed on the interlayer dielectric layer, i.e., the source covers the entire interlayer dielectric layer. The drain is disposed on the side of the semiconductor substrate away from the epitaxial layer, i.e., the drain covers the side of the semiconductor substrate where no epitaxial layer is disposed. In practical applications, if signal transmission is required between the source and drain, a contact hole extending along the second direction can be provided in the interlayer dielectric layer. To avoid contact between the source and gate, the projection of the contact hole in the third direction can be made so that it does not overlap with the gate. Furthermore, the contact hole can expose a portion of the epitaxial layer; for example, it can expose a portion of the source region, allowing the source to contact the source region through the contact hole. When the gate-controlled channel is turned on, signals can be transmitted between the source and drain. The portion of the two sidewalls of each first trench in the trench structure that are opposite each other in the second direction constitutes the channel.

[0007] The semiconductor device provided in this application embodiment has a second extension direction for the contact holes in the interlayer dielectric layer and a first extension direction for each first trench in the trench structure. Therefore, the extension direction of the contact holes is perpendicular to the extension direction of each first trench, meaning the contact holes are placed perpendicular to the first trench. Compared to the prior art where the trench structure and contact holes are parallel, the semiconductor device provided in this application embodiment reduces the restriction on the trench spacing of adjacent first trenches in the second direction imposed by the contact holes. This allows for a more compact trench structure fabrication, resulting in a more compact gate. Therefore, the trench structure array density of the semiconductor device provided in this application embodiment can be significantly higher than that of prior art devices, thereby increasing the channel density of the SiC MOSFET, significantly reducing the total on-resistance of the device, improving device performance, and reducing device losses.

[0008] In this application, the semiconductor substrate can be a single-crystal SiC substrate doped with pentavalent elements. The epitaxial layer can be SiC material doped with corresponding impurities, grown epitaxially. For example, the first N-type semiconductor region can be a portion of the epitaxial layer formed by epitaxial growth, and the second N-type semiconductor region and the source region can be formed by doping the epitaxial layer using an ion implantation process. Furthermore, the N-type semiconductor region is mainly doped with N-type impurities, such as nitrogen (N), phosphorus (P), or arsenic (As). Exemplarily, the doping concentration of the semiconductor substrate is generally greater than the doping concentration of the second N-type semiconductor region, the doping concentration of the second N-type semiconductor region is generally greater than the doping concentration of the first N-type semiconductor region, and the doping concentration of the source region is generally greater than the doping concentration of the second N-type semiconductor region.

[0009] In this application, the first P-type semiconductor region can be formed by doping an epitaxial layer using an ion implantation process. Furthermore, the dopant in the P-type semiconductor region is primarily P-type impurities, such as boron (B), aluminum (Al), or gallium (Ga).

[0010] This application does not limit the material of the gate 11. For example, the material of the gate can be polycrystalline silicon, or other materials with good conductivity such as metals (e.g., W, Al, Ti, Cu, Mo or Pt).

[0011] This application does not limit the material used to form the interlayer dielectric layer. For example, the material used to form the interlayer dielectric layer can be a dielectric material, including but not limited to silicon dioxide (SiO2), silicon oxynitride (SiNO), silicon oxycarbide (SiCO), silicon nitride (SiNx), etc.

[0012] This application does not limit the materials used to form the source and drain electrodes. For example, the materials used to form the source and drain electrodes can be metallic materials. Exemplarily, the metallic materials may include W, Al, Ti, Cu, Mo, or Pt, etc.

[0013] In some possible implementations of this application, the semiconductor device can contain multiple trench structures and multiple contact holes. Specifically, a trench structure can be set between two adjacent contact holes, which can make the signal flow more uniform. When multiple trench structures exist, the structural parameters in each trench structure can be the same, which can ensure that the trench structures are evenly distributed. For example, the number of first trenches can be the same, the trench spacing between the first trenches can be the same, the trench length of each first trench can be the same, and the length of the second trenches can be the same. In practical applications, the number of first trenches in the trench structure can be determined according to the needs of the actual application, and this application does not limit it.

[0014] In some possible implementations of this application, the number of first grooves may be the same in some trench structures, while the number of first grooves may differ in the remaining trench structures. Alternatively, the number of first grooves may differ in different trench structures. In practical applications, the number of first grooves in a trench structure can be determined according to the needs of the actual application, and this application does not impose any limitations on this.

[0015] In some possible implementations of this application, in the second direction, the two first grooves at the edges of the trench structure can be defined as a first edge groove and a second edge groove, respectively. The contact hole extends along the second direction from the side of the first edge groove away from the second edge groove to the side of the second edge groove away from the first edge groove. That is, the contact hole is a continuous opening, and the first grooves in different trench structures are not interconnected.

[0016] The semiconductor device provided in this application is a trench gate SiC MOSFET device. In the trench gate SiC MOSFET device, the gate dielectric layer at the bottom and corner of the trench structure will be subjected to extremely high electric field strength when the device is working. This is a weak point for electric field breakdown and is prone to long-term reliability failure of the device. Therefore, how to effectively shield the gate dielectric layer from the high electric field stress has become the key to the high robustness / reliability design of the device.

[0017] In some possible embodiments of this application, a second P-type semiconductor region may also be provided in the epitaxial layer. This second P-type semiconductor region is disposed below the trench structure and can be connected to the source. In some possible embodiments of this application, the second P-type semiconductor region may be directly contacted with the bottom end of the trench structure. When the SiCMOSFET device is operating, a voltage is applied to the source. Since the second P-type semiconductor region is connected to the source, the voltage applied to the source is input to the second P-type semiconductor region, giving the second P-type semiconductor region a corresponding voltage. This effectively shields the electric field of the gate dielectric layer at the bottom of the trench structure, thereby improving the robustness of the device operation.

[0018] For example, when the SiC MOSFET provided in this application is applied to an electronic device, its source can be grounded and its drain can be connected to other components. In this case, the voltage of the source of the SiC MOSFET is the ground voltage (0V). Since the second P-type semiconductor region is connected to the source, the voltage of the second P-type semiconductor region is also the ground voltage, which can effectively shield the electric field of the gate dielectric layer at the bottom of the trench structure, thereby improving the robustness of the device operation.

[0019] For example, when the SiC MOSFET provided in this application is applied to an electronic device, its source can also be connected to other components, and its drain can also be connected to other components. In this case, the voltage at the source of the SiC MOSFET is the voltage of the signal input to the other components. Since the second P-type semiconductor region is connected to the source, the voltage of the second P-type semiconductor region is also the voltage of the input signal, thereby effectively shielding the electric field of the gate dielectric layer at the bottom of the trench structure, thereby improving the robustness of the device operation.

[0020] This application does not limit the thickness of the second P-type semiconductor region in the third direction. In some embodiments of this application, the thickness of the second P-type semiconductor region in the third direction may be less than 1 μm, for example, the thickness of the second P-type semiconductor region in the third direction may be 0.3 μm to 0.8 μm.

[0021] In some possible embodiments of this application, the epitaxial layer may further include a third P-type semiconductor region and a fourth P-type semiconductor region. The third P-type semiconductor region is disposed on at least one sidewall of the trench structure, and the fourth P-type semiconductor region is disposed on the same layer as the source region. The third P-type semiconductor region is in contact with the second P-type semiconductor region, and the fourth P-type semiconductor region is disposed in a one-to-one correspondence with the third P-type semiconductor region and is in contact with it. Voltage can be sequentially input to the second P-type semiconductor region through the fourth P-type semiconductor region and the third P-type semiconductor region, thereby effectively shielding the electric field of the gate dielectric layer at the bottom of the trench structure, thereby improving the robustness of device operation.

[0022] Specifically, the first, second, third, and fourth P-type semiconductor regions can be formed by doping the epitaxial layer using an ion implantation process. Furthermore, the dopants in the P-type semiconductor regions are primarily P-type impurities, such as boron (B), aluminum (Al), or gallium (Ga).

[0023] For example, the doping concentrations of the second, third, and fourth P-type semiconductor regions are greater than the doping concentration of the first P-type semiconductor region. Optionally, the doping concentrations of the second, third, and fourth P-type semiconductor regions can be the same or similar. Of course, at least two of the doping concentrations of the second, third, and fourth P-type semiconductor regions can be different. It should be noted that the doping concentrations of the second, third, and fourth P-type semiconductor regions can be determined according to the requirements of the actual application environment, and are not limited here.

[0024] In some possible embodiments of this application, in a first direction, each of the plurality of first trenches may have a first sidewall and a second sidewall disposed opposite to each other. A third P-type semiconductor region may be disposed on the first sidewall and the second sidewall of at least one of the plurality of first trenches, that is, a third P-type semiconductor region is disposed on the first sidewall and the second sidewall of at least one first trench. Furthermore, each of the third P-type semiconductor regions is in contact with a second P-type semiconductor region, thereby enabling the third P-type semiconductor region to be connected to the second P-type semiconductor region for signal transmission, and thus the voltage of each third P-type semiconductor region is the same as that of the second P-type semiconductor region. Correspondingly, a fourth P-type semiconductor region corresponds one-to-one with the third P-type semiconductor region and is disposed in contact, with the fourth P-type semiconductor region contacting the corresponding source electrode through a contact hole. Specifically, a third P-type semiconductor region disposed on the first sidewall corresponds to a fourth P-type semiconductor region, and the fourth P-type semiconductor region is disposed on the side of the third P-type semiconductor region away from the first sidewall of the first trench. Furthermore, a fourth P-type semiconductor region is correspondingly disposed on the third P-type semiconductor region located on the second sidewall away from the first trench. The source is sequentially connected to the second P-type semiconductor region through the corresponding fourth and third P-type semiconductor regions, so that the voltage applied to the source is sequentially input to the second P-type semiconductor region through the fourth and third P-type semiconductor regions, giving the second P-type semiconductor region a voltage. This effectively shields the electric field of the gate dielectric layer at the bottom of the trench structure, thereby improving the robustness of the device operation.

[0025] In some possible embodiments of this application, multiple third P-type semiconductor regions can be provided. One of these third P-type semiconductor regions is provided on the first sidewall of each first trench, and another third P-type semiconductor region is provided on the second sidewall of each first trench. That is, a third P-type semiconductor region is provided on both the first and second sidewalls of each first trench. Furthermore, these third P-type semiconductor regions are all in contact with the second P-type semiconductor regions, allowing them to connect and transmit signals, thus ensuring that the voltages of the third P-type semiconductor regions are the same as those of the second P-type semiconductor regions. Correspondingly, multiple fourth P-type semiconductor regions can be provided, each corresponding to and in contact with the aforementioned multiple third P-type semiconductor regions. Specifically, one of the multiple fourth P-type semiconductor regions is provided on the side of the third P-type semiconductor region furthest from the first sidewall of the first trench, corresponding to the third P-type semiconductor region on the first sidewall. Furthermore, a fourth P-type semiconductor region is correspondingly disposed on one of a plurality of fourth P-type semiconductor regions on the second sidewall of the third P-type semiconductor region, and this fourth P-type semiconductor region is disposed on the side of the second sidewall of the third P-type semiconductor region away from the first trench. The source is sequentially connected to the second P-type semiconductor region through the corresponding fourth P-type semiconductor regions and the third P-type semiconductor regions, so that the voltage applied to the source is sequentially input to the second P-type semiconductor region through the fourth P-type semiconductor region and the third P-type semiconductor region, so that the second P-type semiconductor region has a voltage, thereby effectively shielding the electric field of the gate dielectric layer at the bottom of the trench structure, thereby improving the robustness of device operation.

[0026] In some possible embodiments of this application, multiple source regions may be provided, with multiple source regions and multiple fourth P-type semiconductor regions located at the same end of the trench structure alternating. For example, multiple source regions and multiple fourth P-type semiconductor regions located at the first sidewalls of multiple first trenches in the same trench structure may be alternating. Also, multiple source regions and multiple fourth P-type semiconductor regions located at the second sidewalls of multiple first trenches in the same trench structure may be alternating.

[0027] Specifically, this application does not limit the width of the fourth P-type semiconductor region along the second direction. For example, the width of the fourth P-type semiconductor region along the second direction can be the same as or similar to the width of the first trench. Correspondingly, the width of the source region along the second direction can be the same as or similar to the trench spacing between two adjacent first trenches. Of course, the width of the fourth P-type semiconductor region along the second direction can also be different from the width of the first trench, which is not limited here.

[0028] In some possible embodiments of this application, the projection of the second P-type semiconductor region onto the third direction can cover both the trench structure and the third P-type semiconductor region. That is, the orthogonal projection of the second P-type semiconductor region onto the semiconductor substrate not only covers the orthogonal projection of the trench structure onto the semiconductor substrate, but also covers the orthogonal projections of all the third P-type semiconductor regions onto the semiconductor substrate.

[0029] In some possible embodiments of this application, the second P-type semiconductor region can be a planar region extending along the second direction. Furthermore, this application does not limit the shape of the second P-type semiconductor region; for example, the shape of the second P-type semiconductor region can be rectangular.

[0030] In some possible embodiments of this application, the projection of the second P-type semiconductor region in the third direction may also cover the gap between two adjacent first trenches. For example, the projection of the second P-type semiconductor region in the third direction may also cover the gap between two adjacent first trenches in the second direction. That is, the orthogonal projection of the second P-type semiconductor region on the semiconductor substrate also covers the orthogonal projection of the gap between two adjacent first trenches in the second direction on the semiconductor substrate.

[0031] In some possible embodiments of this application, generally one trench structure corresponds to one second P-type semiconductor region. That is, if one trench structure is provided, a second P-type semiconductor region in the planar region is correspondingly provided. If two trench structures are provided, two second P-type semiconductor regions in the planar region are correspondingly provided. Furthermore, there is a gap between these two second P-type semiconductor regions. If multiple trench structures are provided, multiple second P-type semiconductor regions in the planar region are correspondingly provided. Furthermore, there is a gap between every two adjacent second P-type semiconductor regions.

[0032] Specifically, in the second direction, there is a trench spacing between two adjacent first trenches. This application does not limit the specific value of the trench spacing; for example, the trench spacing can be less than 1 μm. Optionally, the trench spacing ranges from 50 nm to 0.5 μm. It should be noted that when the trench spacing is less than 100 nm, the semiconductor device provided in this application will form a Fin Field-Effect Transistor (Fin FET) effect, which can significantly improve carrier channel mobility and further reduce the total on-resistance of the device.

[0033] Specifically, in the first direction, the first trench has a trench length. This application does not limit the trench length; for example, the trench length can be greater than 5 μm.

[0034] Specifically, in the second direction, the first trench has a trench width. This application does not limit the trench width; for example, the trench width may be less than 1 μm.

[0035] Specifically, in the first direction, the contact hole has a contact width, which can ensure that the groove spacing is no greater than the contact width. Of course, the groove spacing can also be greater than the contact width. In practical applications, the groove spacing and contact width can be determined according to the environmental requirements of the actual application, and are not limited here.

[0036] In the semiconductor device provided in this application embodiment, the first P-type semiconductor region at the two sidewalls of the first trench in the second direction forms the channel region of the SiC MOSFET. Therefore, by increasing the trench width or decreasing the trench spacing, the conductive channel density of the SiC MOSFET device can be increased and the total on-resistance of the SiC MOSFET device can be reduced.

[0037] In some possible embodiments of this application, the semiconductor device may include: an N-type semiconductor substrate, an epitaxial layer, a trench structure, a gate, an interlayer dielectric layer, a source, and a drain. Furthermore, the epitaxial layer may include: a first N-type semiconductor region, a second N-type semiconductor region, a first P-type semiconductor region, a source region, a second P-type semiconductor region, a third P-type semiconductor region, and a fourth P-type semiconductor region. This embodiment modifies the implementation methods described in the above embodiments. The differences between this embodiment and the above embodiments will be described below; similarities will not be repeated.

[0038] In this embodiment, a gap region exists between the second P-type semiconductor region and the bottom of the trench structure. That is, the second P-type semiconductor region at the bottom of the trench structure does not directly contact the bottom of the trench structure, but is connected to the bottom of the trench structure through the gap region. Exemplarily, this gap region can be an N-type semiconductor region, and the doping concentration of this gap region is the same as or similar to that of the first N-type semiconductor region. Optionally, this gap region can be a part of the first N-type semiconductor region.

[0039] In this embodiment, the interval region can serve as a flow path for the conduction current of the SiC MOSFET device, thereby increasing the current-carrying area of ​​the SiC MOSFET device and further reducing the total on-resistance of the SiC MOSFET device.

[0040] In some possible embodiments of this application, the semiconductor device may specifically include: an N-type semiconductor substrate, an epitaxial layer, a trench structure, a gate, an interlayer dielectric layer, a source, and a drain. Furthermore, the epitaxial layer may include: a first N-type semiconductor region, a second N-type semiconductor region, a first P-type semiconductor region, a source region, a second P-type semiconductor region, a third P-type semiconductor region, and a fourth P-type semiconductor region. This embodiment modifies the implementation methods described in the above embodiments. The differences between this embodiment and the above embodiments are only described below; the similarities are not repeated here.

[0041] In this embodiment, multiple third P-type semiconductor regions are provided. One of the multiple third P-type semiconductor regions is provided on the first sidewall of each first trench, and no third P-type semiconductor region is provided on the second sidewall of each first trench. That is, third P-type semiconductor regions are provided only on the first sidewall of each first trench. Furthermore, these third P-type semiconductor regions are all in contact with the second P-type semiconductor regions, so that the third P-type semiconductor regions are all connected to the second P-type semiconductor regions for signal transmission. Therefore, the voltage of each third P-type semiconductor region is the same as that of the second P-type semiconductor region.

[0042] Correspondingly, multiple fourth P-type semiconductor regions are also provided, each corresponding to and in contact with one of the aforementioned multiple third P-type semiconductor regions. Specifically, one of the multiple fourth P-type semiconductor regions is located on the side of the first sidewall corresponding to the third P-type semiconductor region, and this fourth P-type semiconductor region is located on the side of the third P-type semiconductor region away from the first sidewall of the first trench. The source is sequentially connected to the second P-type semiconductor region through the corresponding fourth and third P-type semiconductor regions, so that the voltage applied to the source is sequentially input to the second P-type semiconductor region through the fourth and third P-type semiconductor regions, giving the second P-type semiconductor region a voltage. This effectively shields the electric field of the gate dielectric layer at the bottom of the trench structure, thereby improving the robustness of the device operation.

[0043] In this embodiment, the epitaxial layer may further include a fifth P-type semiconductor region, which is disposed in the same layer as the source region. The fifth P-type semiconductor region is disposed on the side of the second sidewall of the first trench away from the first sidewall, and the fifth P-type semiconductor region is in contact with the source electrode through a contact hole.

[0044] In this embodiment, multiple fifth P-type semiconductor regions can be provided, each corresponding to a second sidewall of each first trench. Furthermore, multiple source regions and multiple fifth P-type semiconductor regions located on the second sidewalls of the first trench are alternately arranged.

[0045] Optionally, the fifth P-type semiconductor region can be formed by doping the epitaxial layer using an ion implantation process. Furthermore, the fifth P-type semiconductor region is primarily doped with P-type impurities, such as boron (B), aluminum (Al), or gallium (Ga). For example, the doping concentration of the fifth P-type semiconductor region can be the same as or similar to that of the fourth P-type semiconductor region.

[0046] In this embodiment, a third P-type semiconductor region is provided at the first sidewall of the first trench, without forming a channel.

[0047] In some possible embodiments of this application, the semiconductor device may specifically include: an N-type semiconductor substrate, an epitaxial layer, a trench structure, a gate, an interlayer dielectric layer, a source, and a drain. Furthermore, the epitaxial layer may include: a first N-type semiconductor region, a second N-type semiconductor region, a first P-type semiconductor region, a source region, a second P-type semiconductor region, a third P-type semiconductor region, and a fourth P-type semiconductor region. This embodiment modifies the implementation methods described in the above embodiments. The differences between this embodiment and the above embodiments are only described below; the similarities are not repeated here.

[0048] In this embodiment, multiple third P-type semiconductor regions are provided. One of the multiple third P-type semiconductor regions is provided on the first sidewall of each first trench, and no third P-type semiconductor region is provided on the second sidewall of each first trench. That is, a third P-type semiconductor region is provided only on the first sidewall of each first trench. Furthermore, these third P-type semiconductor regions are all in contact with the second P-type semiconductor regions, so that the third P-type semiconductor regions are all connected to the second P-type semiconductor regions for signal transmission. Therefore, the voltage of the third P-type semiconductor regions is the same as that of the second P-type semiconductor regions.

[0049] In this embodiment, multiple fourth P-type semiconductor regions are also provided, each corresponding to and in contact with the aforementioned multiple third P-type semiconductor regions. Specifically, one of the multiple fourth P-type semiconductor regions is located on the side of the first sidewall corresponding to the third P-type semiconductor region, and this fourth P-type semiconductor region is located on the side of the third P-type semiconductor region away from the first sidewall of the first trench. The source is sequentially connected to the second P-type semiconductor region through the corresponding fourth and third P-type semiconductor regions, so that the voltage applied to the source is sequentially input to the second P-type semiconductor region through the fourth and third P-type semiconductor regions, giving the second P-type semiconductor region a voltage. This effectively shields the electric field of the gate dielectric layer at the bottom of the trench structure, thereby improving the robustness of the device operation.

[0050] In this embodiment, a fourth P-type semiconductor region is provided only on the first sidewall of the first trench, while the second sidewall of the first trench is provided with source regions.

[0051] In some possible embodiments of this application, the positions of the first sidewall and the second sidewall of the first trench can also be interchanged. That is, one of the multiple third P-type semiconductor regions can be provided on the second sidewall of the first trench, and no third P-type semiconductor region is provided on the first sidewall of each first trench.

[0052] In some possible embodiments of this application, the semiconductor device may specifically include: an N-type semiconductor substrate, an epitaxial layer, a trench structure, a gate, an interlayer dielectric layer, a source, and a drain. Furthermore, the epitaxial layer may include: a first N-type semiconductor region, a second N-type semiconductor region, a first P-type semiconductor region, a source region, a second P-type semiconductor region, a third P-type semiconductor region, and a fourth P-type semiconductor region. This embodiment modifies the implementation methods described in the above embodiments. The differences between this embodiment and the above embodiments are only described below; the similarities are not repeated here.

[0053] In this embodiment, at least one end of the second trench can extend out of the first trench located at the edge of the plurality of first trenches. In a second direction, the second trench can have a third sidewall and a fourth sidewall disposed opposite to each other, and a third P-type semiconductor region can be disposed on the third sidewall and / or the fourth sidewall of the second trench. Exemplarily, both ends of the second trench can extend out of the first trench located at the edge of the plurality of first trenches, and the third P-type semiconductor region can be disposed on the third sidewall and the fourth sidewall of the second trench; that is, the third sidewall and the fourth sidewall of the second trench are respectively provided with a third P-type semiconductor region. Furthermore, the third P-type semiconductor regions are all in contact with the second P-type semiconductor regions, thereby enabling the third P-type semiconductor regions to be connected to the second P-type semiconductor regions for signal transmission, and thus the voltage of the third P-type semiconductor regions is the same as that of the second P-type semiconductor regions. Correspondingly, the fourth P-type semiconductor region corresponds one-to-one with the third P-type semiconductor region and is disposed in contact. A third P-type semiconductor region is disposed on the third sidewall, and a fourth P-type semiconductor region is disposed on the side of the third P-type semiconductor region away from the third sidewall of the second trench. Similarly, a fourth P-type semiconductor region is disposed on the fourth sidewall, and the fourth P-type semiconductor region is disposed on the side of the third P-type semiconductor region away from the fourth sidewall of the second trench. Voltage can be sequentially input to the second P-type semiconductor region through the fourth and third P-type semiconductor regions, giving the second P-type semiconductor region a voltage. This effectively shields the electric field of the gate dielectric layer at the bottom of the trench structure, thereby improving the robustness of the device operation.

[0054] In this embodiment, the epitaxial layer may further include: a fifth P-type semiconductor region, which is disposed in the same layer as the source region. The fifth P-type semiconductor region may be disposed on the side of the second sidewall of the first trench away from the first sidewall. The fifth P-type semiconductor region may also be disposed on the side of the first sidewall of the first trench away from the second sidewall, and the fifth P-type semiconductor region is in contact with the source electrode through a contact hole.

[0055] In this embodiment, multiple fifth P-type semiconductor regions can be provided, each corresponding to a first sidewall and a second sidewall of each first trench. Furthermore, multiple source regions and multiple fifth P-type semiconductor regions located on the first sidewall of the first trench are alternately arranged, as are multiple source regions and multiple fifth P-type semiconductor regions located on the second sidewall of the first trench.

[0056] Optionally, the fifth P-type semiconductor region can be formed by doping the epitaxial layer using an ion implantation process. Furthermore, the fifth P-type semiconductor region is primarily doped with P-type impurities, such as boron (B), aluminum (Al), or gallium (Ga). For example, the doping concentration of the fifth P-type semiconductor region can be the same as or similar to that of the fourth P-type semiconductor region.

[0057] In this embodiment, a third P-type semiconductor region is provided at the third and fourth sidewalls of the second trench, without forming a channel.

[0058] In some possible embodiments of this application, the semiconductor device may specifically include: an N-type semiconductor substrate, an epitaxial layer, a trench structure, a gate, an interlayer dielectric layer, a source, and a drain. Furthermore, the epitaxial layer may include: a first N-type semiconductor region, a second N-type semiconductor region, a first P-type semiconductor region, a source region, a second P-type semiconductor region, a third P-type semiconductor region, and a fourth P-type semiconductor region. This embodiment modifies the implementation methods described in the above embodiments. The differences between this embodiment and the above embodiments are only described below; the similarities are not repeated here.

[0059] In this embodiment, in some of the trench structures of two adjacent trench structures, the first trenches arranged along the first direction are interconnected. That is, the plurality of first trenches may include a first gate trench and a second gate trench that are interconnected along the first direction, wherein the first gate trench and the second gate trench can be considered to be located in two adjacent trench structures, respectively. For example, the first edge trenches in two adjacent left and right trench structures are arranged along the first direction, and the two first edge trenches are interconnected. The second edge trenches in two adjacent left and right trench structures are arranged along the first direction, and the two second edge trenches are interconnected. As another example, a first trench in the middle of the left trench structure may also be interconnected with a first trench in the middle of the right trench structure.

[0060] Accordingly, the contact hole may include multiple sub-contact holes spaced apart from each other, and at least one through-groove is provided between two adjacent sub-contact holes in the same contact hole. This application does not limit the number of sub-contact holes into which the contact hole is divided; for example, it can be two, three, four, or more. Furthermore, this application does not limit the number of through-grooves provided between two adjacent sub-contact holes in the same contact hole; for example, it can be one, two, three, four, or more. This increases the design freedom of the contact hole and improves the current uniformity of the SiC MOSFET device.

[0061] In some possible embodiments of this application, the semiconductor device may specifically include: an N-type semiconductor substrate, an epitaxial layer, a trench structure, a gate, an interlayer dielectric layer, a source, and a drain. Furthermore, the epitaxial layer may include: a third N-type semiconductor region, a first N-type semiconductor region, a second N-type semiconductor region, a first P-type semiconductor region, a source region, a second P-type semiconductor region, a third P-type semiconductor region, and a fourth P-type semiconductor region. This embodiment modifies the implementation methods described in the above embodiments. The differences between this embodiment and the above embodiments are only described below; the similarities are not repeated here.

[0062] In this embodiment, the third N-type semiconductor region can be disposed between the first N-type semiconductor region and the semiconductor substrate. Because of the third N-type semiconductor region, the thickness of the second P-type semiconductor region in the epitaxial layer in the third direction can be made thicker; for example, the thickness of the second P-type semiconductor region in the third direction can be greater than 1 μm.

[0063] In this embodiment, the third N-type semiconductor region can be SiC doped with N-type impurities, such as nitrogen (N), phosphorus (P), or arsenic (As). Exemplarily, the doping concentration of the third N-type semiconductor region can be lower than the doping concentration of the first N-type semiconductor region.

[0064] Secondly, embodiments of this application also provide a method for fabricating a semiconductor device, which may include the following steps: epitaxially growing an epitaxial layer on an N-type semiconductor substrate; etching the epitaxial layer to form a trench structure, the trench structure including a plurality of first trenches and a second trench, each of the plurality of first trenches extending along a first direction parallel to the plane of the semiconductor substrate and spaced apart along a second direction parallel to the plane of the semiconductor substrate, the second trench extending along the second direction and intersecting with each of the plurality of first trenches and being interconnected; sequentially forming a gate dielectric layer and a gate electrode within the trench structure; forming an interlayer dielectric layer covering the epitaxial layer on the gate electrode; etching the interlayer dielectric layer to form a contact hole extending along the second direction, the contact hole exposing a portion of the epitaxial layer, and the projection of the contact hole in a third direction not overlapping with the gate electrode; the first direction, the second direction, and the third direction intersecting each other; forming a source electrode on the interlayer dielectric layer, the source electrode contacting the epitaxial layer exposed by the contact hole through the contact hole; and forming a drain electrode on the side of the semiconductor substrate away from the epitaxial layer.

[0065] In some possible implementations, the fabrication method may further include: before sequentially forming a gate dielectric layer and a gate in the trench structure, forming a third P-type semiconductor region in contact with the second P-type semiconductor region by using a tilted ion implantation process on at least one sidewall of the trench structure; and forming a fourth P-type semiconductor region in the epitaxial layer that is disposed in the same layer as the source region by using an ion implantation process.

[0066] In some possible implementations, the epitaxial growth of the epitaxial layer on an N-type semiconductor substrate may include the following steps:

[0067] First, an epitaxial layer of a first predetermined thickness (i.e., thickness in the third direction) is epitaxially grown on an N-type SiC semiconductor substrate. Exemplarily, an epitaxial process is used to epitaxially grow SiC material doped with N-type impurities on an N-type SiC semiconductor substrate to form an epitaxial layer of the first predetermined thickness. This application does not limit the specific value of the first predetermined thickness. In practical applications, the specific value of the first predetermined thickness can be determined according to the requirements of the actual application environment.

[0068] Subsequently, an ion implantation process is used to implant ions into the epitaxial layer to form a second P-type semiconductor region. Exemplarily, an ion implantation process is used to dope P-type impurities in the epitaxial layer corresponding to the second P-type semiconductor region to be formed, forming a planar region of the second P-type semiconductor region. This application does not limit the thickness of the second P-type semiconductor region (i.e., the thickness in the third direction). In practical applications, the specific value of the thickness of the second P-type semiconductor region can be determined according to the requirements of the actual application environment.

[0069] Subsequently, epitaxial growth continues on the epitaxial layer forming the second P-type semiconductor region until an epitaxial layer reaching a second predetermined thickness is formed. For example, using an epitaxial process, SiC material doped with N-type impurities is further epitaxially grown on the epitaxial layer forming the second P-type semiconductor region to form a first epitaxial layer reaching the second predetermined thickness.

[0070] In some possible implementations, after epitaxially growing an epitaxial layer on an N-type semiconductor substrate, the fabrication method may further include: employing an ion implantation process to perform ion implantation in a portion of the epitaxial layer, sequentially forming a second N-type semiconductor region, a first P-type semiconductor region, and a source region, with the un-ion-implanted region of the epitaxial layer forming the first N-type semiconductor region. For example, to form the second N-type semiconductor region, the first P-type semiconductor region, and the source region, the un-ion-implanted region of the epitaxial layer forms the first N-type semiconductor region. Employing an ion implantation process to perform ion implantation in a portion of the epitaxial layer to form the second N-type semiconductor region, the first P-type semiconductor region, and the source region, with the un-ion-implanted region of the first epitaxial layer forming the first N-type semiconductor region, may include the following steps:

[0071] An ion implantation process is used to dope the surface of the epitaxial layer with N-type impurities to form a second N-type semiconductor region. Then, an ion implantation process is used to dope the surface of the epitaxial layer with P-type impurities to form a first P-type semiconductor region. Next, an ion implantation process is used to dope the surface of the epitaxial layer with N-type impurities to form a source region, and P-type impurities are doped on the surface of the epitaxial layer at the first and second sidewalls of the first trench to form a fourth P-type semiconductor region disposed on the same layer as the source region. Therefore, in this embodiment, after this ion implantation process, a portion of the epitaxial layer forms the second N-type semiconductor region, the first P-type semiconductor region, the source region, and the fourth P-type semiconductor region, while the regions of the epitaxial layer not implanted using this ion implantation process form the first N-type semiconductor region.

[0072] In some possible implementations, in order to form a trench structure, etching the epitaxial layer down to the first N-type semiconductor region and forming the trench structure in the epitaxial layer may include the following steps:

[0073] First, a trench mask (which can be a photoresist mask or a hard mask) is formed on the epitaxial layer. This trench mask covers the areas of the epitaxial layer where trench structures are not required, while exposing the areas where trench structures are needed. Then, a suitable etching process is selected from plasma etching, ion sputtering etching, and reactive ion etching to etch the areas of the epitaxial layer not covered by the trench mask. Etching continues until the first N-type semiconductor region is reached and the second P-type semiconductor region is exposed, at which point etching stops, thus forming a trench structure composed of multiple first and second trenches in the epitaxial layer.

[0074] In some possible implementations, to form the third P-type semiconductor region, a tilted ion implantation process is used to form a third P-type semiconductor region in contact with the second P-type semiconductor region on the first sidewall and the second sidewall of each first trench along the first direction, which may include the following steps:

[0075] Using a tilted ion implantation process, P-type impurities are doped on the surfaces of the first and second sidewalls of each first trench to form a third P-type semiconductor region that contacts the second P-type semiconductor region.

[0076] In some possible implementations, forming a gate dielectric layer in a trench structure may include the following steps: using an oxidation process to oxidize the surface of the trench structure so that a gate dielectric layer is formed on the surface of the trench structure.

[0077] In some possible implementations, forming the gate in a trench structure having a gate dielectric layer may include the following steps:

[0078] First, a deposition process is used to deposit polysilicon material on the entire epitaxial layer with the trench structure, filling the trench structure with the polysilicon material. After filling the trench structure with polysilicon, a polysilicon film is then applied to the entire epitaxial layer. Next, a suitable etching process is selected from plasma etching, ion sputtering etching, and reactive ion etching to etch the areas of polysilicon material not covered by the trench mask. Etching continues until the source region and the fourth P-type semiconductor region are exposed, at which point the etching stops to form the gate.

[0079] In some possible implementations, in order to form an interlayer dielectric layer, forming an interlayer dielectric layer on the gate that covers the entire epitaxial layer may include the following steps: using a deposition process to deposit an interlayer dielectric layer on the entire epitaxial layer and to make the interlayer dielectric layer cover the entire epitaxial layer.

[0080] In some possible implementations, in order to form a contact hole, etching the interlayer dielectric layer to form a contact hole extending along the second direction may include the following steps:

[0081] First, a contact hole mask (which can be a photoresist mask or a hard mask) is formed on the epitaxial layer. This mask covers the areas where contact holes do not need to be formed, while exposing the areas where contact holes need to be formed. Then, a suitable etching process is selected from plasma etching, ion sputtering etching, and reactive ion etching to etch the areas of the interlayer dielectric layer not covered by the contact hole mask, exposing a portion of the source region, such as the portion of the source region located on both sides of the gate in the first direction, and the portion of the fourth P-type semiconductor region located on both sides of the gate.

[0082] In some possible implementations, to form the source and drain, the source is formed on the interlayer dielectric layer and contacted with the source region through a contact hole. Forming the drain on the side of the semiconductor substrate away from the epitaxial layer may include the following steps:

[0083] A metal material is deposited on the interlayer dielectric layer using a deposition process to form the source electrode. Contact holes are then filled with the metal material, allowing the source electrode to contact the source region through the metal material filling the contact holes. For example, before forming the source electrode, a metal material can be deposited on the side of the semiconductor substrate away from the epitaxial layer using a deposition process to form the drain electrode. Alternatively, after forming the source electrode, a metal material can be deposited on the side of the semiconductor substrate away from the epitaxial layer using a deposition process to form the drain electrode.

[0084] This application does not limit the materials used for the source and drain electrodes. For example, the materials forming the source and drain electrodes can be metallic materials. Exemplarily, the metallic material may include W, Al, Ti, Cu, Mo, or Pt.

[0085] Thirdly, embodiments of this application also provide a power conversion circuit, which can be an AC-to-DC conversion circuit and / or a DC-to-DC conversion circuit. The power conversion circuit may include a circuit board and one or more semiconductor devices, with the semiconductor devices connected to the circuit board. The semiconductor devices may be those used in the first aspect or various possible designs of the first aspect, or those fabricated using the second aspect or various possible designs of the second aspect. Because the aforementioned semiconductor devices have better performance, the power conversion circuit including these semiconductor devices also has better performance. Furthermore, the principle by which this power conversion circuit solves the problem is similar to the principle by which the aforementioned semiconductor devices can solve the problem; therefore, the technical effects of this power conversion circuit can be referred to the technical effects of the aforementioned semiconductor devices, and repetitions will not be repeated.

[0086] Fourthly, embodiments of this application also provide a vehicle that may include a power conversion circuit. This power conversion circuit can be as described in the third aspect or various possible designs of the third aspect. Because the power conversion circuit described above has good performance, the vehicle including the power conversion circuit also has good circuit performance. Furthermore, the principle by which this vehicle solves the problem is similar to the principle by which the aforementioned power conversion circuit solves the problem; therefore, the technical effects of this vehicle can be referred to the technical effects of the aforementioned power conversion circuit, and repetitions will not be repeated. Attached Figure Description

[0087] Figure 1 This diagram shows the relationship between the channel resistance and the JFET resistance in a SiC MOSFET device.

[0088] Figure 2a This is a schematic diagram of the structure of an electric vehicle provided in one embodiment of this application;

[0089] Figure 2b This is a schematic diagram of the structure of an electronic device provided in one embodiment of this application;

[0090] Figure 3 A top view of a semiconductor device provided in one embodiment of this application;

[0091] Figure 4 for Figure 3 A schematic cross-sectional view of the structure along the tangent direction of line A1A2;

[0092] Figure 5 for Figure 3 A schematic cross-sectional view of the structure along the tangent direction of line A3A4;

[0093] Figure 6 for Figure 3 A schematic diagram of the cross-sectional structure along the tangent direction of V1V2;

[0094] Figure 7 for Figure 3 A schematic diagram of the cross-sectional structure along the V3V4 tangent direction;

[0095] Figure 8 for Figure 3 A schematic diagram of a partial three-dimensional structure;

[0096] Figure 9 for Figure 8 The diagram shows a three-dimensional structure of a semiconductor device without an interlayer dielectric layer and a source electrode.

[0097] Figure 10 for Figure 8 A three-dimensional structural diagram of the trench structure in the semiconductor device shown.

[0098] Figure 11 Some schematic diagrams showing the generation of conduction current in the semiconductor device provided in the embodiments of this application;

[0099] Figure 12 for Figure 11 A schematic diagram of the cross-sectional structure along the tangent direction of C1C2;

[0100] Figure 13 Some flowcharts illustrating the fabrication method of the semiconductor device provided in the embodiments of this application;

[0101] Figures 14a to 14j These are schematic diagrams illustrating a process for fabricating a semiconductor device according to embodiments of this application.

[0102] Figure 15 A three-dimensional structural schematic diagram of a semiconductor device provided in another embodiment of this application;

[0103] Figure 16 for Figure 15 The diagram shows a three-dimensional structure of a semiconductor device without an interlayer dielectric layer and a source electrode.

[0104] Figure 17 for Figure 15 A schematic diagram of the trench structure in the semiconductor device shown.

[0105] Figure 18 A three-dimensional structural schematic diagram of a semiconductor device provided in another embodiment of this application;

[0106] Figure 19 for Figure 18 The diagram shows a three-dimensional structure of a semiconductor device without an interlayer dielectric layer and a source electrode.

[0107] Figure 20 for Figure 18 A three-dimensional structural diagram of the trench structure in the semiconductor device shown.

[0108] Figure 21 A three-dimensional structural schematic diagram of a semiconductor device provided in another embodiment of this application;

[0109] Figure 22 for Figure 21 The diagram shows a three-dimensional structure of a semiconductor device without an interlayer dielectric layer and a source electrode.

[0110] Figure 23 for Figure 21 A three-dimensional structural diagram of the trench structure in the semiconductor device shown.

[0111] Figure 24 A top view of a semiconductor device provided in another embodiment of this application;

[0112] Figure 25 for Figure 24 A schematic diagram of the cross-sectional structure along the tangent direction of B1B2;

[0113] Figure 26 for Figure 24 A schematic diagram of the cross-sectional structure along the tangent direction of B3B4;

[0114] Figure 27 for Figure 24 A schematic diagram of the cross-sectional structure along the X1X2 tangent direction;

[0115] Figure 28 for Figure 24 A schematic diagram of the cross-sectional structure along the X3X4 tangent direction;

[0116] Figure 29 for Figure 24 A schematic diagram of a partial three-dimensional structure;

[0117] Figure 30 for Figure 29 The diagram shows a three-dimensional structure of a semiconductor device without an interlayer dielectric layer and a source electrode.

[0118] Figure 31 for Figure 30 A schematic diagram of a partial three-dimensional structure in a semiconductor device is shown.

[0119] Figure 32 A top view of a semiconductor device provided in another embodiment of this application;

[0120] Figure 33 A top view of a semiconductor device provided in another embodiment of this application;

[0121] Figure 34 This is a three-dimensional structural schematic diagram of a semiconductor device provided in another embodiment of this application.

[0122] Figure label:

[0123] 010-Electric vehicle, 012-Battery, 0100-Electronic device, 0110-Power conversion circuit, 0120-Load module, 0200-Power supply, 0111-DC-DC converter, 1-Semiconductor substrate, 100-Epiaxial layer, 2-First N-type semiconductor region, 3-Second N-type semiconductor region, 4-First P-type semiconductor region, 5-Fourth P-type semiconductor region, 6-Source region, 7-Trench structure, 8-Second P-type semiconductor region, 9-Third P-type semiconductor region, 10-Gate dielectric layer, 11-Gate, 1 2-Interlayer dielectric layer, 13-Source, 14-Drain, 15-Fifth P-type semiconductor region, 16-Third N-type semiconductor region, 202-Spacer region, 71-First trench, 72-Second trench, 121-Contact hole, x-First direction, y-Second direction, z-Third direction, C-Trench spacing; D-Trench length, E-Trench width, F-Contact width, S1-First sidewall, S2-Second sidewall, S3-Third sidewall, S4-Fourth sidewall, DS1-First set thickness, DS2-Second set thickness. Detailed Implementation

[0124] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. The specific operational methods in the method embodiments can also be applied to the device embodiments or system embodiments. It should be noted that in the description of this application, "at least one" refers to one or more, where "multiple" refers to two or more. Therefore, in the embodiments of this application, "multiple" can also be understood as "at least two". "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / ", unless otherwise specified, generally indicates that the preceding and following related objects have an "or" relationship. Furthermore, it should be understood that in the description of this application, words such as "first" and "second" are only used for distinguishing the purpose of description and should not be construed as indicating or implying relative importance or order.

[0125] It should be noted that in the embodiments of this application, "connection" refers to electrical connection. The connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be a direct connection between A and B, or an indirect connection between A and B through one or more other electrical components, such as the connection between A and B. Alternatively, it can be a direct connection between A and C, a direct connection between C and B, with A and B connected through C.

[0126] Furthermore, the exemplary embodiments can be implemented in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided to make this application more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the figures denote the same or similar structures, and therefore repeated descriptions of them are omitted. Terms expressing position and direction described in this application are illustrative based on the accompanying drawings, but may be modified as needed, and all such modifications are included within the scope of protection of this application. The accompanying drawings of this application are for illustrating relative positional relationships only and do not represent actual scale.

[0127] It should be noted that specific details are set forth in the following description to provide a full understanding of this application. However, this application can be implemented in many ways other than those described herein, and those skilled in the art can make similar extensions without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below. The following description is a preferred embodiment for carrying out this application; however, the description is for the purpose of illustrating the general principles of this application and is not intended to limit the scope of this application.

[0128] To facilitate understanding of the semiconductor devices, their fabrication methods, power conversion circuits, and vehicles provided in the embodiments of this application, their application scenarios will be introduced first below.

[0129] The semiconductor devices provided in this application can be used in vehicles (e.g., electric vehicles), such as in onboard microcontroller units (MCUs) and onboard battery chargers (OBCs). It should be noted that the semiconductor devices proposed in this application are intended for use in these and any other suitable types of devices, including but not limited to. The following description uses an electric vehicle as an example.

[0130] Figure 2a This is a schematic diagram of the structure of an electric vehicle provided in an embodiment of this application. (Refer to...) Figure 2a The electric vehicle 010 may include a power conversion circuit 0110 and a battery 012.

[0131] In one possible implementation, the power conversion circuit 0110 may include an alternating current (AC) to direct current (DC) conversion circuit and a DC-DC conversion circuit. The power conversion circuit 0110 may also be referred to as an inverter. For example, when an electric vehicle is charging, the electric vehicle 010 can be connected to a three-phase power grid and receive three-phase AC power from the grid. By controlling the operation of the power switch in the AC-DC conversion circuit of the power conversion circuit 0110, the AC-DC conversion circuit can convert the three-phase AC power into DC power. Furthermore, by controlling the operation of the power switch in the DC-DC conversion circuit of the power conversion circuit 0110, the DC-DC conversion circuit can regulate the voltage of the DC power output from the AC-DC conversion circuit, thereby providing voltage-matched DC power to the battery 012. This allows the battery 012 to store the DC power, thus achieving the charging function.

[0132] In another possible implementation, the power conversion circuit 0110 can also be a DC-DC converter circuit, and the electric vehicle 010 can also include a load 013, which can be an on-board device, power system, etc. of the electric vehicle 010. For example, by controlling the operation of the power switch of the DC-DC converter circuit of the power conversion circuit 0110, the power conversion circuit 0110 can regulate the DC power output from the battery and output it to the load 013, thereby providing voltage-adapted DC power to the load 013.

[0133] The semiconductor device provided in this application is a trench-gate MOSFET, which can increase the conduction channel density without increasing the JFET region resistance, thereby reducing the total conduction resistance, improving device performance, and reducing device losses. For example, the semiconductor device provided in this application can be applied to the power conversion circuit 0110 of a vehicle as a power switch in an AC-DC converter and / or a DC-DC converter. Because the semiconductor device provided in this application has good device performance, when applied to an AC-DC converter and / or a DC-DC converter, it can improve the performance of the AC-DC converter and / or the DC-DC converter and reduce drive losses, thereby improving the overall circuit performance and reducing drive losses.

[0134] The semiconductor devices provided in this application can also be widely used in various electronic devices, such as those with logic devices or memory devices. For example, such electronic devices can be smartphones, smart TVs, laptops, PDAs (personal digital assistants), wearable devices with wireless communication capabilities (such as smartwatches, smart glasses, and smart bracelets), etc. It should be noted that the semiconductor devices proposed in this application are intended for use in these and any other suitable types of electronic devices, including but not limited to.

[0135] Figure 2b This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. (Refer to...) Figure 2b The electronic device 0100 provided in this application embodiment includes a power conversion circuit 0110 and a load module 0120, with the power conversion circuit 0110 and load module 0120 electrically connected. Exemplarily, the electronic device 0100 can be any electrical device. Examples include smartphones, smart TVs, laptops, PDAs (personal digital assistants), wearable devices with wireless communication capabilities (such as smartwatches, smart glasses, and smart bracelets), in-vehicle microcontroller units (MCUs), and on-board battery chargers (OBCs). It should be noted that this application does not limit the specific type of electronic device.

[0136] In some embodiments, the power conversion circuit 0110 can be a direct current (DC) to direct current (DC) power conversion circuit, used to boost or buck DC power and output DC power to supply power to the load module 0120. For example, the power conversion circuit 0110 can convert the DC power (e.g., 48V) output from the power supply 0200 into DC power suitable for all types of load modules 0120 and output it to the load module 0120 for operation. This application does not impose any limitations on the power supply 0200 and the load module 0120. The power supply 0200 can be any device or component capable of outputting DC power. For example, the power supply 0200 can be a battery (e.g., a storage battery). The power conversion circuit 0110 can receive the battery voltage provided by the battery, convert the battery voltage into the operating voltage of the load module 0120, and output it to the load module 0120. The load module 0120 can be any functional module that uses DC power, such as a processor, chip, etc.

[0137] Reference Figure 2aThe power conversion circuit 0110 may include a DC-DC converter 0111. In specific operation, the MOSFETs in the DC-DC converter 0111 operate at a certain switching frequency, causing the DC-DC converter 0111 to boost or buck the DC power from the power supply 0200 before outputting it to the load module 0120 to provide the operating DC voltage. For example, the DC-DC converter may be a Buck converter, a Boost converter, a half-bridge converter, a full-bridge converter, or an inductor-inductor-capacitor (LLC) resonant converter, etc.

[0138] The semiconductor device provided in this application embodiment is a trench-gate MOSFET, which can increase the conduction channel density without increasing the JFET region resistance, thereby reducing the total conduction resistance, improving device performance, and reducing device losses. Exemplarily, the semiconductor device provided in this application embodiment can be applied to a DC-DC converter 0111 as a MOSFET in the DC-DC converter 0111. Because the semiconductor device provided in this application embodiment has good device performance, when applied to the MOSFET in the DC-DC converter 0111, it can improve the performance of the DC-DC converter 0111 and reduce drive losses, thereby improving the performance of the entire electronic device and reducing drive losses.

[0139] It should be noted that the above scenario descriptions are merely illustrative of some feasible application methods of the semiconductor device of this application. This application does not limit the specific application scenarios of the semiconductor device provided in the embodiments of this application, and can be determined according to the actual application requirements.

[0140] In some embodiments provided in this application, the materials of the semiconductor substrate 1 and the epitaxial layer 100 can be SiC, and the semiconductor device provided in the embodiments of this application is a SiC MOSFET.

[0141] It should be explicitly stated that, in this application, layers and regions prefixed with N or P represent electrons or holes as the majority carriers, respectively. Furthermore, a "+" sign marked with N or P indicates a higher doping concentration than layers or regions without a "+" sign, and the more "+" signs, the higher the doping concentration. The presence of the same number of "+" signs in N or P indicates similar doping concentrations, but is not limited to the same doping concentration. Similarly, a "-" sign marked with N or P indicates a lower doping concentration than layers or regions without a "-" sign, and the more "-" signs, the lower the doping concentration. The presence of the same number of "-" signs in N or P indicates similar doping concentrations, but is not limited to the same doping concentration.

[0142] It should also be noted that the comparison of doping concentration between the two regions in this application refers only to the comparison of the concentration of impurities doped in the two regions. The composition of the impurities is not limited to the substrate used to dope the impurities; that is, the composition of the impurities may be the same or different. The materials of the substrates used to dope the impurities may be the same or different.

[0143] Figure 3 This illustration shows a top view of a semiconductor device according to an embodiment of the present application. Figure 4 It shows Figure 3 A cross-sectional view of the structure along the tangent direction of line A1A2. Figure 5 It shows Figure 3 A schematic cross-sectional view of the structure along the tangent direction of line A3A4. Figure 6 It shows Figure 3 A schematic cross-sectional view of the structure along the tangent direction of V1V2. Figure 7 It shows Figure 3 A schematic diagram of the cross-sectional structure along the V3V4 tangent direction. Figure 8 It shows Figure 3 A partial three-dimensional structural diagram in the image. Figure 9 It shows Figure 8 The diagram shown illustrates the three-dimensional structure of the semiconductor device without the interlayer dielectric layer 12 and the source electrode 13. Figure 10 It shows Figure 8 The diagram shows a three-dimensional structural schematic of the trench structure in the semiconductor device.

[0144] Reference Figures 3 to 10 The semiconductor device provided in this application embodiment may specifically include: an N-type semiconductor substrate 1, an epitaxial layer 100, a trench structure 7, a gate 11, an interlayer dielectric layer 12, a source 13, and a drain 14. Exemplarily, the epitaxial layer 100 includes: a first N-type semiconductor region 2, a second N-type semiconductor region 3, a first P-type semiconductor region 4, and a source region 6 sequentially disposed on the semiconductor substrate 1.

[0145] In this application, the semiconductor substrate 1 can be a single-crystal SiC substrate doped with pentavalent elements. The epitaxial layer 100 can be SiC material doped with corresponding impurities and grown epitaxially. For example, the first N-type semiconductor region 2 can be a portion of the epitaxial layer 100 formed by epitaxial growth, and the second N-type semiconductor region 3 and the source region 6 can be formed by doping the epitaxial layer 100 using an ion implantation process. Furthermore, the dopants in the N-type semiconductor region are mainly N-type impurities, such as nitrogen (N), phosphorus (P), or arsenic (As). Exemplarily, the doping concentration of the semiconductor substrate 1 is generally greater than the doping concentration of the second N-type semiconductor region 3, the doping concentration of the second N-type semiconductor region 3 is generally greater than the doping concentration of the first N-type semiconductor region 2, and the doping concentration of the source region 6 is generally greater than the doping concentration of the second N-type semiconductor region 3.

[0146] In this application, the first P-type semiconductor region 4 can be formed by doping the epitaxial layer 100 using an ion implantation process. Furthermore, the dopants in the P-type semiconductor region are primarily P-type impurities, such as boron (B), aluminum (Al), or gallium (Ga).

[0147] Continue to refer to Figures 3 to 10 A trench structure 7 is disposed in the epitaxial layer 100 and extends into the first N-type semiconductor region 2 along a third direction z perpendicular to the plane of the semiconductor substrate 1. Specifically, the trench structure 7 may include a plurality of first trenches 71 and a second trench 72. Each of the plurality of first trenches 71 extends along a first direction x parallel to the plane of the semiconductor substrate 1 and is spaced apart along a second direction y parallel to the plane of the semiconductor substrate 1. The second trench 72 extends along the second direction y and is intersected with and interconnected with each of the plurality of first trenches 71. The main function of the second trench 72 is to connect the first trenches 71. By providing the first trenches 71 and the second trench 72 in the epitaxial layer 100, a closely arranged trench structure 7 can be formed. The first direction x, the second direction y, and the third direction z are intersected with each other; for example, the first direction x, the second direction y, and the third direction z are perpendicular to each other.

[0148] Continue to refer to Figures 3 to 10The gate 11 is filled and disposed within the trench structure 7, separated by the gate dielectric layer 10. A portion of the gate 11 disposed in each of the plurality of first trenches 71 extends along a first direction x, and a portion of the gate 11 disposed in the second trench 72 extends along a second direction y, serving to connect the portions of the gate 11 extending along the first direction x. The presence of the trench structure 7 embeds the gate 11 within the epitaxial layer 100 of the SiC material. The gate 11, together with the first P-type semiconductor region 4 through the gate dielectric layer 10, forms the trench gate structure of the SiC MOSFET device, making the semiconductor device provided in this embodiment a SiC MOSFET with a trench gate structure.

[0149] This application does not limit the material of the gate 11. For example, the material of the gate 11 can be polycrystalline silicon, or other materials with good conductivity such as metals (e.g., W, Al, Ti, Cu, Mo or Pt).

[0150] Continue to refer to Figures 3 to 10 An interlayer dielectric layer 12 is disposed on and covers the gate 11. A source 13 is disposed on the interlayer dielectric layer 12, meaning the source 13 covers the entire interlayer dielectric layer 12. A drain 14 is disposed on the side of the semiconductor substrate 1 away from the epitaxial layer 100, meaning the drain 14 covers the side of the semiconductor substrate 1 where the epitaxial layer 100 is not disposed. In practical applications, if signal transmission is required between the source 13 and the drain 14, a contact hole 121 extending along the second direction y can be provided in the interlayer dielectric layer 12. To prevent the source 13 from contacting the gate 11, the projection of the contact hole 121 onto the third direction z can be made so that it does not overlap with the gate 11, i.e., the contact hole 121 and the gate 11 do not overlap. The contact hole 121 exposes a portion of the source region 6, such as the portion of the source region 6 located on both sides of the gate 11 in the first direction x. This allows the source 13 to contact the source region 6 through the contact hole 121, achieving the effect of connecting the source 13 to the source region 6. When the gate 11 controls the channel to be turned on, signals can be transmitted between the source 13 and the drain 14. The portion of the two sidewalls of each first trench 71 in the trench structure 7 that are opposite each other in the second direction y constitutes the channel.

[0151] This application does not limit the material used to form the interlayer dielectric layer 12. For example, the material used to form the interlayer dielectric layer 12 can be a dielectric material, including but not limited to silicon dioxide (SiO2), silicon oxynitride (SiNO), silicon oxycarbide (SiCO), silicon nitride (SiNx), etc.

[0152] This application does not limit the materials used to form the source 13 and the drain 14. For example, the materials used to form the source 13 and the drain 14 can be metallic materials. Exemplarily, the metallic materials may include W, Al, Ti, Cu, Mo, or Pt, etc.

[0153] The semiconductor device provided in this application embodiment has a second direction y for the extension direction of the contact hole 121 in the interlayer dielectric layer 12, and a first direction x for the extension direction of each first trench 71 in the trench structure 7. Therefore, the extension direction of the contact hole 121 is perpendicular to the extension direction of each first trench 71, meaning the contact hole 121 is placed perpendicular to the first trench 71. Compared to the prior art where the trench structure and contact hole are parallel, the semiconductor device provided in this application embodiment reduces the restriction of the contact hole 121 on the trench spacing C of adjacent first trenches 71 in the second direction y, allowing for a more compact trench structure fabrication, i.e., a more compact gate 11. Therefore, the trench structure array density of the semiconductor device provided in this application embodiment can be much higher than that of the prior art, thus increasing the channel density of the SiC MOSFET, significantly reducing the total on-resistance of the device, improving device performance, and reducing device losses.

[0154] In some embodiments of this application, the semiconductor device may contain multiple trench structures 7 and multiple contact holes 121. Specifically, a trench structure 7 may be provided between two adjacent contact holes 121, which can make the signal flow more uniform. For example, referring to... Figures 3 to 5 The example illustrates two trench structures 7 and three contact holes 121. When multiple trench structures 7 exist, the structural parameters of each trench structure 7 can be the same, ensuring a uniform distribution of the trench structures 7. For example, the number of first trenches 71 can be the same, the trench spacing between the first trenches 71 can be the same, the trench length of each first trench 71 can be the same, and the length of the second trenches 72 can be the same. For example, refer to... Figure 3 Each of the two trench structures 7 has five first trenches 71. It should be noted that... Figure 3 The number of first trenches 71 shown in the trench structure 7 is for illustrative purposes only and does not limit the number of first trenches 71 in the actual fabricated semiconductor device. In practical applications, the number of first trenches 71 in the trench structure 7 can be determined according to the needs of the actual application, and this application does not limit it in this regard.

[0155] In some embodiments of this application, the number of first grooves 71 in some trench structures 7 may be the same, while the number of first grooves 71 in the remaining trench structures 7 may be different. Alternatively, the number of first grooves 71 in different trench structures 7 may be different. In practical applications, the number of first grooves 71 in the trench structure 7 can be determined according to the needs of the actual application, and this application does not limit it in this regard.

[0156] In some embodiments of this application, in the second direction y, the two first grooves 71 located at the edges of the groove structure 7 can be defined as a first edge groove and a second edge groove, respectively. The contact hole 121 extends from the side of the first edge groove away from the second edge groove along the second direction to the side of the second edge groove away from the first edge groove. For example, referring to... Figure 3 In the second direction y, the two first grooves 71 at the upper and lower edges of the two groove structures 7 are defined as the first edge groove and the second edge groove, respectively. Then, the contact hole 121 extends from the side of the first edge groove away from the second edge groove along the second direction y to the side of the second edge groove away from the first edge groove. That is to say, the contact hole 121 is a continuous opening, and the first grooves 71 in different groove structures 7 are not connected.

[0157] The semiconductor device provided in this application embodiment is a SiC MOSFET device with a trench gate structure. In the SiC MOSFET device with a trench gate structure, the gate dielectric layer 10 at the bottom and corner of the trench structure 7 will be subjected to extremely high electric field strength when the device is working. It is a weak point of electric field breakdown and is prone to long-term reliability failure of the device. Therefore, how to effectively shield the gate dielectric layer 10 from the high electric field stress has become the key to the high robustness / reliability design of the device.

[0158] Based on this, in the embodiments of this application, refer to Figures 3 to 10 A second P-type semiconductor region 8 may also be provided in the epitaxial layer 100. This second P-type semiconductor region 8 is disposed below the trench structure 7 and can be connected to the source 13. In some embodiments of this application, the second P-type semiconductor region 8 can be directly contacted with the bottom end of the trench structure 7. When the SiC MOSFET device is operating, a voltage is applied to the source 13. Since the second P-type semiconductor region 8 is connected to the source 13, the voltage applied to the source 13 is input to the second P-type semiconductor region 8, giving the second P-type semiconductor region 8 a corresponding voltage. This effectively shields the electric field of the gate dielectric layer 10 at the bottom of the trench structure 7, thereby improving the robustness of the device operation.

[0159] For example, when the SiC MOSFET provided in this embodiment is applied to an electronic device, its source 13 can be grounded and its drain 14 can be connected to other components. In this case, the voltage of the source 13 of the SiC MOSFET is the ground voltage (0V). Since the second P-type semiconductor region 8 is connected to the source 13, the voltage of the second P-type semiconductor region 8 is also the ground voltage, thereby effectively shielding the electric field of the gate dielectric layer 10 at the bottom of the trench structure 7, thereby improving the robustness of the device operation.

[0160] For example, when the SiC MOSFET provided in this application embodiment is applied to an electronic device, its source 13 can also be connected to other components, and its drain 14 can also be connected to other components. In this case, the voltage of the source 13 of the SiC MOSFET is the voltage of the signal input to the other components. Since the second P-type semiconductor region 8 is connected to the source 13, the voltage of the second P-type semiconductor region 8 is also the voltage of the input signal, thereby effectively shielding the electric field of the gate dielectric layer 10 at the bottom of the trench structure 7, thereby improving the robustness of the device operation.

[0161] This application does not limit the thickness of the second P-type semiconductor region 8 in the third direction x. In some embodiments of this application, the thickness of the second P-type semiconductor region 8 in the third direction z can be less than 1 μm, for example, the thickness of the second P-type semiconductor region 8 in the third direction z can be 0.3 μm to 0.8 μm.

[0162] In some embodiments of this application, reference is made to Figure 4 , Figures 8 to 10 The epitaxial layer 100 may further include a third P-type semiconductor region 9 and a fourth P-type semiconductor region 5. The third P-type semiconductor region 9 is disposed on at least one sidewall of the trench structure 7, and the fourth P-type semiconductor region 5 and the source region 6 are disposed in the same layer. The third P-type semiconductor region 9 is in contact with the second P-type semiconductor region 8, and the fourth P-type semiconductor region 5 is disposed in a one-to-one correspondence with the third P-type semiconductor region 9 and is in contact with each other. Voltage can be sequentially input to the second P-type semiconductor region 8 through the fourth P-type semiconductor region 5 and the third P-type semiconductor region 9, thereby effectively shielding the electric field of the gate dielectric layer 10 at the bottom of the trench structure 7, thereby improving the robustness of device operation.

[0163] Specifically, the first P-type semiconductor region 4, the second P-type semiconductor region 8, the third P-type semiconductor region 9, and the fourth P-type semiconductor region 5 can be formed by doping the epitaxial layer 100 using an ion implantation process. Furthermore, the dopants in the P-type semiconductor regions are primarily P-type impurities, such as boron (B), aluminum (Al), or gallium (Ga).

[0164] For example, the doping concentrations of the second P-type semiconductor region 8, the third P-type semiconductor region 9, and the fourth P-type semiconductor region 5 are greater than the doping concentration of the first P-type semiconductor region 4. Optionally, the doping concentrations of the second P-type semiconductor region 8, the third P-type semiconductor region 9, and the fourth P-type semiconductor region 5 can be the same or similar. Of course, at least two of the doping concentrations of the second P-type semiconductor region 8, the third P-type semiconductor region 9, and the fourth P-type semiconductor region 5 can be different. It should be noted that the doping concentrations of the second P-type semiconductor region 8, the third P-type semiconductor region 9, and the fourth P-type semiconductor region 5 can be determined according to the requirements of the actual application environment, and are not limited here.

[0165] In some embodiments of this application, reference is made to Figure 4 and Figure 10 In the first direction x, each of the plurality of first trenches 71 may have a first sidewall S1 and a second sidewall S2 disposed opposite to each other. A third P-type semiconductor region 9 may be disposed on the first sidewall S1 and the second sidewall S2 of at least one of the plurality of first trenches 71. That is, the first sidewall S1 and the second sidewall S2 of at least one first trench 71 are respectively provided with a third P-type semiconductor region 9. Furthermore, each of the third P-type semiconductor regions 9 is in contact with a second P-type semiconductor region 8, thereby enabling the third P-type semiconductor region 9 to be connected to the second P-type semiconductor region 8 for signal transmission. Therefore, the voltage of each third P-type semiconductor region 9 is the same as that of the second P-type semiconductor region 8. Correspondingly, a fourth P-type semiconductor region 5 corresponds one-to-one with and is in contact with the third P-type semiconductor region 9. The fourth P-type semiconductor region 5 can contact the corresponding source electrode 13 through the contact hole 121. A third P-type semiconductor region 9 disposed on the first sidewall S1 is correspondingly provided with a fourth P-type semiconductor region 5, and the fourth P-type semiconductor region 5 is disposed on the side of the third P-type semiconductor region 9 away from the first sidewall S1 of the first trench 71. Similarly, a third P-type semiconductor region 9 disposed on the second sidewall S2 is correspondingly provided with a fourth P-type semiconductor region 5, and the fourth P-type semiconductor region 5 is disposed on the side of the third P-type semiconductor region 9 away from the second sidewall S2 of the first trench 71. The source 13 is sequentially connected to the second P-type semiconductor region 8 through the corresponding fourth P-type semiconductor region 5 and the third P-type semiconductor region 9, so that the voltage applied to the source 13 is sequentially input to the second P-type semiconductor region 8 through the fourth P-type semiconductor region 5 and the third P-type semiconductor region 9, giving the second P-type semiconductor region 8 a voltage. This effectively shields the electric field of the gate dielectric layer 10 at the bottom of the trench structure 7, thereby improving the robustness of the device operation.

[0166] In some embodiments of this application, multiple third P-type semiconductor regions 9 can be provided. One of the multiple third P-type semiconductor regions 9 is provided on the first sidewall S1 of each first trench 71, and one of the multiple third P-type semiconductor regions 9 is also provided on the second sidewall S2 of each first trench 71. That is, each first sidewall S1 and second sidewall S2 of each first trench 71 is respectively provided with a third P-type semiconductor region 9. Furthermore, these third P-type semiconductor regions 9 are all in contact with the second P-type semiconductor regions 8, thereby enabling the third P-type semiconductor regions 9 to be connected to the second P-type semiconductor regions 8 for signal transmission, and thus the voltage of each third P-type semiconductor region 9 is the same as that of the second P-type semiconductor regions 8. Correspondingly, multiple fourth P-type semiconductor regions 5 can be provided, which correspond one-to-one with and are in contact with the aforementioned multiple third P-type semiconductor regions 9. The third P-type semiconductor region 9 disposed on the first sidewall S1 corresponds to one of a plurality of fourth P-type semiconductor regions 5, and this fourth P-type semiconductor region 5 is disposed on the side of the third P-type semiconductor region 9 away from the first sidewall S1 of the first trench 71. Similarly, the third P-type semiconductor region 9 disposed on the second sidewall S2 corresponds to one of a plurality of fourth P-type semiconductor regions 5, and this fourth P-type semiconductor region 5 is disposed on the side of the third P-type semiconductor region 9 away from the second sidewall S2 of the first trench 71. The source 13 is sequentially connected to the second P-type semiconductor region 8 through the corresponding fourth P-type semiconductor regions 5 and the third P-type semiconductor region 9, so that the voltage applied to the source 13 is sequentially input to the second P-type semiconductor region 8 through the fourth P-type semiconductor regions 5 and the third P-type semiconductor region 9, giving the second P-type semiconductor region 8 a voltage. This effectively shields the electric field of the gate dielectric layer 10 at the bottom of the trench structure 7, thereby improving the robustness of the device operation.

[0167] It is worth noting that, in the semiconductor device provided in this application embodiment, since a third P-type semiconductor region 9 is respectively provided at the first sidewall S1 and the second sidewall S2 of the trench structure 7, the first P-type semiconductor region 4 (i.e., the first P-type semiconductor region 4 below the fourth P-type semiconductor region 5) provided at the first sidewall S1 and the second sidewall S2 of the trench structure 7 does not have the channel performance controlled by the gate 11. Therefore, in the second direction y, the portion of the trench structure 7 sidewall corresponding to the gate 11 is the channel.

[0168] For example, refer to Figures 8 to 10In the semiconductor device provided in this application embodiment, multiple source regions 6 may also be provided, with multiple source regions 6 and multiple fourth P-type semiconductor regions 5 located at the same end of the trench structure 7 being alternately arranged. For example, multiple source regions 6 and multiple fourth P-type semiconductor regions 5 located at the first sidewalls S1 of multiple first trenches 71 in the same trench structure 7 may be alternately arranged. Also, multiple source regions 6 and multiple fourth P-type semiconductor regions 5 located at the second sidewalls S2 of multiple first trenches 71 in the same trench structure 7 may be alternately arranged.

[0169] Specifically, this application does not limit the width of the fourth P-type semiconductor region 5 along the second direction y. For example, the width of the fourth P-type semiconductor region 5 along the second direction y can be the same as or similar to the width of the first trench 71. Correspondingly, the width of the source region 6 along the second direction y can be the same as or similar to the trench spacing C between two adjacent first trenches 71. Of course, the width of the fourth P-type semiconductor region 5 along the second direction y can also be different from the width of the first trench 71, which is not limited here.

[0170] In some embodiments of this application, reference is made to Figures 3 to 10 The projection of the second P-type semiconductor region 8 onto the third direction z can cover the trench structure 7 and the third P-type semiconductor region 9. That is, the orthogonal projection of the second P-type semiconductor region 8 onto the semiconductor substrate 1 not only covers the orthogonal projection of the trench structure 7 onto the semiconductor substrate 1, but also covers all the orthogonal projections of the third P-type semiconductor regions 9 onto the semiconductor substrate 1.

[0171] In some embodiments of this application, reference is made to Figures 3 to 10 The second P-type semiconductor region 8 can be a planar region extending along the second direction y. Furthermore, this application does not limit the shape of the second P-type semiconductor region 8; for example, the shape of the second P-type semiconductor region 8 can be set to rectangular.

[0172] In some embodiments of this application, reference is made to Figures 3 to 10 The projection of the second P-type semiconductor region 8 onto the third direction z can also cover the gap between two adjacent first trenches 71. For example, the projection of the second P-type semiconductor region 8 onto the third direction z can also cover the gap between two adjacent first trenches 71 in the second direction y. That is, the orthogonal projection of the second P-type semiconductor region 8 onto the semiconductor substrate 1 also covers the orthogonal projection of the gap between two adjacent first trenches 71 in the second direction y onto the semiconductor substrate 1.

[0173] In some embodiments of this application, reference is made to Figures 3 to 10Generally, one trench structure 7 corresponds to one second P-type semiconductor region 8. That is, if one trench structure 7 is provided, then one second P-type semiconductor region 8 is correspondingly provided in the planar region. If two trench structures 7 are provided, then two second P-type semiconductor regions 8 are correspondingly provided in the planar region. Furthermore, there is a gap between these two second P-type semiconductor regions 8. If multiple trench structures 7 are provided, then multiple second P-type semiconductor regions 8 are correspondingly provided in the planar region. Furthermore, there is a gap between every two adjacent second P-type semiconductor regions 8.

[0174] Specifically, refer to Figure 3 and Figure 9 In the second direction y, there is a trench spacing C between two adjacent first trenches 71. This application does not limit the specific value of the trench spacing C; for example, the trench spacing C can be less than 1 μm. Optionally, the trench spacing C ranges from 50 nm to 0.5 μm. It should be noted that when the trench spacing C is less than 100 nm, the semiconductor device provided in this application will form a Fin Field-Effect Transistor (Fin FET) effect, which can significantly improve carrier channel mobility and further reduce the total on-resistance of the device.

[0175] Specifically, continue to refer to Figure 3 , Figure 4 and Figure 9 In the first direction, the first trench 71 has a trench length D. This application does not limit the trench length D; for example, the trench length D can be greater than 5 μm.

[0176] Specifically, continue to refer to Figure 3 In the second direction y, the first trench 71 has a trench width E. This application does not limit the trench width E; for example, the trench width E can be less than 1 μm.

[0177] Specifically, continue to refer to Figure 3 In the first direction x, the contact hole 121 has a contact width F, which can ensure that the groove spacing C is not greater than the contact width F. Of course, the groove spacing C can also be greater than the contact width F. In practical applications, the groove spacing C and the contact width F can be determined according to the environmental requirements of the actual application, and are not limited here.

[0178] In the semiconductor device provided in this application embodiment, the first P-type semiconductor region 4 at the two sidewalls of the first trench 71 in the second direction y forms the channel region of the SiC MOSFET. Therefore, by increasing the trench width D or decreasing the trench spacing C, the conductive channel density of the SiC MOSFET device can be increased and the total on-resistance of the SiC MOSFET device can be reduced.

[0179] Figure 11 The following are some schematic diagrams illustrating the generation of conduction current in the semiconductor device provided in the embodiments of this application. Figure 12 It shows Figure 11 A schematic cross-sectional view of the structure along the tangent line C1C2. (Refer to...) Figure 11 and Figure 12 The black straight line with an arrow represents the direction of current flow when the SiC MOSFET is turned on. For example, when a positive voltage is applied to the gate 11 of the SiC MOSFET, the MOSFET of the trench structure 7 provided in this application can be controlled to turn on. If different voltages are applied to the source 13 and drain 14 (e.g., the voltage applied to the source 13 is greater than the voltage applied to the drain 14), a current flow will occur between the source 13 and drain 14, such as... Figure 11 and Figure 12 The conduction current shown is flowing from the source 13 to the drain 14.

[0180] Figure 13 Some flowcharts of the method for fabricating semiconductor devices provided in the embodiments of this application are shown; Figures 14a to 14j Schematic diagrams illustrating the process of fabricating a semiconductor device according to embodiments of this application are shown below. (Refer to...) Figure 13 To prepare Figure 8 Taking the structure shown as an example, the preparation method may include the following steps:

[0181] S10. An epitaxial layer is grown on an N-type semiconductor substrate.

[0182] For example, step S10 includes:

[0183] First, refer to Figure 14a An epitaxial layer 100 is epitaxially grown on an N-type SiC semiconductor substrate 1 to a first predetermined thickness DS1 (i.e., the thickness in the third direction z).

[0184] For example, using an epitaxial process, SiC material doped with N-type impurities is epitaxially grown on an N-type SiC semiconductor substrate 1 to form an epitaxial layer 100 reaching a first predetermined thickness DS1.

[0185] This application does not limit the specific value of the first set thickness DS1. In practical applications, the specific value of the first set thickness DS1 can be determined according to the requirements of the actual application environment.

[0186] Then, refer to Figure 14b Ion implantation is performed on the epitaxial layer 100 to form the second P-type semiconductor region 8.

[0187] For example, an ion implantation process is used to dop P-type impurities in the epitaxial layer 100 corresponding to the second P-type semiconductor region 8 to be formed, thereby forming a planar region of the second P-type semiconductor region 8.

[0188] This application does not limit the thickness of the second P-type semiconductor region 8 (i.e., the thickness in the third direction). In practical applications, the specific value of the thickness of the second P-type semiconductor region 8 can be determined according to the requirements of the actual application environment.

[0189] Then, refer to Figure 14c On the epitaxial layer 100 forming the second P-type semiconductor region 8, epitaxial growth continues until an epitaxial layer 100 reaching the second set thickness DS2 is formed.

[0190] For example, using an epitaxial process, on the epitaxial layer 100 forming the second P-type semiconductor region 8, SiC material doped with N-type impurities is further epitaxially grown to form an epitaxial layer 100 reaching a second set thickness DS2.

[0191] S20. Using an ion implantation process, ion implantation is performed in a portion of the epitaxial layer to form a second N-type semiconductor region, a first P-type semiconductor region, and a source region. The region in the epitaxial layer that has not been ion implanted forms the first N-type semiconductor region.

[0192] For example, refer to Figure 14d An ion implantation process is used to dope the surface of the epitaxial layer 100 with N-type impurities to form a second N-type semiconductor region 3. Then, an ion implantation process is used to dope the surface of the epitaxial layer with P-type impurities to form a first P-type semiconductor region 4. Next, an ion implantation process is used to dope the surface of the epitaxial layer 100 with N-type impurities to form a source region 6, and an ion implantation process is used to dope the surface of the epitaxial layer 100 at the first sidewall S1 and the second sidewall S2 of the first trench 71 with P-type impurities to form a fourth P-type semiconductor region 5 disposed on the same layer as the source region 6.

[0193] Therefore, in this embodiment of the application, after the ion implantation process, a portion of the epitaxial layer 100 forms a second N-type semiconductor region 3, a first P-type semiconductor region 4, a source region 6, and a fourth P-type semiconductor region 5, while the region of the epitaxial layer 100 that was not ion implanted using the ion implantation process forms a first N-type semiconductor region 2.

[0194] S30. Etch the epitaxial layer to the first N-type semiconductor region to form a trench structure.

[0195] For example, firstly, a trench mask (which can be a mask formed using photoresist or a hard mask) is formed on the epitaxial layer. This trench mask covers the areas in the epitaxial layer where the trench structure 7 does not need to be formed, while exposing the areas in the epitaxial layer where the trench structure 7 needs to be formed. Then, referring to… Figure 14e A suitable etching process is selected from etching processes such as plasma etching, ion sputtering etching, and reactive ion etching. The area in the epitaxial layer not covered by the trench mask is etched until the first N-type semiconductor region 2 is etched and the second P-type semiconductor region 8 is exposed, and the etching is stopped to form a trench structure 7 composed of multiple first trenches and second trenches in the epitaxial layer.

[0196] S40. Using a tilted ion implantation process, a third P-type semiconductor region that contacts the second P-type semiconductor region is formed on the first sidewall and the second sidewall of each first trench along the first direction.

[0197] For example, refer to Figure 14f Using a tilted ion implantation process, P-type impurities are doped on the surfaces of the first sidewall S1 and the second sidewall S2 of each first trench 71 to form a third P-type semiconductor region 9 that contacts the second P-type semiconductor region 8.

[0198] S50. A gate dielectric layer and a gate electrode are formed in the trench structure.

[0199] For example, refer to Figure 14g First, an oxidation process is used to oxidize the surface of the trench structure 7, so that a gate dielectric layer 10 is formed on the surface of the trench structure 7.

[0200] Subsequently, a deposition process is used to deposit polysilicon material on the entire epitaxial layer with the trench structure, and the polysilicon material fills the trench structure. After the trench structure is filled with polysilicon material, a polysilicon film layer is covered on the entire epitaxial layer. Next, a suitable etching process is selected from plasma etching, ion sputtering etching, and reactive ion etching to etch the polysilicon material region until the source region 6 and the fourth P-type semiconductor region 5 are exposed, at which point the etching stops to form the gate 11.

[0201] S60. An interlayer dielectric layer covering the entire epitaxial layer is formed on the gate.

[0202] For example, refer to Figure 14h An interlayer dielectric layer 12 is deposited on the entire epitaxial layer using a deposition process, and the interlayer dielectric layer 12 covers the entire epitaxial layer.

[0203] S70, Etch the interlayer dielectric layer to form a contact hole extending along the second direction.

[0204] For example, firstly, a contact hole mask (which can be a mask formed using photoresist or a hard mask) is formed on the epitaxial layer. This contact hole mask covers the areas where contact holes 121 do not need to be formed, while exposing the areas where contact holes 121 need to be formed. Then, referring to… Figure 14i A suitable etching process is selected from etching processes such as plasma etching, ion sputtering etching, and reactive ion etching to etch the area of ​​the interlayer dielectric layer 12 that is not covered by the contact hole 121 mask, thereby exposing the portion of the source region 6 located on both sides of the gate 11 in the first direction x and the portion of the fourth P-type semiconductor region 5 located on both sides of the gate 11.

[0205] S80. A source electrode is formed on the interlayer dielectric layer, the source electrode is in contact with the source region through a contact hole, and a drain electrode is formed on the side of the semiconductor substrate away from the epitaxial layer.

[0206] This application does not limit the materials used for the source and drain electrodes. For example, the materials forming the source and drain electrodes can be metallic materials. Exemplarily, the metallic material may include W, Al, Ti, Cu, Mo, or Pt.

[0207] For example, refer to Figure 14j A deposition process is used to deposit a metallic material on the interlayer dielectric layer 12 to form the source electrode 13. The source electrode 13 then contacts the source region 6 through the metallic material filling the contact holes 121.

[0208] For example, refer to Figure 14j Before forming the source electrode 13, a deposition process can be used to deposit metal material on the side of the semiconductor substrate 1 away from the epitaxial layer to form the drain electrode 14. Alternatively, after forming the source electrode 13, a deposition process can be used to deposit metal material on the side of the semiconductor substrate 1 away from the epitaxial layer to form the drain electrode 14.

[0209] Figure 15 This illustration shows a three-dimensional structural diagram of a semiconductor device provided in another embodiment of this application. Figure 16 It shows Figure 15 The diagram shows a three-dimensional structure of a semiconductor device without an interlayer dielectric layer and a source electrode. Figure 17 It shows Figure 15 The diagram shows a schematic of the trench structure in the semiconductor device.

[0210] Reference Figures 15 to 17In other embodiments provided in this application, the semiconductor device may include: an N-type semiconductor substrate 1, an epitaxial layer, a trench structure 7, a gate 11, an interlayer dielectric layer 12, a source 13, and a drain 14. Furthermore, the epitaxial layer may include: a first N-type semiconductor region 2, a second N-type semiconductor region 3, a first P-type semiconductor region 4, a source region 6, a second P-type semiconductor region 8, a third P-type semiconductor region 9, and a fourth P-type semiconductor region 5. This embodiment modifies the implementation methods described in the above embodiments. The differences between this embodiment and the above embodiments are only described below; the similarities are not repeated here.

[0211] Reference Figures 15 to 17 In this embodiment, a spacer region 202 is provided between the second P-type semiconductor region 8 and the bottom end of the trench structure 7. That is, the second P-type semiconductor region 8 at the bottom of the trench structure 7 is not in direct contact with the bottom of the trench structure 7, but is connected to the bottom of the trench structure 7 through the spacer region 202. Exemplarily, the spacer region 202 can be an N-type semiconductor region, and the doping concentration of the spacer region 202 is the same as or similar to that of the first N-type semiconductor region 2. Optionally, the spacer region 202 can be a part of the first N-type semiconductor region 2.

[0212] In this embodiment, the interval region 202 can serve as a flow path for the conduction current of the SiC MOSFET device, thereby increasing the current-carrying area of ​​the SiC MOSFET device and further reducing the total on-resistance of the SiC MOSFET device.

[0213] To prepare Figure 15 Taking the structure shown as an example, the corresponding preparation method flowchart can be found in the following diagram. Figure 13 Steps S10-S20 and S40-S80 can be referred to the description of the preparation method above.

[0214] In this embodiment, step S30 involves etching the epitaxial layer down to the first N-type semiconductor region to form a trench structure, which can be implemented in the following manner.

[0215] In some examples, firstly, a trench mask (which can be a photoresist mask or a hard mask) is formed on the epitaxial layer. This trench mask covers the area in the epitaxial layer where the trench structure will be formed, while exposing the area in the epitaxial layer where the trench structure needs to be formed. Then, refer to... Figure 17A suitable etching process is selected from etching processes such as plasma etching, ion sputtering etching, and reactive ion etching. The area in the epitaxial layer not covered by the trench mask is etched until the first N-type semiconductor region 2 is etched, and the etching is stopped when the second P-type semiconductor region 8 is not exposed. This allows the portion of the first N-type semiconductor region 2 remaining above the second P-type semiconductor region 8 to form the spacer region 202.

[0216] In other examples, firstly, a trench mask (which can be a photoresist mask or a hard mask) is formed on the epitaxial layer to cover the area in the epitaxial layer where the trench structure will be formed, while exposing the area in the epitaxial layer where the trench structure needs to be formed. Then, refer to... Figure 17 A suitable etching process is selected from etching processes such as plasma etching, ion sputtering etching, and reactive ion etching to etch the area in the epitaxial layer that is not covered by the trench mask until the first N-type semiconductor region 2 is etched. However, the original design was to stop the etching process when the second P-type semiconductor region 8 is exposed. But due to the precision limitations of the etching process, the etching may stop before the second P-type semiconductor region 8 is exposed. As a result, part of the first N-type semiconductor region 2 is retained above the second P-type semiconductor region 8. The retained first N-type semiconductor region 2 forms the gap region 202.

[0217] Figure 18 This illustration shows a three-dimensional structural schematic diagram of a semiconductor device provided in another embodiment of this application. Figure 19 It shows Figure 18 The diagram shows a three-dimensional structure of a semiconductor device without an interlayer dielectric layer and a source electrode. Figure 20 It shows Figure 18 The diagram shows a three-dimensional structural schematic of the trench structure in the semiconductor device.

[0218] Reference Figures 18 to 20 In some embodiments provided in this application, the semiconductor device provided in this application may specifically include: an N-type semiconductor substrate 1, an epitaxial layer, a trench structure 7, a gate 11, an interlayer dielectric layer 12, a source 13, and a drain 14. Furthermore, the epitaxial layer may include: a first N-type semiconductor region 2, a second N-type semiconductor region 3, a first P-type semiconductor region 4, a source region 6, a second P-type semiconductor region 8, a third P-type semiconductor region 9, and a fourth P-type semiconductor region 5. This embodiment modifies the implementation methods described in the above embodiments. The differences between this embodiment and the above embodiments are only described below; the similarities are not repeated here.

[0219] Reference Figures 18 to 20In this embodiment, multiple third P-type semiconductor regions 9 are provided. One of the multiple third P-type semiconductor regions 9 is provided on the first sidewall S1 of each first trench 71, and no third P-type semiconductor region 9 is provided on the second sidewall S2 of each first trench 71. That is, the third P-type semiconductor region 9 is provided only on the first sidewall S1 of each first trench 71. Furthermore, these third P-type semiconductor regions 9 are all in contact with the second P-type semiconductor regions 8, so that the third P-type semiconductor regions 9 are all connected to the second P-type semiconductor regions 8 for signal transmission, and the voltage of the third P-type semiconductor regions 9 is the same as that of the second P-type semiconductor regions 8. In this embodiment, the positions of the first sidewall S1 and the second sidewall S2 of the first trench 71 can also be interchanged, that is, one of the multiple third P-type semiconductor regions 9 can be provided on the second sidewall S2 of the first trench 71, and no third P-type semiconductor region 9 is provided on the first sidewall S1 of each first trench 71.

[0220] Accordingly, refer to Figures 18 to 20 Multiple fourth P-type semiconductor regions 5 are also provided, each corresponding to and in contact with one of the multiple third P-type semiconductor regions 9. The third P-type semiconductor region 9 located on the first sidewall S1 corresponds to one of the multiple fourth P-type semiconductor regions 5, and this fourth P-type semiconductor region 5 is located on the side of the third P-type semiconductor region 9 away from the first sidewall S1 of the first trench 71. The source 13 is connected to the second P-type semiconductor region 8 sequentially through the corresponding fourth P-type semiconductor regions 5 and third P-type semiconductor regions 9, so that the voltage applied to the source 13 is sequentially input to the second P-type semiconductor region 8 through the fourth P-type semiconductor regions 5 and third P-type semiconductor regions 9, giving the second P-type semiconductor region 8 a voltage. This effectively shields the electric field of the gate dielectric layer 10 at the bottom of the trench structure 7, thereby improving the robustness of the device operation.

[0221] For example, refer to Figures 18 to 20 The epitaxial layer 100 may further include: a fifth P-type semiconductor region 15, which is disposed in the same layer as the source region 6. The fifth P-type semiconductor region 15 is disposed on the side of the second sidewall S2 of the first trench 71 away from the first sidewall S1, and the fifth P-type semiconductor region 15 is in contact with the source electrode 13 through the contact hole 121.

[0222] For example, a plurality of fifth P-type semiconductor regions 15 may be provided, each of which corresponds one-to-one with the second sidewall S2 of each first trench 71. Furthermore, a plurality of source regions 6 and a plurality of fifth P-type semiconductor regions 15 located on the second sidewall S2 of the first trench 71 are alternately provided.

[0223] Optionally, the fifth P-type semiconductor region 15 can be formed by doping the epitaxial layer using an ion implantation process. Furthermore, the fifth P-type semiconductor region 15 is primarily doped with P-type impurities, such as boron (B), aluminum (Al), or gallium (Ga). For example, the doping concentration of the fifth P-type semiconductor region 15 can be the same as or similar to the doping concentration of the fourth P-type semiconductor region 5.

[0224] In this embodiment, a third P-type semiconductor region 9 is provided at the first sidewall S1 of the first trench 71, without forming a channel.

[0225] To prepare Figure 18 Taking the structure shown as an example, the corresponding preparation method flowchart can be found in the following diagram. Figure 13 Steps S10 to S30 and S50 to S80 can be referred to the description of the preparation method above.

[0226] In this embodiment, step S40 is: using a tilted ion implantation process, a third P-type semiconductor region that contacts the second P-type semiconductor region is formed on the first sidewall of each first trench along the first direction.

[0227] For example, refer to Figure 20 Using a tilted ion implantation process, P-type impurities are doped on the surface of the first sidewall S1 of each first trench 71 to form a third P-type semiconductor region 9 that contacts the second P-type semiconductor region 8.

[0228] Figure 21 This illustration shows a three-dimensional structural schematic diagram of a semiconductor device provided in another embodiment of this application. Figure 22 It shows Figure 21 The diagram shows a three-dimensional structure of a semiconductor device without an interlayer dielectric layer and a source electrode. Figure 23 It shows Figure 21 The diagram shows a three-dimensional structural schematic of the trench structure in the semiconductor device.

[0229] Reference Figures 21 to 23 In some embodiments provided in this application, the semiconductor device may specifically include: an N-type semiconductor substrate 1, an epitaxial layer, a trench structure 7, a gate 11, an interlayer dielectric layer 12, a source 13, and a drain 14. Furthermore, the epitaxial layer may include: a first N-type semiconductor region 2, a second N-type semiconductor region 3, a first P-type semiconductor region 4, a source region 6, a second P-type semiconductor region 8, a third P-type semiconductor region 9, and a fourth P-type semiconductor region 5. This embodiment modifies the implementation methods described in the above embodiments. The differences between this embodiment and the above embodiments are only described below; the similarities are not repeated here.

[0230] Reference Figures 21 to 23In this embodiment, multiple third P-type semiconductor regions 9 are provided. One of the multiple third P-type semiconductor regions 9 is provided on the first sidewall S1 of each first trench 71, and no third P-type semiconductor region 9 is provided on the second sidewall S2 of each first trench 71. That is, a third P-type semiconductor region 9 is provided only on the first sidewall S1 of each first trench 71. Furthermore, these third P-type semiconductor regions 9 are all in contact with the second P-type semiconductor regions 8, so that all third P-type semiconductor regions 9 are connected to the second P-type semiconductor regions 8 for signal transmission, and thus the voltage of each third P-type semiconductor region 9 is the same as that of the second P-type semiconductor regions 8. In this embodiment, the positions of the first sidewall S1 and the second sidewall S2 of the first trench 71 can also be interchanged, that is, one of the multiple third P-type semiconductor regions 9 can be provided on the second sidewall S2 of the first trench 71, and no third P-type semiconductor region 9 is provided on the first sidewall S1 of each first trench 71.

[0231] Accordingly, refer to Figures 21 to 23 Multiple fourth P-type semiconductor regions 5 are also provided, each corresponding to and in contact with one of the multiple third P-type semiconductor regions 9. The third P-type semiconductor region 9 located on the first sidewall S1 corresponds to one of the multiple fourth P-type semiconductor regions 5, and this fourth P-type semiconductor region 5 is located on the side of the third P-type semiconductor region 9 away from the first sidewall S1 of the first trench 71. The source 13 is connected to the second P-type semiconductor region 8 sequentially through the corresponding fourth P-type semiconductor regions 5 and third P-type semiconductor regions 9, so that the voltage applied to the source 13 is sequentially input to the second P-type semiconductor region 8 through the fourth P-type semiconductor regions 5 and third P-type semiconductor regions 9, giving the second P-type semiconductor region 8 a voltage. This effectively shields the electric field of the gate dielectric layer 10 at the bottom of the trench structure 7, thereby improving the robustness of the device operation.

[0232] For example, refer to Figures 21 to 23 The fourth P-type semiconductor region 5 is provided only at the first sidewall S1 of the first trench 71, while the source region 6 is provided at the second sidewall S2 of the first trench 71.

[0233] To prepare Figure 21 Taking the structure shown as an example, the corresponding preparation method flowchart can be found in the following diagram. Figure 13 Steps S10, S30, and S50–S80 can be referred to the description of the preparation method above.

[0234] In this embodiment, step S20 is: using an ion implantation process, ion implantation is performed in a portion of the epitaxial layer to form a second N-type semiconductor region, a first P-type semiconductor region, and a source region, while the region in the epitaxial layer that has not been ion implanted forms the first N-type semiconductor region.

[0235] For example, refer to Figure 23 An ion implantation process is used to dope the surface of the epitaxial layer with N-type impurities to form a second N-type semiconductor region 3. Then, an ion implantation process is used to dope the surface of the epitaxial layer with P-type impurities to form a first P-type semiconductor region 4. Next, an ion implantation process is used to dope the surface of the epitaxial layer with N-type impurities to form a source region 6, and an ion implantation process is used to dope the surface of the epitaxial layer at the first sidewall S1 of the first trench 71 with P-type impurities to form a fourth P-type semiconductor region 5 disposed on the same layer as the source region 6. Therefore, in this embodiment, after this ion implantation process, a portion of the epitaxial layer forms the second N-type semiconductor region 3, the first P-type semiconductor region 4, the source region 6, and the fourth P-type semiconductor region 5, while the region of the epitaxial layer not subjected to this ion implantation process forms the first N-type semiconductor region 2.

[0236] In this embodiment, step S40 is: using a tilted ion implantation process, a third P-type semiconductor region that contacts the second P-type semiconductor region is formed on the first sidewall of each first trench along the first direction.

[0237] For example, refer to Figure 23 Using a tilted ion implantation process, P-type impurities are doped on the surface of the first sidewall S1 of each first trench 71 to form a third P-type semiconductor region 9 that contacts the second P-type semiconductor region 8.

[0238] Figure 24 This illustration shows a top view of a semiconductor device according to another embodiment of the present application. Figure 25 It shows Figure 24 A schematic cross-sectional view of the structure along the tangent direction of B1B2. Figure 26 It shows Figure 24 A cross-sectional view of the structure along the tangent direction of B3B4. Figure 27 It shows Figure 24 A cross-sectional view of the structure along the X1X2 tangent direction. Figure 28 It shows Figure 24 A schematic diagram of the cross-sectional structure along the X3X4 tangent direction. Figure 29 It shows Figure 24 A partial three-dimensional structural diagram in the image. Figure 30 It shows Figure 29 The diagram shows a three-dimensional structure of a semiconductor device without an interlayer dielectric layer and a source electrode. Figure 31 It shows Figure 30 The diagram shows a partial three-dimensional structure of a semiconductor device.

[0239] Reference Figures 24 to 31 In some embodiments provided in this application, the semiconductor device provided in this application may specifically include: an N-type semiconductor substrate 1, an epitaxial layer, a trench structure 7, a gate 11, an interlayer dielectric layer 12, a source 13, and a drain 14. Furthermore, the epitaxial layer may include: a first N-type semiconductor region 2, a second N-type semiconductor region 3, a first P-type semiconductor region 4, a source region 6, a second P-type semiconductor region 8, a third P-type semiconductor region 9, and a fourth P-type semiconductor region 5. This embodiment modifies the implementation methods described in the above embodiments. The differences between this embodiment and the above embodiments are only described below; the similarities are not repeated here.

[0240] In this embodiment, at least one end of the second trench 72 may extend out of the first trench 71 located at the edge of the plurality of first trenches 71. In the second direction y, the second trench 72 may have a third sidewall S3 and a fourth sidewall S4 disposed opposite to each other, and a third P-type semiconductor region 9 may be disposed on the third sidewall S3 and / or the fourth sidewall S4 of the second trench 72. For example, refer to... Figure 24 Both ends of the second groove 72 extend beyond the first groove 71 located at the edge of one of the plurality of first grooves 71. (Refer to...) Figure 28 The third P-type semiconductor region 9 can be disposed on the third sidewall S3 and the fourth sidewall S4 of the second trench 72. That is, the third P-type semiconductor region 9 is disposed on the third sidewall S3 and the fourth sidewall S4 of the second trench 72 respectively. Furthermore, each of the third P-type semiconductor regions 9 is in contact with the second P-type semiconductor region 8, thereby enabling the third P-type semiconductor region 9 to be connected to the second P-type semiconductor region 8 for signal transmission. Therefore, the voltage of each of the third P-type semiconductor regions 9 and the second P-type semiconductor region 8 is the same. Correspondingly, the fourth P-type semiconductor region 5 corresponds to and is in contact with each of the third P-type semiconductor regions 9. Specifically, one fourth P-type semiconductor region 5 is disposed for each third P-type semiconductor region 9 disposed on the third sidewall S3 away from the third P-type semiconductor region 9 of the second trench 72. Furthermore, a fourth P-type semiconductor region 5 is correspondingly disposed on the third P-type semiconductor region 9 located on the fourth sidewall S4, and the fourth P-type semiconductor region 5 is disposed on the side of the third P-type semiconductor region 9 away from the second trench 72 on the fourth sidewall S4. Voltage can be sequentially input to the second P-type semiconductor region 8 through the fourth P-type semiconductor region 5 and the third P-type semiconductor region 9, so that the second P-type semiconductor region 8 has voltage, thereby effectively shielding the electric field of the gate dielectric layer 10 at the bottom of the trench structure 7, thereby improving the robustness of device operation.

[0241] For example, refer to Figures 24 to 31The epitaxial layer 100 may further include a fifth P-type semiconductor region 15, which is disposed in the same layer as the source region 6. The fifth P-type semiconductor region 15 may be disposed on the side of the second sidewall S2 of the first trench 71 away from the first sidewall S1. The fifth P-type semiconductor region 15 may also be disposed on the side of the first sidewall S1 of the first trench 71 away from the second sidewall S2. The fifth P-type semiconductor region 15 is in contact with the source electrode 13 through the contact hole 121.

[0242] For example, a plurality of fifth P-type semiconductor regions 15 may be provided, which are respectively provided with a first sidewall S1 and a second sidewall S2 of each first trench 71. Furthermore, a plurality of source regions 6 and a plurality of fifth P-type semiconductor regions 15 located on the first sidewall S1 of the first trench 71 are alternately provided, and a plurality of source regions 6 and a plurality of fifth P-type semiconductor regions 15 located on the second sidewall S2 of the first trench 71 are alternately provided.

[0243] Optionally, the fifth P-type semiconductor region 15 can be formed by doping the epitaxial layer using an ion implantation process. Furthermore, the fifth P-type semiconductor region 15 is primarily doped with P-type impurities, such as boron (B), aluminum (Al), or gallium (Ga). For example, the doping concentration of the fifth P-type semiconductor region 15 can be the same as or similar to the doping concentration of the fourth P-type semiconductor region 5.

[0244] In this embodiment, a third P-type semiconductor region 9 is provided at the third sidewall S3 and the fourth sidewall S4 of the second trench 72, without forming a channel.

[0245] To prepare Figure 29 Taking the structure shown as an example, the corresponding preparation method flowchart can be found in the following diagram. Figure 13 Steps S10 to S30 and S50 to S80 can be referred to the description of the preparation method above.

[0246] In this embodiment, step S40 is: using a tilted ion implantation process, a third P-type semiconductor region that contacts the second P-type semiconductor region is formed on the third and fourth sidewalls of the second trench along the second direction.

[0247] For example, a tilted ion implantation process can be used to dop the surfaces of the third sidewall S3 and the fourth sidewall S4 of the second trench 72 with P-type impurities to form the third P-type semiconductor region 9 that is in contact with the second P-type semiconductor region 8.

[0248] Figure 32 A top view of a semiconductor device according to another embodiment of this application is shown; Figure 33 A top view of a semiconductor device provided in another embodiment of this application is shown.

[0249] Reference Figure 32 and Figure 33 In some embodiments provided in this application, the semiconductor device may specifically include: an N-type semiconductor substrate 1, an epitaxial layer, a trench structure 7, a gate 11, an interlayer dielectric layer 12, a source 13, and a drain 14. Furthermore, the epitaxial layer may include: a first N-type semiconductor region 2, a second N-type semiconductor region 3, a first P-type semiconductor region 4, a source region 6, a second P-type semiconductor region 8, a third P-type semiconductor region 9, and a fourth P-type semiconductor region 5. This embodiment modifies the implementation methods described in the above embodiments. The differences between this embodiment and the above embodiments will be described below; the similarities will not be repeated here.

[0250] Reference Figure 32 and Figure 33 In a subset of two adjacent trench structures 7, the first trenches 71 arranged along the first direction x are interconnected. That is, the plurality of first trenches 71 may include a first gate trench and a second gate trench that are interconnected along the first direction x, wherein the first gate trench and the second gate trench can be considered to be located in two adjacent trench structures, respectively. For example, the first edge trench (which can be considered a first gate trench) in the left trench structure 7 and the first edge trench (which can be considered a second gate trench) in the right trench structure 7 are arranged along the first direction x, and the two first edge trenches are interconnected. The second edge trench (which can be considered a first gate trench) in the left trench structure 7 and the second edge trench (which can be considered a second gate trench) in the right trench structure 7 are arranged along the first direction x, and the two second edge trenches are interconnected. (Refer to...) Figure 33 The first groove 71 in the middle of the left groove structure 7 can also be interconnected with the first groove 71 in the middle of the right groove structure 7.

[0251] Accordingly, the contact hole 121 may include a plurality of sub-contact holes spaced apart from each other, and at least one through first groove is provided between two adjacent sub-contact holes in the same contact hole 121. Figure 33 The diagram illustrates two sub-contact holes. This application does not limit the number of sub-contact holes into which the contact hole 121 is divided; for example, it can have two, three, four, or more. Furthermore, this application does not limit the number of through-grooves 71 provided between two adjacent sub-contact holes within the same contact hole 121; for example, it can have one, two, three, four, or more. This increases the design freedom of the contact hole 121 and improves the current uniformity of the SiC MOSFET device.

[0252] Figure 34 A three-dimensional structural schematic diagram of a semiconductor device provided in another embodiment of this application is shown.

[0253] Reference Figure 34 In some embodiments provided in this application, the semiconductor device may specifically include: an N-type semiconductor substrate 1, an epitaxial layer, a trench structure 7, a gate 11, an interlayer dielectric layer 12, a source 13, and a drain 14. Furthermore, the epitaxial layer may include: a third N-type semiconductor region 16, a first N-type semiconductor region 2, a second N-type semiconductor region 3, a first P-type semiconductor region 4, a source region 6, a second P-type semiconductor region 8, a third P-type semiconductor region 9, and a fourth P-type semiconductor region 5. This embodiment modifies the implementation methods described in the above embodiments. The differences between this embodiment and the above embodiments are only described below; the similarities are not repeated here.

[0254] Reference Figure 34 The third N-type semiconductor region 16 can be disposed between the first N-type semiconductor region 2 and the semiconductor substrate 1. Because the third N-type semiconductor region 16 is disposed, the thickness of the second P-type semiconductor region 8 in the third direction z in the epitaxial layer 100 can be set to be thicker. For example, the thickness of the second P-type semiconductor region 8 in the third direction z can be set to be greater than 1 μm.

[0255] Reference Figure 34 In this embodiment, the third N-type semiconductor region 16 can be SiC doped with N-type impurities, such as nitrogen (N), phosphorus (P), or arsenic (As). Exemplarily, the doping concentration of the third N-type semiconductor region 16 can be less than the doping concentration of the first N-type semiconductor region 2.

[0256] To prepare Figure 34 Taking the structure shown as an example, the corresponding preparation method flowchart can be found in the following diagram. Figure 13 Steps S10 to S80 can be referred to the description of the preparation method above.

[0257] In this embodiment, step S10 involves epitaxially growing an epitaxial layer on an N-type semiconductor substrate, which can be implemented in the following manner.

[0258] For example, refer to Figure 34 Using an epitaxial process, SiC material doped with N-type impurities is epitaxially grown on an N-type SiC semiconductor substrate 1 to form a third N-type semiconductor region 16. Subsequently, using an epitaxial process, SiC material doped with N-type impurities is epitaxially grown in the third N-type semiconductor region 16 to form an epitaxial layer 100 reaching a first predetermined thickness DS1.

[0259] This application also provides a power conversion circuit, which can be an AC-to-DC conversion circuit and / or a DC-to-DC conversion circuit. The power conversion circuit may include a circuit board and one or more semiconductor devices, with the semiconductor devices connected to the circuit board. Because the aforementioned semiconductor devices have good performance, the power conversion circuit including these semiconductor devices also has good performance. Furthermore, the principle by which this power conversion circuit solves the problem is similar to the principle by which the aforementioned semiconductor devices solve the problem; therefore, the technical effects of this power conversion circuit can be referred to the technical effects of the aforementioned semiconductor devices, and repetitions will not be repeated.

[0260] This application also provides a vehicle that includes the power conversion circuit provided in this application. Because the power conversion circuit has good performance, the vehicle including the power conversion circuit also has good circuit performance. Furthermore, the principle by which this vehicle solves the problem is similar to the principle by which the power conversion circuit solves the problem; therefore, the technical effect of this vehicle can be referred to the technical effect of the power conversion circuit, and repeated details will not be elaborated further.

[0261] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the scope of protection of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A semiconductor device, characterized in that, include: N-type semiconductor substrate; An epitaxial layer is disposed on the semiconductor substrate; A trench structure is disposed within the epitaxial layer; The trench structure includes a plurality of first trenches and a second trench. Each of the plurality of first trenches extends along a first direction parallel to the plane of the semiconductor substrate and is spaced apart along a second direction parallel to the plane of the semiconductor substrate. The second trench extends along the second direction and is intersected with each of the plurality of first trenches and is interconnected with each other. A gate electrode is disposed within the trench structure, separated by a gate dielectric layer; An interlayer dielectric layer is disposed on and covers the gate. The interlayer dielectric layer has a contact hole extending along the second direction, the contact hole penetrating the plurality of first trenches, the contact hole exposing a portion of the epitaxial layer, and the projection of the contact hole in a third direction perpendicular to the plane of the semiconductor substrate does not overlap with the gate. The first direction, the second direction, and the third direction are arranged to intersect each other. The source electrode is disposed on the interlayer dielectric layer, and the source electrode contacts the epitaxial layer exposed by the contact hole through the contact hole; Drain electrode, which is disposed on the side of the semiconductor substrate away from the epitaxial layer.

2. The semiconductor device as claimed in claim 1, characterized in that, The plurality of first trenches include a first gate trench and a second gate trench that extend along the first direction, wherein the first gate trench and the second gate trench are respectively located in two adjacent trench structures. The contact hole includes a plurality of sub-contact holes spaced apart from each other, and at least one through first groove is provided between two adjacent sub-contact holes in the same contact hole.

3. The semiconductor device as described in claim 1 or 2, characterized in that, The epitaxial layer includes: a first N-type semiconductor region, a second N-type semiconductor region, a first P-type semiconductor region, and a source region sequentially disposed on the semiconductor substrate; In a third direction perpendicular to the plane where the semiconductor substrate is located, the trench structure extends into the first N-type semiconductor region; The contact hole exposes a portion of the source region.

4. The semiconductor device as described in claim 3, characterized in that, The epitaxial layer further includes: The second P-type semiconductor region is disposed within the first N-type semiconductor region and located below the trench structure, and the second P-type semiconductor region is connected to the source.

5. The semiconductor device as claimed in claim 4, characterized in that, The epitaxial layer further includes: A third P-type semiconductor region is disposed on at least one sidewall of the trench structure, and the third P-type semiconductor region is in contact with the second P-type semiconductor region; The fourth P-type semiconductor region is disposed on the same layer as the source region, and the fourth P-type semiconductor region is disposed in a one-to-one correspondence with the third P-type semiconductor region and is in contact with each other.

6. The semiconductor device as claimed in claim 5, characterized in that, Each of the plurality of first trenches has a first sidewall and a second sidewall disposed opposite to each other in the first direction; The third P-type semiconductor region is disposed on the first sidewall and / or the second sidewall of at least one of the plurality of first trenches, and the fourth P-type semiconductor region is in contact with the source electrode through the contact hole.

7. The semiconductor device as claimed in claim 6, characterized in that, The third P-type semiconductor region is disposed only on the first sidewall or the second sidewall of at least one of the plurality of first trenches; The epitaxial layer further includes: a fifth P-type semiconductor region, which is disposed in the same layer as the source region, and is disposed on the side of the plurality of first trench sidewalls where the third P-type semiconductor region is not disposed, and the fifth P-type semiconductor region has the same doping concentration as the fourth P-type semiconductor region; The fifth P-type semiconductor region is in contact with the sidewall of the corresponding first trench in the plurality of first trenches, and the fifth P-type semiconductor region is in contact with the corresponding source electrode through the contact hole; On the side of the first trench facing the sidewall, the fifth P-type semiconductor region is alternately disposed with the source region.

8. The semiconductor device as claimed in claim 6 or 7, characterized in that, The width of the fourth P-type semiconductor region is equal to the width of the first trench, and the trench spacing between two adjacent first trenches is equal to the width of the source region.

9. The semiconductor device as claimed in claim 5, characterized in that, At least one end of the second groove extends into the first groove located at the edge of the plurality of first grooves; The second trench has a third sidewall and a fourth sidewall disposed opposite to each other in the second direction; The third P-type semiconductor region is disposed on the third sidewall and / or the fourth sidewall of the second trench.

10. The semiconductor device as claimed in claim 9, characterized in that, The epitaxial layer further includes: a fifth P-type semiconductor region that is co-layered with the source region and alternately disposed with the corresponding source region, wherein the fifth P-type semiconductor region has the same doping concentration as the fourth P-type semiconductor region; The fifth P-type semiconductor region is in contact with the sidewall of at least one of the plurality of first trenches, and the fifth P-type semiconductor region is in contact with the corresponding source electrode through the contact hole.

11. The semiconductor device as claimed in claim 5, 6, 7, 9 or 10, characterized in that, The doping concentrations of the second P-type semiconductor region, the third P-type semiconductor region, and the fourth P-type semiconductor region are all greater than the doping concentration of the first P-type semiconductor region.

12. The semiconductor device as described in claim 5, 6, 7, 9 or 10, characterized in that, The projection of the second P-type semiconductor region onto the third direction covers the trench structure and the third P-type semiconductor region.

13. The semiconductor device as described in claim 4, 5, 6, 7, 9, or 10, characterized in that, The epitaxial layer further includes: a third N-type semiconductor region disposed between the first N-type semiconductor region and the semiconductor substrate, wherein the doping concentration of the third N-type semiconductor region is less than the doping concentration of the first N-type semiconductor region; The thickness of the second P-type semiconductor region is greater than 1 μm.

14. The semiconductor device as claimed in claim 4, 5, 6, 7, 9 or 10, characterized in that, The doping concentration of the semiconductor substrate is greater than the doping concentration of the second N-type semiconductor region, and the doping concentration of the second N-type semiconductor region is greater than the doping concentration of the first N-type semiconductor region.

15. The semiconductor device as described in claim 1, 2, 4, 5, 6, 7, 9, or 10, characterized in that, The semiconductor substrate and the epitaxial layer are made of SiC.

16. A method for fabricating a semiconductor device, characterized in that, include: An epitaxial layer is grown on an N-type semiconductor substrate; The epitaxial layer is etched to form a trench structure, the trench structure including a plurality of first trenches and a second trench. Each of the plurality of first trenches extends along a first direction parallel to the plane of the semiconductor substrate and is spaced apart along a second direction parallel to the plane of the semiconductor substrate. The second trench extends along the second direction and is intersected with each of the plurality of first trenches and is interconnected with each other. A gate dielectric layer and a gate electrode are sequentially formed within the trench structure; An interlayer dielectric layer covering the epitaxial layer is formed on the gate; The interlayer dielectric layer is etched to form a contact hole extending along the second direction. The contact hole exposes a portion of the epitaxial layer, and the projection of the contact hole in a third direction perpendicular to the plane of the semiconductor substrate does not overlap with the gate. The first direction, the second direction, and the third direction are arranged to intersect each other. A source electrode is formed on the interlayer dielectric layer, and the source electrode contacts the epitaxial layer exposed by the contact hole through the contact hole; A drain electrode is formed on the side of the semiconductor substrate away from the epitaxial layer.

17. The preparation method according to claim 16, characterized in that, After epitaxially growing an epitaxial layer on an N-type semiconductor substrate, the fabrication method further includes: Ion implantation is performed in a portion of the epitaxial layer to sequentially form a second N-type semiconductor region, a first P-type semiconductor region, and a source region. The region of the epitaxial layer that is not ion implanted forms the first N-type semiconductor region. The contact hole exposes a portion of the source region.

18. The preparation method according to claim 17, characterized in that, The epitaxial growth of the epitaxial layer on the N-type semiconductor substrate includes: An epitaxial layer of a first predetermined thickness is epitaxially grown on the N-type semiconductor substrate; The epitaxial layer is ion implanted using an ion implantation process to form a second P-type semiconductor region; On the epitaxial layer that forms the second P-type semiconductor region, epitaxial growth continues until an epitaxial layer of a second predetermined thickness is formed.

19. The preparation method according to claim 18, characterized in that, Also includes: Before the gate dielectric layer and the gate are sequentially formed in the trench structure, a tilted ion implantation process is used on at least one sidewall of the trench structure to form a third P-type semiconductor region that contacts the second P-type semiconductor region. An ion implantation process is used to form a fourth P-type semiconductor region in the epitaxial layer, which is disposed in the same layer as the source region.

20. A power conversion circuit, characterized in that, It includes a circuit board and one or more semiconductor devices as described in any one of claims 1-15, wherein the semiconductor devices are connected to the circuit board.

21. A vehicle, characterized in that, Includes the power conversion circuit as described in claim 20, the power conversion circuit being used to convert AC and / or DC power to output DC power.

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