Semiconductor device, method of manufacture, power conversion circuit, and vehicle

Abstract

The application discloses a semiconductor device, a preparation method, a power conversion circuit and a vehicle, comprising: an N-type semiconductor substrate, a first epitaxial layer, a plurality of gate trenches arranged at intervals, a gate, an interlayer dielectric layer, a source and a drain. The plurality of gate trenches are arranged in the first epitaxial layer; the plurality of gate trenches extend along a first direction; the gate comprises a first gate and a second gate in contact with each other, the first gate is filled in the gate trench through the gate dielectric layer, and the second gate is arranged on the top of the first epitaxial layer through the gate dielectric layer; the interlayer dielectric layer is arranged on the side of the gate away from the semiconductor substrate, and has a contact hole extending along a second direction; the source is arranged on the side of the interlayer dielectric layer away from the semiconductor substrate, and is in contact with the first epitaxial layer through the contact hole; and the drain is arranged on the side of the semiconductor substrate away from the first epitaxial layer. In this way, the total on-resistance of the device is reduced.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to semiconductor devices, fabrication methods, power conversion circuits, and vehicles. Background Technology

[0002] Silicon carbide (SiC) materials offer advantages over silicon (Si) materials, including a wider bandgap, higher critical breakdown electric field, higher thermal conductivity, and higher electron saturation drift velocity. Metal-oxide-semiconductor field-effect transistors (MOSFETs) made from SiC exhibit higher breakdown voltage and lower on-state voltage drop compared to insulated-gate bipolar transistors (IGBTs) made from Si. Furthermore, the unipolar conductivity of SiC MOSFETs results in faster switching speeds, lower conduction losses, and lower switching losses compared to Si IGBTs. Therefore, SiC MOSFETs have already replaced Si IGBTs in some applications, such as automotive microcontroller units (MCUs) and on-board battery chargers (OBCs).

[0003] Compared to conventional planar gate devices, SiC MOSFET devices employing trench gate structures embed the gate within the SiC body, shifting the conductive channel from a planar orientation to a vertical one. This significantly reduces the device's cell size and greatly increases the conductive channel density, thereby substantially reducing the chip's on-resistance and improving current-carrying capacity. Trench gate structures have become the mainstream technology for future devices. However, in trench-gate SiC MOSFET devices, there is a significant contradiction between the channel resistance and the junction field-effect transistor (JFET) resistance. (Refer to...) Figure 1 The horizontal axis represents the cell size, and the vertical axis represents the resistance. Figure 1 It is known that by reducing the spacing of the trench gate structure in SiC MOSFET devices, the cell size of SiC MOSFET devices can be reduced, the conductive channel density can be increased, and the channel resistance can be reduced. However, at the same time, the current-carrying width of the JFET region will also decrease, resulting in an increase in the resistance of the JFET region. Consequently, the overall on-resistance of the SiC MOSFET device will increase, reducing device performance and increasing chip losses. Summary of the Invention

[0004] The application provides a semiconductor device, a preparation method, a power conversion circuit and a vehicle, which are used for reducing the on-state total resistance of the device, improving the performance of the device and reducing the loss of the device.

[0005] In a first aspect, an embodiment of the application provides a semiconductor device, comprising: an N-type semiconductor substrate, a first epitaxial layer, a plurality of gate trenches arranged at intervals, a gate, an interlayer dielectric layer, a source and a drain. The first epitaxial layer is arranged on the semiconductor substrate, the plurality of gate trenches arranged at intervals are arranged in the first epitaxial layer, and the plurality of gate trenches extend into the first epitaxial layer in a third direction perpendicular to a plane in which the semiconductor substrate is located (for example, the first epitaxial layer comprises: a first N-type semiconductor region, a second N-type semiconductor region, a first P-type semiconductor region and a source region, the first N-type semiconductor region is arranged between the second N-type semiconductor region and the semiconductor substrate, the first P-type semiconductor region is arranged on a side of the first N-type semiconductor region away from the semiconductor substrate, and the source region is arranged on a side of the first P-type semiconductor region away from the semiconductor substrate, and in the third direction perpendicular to the plane in which the semiconductor substrate is located, the gate trench extends into the first N-type semiconductor region). The plurality of gate trenches extend in a first direction parallel to the plane in which the semiconductor substrate is located, and the plurality of gate trenches are arranged in a second direction parallel to the plane in which the semiconductor substrate is located, so as to form a closely arranged gate trench array in the first epitaxial layer. The gate comprises a first gate and a second gate in contact with each other, the first gate is arranged in the gate trench through a gate dielectric layer, so that the first gate is embedded in the first epitaxial layer of SiC material. The second gate is arranged on the top of the first epitaxial layer of SiC material through the gate dielectric layer. The first gate forms a trench gate structure of a SiC MOSFET device together with the first P-type semiconductor region through the gate dielectric layer, that is, the semiconductor device provided by the embodiment of the application is a SiC MOSFET with a trench gate structure. The interlayer dielectric layer is arranged on a side of the gate away from the semiconductor substrate, that is, the interlayer dielectric layer is arranged on a side of the entire semiconductor substrate having the gate. The source is arranged on a side of the interlayer dielectric layer away from the semiconductor substrate, that is, the source is arranged on the entire interlayer dielectric layer. The drain is arranged on a side of the semiconductor substrate away from the first epitaxial layer, that is, the drain is arranged on a side of the semiconductor substrate not provided with the first epitaxial layer. In actual application, a contact hole extending in the second direction can be arranged in the interlayer dielectric layer in order to transmit a signal between the source and the drain. In order to avoid the contact between the source and the gate, the contact hole is arranged not to overlap with the gate in the semiconductor substrate, that is, the contact hole and the gate do not overlap with each other in the third direction. The contact hole exposes part of the first epitaxial layer (for example, the contact hole exposes part of the source region), so that the source contacts the first epitaxial layer (for example, the source region) through the contact hole. When the gate controls the channel to be turned on, the signal can be transmitted between the source and the drain.

[0006] The semiconductor device provided by the embodiments of the present application is characterized in that: the array of gate trenches is closely arranged in the first epitaxial layer, and the first gate is arranged in the gate trench, and in the second direction, the part of the two sidewalls of the gate trench corresponding to the first gate is the channel. The extending direction of the contact hole arranged in the interlayer dielectric layer is the second direction, and the extending direction of the gate trench (or the first gate) is the first direction. Therefore, the extending direction of the contact hole is perpendicular to the extending direction of the gate trench (or the first gate), that is, the contact hole is arranged in the direction perpendicular to the gate trench (or the first gate). Compared with the prior art in which the gate trench and the contact hole are arranged in parallel, the semiconductor device provided by the embodiments of the present application reduces the restriction of the contact hole on the channel distance of the adjacent gate trench in the second direction, and enables the gate trench to be prepared more closely, that is, the first gate is also more closely arranged. Therefore, the gate trench array density of the semiconductor device provided by the embodiments of the present application can be much higher than that of the device structure in the prior art, thereby improving the channel density of the SiC MOSFET, significantly reducing the total on-resistance of the device, improving the performance of the device, and reducing the loss of the device.

[0007] In the present application, the semiconductor substrate can be a silicon carbide single crystal substrate doped with a pentavalent element. The first epitaxial layer can be formed by epitaxial growth of SiC material doped with corresponding impurities. For example, the first N-type semiconductor region is a part of the first epitaxial layer formed by epitaxial growth, and the second N-type semiconductor region and the source region can be formed by doping the first epitaxial layer by ion implantation process. Moreover, the N-type semiconductor region is mainly doped with N-type impurities, such as nitrogen (N), phosphorus (P) or arsenic (As), etc. For example, the doping concentration of the semiconductor substrate is greater than that of the second N-type semiconductor region, the doping concentration of the second N-type semiconductor region is greater than that of the first N-type semiconductor region, and the doping concentration of the source region is greater than that of the second N-type semiconductor region.

[0008] In the present application, the first P-type semiconductor region can be formed by doping the first epitaxial layer by ion implantation process. Moreover, the P-type semiconductor region is mainly doped with P-type impurities, such as boron (B), aluminum (Al) or gallium (Ga), etc.

[0009] For example, the first gate is arranged in the gate trench, which is equivalent to that the first gate extends in the first direction. The second gate can be arranged to extend in the second direction, so that a part of the second gate is arranged on the first epitaxial layer through the gate dielectric layer, and the other part is arranged on the first gate and directly contacts the first gate.

[0010] The material of the gate is not limited in the present application. For example, the material of the gate can be polysilicon material, or other materials with good conductive properties, such as metal (e.g. W, Al, Ti, Cu, Mo or Pt).

[0011] The application does not limit the material forming the interlayer dielectric layer. For example, the material forming the interlayer dielectric layer can be a dielectric material, including but not limited to silicon dioxide (SiO2), silicon oxynitride (SiNO), silicon oxycarbide (SiCO), silicon nitride (SiNx), etc.

[0012] The application does not limit the material forming the source and drain. For example, the material forming the source and drain can be a metal material. Illustratively, the metal material can include W, Al, Ti, Cu, Mo or Pt.

[0013] In the application, the first direction, the second direction and the third direction are arranged to intersect with each other. For example, the first direction, the second direction and the third direction are arranged to be perpendicular to each other.

[0014] The semiconductor device provided by the embodiments of the application has the third P-type semiconductor region arranged at the first sidewall and the second sidewall of the gate trench, so that the first P-type semiconductor region arranged at the first sidewall and the second sidewall of the gate trench (i.e. the first P-type semiconductor region below the fourth P-type semiconductor region) does not have the channel performance controlled by the first gate. Therefore, in the second direction, the part of the sidewall of the gate trench corresponding to the first gate is the channel.

[0015] In some possible embodiments of the application, the plurality of gate trenches in the semiconductor device can be divided into one or more groups of trenches, and the contact hole is provided as two or more. In addition, one group of trenches is arranged between the two adjacent contact holes, and the contact hole penetrates the group of trenches in the second direction, so that the signal flows more uniformly.

[0016] In some possible embodiments of the application, the number of gate trenches in different groups of trenches can be the same. In this way, the gate trenches can be uniformly distributed. Illustratively, five gate trenches are arranged in each of the different groups of trenches. It should be noted that in actual application, the number of gate trenches in the group of trenches can be determined according to the requirements of actual application, and the application does not limit this.

[0017] In some possible embodiments of the application, the number of gate trenches in part of the groups of trenches can be the same, and the number of gate trenches in the remaining groups of trenches can be different. Alternatively, the number of gate trenches in different groups of trenches can be different. In actual application, the number of gate trenches in the group of trenches can be determined according to the requirements of actual application, and the application does not limit this.

[0018] In some possible implementation of the present application, in the second direction, two gate trenches at the edge in the trench group are defined as a first edge trench and a second edge trench respectively, and the contact hole extends from the side of the first edge trench away from the second edge trench to the side of the second edge trench away from the first edge trench in the second direction. That is, the contact hole is a continuous opening, and the gate trenches in different trench groups are not through.

[0019] The semiconductor device provided by the embodiments of the present application is a trench gate structure SiC MOSFET device. In the trench gate structure SiC MOSFET device, the gate dielectric layer at the bottom and the corner of the trench gate structure will bear extremely high electric field intensity when the device is working, which is a weak point of electric field breakdown and is easy to cause long-term working reliability failure of the device. Therefore, how to effectively shield the gate dielectric layer from high electric field stress becomes the key to the high robustness / reliability design of the device. In some possible implementation of the present application, a second P-type semiconductor region is further arranged in the first epitaxial layer. The second P-type semiconductor region is arranged below the gate trench, and the second P-type semiconductor region is in direct contact with the bottom end of the gate trench. In the present application, the second P-type semiconductor region can be connected with the source. When the SiC MOSFET device is working, the source will be loaded with voltage. Since the second P-type semiconductor region is connected with the source, the voltage loaded on the source will be input into the second P-type semiconductor region, so that the second P-type semiconductor region also has a corresponding voltage, thereby effectively shielding the electric field of the gate dielectric layer at the bottom of the gate trench, and further improving the robustness of the device working.

[0020] The present application does not limit the thickness of the second P-type semiconductor region in the third direction x. For example, the thickness of the second P-type semiconductor region in the third direction can be less than 1 um, for example, the thickness of the second P-type semiconductor region in the third direction can be 0.3 um to 0.8 um.

[0021] Exemplarily, when the SiC MOSFET provided by the embodiments of the present application is applied to a power conversion circuit, the source of the SiC MOSFET can be grounded, and the drain can be connected with other elements, so that the voltage of the source of the SiC MOSFET is the ground voltage (0V). Since the second P-type semiconductor region is connected with the source, the voltage of the second P-type semiconductor region is also the ground voltage, thereby effectively shielding the electric field of the gate dielectric layer at the bottom of the gate trench, and further improving the robustness of the device working.

[0022] Exemplarily, when the SiC MOSFET provided by the embodiment of the present application is applied to a power conversion circuit, the source of the SiC MOSFET can also be connected to other elements, and the drain of the SiC MOSFET can also be connected to other elements, and the voltage of the source of the SiC MOSFET is the voltage of the input signal of the other elements. Since the second P-type semiconductor region is connected to the source, the voltage of the second P-type semiconductor region is also the voltage of the input signal, so that the electric field of the gate dielectric layer at the bottom of the gate trench can be effectively shielded, and the robustness of the device in operation is improved.

[0023] In some possible implementation of the present application, the first epitaxial layer further comprises: a third P-type semiconductor region and a fourth P-type semiconductor region. The third P-type semiconductor region is arranged at the sidewall of the gate trench along the first direction, and the fourth P-type semiconductor region is arranged in the same layer as the source region. The first P-type semiconductor region, the second P-type semiconductor region, the third P-type semiconductor region and the fourth P-type semiconductor region can be formed by doping the first epitaxial layer through an ion implantation process. In addition, the P-type impurities doped in the P-type semiconductor region are mainly P-type impurities such as boron (B), aluminum (Al) or gallium (Ga).

[0024] Exemplarily, the doping concentration of the second P-type semiconductor region, the third P-type semiconductor region and the fourth P-type semiconductor region is greater than the doping concentration of the first P-type semiconductor region. Alternatively, the doping concentration of the second P-type semiconductor region, the third P-type semiconductor region and the fourth P-type semiconductor region can be the same or similar. Of course, the doping concentration of the second P-type semiconductor region, the third P-type semiconductor region and the fourth P-type semiconductor region can also be different from at least two. It should be noted that the doping concentration of the second P-type semiconductor region, the third P-type semiconductor region and the fourth P-type semiconductor region can be determined according to the requirements of the actual application environment, which is not limited herein.

[0025] In some possible implementation of the present application, the third P-type semiconductor region and the second P-type semiconductor region are in contact with each other, the fourth P-type semiconductor region is in contact with the third P-type semiconductor region, and the fourth P-type semiconductor region is in contact with the source through the contact hole. The source is connected to the second P-type semiconductor region through the fourth P-type semiconductor region and the third P-type semiconductor region in sequence, so that the voltage loaded on the source is input to the second P-type semiconductor region through the fourth P-type semiconductor region and the third P-type semiconductor region in sequence, thereby the electric field of the gate dielectric layer at the bottom of the gate trench can be effectively shielded, and the robustness of the device in operation is improved.

[0026] In some possible embodiments of the present application, in the first direction, the gate trench has oppositely arranged first and second sidewalls; the first epitaxial layer further comprises at least one third P-type semiconductor region and at least one fourth P-type semiconductor region. Wherein, the first and / or second sidewall of at least one gate trench is provided with one of the at least one third P-type semiconductor region, and all the third P-type semiconductor regions are in contact with the second P-type semiconductor region. Moreover, the fourth P-type semiconductor region is co-layered with the source region, the at least one fourth P-type semiconductor region is in one-to-one correspondence with and in contact with the at least one third P-type semiconductor region, and the fourth P-type semiconductor region is arranged on the side of the corresponding third P-type semiconductor region away from the gate trench, and the fourth P-type semiconductor region is in contact with the corresponding source electrode through the contact hole.

[0027] Exemplarily, in the first direction, the gate trench has oppositely arranged first and second sidewalls. The third P-type semiconductor region is provided in multiple, and each first sidewall of each gate trench is provided with one of the multiple third P-type semiconductor regions, and each second sidewall of each gate trench is also provided with one of the multiple third P-type semiconductor regions. That is, the first and second sidewalls of each gate trench are respectively provided with the third P-type semiconductor region. Moreover, the third P-type semiconductor regions are all in contact with the second P-type semiconductor region, so that the third P-type semiconductor regions can be connected with the second P-type semiconductor region for signal transmission, and the voltage of the third P-type semiconductor region is the same as that of the second P-type semiconductor region.

[0028] Exemplarily, the fourth P-type semiconductor region is also provided in multiple, and the multiple fourth P-type semiconductor regions are in one-to-one correspondence with and in contact with the multiple third P-type semiconductor regions. Wherein, each of the third P-type semiconductor regions arranged on the first sidewall is correspondingly provided with one of the multiple fourth P-type semiconductor regions, and the fourth P-type semiconductor region is arranged on the side of the third P-type semiconductor region away from the first sidewall of the gate trench. And, each of the third P-type semiconductor regions arranged on the second sidewall is also correspondingly provided with one of the multiple fourth P-type semiconductor regions, and the fourth P-type semiconductor region is arranged on the side of the third P-type semiconductor region away from the second sidewall of the gate trench. The source electrode is connected with the second P-type semiconductor region through the fourth P-type semiconductor region and the third P-type semiconductor region arranged in correspondence with each other in sequence, so that the voltage loaded on the source electrode is input to the second P-type semiconductor region through the fourth P-type semiconductor region and the third P-type semiconductor region in sequence, so that the second P-type semiconductor region has a voltage, thereby effectively shielding the gate dielectric layer electric field at the bottom of the gate trench, and further improving the robustness of the device operation.

[0029] Exemplarily, the semiconductor device provided by the embodiments of the present application is provided with multiple source regions, and the multiple source regions and the multiple fourth P-type semiconductor regions are alternately arranged at the same end of the gate trenches. For example, the multiple source regions and the multiple fourth P-type semiconductor regions are alternately arranged at the first sidewall of the gate trenches in the same trench group. In addition, the multiple source regions and the multiple fourth P-type semiconductor regions are alternately arranged at the second sidewall of the gate trenches in the same trench group.

[0030] The present application does not limit the width of the fourth P-type semiconductor region along the second direction, for example, the width of the fourth P-type semiconductor region along the second direction can be the same as or similar to the trench width. Of course, the width of the fourth P-type semiconductor region along the second direction can also be different from the trench width, which is not limited herein.

[0031] In some possible embodiments of the present application, in the third direction, the second P-type semiconductor region covers the gate trenches and the third P-type semiconductor regions. That is, the orthographic projection of the second P-type semiconductor region on the semiconductor substrate covers not only the orthographic projection of all the gate trenches on the semiconductor substrate, but also the orthographic projection of all the third P-type semiconductor regions on the semiconductor substrate.

[0032] In some possible embodiments of the present application, the second P-type semiconductor region is a planar region extending along the second direction. In addition, the present application does not limit the shape of the second P-type semiconductor region, for example, the shape of the second P-type semiconductor region can be set as a rectangle.

[0033] Exemplarily, in the third direction, the orthographic projection of the second P-type semiconductor region on the semiconductor substrate also covers the gap between the orthographic projections of the adjacent two gate trenches on the semiconductor substrate. That is, the orthographic projection of the second P-type semiconductor region on the semiconductor substrate also covers the orthographic projection of the gap between the adjacent two gate trenches in the second direction on the semiconductor substrate.

[0034] Optionally, one trench group is correspondingly provided with one second P-type semiconductor region. That is, if one trench group is provided, a planar region of one second P-type semiconductor region is correspondingly provided. If two trench groups are provided, a planar region of two second P-type semiconductor regions is correspondingly provided. In addition, the two second P-type semiconductor regions have a gap therebetween. If multiple trench groups are provided, a planar region of multiple second P-type semiconductor regions is correspondingly provided. In addition, each adjacent two second P-type semiconductor regions have a gap therebetween.

[0035] In the second direction, there is a trench spacing between two adjacent gate trenches. The application does not limit the specific value of the trench spacing, for example, the trench spacing is less than 1 um. Optionally, the range of the trench spacing is 50 nm-0.5 um. It should be noted that when the trench spacing is less than 100 nm, the semiconductor device provided by the application will form a Fin Field-Effect Transistor (Fin FET) effect, which can significantly improve the carrier channel mobility and further reduce the total resistance of the device.

[0036] In the first direction, the gate trench has a trench length. The application does not limit the trench length, for example, the trench length is greater than 5 um.

[0037] In the second direction, the gate trench has a trench width. The application does not limit the trench width, for example, the trench width is less than 1 um.

[0038] In the first direction, the contact hole has a contact width, which can make the trench spacing not greater than the contact width. Of course, the trench spacing can also be greater than the contact width. In actual application, the trench spacing and the contact width can be determined according to the actual application environment requirements, which are not limited here.

[0039] The application does not limit the width of the source region along the second direction, for example, the width of the source region along the second direction can be the same or similar to the trench spacing, which is not limited here.

[0040] In the semiconductor device provided by the embodiment of the application, the first P-type semiconductor region at the two side walls of the gate trench of the trench gate structure in the second direction forms the channel region of the SiC MOSFET, so that by increasing the trench width or reducing the trench spacing, the conductive channel density of the SiC MOSFET device can be improved, and the total on-resistance of the SiC MOSFET device can be reduced.

[0041] In some possible embodiments of the application, the semiconductor device includes: an N-type semiconductor substrate, a first epitaxial layer, a plurality of gate trenches arranged at intervals, a gate, an interlayer dielectric layer, a source, and a drain. Moreover, the first epitaxial layer includes: a first N-type semiconductor region, a second N-type semiconductor region, a first P-type semiconductor region, a source region, a second P-type semiconductor region, a third P-type semiconductor region, and a fourth P-type semiconductor region. The embodiment is a transformation of the embodiment in the above embodiment. Only the differences between the embodiment and the above embodiment will be described below, and the same parts will not be described here.

[0042] In the embodiment, a spacing region is provided between the second P-type semiconductor region and the bottom end of the gate trench. That is, the second P-type semiconductor region at the bottom of the gate trench is not in direct contact with the bottom of the gate trench, but is connected to the bottom of the gate trench through the spacing region. Exemplarily, the spacing region is an N-type semiconductor region, and the doping concentration of the spacing region is the same as or similar to that of the first N-type semiconductor region. Alternatively, the spacing region is part of the first N-type semiconductor region.

[0043] In the embodiment, the spacing region can serve as a flow path of the on-state current of the SiC MOSFET device, can increase the on-current area of the SiC MOSFET device, and further reduce the total on-state resistance of the SiC MOSFET device.

[0044] In some possible embodiments of the present application, the semiconductor device comprises an N-type semiconductor substrate, a first epitaxial layer, a plurality of gate trenches arranged at intervals, a gate, an interlayer dielectric layer, a source and a drain. The first epitaxial layer comprises a first N-type semiconductor region, a second N-type semiconductor region, a first P-type semiconductor region, a source region, a second P-type semiconductor region, a third P-type semiconductor region and a fourth P-type semiconductor region. The present embodiment is a variation of the embodiment in the above embodiment. Only the differences between the present embodiment and the above embodiment will be described below, and the same parts will not be described herein.

[0045] In the embodiment, a plurality of third P-type semiconductor regions are provided, one third P-type semiconductor region of the plurality of third P-type semiconductor regions is arranged on the first sidewall of each gate trench, and the second sidewall of each gate trench is not provided with a third P-type semiconductor region. That is, the third P-type semiconductor regions are arranged only on the first sidewall of each gate trench, respectively. Moreover, the third P-type semiconductor regions are all in contact with the second P-type semiconductor region, so that the third P-type semiconductor regions can be connected to the second P-type semiconductor region for signal transmission, and the voltage of the third P-type semiconductor regions is the same as that of the second P-type semiconductor region.

[0046] Exemplarily, a plurality of fourth P-type semiconductor regions are also provided, which are one-to-one corresponding to and in contact with the plurality of third P-type semiconductor regions. Each of the third P-type semiconductor regions provided on the first side wall of the gate trench corresponds to one of the plurality of fourth P-type semiconductor regions, and the fourth P-type semiconductor region is provided on the side of the third P-type semiconductor region away from the first side wall of the gate trench. The source is connected to the second P-type semiconductor region through the fourth P-type semiconductor region and the third P-type semiconductor region in sequence, so that the voltage loaded on the source is input to the second P-type semiconductor region through the fourth P-type semiconductor region and the third P-type semiconductor region in sequence, so that the second P-type semiconductor region has a voltage, thereby effectively shielding the gate dielectric layer electric field at the bottom of the gate trench, and further improving the robustness of the device.

[0047] Exemplarily, the first epitaxial layer further comprises: a fifth P-type semiconductor region, the fifth P-type semiconductor region is provided in the same layer as the source region, the fifth P-type semiconductor region is provided on the side of the second side wall of the gate trench away from the first side wall, and the fifth P-type semiconductor region is in contact with the source through the contact hole.

[0048] Exemplarily, the fifth P-type semiconductor region is a plurality of fifth P-type semiconductor regions, which are one-to-one corresponding to the second side walls of the plurality of gate trenches, that is, the second side wall of one gate trench is one-to-one corresponding to one fifth P-type semiconductor region. Alternatively, the plurality of source regions and the plurality of fifth P-type semiconductor regions on the second side wall of the gate trench are alternately arranged. That is, the plurality of source regions and the plurality of fifth P-type semiconductor regions on the same side wall of the gate trench are alternately arranged along the second direction.

[0049] Exemplarily, the fifth P-type semiconductor region is a plurality of fifth P-type semiconductor regions, which are one-to-one corresponding to the second side walls of the plurality of gate trenches, that is, the second side wall of one gate trench is one-to-one corresponding to one fifth P-type semiconductor region. Alternatively, the source region is a plurality of source regions, and the gate trench and the plurality of source regions are alternately arranged. That is, the gate trench and the source region are alternately arranged along the second direction.

[0050] Alternatively, the fifth P-type semiconductor region can be formed by doping the first epitaxial layer through an ion implantation process. Moreover, the fifth P-type semiconductor region is mainly doped with P-type impurities, such as boron (B), aluminum (Al) or gallium (Ga), etc. Exemplarily, the doping concentration of the fifth P-type semiconductor region is the same as or similar to the doping concentration of the fourth P-type semiconductor region.

[0051] In the embodiment of the present application, the third P-type semiconductor region is provided at the first side wall of the gate trench, and no channel is formed.

[0052] In some possible embodiments of the present application, a semiconductor device includes an N-type semiconductor substrate, a first epitaxial layer, a plurality of gate trenches arranged in a spaced-apart manner, a gate, an interlayer dielectric layer, a source, and a drain. The first epitaxial layer includes a first N-type semiconductor region, a second N-type semiconductor region, a first P-type semiconductor region, a source region, a second P-type semiconductor region, a third P-type semiconductor region, and a fourth P-type semiconductor region. The present embodiment is a variation of the embodiments in the above embodiments. Only the differences between the present embodiment and the above embodiments are described below, and the same parts are not described herein.

[0053] In the present embodiment, a plurality of third P-type semiconductor regions are arranged, one third P-type semiconductor region of the plurality of third P-type semiconductor regions is arranged on the first sidewall of each gate trench, and the second sidewall of each gate trench is not provided with a third P-type semiconductor region. That is, the third P-type semiconductor regions are arranged only on the first sidewall of each gate trench, respectively. In addition, the third P-type semiconductor regions are in contact with the second P-type semiconductor region, so that the third P-type semiconductor regions are connected to the second P-type semiconductor region for signal transmission, and the voltage of the third P-type semiconductor regions is the same as that of the second P-type semiconductor region.

[0054] Exemplarily, a plurality of fourth P-type semiconductor regions are arranged, and the plurality of fourth P-type semiconductor regions are arranged in a one-to-one correspondence with the plurality of third P-type semiconductor regions. Each of the third P-type semiconductor regions arranged on the first sidewall is provided with one of the plurality of fourth P-type semiconductor regions, and the fourth P-type semiconductor region is arranged on the side of the third P-type semiconductor region away from the first sidewall of the gate trench. In this way, the source is sequentially connected to the second P-type semiconductor region through the fourth P-type semiconductor region and the third P-type semiconductor region arranged in a corresponding manner, so that the voltage loaded on the source is input to the second P-type semiconductor region through the fourth P-type semiconductor region and the third P-type semiconductor region, and the second P-type semiconductor region has a voltage, thereby effectively shielding the gate dielectric layer field at the bottom of the gate trench, and further improving the robustness of the device operation.

[0055] Exemplarily, the fourth P-type semiconductor regions are arranged only on the first sidewall of the gate trench, and the source regions are arranged on the second sidewall of the gate trench. The first P-type semiconductor region on the second sidewall of the gate trench can be controlled by the first gate to form a channel, and the source region is arranged on the second sidewall of the gate trench, so that the conduction current can be transmitted from the first P-type semiconductor region on the second sidewall of the gate trench to the drain, further improving the flow path of the conduction current.

[0056] In some possible embodiments of the present application, the semiconductor device comprises: a semiconductor substrate of N type, a first epitaxial layer, a plurality of gate trenches arranged in mutual spaces, a gate, an interlayer dielectric layer, a source and a drain. The first epitaxial layer comprises: a first N-type semiconductor region, a second N-type semiconductor region, a first P-type semiconductor region, a source region, a second P-type semiconductor region, a third P-type semiconductor region and a fourth P-type semiconductor region. The present embodiment is a variation of the embodiments in the above-mentioned embodiments. Only the differences between the present embodiment and the above-mentioned embodiments are described below, and the same parts are not described herein again.

[0057] Exemplarily, the plurality of gate trenches comprise a first gate trench and a second gate trench which penetrate along the first direction, wherein the first gate trench and the second gate trench are respectively located in two adjacent trench groups. That is, the first gate trench is located in one of the two adjacent trench groups, the second gate trench is located in the other of the two adjacent trench groups, and the first gate trench and the second gate trench penetrate each other.

[0058] Exemplarily, in at least part of the gate trenches in the two adjacent trench groups, the gate trenches arranged along the first direction penetrate.

[0059] Exemplarily, the contact hole comprises a plurality of sub-contact holes arranged in mutual spaces, and at least one penetrating gate trench is arranged between two adjacent sub-contact holes in the same contact hole. The present application does not limit the number of the sub-contact holes divided by the contact hole, which can be two, three, four or more. And the present application does not limit the number of the penetrating gate trenches arranged between two adjacent sub-contact holes in the same contact hole, which can be one, two, three, four or more. In this way, the design freedom of the contact hole can be improved, and the current uniformity of the SiC MOSFET device can be improved.

[0060] In some possible embodiments of the present application, the semiconductor device comprises: a semiconductor substrate of N type, a first epitaxial layer, a second epitaxial layer, a plurality of gate trenches arranged in mutual spaces, a gate, an interlayer dielectric layer, a source and a drain. The first epitaxial layer comprises: a first N-type semiconductor region, a second N-type semiconductor region, a first P-type semiconductor region, a source region, a second P-type semiconductor region, a third P-type semiconductor region and a fourth P-type semiconductor region. The present embodiment is a variation of the embodiments in the above-mentioned embodiments. Only the differences between the present embodiment and the above-mentioned embodiments are described below, and the same parts are not described herein again.

[0061] In the embodiment, the second epitaxial layer is arranged between the first epitaxial layer (for example, the first N-type semiconductor region) and the semiconductor substrate. Since the second epitaxial layer is arranged, the thickness of the second P-type semiconductor region in the first epitaxial layer in the third direction can be arranged to be relatively thick, for example, the thickness of the second P-type semiconductor region in the third direction can be arranged to be greater than 1 um.

[0062] In the embodiment, the second epitaxial layer is an N-type semiconductor region. For example, the second epitaxial layer is SiC doped with an N-type impurity, for example, nitrogen (N), phosphorus (P), or arsenic (As), etc. For example, the doping concentration of the second epitaxial layer is less than the doping concentration of the first N-type semiconductor region.

[0063] In a second aspect, the embodiments of the present application further provide a method for manufacturing a semiconductor device, which can include the following steps:

[0064] The first epitaxial layer is epitaxially grown on the N-type semiconductor substrate. The first epitaxial layer is etched to form a plurality of gate trenches arranged in the first epitaxial layer and spaced from each other in a third direction perpendicular to the plane in which the semiconductor substrate lies. The plurality of gate trenches extend in a first direction parallel to the plane in which the semiconductor substrate lies, the plurality of gate trenches are arranged in a second direction parallel to the plane in which the semiconductor substrate lies, and the first direction, the second direction and the third direction are arranged to intersect each other.

[0065] The gate dielectric layer is formed in the gate trench.

[0066] The first gate of the gate is formed in the gate trench in which the gate dielectric layer is formed, and the second gate of the gate is formed on the top of the first epitaxial layer, and the first gate and the second gate are in contact with each other.

[0067] The interlayer dielectric layer covering the entire first epitaxial layer is formed on the gate.

[0068] The interlayer dielectric layer is etched to form a contact hole extending in the second direction. The contact hole exposes a part of the first epitaxial layer, and the contact hole does not overlap with the projection of the semiconductor substrate and the projection of the gate on the semiconductor substrate.

[0069] The source is formed on the side of the interlayer dielectric layer away from the semiconductor substrate, and the source is in contact with the source region through the contact hole. The drain is formed on the side of the semiconductor substrate away from the first epitaxial layer.

[0070] In some possible implementation manners, in order to form the first epitaxial layer, the first epitaxial layer is epitaxially grown on the N-type semiconductor substrate, which can include the following steps:

[0071] First, a first epitaxial layer reaching a first set thickness (i.e. thickness in the third direction) is epitaxially grown on the N-type SiC semiconductor substrate. Exemplarily, by using an epitaxial process, SiC material doped with N-type impurities is epitaxially grown on the N-type SiC semiconductor substrate to form the first epitaxial layer reaching the first set thickness. The present application does not limit the specific value of the first set thickness. In practical applications, the specific value of the first set thickness can be determined according to the requirements of the practical application environment.

[0072] Then, the first epitaxial layer is ion implanted by using an ion implantation process to form the second P-type semiconductor region. Exemplarily, by using an ion implantation process, P-type impurities are doped in the first epitaxial layer corresponding to the second P-type semiconductor region to be formed to form the second P-type semiconductor region in a planar region. The present application does not limit the thickness (i.e. thickness in the third direction) of the second P-type semiconductor region. In practical applications, the specific value of the thickness of the second P-type semiconductor region can be determined according to the requirements of the practical application environment.

[0073] Then, on the first epitaxial layer on which the second P-type semiconductor region is formed, epitaxial growth is continued until the first epitaxial layer reaching a second set thickness is formed. Exemplarily, by using an epitaxial process, SiC material doped with N-type impurities is epitaxially grown on the first epitaxial layer on which the second P-type semiconductor region is formed to form the first epitaxial layer reaching the second set thickness.

[0074] In some possible implementation, after the first epitaxial layer is epitaxially grown on the N-type semiconductor substrate, the method further includes the following steps: performing ion implantation on a part of the first epitaxial layer by using an ion implantation process to form the second N-type semiconductor region, the first P-type semiconductor region and the source region, and the region of the first epitaxial layer on which ion implantation is not performed forms the first N-type semiconductor region. For example, in order to form the second N-type semiconductor region, the first P-type semiconductor region and the source region, the region of the first epitaxial layer on which ion implantation is not performed forms the first N-type semiconductor region. The ion implantation process is performed on a part of the first epitaxial layer to form the second N-type semiconductor region, the first P-type semiconductor region and the source region, and the region of the first epitaxial layer on which ion implantation is not performed forms the first N-type semiconductor region, which can include the following steps: performing N-type impurity doping on the surface of the first epitaxial layer by using an ion implantation process to form the second N-type semiconductor region. Then, P-type impurity doping is performed on the surface of the first epitaxial layer by using an ion implantation process to form the first P-type semiconductor region. Then, N-type impurity doping is performed on the surface of the first epitaxial layer by using an ion implantation process to form the source region, and P-type impurity doping is performed on the surface of the first epitaxial layer at the first side wall and the second side wall of the gate trench to form the fourth P-type semiconductor region arranged in the same layer as the source region. Therefore, in the embodiment of the present application, after the ion implantation process, a part of the first epitaxial layer forms the second N-type semiconductor region, the first P-type semiconductor region, the source region and the fourth P-type semiconductor region, and the region of the first epitaxial layer on which the ion implantation process is not performed forms the first N-type semiconductor region.

[0075] In some possible implementation, in order to form the gate trench, the first epitaxial layer is etched to the first N-type semiconductor region to form a plurality of gate trenches arranged at intervals in the first epitaxial layer, which can include the following steps: first, a trench mask (which can be a mask formed by using photoresist or a hard mask plate) is formed on the first epitaxial layer, the region of the first epitaxial layer on which the gate trench is to be formed is exposed by covering the region of the first epitaxial layer on which the gate trench is to be formed by the trench mask. Then, a suitable etching process is selected from the etching processes such as plasma etching process, ion sputtering etching process and reactive ion etching process, and the region of the first epitaxial layer which is not covered by the trench mask is etched until the first N-type semiconductor region is etched and the second P-type semiconductor region is exposed, and the etching is stopped to form a plurality of gate trenches extending along the first direction and arranged along the second direction in the first epitaxial layer.

[0076] In some possible implementation manners, after the first epitaxial layer is etched to the first N-type semiconductor region, and the plurality of gate trenches are formed in the first epitaxial layer, before the gate dielectric layer is formed in the gate trenches, the method further includes the following step: using a tilted ion implantation process, a third P-type semiconductor region in contact with the second P-type semiconductor region is formed on the first sidewall and the second sidewall of each gate trench along the first direction. For example, to form the third P-type semiconductor region in contact with the second P-type semiconductor region on the first sidewall and the second sidewall of each gate trench along the first direction using the tilted ion implantation process, the following step can be included: using the tilted ion implantation process, P-type impurities are doped on the surfaces of the first sidewall and the second sidewall of each gate trench, to form the third P-type semiconductor region in contact with the second P-type semiconductor region.

[0077] In some possible implementation manners, to form the gate dielectric layer, the gate dielectric layer can be formed in the gate trenches by using an oxidation process to perform oxidation treatment on the entire first epitaxial layer, so that the surface of the first epitaxial layer forms the gate dielectric layer. That is, the surface of each gate trench forms the gate dielectric layer, and the side of the first epitaxial layer away from the semiconductor substrate also forms the gate dielectric layer.

[0078] In some possible implementation manners, to form the gate, the first gate of the gate is formed in the gate trench in which the gate dielectric layer is formed, and the second gate of the gate is formed on the top of the first epitaxial layer, and the first gate and the second gate are in contact with each other, the following steps can be included: first, a deposition process is used to deposit a polysilicon material on the entire first epitaxial layer in which the gate trench is formed, and the polysilicon material fills the gate trench, and after the gate trench is filled with the polysilicon material, a polysilicon material film layer covers the entire first epitaxial layer. Then, a gate mask (which can be a mask formed by photoresist or a hard mask plate) is formed on the first epitaxial layer, and the area in which the second gate is to be formed is covered by the gate mask, and the remaining area is exposed. Then, a suitable etching process is selected from an ion etching process, a plasma etching process, a reactive ion etching process, and the like, to etch the polysilicon material area that is not covered by the trench mask, until the etching stops when the source region and the fourth P-type semiconductor region are exposed, to form the first gate and the second gate.

[0079] In some possible implementation manners, to form the interlayer dielectric layer, the interlayer dielectric layer covering the entire first epitaxial layer is formed on the gate, the following steps can be included: using a deposition process, the interlayer dielectric layer is deposited on the entire first epitaxial layer, and the interlayer dielectric layer covers the entire first epitaxial layer.

[0080] In some possible implementation manners, to form the contact hole, etching the interlayer dielectric layer to form the contact hole extending along the second direction can include the following steps: first, forming a contact hole mask (which can be a mask formed by using photoresist or a hard mask plate) on the first epitaxial layer, covering the area where the contact hole is not needed to be formed by the contact hole mask, and exposing the area where the contact hole is needed to be formed. Then, selecting a suitable etching process from the etching processes such as a plasma etching process, an ion sputtering etching process and a reactive ion etching process, and etching the area of the interlayer dielectric layer not covered by the contact hole mask to expose part of the source region (for example, the part of the source region located on both sides of the first gate in the first direction) and part of the fourth P-type semiconductor region located on both sides of the first gate.

[0081] In some possible implementation manners, to form the source and the drain, the source is formed on the side of the interlayer dielectric layer away from the semiconductor substrate and is in contact with the source region through the contact hole, and the drain is formed on the side of the semiconductor substrate away from the first epitaxial layer. The forming can include the following steps: depositing a metal material on the side of the interlayer dielectric layer away from the semiconductor substrate by using a deposition process to form the source. The source is in contact with the source region through the metal material filled in the contact hole. For example, when the source is formed, a metal material can be deposited on the side of the semiconductor substrate away from the first epitaxial layer by using a deposition process to form the drain. Alternatively, the drain can also be formed by depositing a metal material on the side of the semiconductor substrate away from the first epitaxial layer by using a deposition process after the source is formed.

[0082] The application does not limit the material of the source and the drain. For example, the material of the source and the drain can be a metal material. For example, the metal material can include W, Al, Ti, Cu, Mo or Pt.

[0083] In a third aspect, the embodiments of the application further provide a power conversion circuit, which can be an alternating current-direct current conversion circuit and / or a direct current-direct current conversion circuit. The power conversion circuit can include a circuit board and one or more semiconductor devices, and the semiconductor devices are connected to the circuit board. The semiconductor devices can be the semiconductor devices in the first aspect or various possible designs of the first aspect, or the semiconductor devices prepared by using the second aspect or various possible designs of the second aspect. Since the semiconductor devices have good performance, the power conversion circuit including the semiconductor devices also has good performance. The power conversion circuit solves problems by similar principles to the semiconductor devices, and the technical effects of the power conversion circuit can be referred to the technical effects of the semiconductor devices, and the repeated parts will not be described herein.

[0084] In a fourth aspect, the embodiments of the present application further provide a vehicle, which can comprise a power conversion circuit. The power conversion circuit can be the power conversion circuit as described in the third aspect or any possible design of the third aspect. Since the power conversion circuit has good performance, the circuit of the vehicle comprising the power conversion circuit also has good performance. The vehicle has similar problem solving principles as the power conversion circuit, and thus the technical effects of the vehicle can refer to those of the power conversion circuit, and the repeated parts will not be described herein. BRIEF DESCRIPTION OF DRAWINGS

[0085] Figure 1 A relationship diagram between channel region resistance and JFET region resistance in a SiC MOSFET device;

[0086] Figure 2a A structural schematic diagram of an electric vehicle according to an embodiment of the present application;

[0087] Figure 2b A structural schematic diagram of an electronic device according to an embodiment of the present application;

[0088] Figure 3 A top view structural schematic diagram of a semiconductor device according to an embodiment of the present application;

[0089] Figure 4 A cross-sectional structural schematic diagram of the semiconductor device shown in Figure 3 along the direction of the tangent AA';

[0090] Figure 5 A cross-sectional structural schematic diagram of the semiconductor device shown in Figure 3 along the direction of the tangent BB';

[0091] Figure 6 A cross-sectional structural schematic diagram of the semiconductor device shown in Figure 3 along the direction of the tangent VV';

[0092] Figure 7 A partial three-dimensional structural schematic diagram of the semiconductor device shown in Figure 3

[0093] A three-dimensional structural schematic diagram of the semiconductor device shown in Figure 8 Figure 7 A three-dimensional structural schematic diagram of the semiconductor device shown in

[0094] Figure 9 Figure 7 A three-dimensional structural schematic diagram of the gate trench in the semiconductor device shown in

[0095] Figure 10 Some schematic diagrams of the semiconductor device according to an embodiment of the present application when generating conduction current;

[0096] ​​Figure 11 For Figure 10 A cross-sectional structural schematic view of the semiconductor device along the tangential direction of GG';

[0097] Figure 12 Some flowcharts of the method for manufacturing the semiconductor device provided by the embodiments of the present application;

[0098] Figures 13a to 13j A structural schematic view of the process for manufacturing the semiconductor device provided by the embodiments of the present application;

[0099] Figure 14 A three-dimensional structural schematic view of the semiconductor device provided by another embodiment of the present application;

[0100] Figure 15 For Figure 14 A structural schematic view of the gate trench in the semiconductor device shown in FIG. 1;

[0101] Figure 16 A three-dimensional structural schematic view of the semiconductor device provided by another embodiment of the present application;

[0102] Figure 17 For Figure 16 A three-dimensional structural schematic view of the semiconductor device without the interlayer dielectric layer and the source shown in FIG. 1;

[0103] Figure 18 For Figure 16 A three-dimensional structural schematic view of the gate trench in the semiconductor device shown in FIG. 1;

[0104] Figure 19 A three-dimensional structural schematic view of the semiconductor device provided by another embodiment of the present application;

[0105] Figure 20 For Figure 19 A three-dimensional structural schematic view of the semiconductor device without the interlayer dielectric layer and the source shown in FIG. 1;

[0106] Figure 21 For Figure 19 A three-dimensional structural schematic view of the gate trench in the semiconductor device shown in FIG. 1;

[0107] Figure 22 A top view structural schematic view of the semiconductor device provided by another embodiment of the present application;

[0108] Figure 23 A three-dimensional structural schematic view of the semiconductor device provided by another embodiment of the present application;

[0109] Figure 24 Some other flowcharts of the method for manufacturing the semiconductor device provided by the embodiments of the present application.

[0110] Reference signs:

[0111] 010 - electric vehicle; 012 - battery; 013 - load; 0100 - electronic device; 011 / 0110 - power conversion circuit; 0120 - load module; 0200 - power supply; 0111 - DC-DC converter; 01 / 01c1 / 01c2 / 01d1 / 01d2 / 01e1 / 01e2 - gate trench; 02 / 021 / 022 / 023 - contact hole; 02a / 02b - sub-contact hole; 1 - semiconductor substrate; 100 - first epitaxial layer; 2 - first N-type semiconductor region; 3 - second N-type semiconductor region; 4 - first P-type semiconductor region; 5 - fourth P-type semiconductor region; 6 - source region; 7 - trench gate structure; 8 - second P-type semiconductor region; 9 - third P-type semiconductor region; 10 - gate dielectric layer; 11 - gate; 111 - first gate; 112 - second gate; 12 - interlayer dielectric layer; 13 - source; 14 - drain; 15 - fifth P-type semiconductor region; 201 - second epitaxial layer; 202 - spacer region; 01a - first edge trench; 01b - second edge trench; x - first direction; y - second direction; z - third direction; C - trench pitch; D - trench length; E - trench width; F - contact width; GK1 / GK2 - trench group; S1 - first side wall; S2 - second side wall; DS1 - first set thickness; DS2 - second set thickness. DETAILED DESCRIPTION

[0112] In order to make the purposes, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the drawings. The specific operation methods in the method embodiments can also be applied to the device embodiments or system embodiments. It should be noted that in the description of the present application, "at least one" means one or more, wherein more means two or more. Therefore, in the embodiments of the present application, "more" can also be understood as "at least two". "And / or", which describes the association relationship of the associated objects, means that there can be three relationships, for example, A and / or B can mean that there are three cases of A alone, A and B together, and B alone. In addition, the character " / ", if not specially stated, generally represents that the front and rear associated objects are in an "or" relationship. In addition, it should be understood that in the description of the present application, "first", "second", etc. are used only for the purpose of distinguishing the description, and cannot be understood as indicating or implying relative importance or indicating or implying sequence.

[0113] It should be noted that the "connection" in the embodiments of the present application refers to electrical connection, and the connection between two electrical elements can be direct or indirect connection between the two electrical elements. For example, A and B are connected, which can be direct connection between A and B, or indirect connection between A and B through one or more other electrical elements, for example, A and B are connected, which can be direct connection between A and C, direct connection between C and B, and connection between A and B through C.

[0114] Also, the example embodiments can be implemented in various forms and should not be construed as being limited to the embodiments set forth herein; rather, these embodiments are provided so that the present application will be thorough and complete, and will fully convey the inventive concept of the example embodiments to those skilled in the art. Identical reference numerals in the drawings denote identical or similar structures, and thus repeated description thereof will be omitted. The expressions of position and direction described in the present application are described with reference to the drawings, but can be changed as needed, and the changes are included in the scope of the present application. The drawings of the present application are only used to show the relative positional relationship and do not represent the actual proportions.

[0115] It should be noted that specific details are set forth in the following description in order to provide a thorough understanding of the present application. However, the present application can be practiced in a variety of ways other than those described herein, and skilled artisans can make similar substitutions without departing from the scope of the present application. Therefore, the present application is not limited by the specific embodiments disclosed below. The subsequent description of the specification is a preferred embodiment for implementing the present application, but the description is for the purpose of illustrating the general principles of the present application, and is not intended to limit the scope of the present application.

[0116] In order to facilitate the understanding of the semiconductor device, the preparation method, the power conversion circuit and the vehicle provided by the embodiments of the present application, the application scenarios thereof will be introduced first as follows.

[0117] The semiconductor device provided by the embodiments of the present application can be applied in a vehicle (for example, an electric vehicle), for example, can be applied in a vehicle micro controller unit (MCU), a vehicle on-board battery charger (OBC) and the like. It should be noted that the semiconductor device proposed by the embodiments of the present application is intended to include but not limited to be applied in these and any other suitable types of devices. The following will be described taking the electric vehicle as an example.

[0118] Figure 2a The structure schematic diagram of the electric vehicle provided by the embodiments of the present application is shown in FIG. 1. Referring to FIG. 1, the electric vehicle 010 can include a power conversion circuit 011 and a storage battery 012. Figure 2a

[0119] ​In a possible implementation, the power conversion circuit 011 can include an alternating current (AC)-direct current (DC) conversion circuit and a DC-DC conversion circuit, and the power conversion circuit 011 can also be referred to as an inverter. For example, when the electric vehicle 010 is charging, the electric vehicle 010 can be connected to a three-phase power grid to receive three-phase alternating current provided by the three-phase power grid. By controlling the power switch of the AC-DC conversion circuit in the power conversion circuit 011, the AC-DC conversion circuit can convert the three-phase alternating current into direct current, and by controlling the power switch of the DC-DC conversion circuit in the power conversion circuit 011, the DC-DC conversion circuit can regulate the voltage of the direct current output by the AC-DC conversion circuit, thereby providing the battery 012 with direct current of an appropriate voltage, and then the battery 012 can store the direct current to achieve the function of charging.

[0120] In another possible implementation, the power conversion circuit 011 can also be a DC-DC conversion circuit, and the electric vehicle 010 can further include a load 013, which can be a vehicle-mounted device, a power system, or the like of the electric vehicle 010. For example, by controlling the power switch of the DC-DC conversion circuit in the power conversion circuit 011, the power conversion circuit 011 can regulate the voltage of the direct current output by the battery and output the direct current to the load 013, thereby providing the load 013 with direct current of an appropriate voltage.

[0121] The semiconductor device provided in the embodiment of the present application is a MOSFET with a trench gate structure, which can improve the on-conduction channel density and will not increase the resistance of the JFET region, thereby reducing the total on-conduction resistance and improving the performance of the device and reducing the loss of the device. For example, the semiconductor device provided in the embodiment of the present application can be applied to the power conversion circuit 011 of a vehicle as a power switch in an AC-DC converter and / or a DC-DC converter. Since the semiconductor device provided in the embodiment of the present application has good performance, when the semiconductor device is applied to the AC-DC converter and / or the DC-DC converter, the performance of the AC-DC converter and / or the DC-DC converter can be improved and the driving loss can be reduced, thereby improving the performance of the entire circuit and reducing the driving loss.

[0122] The semiconductor device provided by the embodiments of the present application can also be widely applied in various electronic devices, for example, can be applied in electronic devices with logic devices or memory devices, etc. Illustratively, the electronic device can be a smart phone, a smart television, a notebook computer, a personal digital assistant (PDA), a wearable device with wireless communication function (such as a smart watch, smart glasses, a smart bracelet), etc. It should be noted that the semiconductor device provided by the embodiments of the present application is intended to include but not limited to be applied in these and any other suitable types of electronic devices.

[0123] Figure 2b The structure schematic diagram of the electronic device provided by the embodiments of the present application is shown in FIG. 1. Referring to FIG. 1, Figure 2b The electronic device 0100 provided by the embodiments of the present application includes a power conversion circuit 0110 and a load module 0120, and the power conversion circuit 0110 is electrically connected with the load module 0120. Illustratively, the electronic device 0100 can be any power consumption device. For example, a smart phone, a smart television, a notebook computer, a personal digital assistant (PDA), a wearable device with wireless communication function (such as a smart watch, smart glasses, a smart bracelet), an on-board micro controller unit (MCU), an on-board battery charger (OBC), etc. It should be noted that the specific type of the electronic device is not limited by the present application.

[0124] In some embodiments, the power conversion circuit 0110 can be a DC-DC power conversion circuit, which is used to convert the direct current output by the power supply 0200 (for example, 48V) into direct current for all types of load modules 0120, and output to the load module 0120 for the load module 0120 to work. The power supply 0200 and the load module 0120 are not limited by the present application. The power supply 0200 can be any device or element that can output direct current, for example, the power supply 0200 can be a battery (such as a storage battery), then the power conversion circuit 0110 can receive the battery voltage provided by the battery, and convert the battery voltage into the working voltage of the load module 0120, and then output to the load module 0120. The load module 0120 can be any functional module using direct current, for example, the load module 0120 can be a processor, a chip, etc.

[0125] Referring to Figure 2aThe power conversion circuit 0110 includes a DC-DC converter 0111. In operation, the MOSFET in the DC-DC converter 0111 operates at a certain switching frequency, so that the DC-DC converter 0111 converts the DC power from the power supply 0200 to output DC power with a voltage suitable for the load module 0120. Exemplarily, the DC-DC converter can be a Buck converter, a Boost converter, a half-bridge converter, a full-bridge converter, an LLC resonant converter, or the like.

[0126] The semiconductor device provided by the embodiments of the present application is a MOSFET with a trench gate structure, which can increase the on-state channel density without increasing the resistance of the JFET region, thereby reducing the total on-state resistance and improving the performance of the device and reducing the power loss of the device. Exemplarily, the semiconductor device provided by the embodiments of the present application can be applied to the MOSFET in the DC-DC converter 0111. Since the semiconductor device provided by the embodiments of the present application has good performance, when the semiconductor device is applied to the MOSFET in the DC-DC converter 0111, the performance of the DC-DC converter 0111 can be improved and the driving loss can be reduced, thereby improving the performance of the entire electronic device and reducing the driving loss.

[0127] It should be noted that the above scenarios are only illustrative of some possible application modes of the semiconductor device provided by the present application. The specific application scenarios of the semiconductor device provided by the embodiments of the present application are not limited, and can be determined according to the actual application requirements.

[0128] In some embodiments provided by the present application, the materials of the semiconductor substrate and the first epitaxial layer are SiC. Therefore, the semiconductor device provided by the embodiments of the present application is a SiC MOSFET.

[0129] It should be noted that in the present application, the layers and regions with the prefix N or P represent that electrons or holes are the majority carriers. In addition, the "+" marked on N or P indicates that the doping concentration is higher than that of the layer or region without the "+" mark, and the more "+" marks, the higher the doping concentration. N or P containing the same number of "+" marks indicates that the doping concentrations are similar and are not limited to the same doping concentration. In addition, the "-" marked on N or P indicates that the doping concentration is lower than that of the layer or region without the "-" mark, and the more "-" marks, the lower the doping concentration. N or P containing the same number of "-" marks indicates that the doping concentrations are similar and are not limited to the same doping concentration.

[0130] It should be further noted that the comparison of the doping concentrations of the two regions in the present application only refers to the comparison of the concentrations of the doped impurities, and the composition of the impurities is not limited, i.e., the composition of the impurities can be the same or different; the material of the substrate used for doping the impurities can be the same or different.

[0131] Figure 3 A top view structural schematic diagram of a semiconductor device provided by an embodiment of the present application is shown, Figure 4 A top view structural schematic diagram of a semiconductor device provided by an embodiment of the present application is shown, Figure 3 A sectional view structural schematic diagram of the semiconductor device provided by an embodiment of the present application along the direction of the AA' cutting line is shown, Figure 5 A sectional view structural schematic diagram of the semiconductor device provided by an embodiment of the present application along the direction of the BB' cutting line is shown, Figure 3 A sectional view structural schematic diagram of the semiconductor device provided by an embodiment of the present application along the direction of the BB' cutting line is shown, Figure 6 A sectional view structural schematic diagram of the semiconductor device provided by an embodiment of the present application along the direction of the VV' cutting line is shown, Figure 3 A sectional view structural schematic diagram of the semiconductor device provided by an embodiment of the present application along the direction of the VV' cutting line is shown, Figure 7 A sectional view structural schematic diagram of the semiconductor device provided by an embodiment of the present application along the direction of the VV' cutting line is shown, Figure 3 A sectional view structural schematic diagram of the semiconductor device provided by an embodiment of the present application along the direction of the VV' cutting line is shown, Figure 8 A sectional view structural schematic diagram of the semiconductor device provided by an embodiment of the present application along the direction of the VV' cutting line is shown, Figure 7 A sectional view structural schematic diagram of the semiconductor device provided by an embodiment of the present application along the direction of the VV' cutting line is shown, Figure 9 A sectional view structural schematic diagram of the semiconductor device provided by an embodiment of the present application along the direction of the VV' cutting line is shown, Figure 7 A sectional view structural schematic diagram of the semiconductor device provided by an embodiment of the present application along the direction of the VV' cutting line is shown.

[0132] With reference to Figures 3 to 9 The semiconductor device provided by the embodiment of the present application comprises an N-type semiconductor substrate 1, a first epitaxial layer 100, a plurality of gate trenches 01 arranged at intervals, a gate 11, an interlayer dielectric layer 12, a source 13, and a drain 14. The first epitaxial layer 100 is arranged on the semiconductor substrate 1, and the first epitaxial layer 100 comprises a first N-type semiconductor region 2, a second N-type semiconductor region 3, a first P-type semiconductor region 4, and a source region 6. The first N-type semiconductor region 2 is arranged between the second N-type semiconductor region 3 and the semiconductor substrate 1, the first P-type semiconductor region 4 is arranged on the side of the first N-type semiconductor region 2 away from the semiconductor substrate 1, and the source region 6 is arranged on the side of the first P-type semiconductor region 4 away from the semiconductor substrate 1.

[0133] In the present application, the semiconductor substrate can be a single crystal silicon carbide substrate doped with pentavalent elements. The first epitaxial layer 100 can be formed by epitaxial growth of SiC material doped with corresponding impurities. For example, the first N-type semiconductor region 2 is a part of the first epitaxial layer 100 formed by epitaxial growth, and the second N-type semiconductor region 3 and the source region 6 can be formed by ion implantation process by doping the first epitaxial layer 100. In addition, the N-type semiconductor region is mainly doped with N-type impurities such as nitrogen (N), phosphorus (P) or arsenic (As) and the like. For example, the doping concentration of the semiconductor substrate 1 is greater than that of the second N-type semiconductor region 3, the doping concentration of the second N-type semiconductor region 3 is greater than that of the first N-type semiconductor region 2, and the doping concentration of the source region 6 is greater than that of the second N-type semiconductor region 3.

[0134] In the present application, the first P-type semiconductor region 4 can be formed by ion implantation process by doping the first epitaxial layer 100. In addition, the P-type semiconductor region is mainly doped with P-type impurities such as boron (B), aluminum (Al) or gallium (Ga) and the like.

[0135] Continuing to refer to Figures 3 to 9 , a plurality of gate trenches 01 are arranged in the first epitaxial layer 100, and in the third direction z perpendicular to the plane in which the semiconductor substrate 1 is located, the gate trenches 01 extend into the first N-type semiconductor region 2. In addition, the plurality of gate trenches 01 extend along the first direction x parallel to the plane in which the semiconductor substrate 1 is located, and the plurality of gate trenches 01 are arranged along the second direction y parallel to the plane in which the semiconductor substrate 1 is located. The array of closely arranged gate trenches 01 is formed in the first epitaxial layer 100.

[0136] Continuing to refer to Figures 3 to 9 , the gate 11 includes a first gate 111 and a second gate 112 in contact with each other, the first gate 111 is arranged in the gate trench 01 through the gate dielectric layer 10, so that the first gate 111 is embedded in the first epitaxial layer 100 of SiC material. The second gate 112 is also arranged on the top of the first epitaxial layer 100 of SiC material through the gate dielectric layer 10. The first gate 111 forms a trench gate structure 7 of a SiC MOSFET device together with the first P-type semiconductor region 4 through the gate dielectric layer 10, that is, the semiconductor device provided by the present application is a SiC MOSFET with trench gate structure.

[0137] For example, the first gate 111 is arranged in the gate trench 01, which is equivalent to that the first gate 111 extends along the first direction x. The second gate 112 can be arranged to extend along the second direction y, so that part of the second gate 112 is arranged on the top of the first epitaxial layer 100 through the gate dielectric layer 10, and the other part is arranged on the top of the first gate 111, directly contacting the first gate 111.

[0138] The material of the gate 11 is not limited in the present application. For example, the material of the gate 11 can be polysilicon material, or other material with good conductive property, such as metal (e.g., W, Al, Ti, Cu, Mo, or Pt).

[0139] Continuing to refer to Figures 3 to 9 , the interlayer dielectric layer 12 covers the side of the gate 11 away from the semiconductor substrate 1, i.e., the interlayer dielectric layer 12 covers the side of the entire semiconductor substrate 1 with the gate 11. The source 13 is disposed on the side of the interlayer dielectric layer 12 away from the semiconductor substrate 1, i.e., the source 13 covers the entire interlayer dielectric layer 12. The drain 14 is disposed on the side of the semiconductor substrate 1 away from the first epitaxial layer 100, i.e., the drain 14 covers the side of the semiconductor substrate 1 without the first epitaxial layer 100. In actual application, if the signal needs to be transmitted between the source 13 and the drain 14, a contact hole 02 extending along the second direction y can be disposed in the interlayer dielectric layer 12. In order to avoid the contact between the source 13 and the gate 11, the contact hole 02 can be made not to overlap with the gate 11 in the orthographic projection of the semiconductor substrate 1, i.e., the contact hole 02 and the gate 11 are not overlapped in the third direction. The contact hole 02 exposes part of the source region 6, such as the part of the source region 6 on both sides of the first gate 111 in the first direction x, so that the source 13 can contact the source region 6 through the contact hole 02, realizing the connection between the source 13 and the source region 6. When the channel is turned on by the gate 11, the signal can be transmitted between the source 13 and the drain 14.

[0140] The material forming the interlayer dielectric layer 12 is not limited in the present application. For example, the material forming the interlayer dielectric layer 12 can be dielectric material, including but not limited to silicon dioxide (SiO2), silicon oxynitride (SiNO), silicon oxycarbide (SiCO), silicon nitride (SiNx), etc.

[0141] The material forming the source 13 and the drain 14 is not limited in the present application. For example, the material forming the source 13 and the drain 14 can be metal material. Exemplarily, the metal material can include W, Al, Ti, Cu, Mo, or Pt.

[0142] Continuing to refer to Figures 3 to 9 , the first direction x, the second direction y, and the third direction z are arranged to intersect with each other. For example, the first direction x, the second direction y, and the third direction z are arranged to be perpendicular to each other.

[0143] The semiconductor device provided by the embodiments of the present application is characterized in that: the first side wall S1 and the second side wall S2 of the gate trench 01 are respectively provided with a third P-type semiconductor region 9, and the first P-type semiconductor region 4 provided at the first side wall S1 and the second side wall S2 of the gate trench 01 (i.e., the first P-type semiconductor region 4 below the fourth P-type semiconductor region 5) is not controlled by the first gate 111 to have the performance of a channel. Therefore, in the second direction y, the part of the side wall of the gate trench 01 corresponding to the first gate 111 is the channel.

[0144] The semiconductor device provided by the embodiments of the present application is characterized in that: the semiconductor device is provided with a plurality of gate trenches 01 closely arranged in the first epitaxial layer, and the first gate is arranged in the gate trench 01. In the second direction y, the part of the two side walls of the gate trench corresponding to the first gate is the channel. In addition, the contact hole arranged in the interlayer dielectric layer extends in the second direction y, and the gate trench (or the first gate) extends in the first direction x. Therefore, the extension direction of the contact hole is perpendicular to the extension direction of the gate trench (or the first gate), that is, the contact hole is arranged in the direction perpendicular to the gate trench (or the first gate). Compared with the prior art in which the gate trench and the contact hole are arranged in parallel, the semiconductor device provided by the embodiments of the present application reduces the limitation of the contact hole on the channel spacing C of the adjacent gate trench in the second direction y, and enables the gate trench to be prepared more closely, that is, the first gate is also more closely arranged. Therefore, the gate trench array density of the semiconductor device provided by the embodiments of the present application can be much higher than that of the device structure in the prior art, thereby improving the channel density of the SiC MOSFET, significantly reducing the total on-resistance of the device, improving the performance of the device, and reducing the loss of the device.

[0145] In some embodiments of the present application, the plurality of gate trenches in the semiconductor device can be divided into one or more groups of trenches, and the contact hole can be provided as two or more. In addition, a group of trenches is arranged between the two adjacent contact holes, and the contact hole extends through the group of trenches in the second direction. In this way, the signal flow can be more uniform. For example, referring to Figures 3 to 5 , the plurality of gate trenches 01 in the semiconductor device are divided into two groups of trenches, and the two groups of trenches are respectively GK1 and GK2. In addition, the contact hole 02 is provided as three, and the three contact holes 02 are respectively 021, 022 and 023. The group of trenches GK1 is arranged between the contact holes 021 and 022, and the group of trenches GK2 is arranged between the contact holes 022 and 023. Alternatively, the plurality of gate trenches 01 in the semiconductor device are divided into one group of trenches, for example, the group of trenches GK1. In addition, the contact hole 02 is provided as two, for example, the two contact holes 02 are respectively 021 and 022. The group of trenches GK1 is arranged between the contact holes 021 and 022.

[0146] In some embodiments of the present application, the number of gate trenches in different trench groups can be made the same. In this way, the gate trenches can be uniformly distributed. For example, referring to Figure 3 In the trench groups GK1 and GK2, 5 gate trenches 01 are respectively arranged. It should be noted that Figure 3 The number of gate trenches 01 arranged in the trench groups GK1 and GK2 shown is only for explanation and is not the number of gate trenches 01 in the actually prepared semiconductor device. In actual application, the number of gate trenches 01 in the trench groups can be determined according to the needs of actual application, which is not limited in the present application.

[0147] In some embodiments of the present application, the number of gate trenches 01 in part of the trench groups can be made the same, and the number of gate trenches 01 in the remaining part of the trench groups can be different. Alternatively, the number of gate trenches 01 in different trench groups can be different. In actual application, the number of gate trenches 01 in the trench groups can be determined according to the needs of actual application, which is not limited in the present application.

[0148] In some embodiments of the present application, in the second direction, two gate trenches at the edge of the trench group are defined as a first edge trench and a second edge trench, and the contact hole extends from the side of the first edge trench away from the second edge trench to the side of the second edge trench away from the first edge trench along the second direction. For example, referring to Figure 5 For example, taking the trench group GK1, in the second direction, two gate trenches 01 at the edge of the trench group GK1 are defined as a first edge trench 01a and a second edge trench 01b, then the contact hole 02 extends from the side of the first edge trench 01a away from the second edge trench 01b to the side of the second edge trench 01b away from the first edge trench 01a along the second direction y. The contact hole 02 penetrates the trench group, and the contact hole 02 is a continuous opening, and the gate trenches 01 in different trench groups are not penetrated.

[0149] The semiconductor device provided by the embodiments of the present application is a trench gate structure SiC MOSFET device. In the trench gate structure SiC MOSFET device, the gate dielectric layer at the bottom and the corner of the trench gate structure 7 will bear extremely high electric field intensity when the device is working, which is a weak point of electric field breakdown, and is easy to cause long-term working reliability failure of the device. Therefore, how to effectively shield the gate dielectric layer from high electric field stress has become the key to the high robustness / reliability design of the device. In the embodiments of the present application, referring to Figures 3 to 9, the first epitaxial layer 100 further comprises a second P-type semiconductor region 8. The second P-type semiconductor region 8 is arranged below the gate trench 01, and the second P-type semiconductor region 8 is directly in contact with the bottom end of the gate trench 01. In the present application, the second P-type semiconductor region 8 can be connected with the source 13. When the SiC MOSFET device is working, the source 13 will be loaded with voltage. Since the second P-type semiconductor region 8 is connected with the source 13, the voltage loaded on the source 13 will be input into the second P-type semiconductor region 8, so that the second P-type semiconductor region 8 also has a corresponding voltage, thereby effectively shielding the gate dielectric layer electric field at the bottom of the gate trench 01, and further improving the robustness of the device working.

[0150] The present application does not limit the thickness of the second P-type semiconductor region 8 in the third direction x. For example, the thickness of the second P-type semiconductor region 8 in the third direction can be less than 1u, for example, the thickness of the second P-type semiconductor region 8 in the third direction can be 0.3u-0.8um.

[0151] For example, when the SiC MOSFET provided by the embodiments of the present application is applied to a power conversion circuit, the source thereof can be grounded, and the drain thereof can be connected to other elements, so that the voltage of the source of the SiC MOSFET is the ground voltage (0V). Since the second P-type semiconductor region is connected with the source, the voltage of the second P-type semiconductor region is also the ground voltage, thereby effectively shielding the gate dielectric layer electric field at the bottom of the gate trench, and further improving the robustness of the device working.

[0152] For example, when the SiC MOSFET provided by the embodiments of the present application is applied to a power conversion circuit, the source thereof can also be connected to other elements, and the drain thereof is also connected to other elements, so that the voltage of the source of the SiC MOSFET is the voltage of the input signal of the other elements. Since the second P-type semiconductor region is connected with the source, the voltage of the second P-type semiconductor region is also the voltage of the input signal, thereby effectively shielding the gate dielectric layer electric field at the bottom of the gate trench, and further improving the robustness of the device working.

[0153] In some embodiments of the present application, with reference to Figure 3 , Figure 4 and Figures 7 to 9 , the first epitaxial layer 100 further comprises a third P-type semiconductor region 9 and a fourth P-type semiconductor region 5. The third P-type semiconductor region 9 is arranged at the sidewall of the gate trench 01 along the first direction, and the fourth P-type semiconductor region 5 is arranged in the same layer as the source region 6. The first P-type semiconductor region 4, the second P-type semiconductor region 8, the third P-type semiconductor region 9 and the fourth P-type semiconductor region 5 can be formed by doping the first epitaxial layer 100 by ion implantation process. Moreover, the main impurity doped in the P-type semiconductor region is P-type impurity, such as boron (B), aluminum (Al) or gallium (Ga) and the like.

[0154] Exemplarily, the doping concentration of the second P-type semiconductor region 8, the third P-type semiconductor region 9 and the fourth P-type semiconductor region 5 is greater than the doping concentration of the first P-type semiconductor region 4. Alternatively, the doping concentration of the second P-type semiconductor region 8, the third P-type semiconductor region 9 and the fourth P-type semiconductor region 5 can be the same or similar. Of course, the doping concentration of the second P-type semiconductor region 8, the third P-type semiconductor region 9 and the fourth P-type semiconductor region 5 can also be different from at least two. It should be noted that the doping concentration of the second P-type semiconductor region 8, the third P-type semiconductor region 9 and the fourth P-type semiconductor region 5 can be determined according to the needs of the actual application environment, which is not limited here.

[0155] Referring to Figure 3 , Figure 4 and Figures 7 to 9 , the third P-type semiconductor region 9 is in contact with the second P-type semiconductor region 8, the fourth P-type semiconductor region 5 is in contact with the third P-type semiconductor region 9, and the fourth P-type semiconductor region 5 is in contact with the source 13 through the contact hole 02. Then the source 13 is connected to the second P-type semiconductor region 8 through the fourth P-type semiconductor region 5 and the third P-type semiconductor region 9 in turn, so that the voltage loaded on the source 13 is input to the second P-type semiconductor region 8 through the fourth P-type semiconductor region 5 and the third P-type semiconductor region 9 in turn, thereby effectively shielding the gate dielectric layer electric field at the bottom of the gate trench 01, and further improving the robustness of the device working.

[0156] Exemplarily, referring to Figure 3 , Figure 4 and Figures 7 to 9 , in the first direction x, the gate trench 01 has oppositely arranged first and second side walls S1 and S2. The third P-type semiconductor region 9 is provided in multiple, one of the third P-type semiconductor regions 9 is arranged on the first side wall S1 of each gate trench 01, and one of the third P-type semiconductor regions 9 is also arranged on the second side wall S2 of each gate trench 01. That is, the first and second side walls S1 and S2 of each gate trench 01 are respectively provided with the third P-type semiconductor region 9. And these third P-type semiconductor regions 9 are all in contact with the second P-type semiconductor region 8, so that the third P-type semiconductor regions 9 can be connected to the second P-type semiconductor region 8 for signal transmission, and the voltage of the third P-type semiconductor regions 9 is the same as that of the second P-type semiconductor region 8.

[0157] Exemplarily, referring to Figure 3 , Figure 4 and Figures 7 to 9The fourth P-type semiconductor region 5 is also provided with a plurality of fourth P-type semiconductor regions 5, which are arranged in one-to-one correspondence with the plurality of third P-type semiconductor regions 9. Among them, the third P-type semiconductor region 9 arranged on the first side wall S1 is arranged in correspondence with one of the plurality of fourth P-type semiconductor regions 5, and the fourth P-type semiconductor region 5 is arranged on the side of the third P-type semiconductor region 9 away from the first side wall S1 of the gate trench 01. In addition, the third P-type semiconductor region 9 arranged on the second side wall S2 is arranged in correspondence with one of the plurality of fourth P-type semiconductor regions 5, and the fourth P-type semiconductor region 5 is arranged on the side of the third P-type semiconductor region 9 away from the second side wall S2 of the gate trench 01. Then, the source electrode 13 is connected to the second P-type semiconductor region 8 through the fourth P-type semiconductor region 5 and the third P-type semiconductor region 9 arranged in correspondence with each other in sequence, so that the voltage loaded on the source electrode 13 is input to the second P-type semiconductor region 8 through the fourth P-type semiconductor region 5 and the third P-type semiconductor region 9 in sequence, so that the second P-type semiconductor region 8 has a voltage, thereby effectively shielding the gate dielectric layer electric field at the bottom of the gate trench 01, and further improving the robustness of the device.

[0158] Exemplarily, with reference to Figure 3 , Figure 4 and Figures 7 to 9 , the semiconductor device provided by the embodiment of the present application is also provided with a plurality of source regions 6, and the plurality of source regions and the plurality of fourth P-type semiconductor regions 5 located at the same end of the gate trench 01 are arranged alternately. For example, the plurality of source regions 6 and the plurality of fourth P-type semiconductor regions 5 located at the first side wall S1 of the gate trench 01 in the same trench group are arranged alternately. In addition, the plurality of source regions 6 and the plurality of fourth P-type semiconductor regions 5 located at the second side wall S2 of the gate trench 01 in the same trench group are arranged alternately.

[0159] The present application does not limit the width of the fourth P-type semiconductor region 5 along the second direction y, for example, the width of the fourth P-type semiconductor region 5 along the second direction y can be the same as or similar to the trench width. Of course, the width of the fourth P-type semiconductor region 5 along the second direction can also be different from the trench width, which is not limited here.

[0160] Exemplarily, with reference to Figures 3 to 9 , the orthographic projection of the second P-type semiconductor region 8 on the semiconductor substrate 1 covers the orthographic projection of the gate trench 01 on the semiconductor substrate 1 and the orthographic projection of the third P-type semiconductor region 9 on the semiconductor substrate 1. That is, in the third direction z, the second P-type semiconductor region 8 covers the gate trench 01 and the third P-type semiconductor region 9. That is, the orthographic projection of the second P-type semiconductor region 8 on the semiconductor substrate 1 not only covers the orthographic projection of all the gate trenches 01 on the semiconductor substrate 1, but also covers the orthographic projection of all the third P-type semiconductor regions 9 on the semiconductor substrate 1.

[0161] Exemplarily, referring to Figures 3 to 9 , the second P-type semiconductor region 8 is a planar region extending along the second direction y. And the present application does not limit the shape of the second P-type semiconductor region 8, for example, the shape of the second P-type semiconductor region 8 can be set as a rectangle.

[0162] Exemplarily, referring to Figures 3 to 9 , the second P-type semiconductor region 8 also covers the gap between the orthographic projections of the two adjacent gate trenches 01 on the semiconductor substrate 1. That is, the orthographic projection of the second P-type semiconductor region 8 on the semiconductor substrate 1 also covers the orthographic projection of the gap between the two adjacent gate trenches 01 in the second direction y on the semiconductor substrate 1.

[0163] Optionally, referring to Figures 3 to 9 , one second P-type semiconductor region 8 is provided for one trench group. That is, if one trench group is provided, a second P-type semiconductor region 8 of a planar region is correspondingly provided. If two trench groups are provided, two second P-type semiconductor regions 8 of planar regions are correspondingly provided. And there is a gap between the two second P-type semiconductor regions 8. If multiple trench groups are provided, multiple second P-type semiconductor regions 8 of planar regions are correspondingly provided. And there is a gap between every two adjacent second P-type semiconductor regions 8.

[0164] Referring to Figure 3 and Figure 8 , in the second direction y, there is a trench spacing C between the two adjacent gate trenches 01. The present application does not limit the specific value of the trench spacing C, for example, the trench spacing C is less than 1um. Optionally, the range of the trench spacing C is 50nm-0.5um. It should be noted that when the trench spacing C is less than 100nm, the semiconductor device provided by the present application will form a Fin Field-Effect Transistor (Fin FET) effect, which can significantly improve the carrier channel mobility and further reduce the total resistance of the device.

[0165] Continuing to refer to Figure 3 , Figure 4 and Figure 8 , in the first direction, the gate trench 01 has a trench length D. The present application does not limit the trench length D, for example, the trench length D is greater than 5um.

[0166] Continuing to refer to Figure 3 , in the second direction y, the gate trench 01 has a trench width E. The present application does not limit the trench width E, for example, the trench width is less than 1um.

[0167] Continuing to refer to Figure 3In the first direction, the contact hole 02 has a contact width F, and the trench interval C can be made not greater than the contact width F. Of course, the trench interval C can also be made greater than the contact width F. In actual applications, the trench interval C and the contact width F can be determined according to the environmental requirements of actual applications, and are not limited herein.

[0168] The present application does not limit the width of the source region 6 along the second direction, for example, the width of the source region 6 along the second direction y can be the same or similar to the trench interval C, which is not limited herein.

[0169] Referring to Figure 5 , the first P-type semiconductor region 4 at the two side walls of the gate trench 01 of the trench gate structure 7 in the second direction y forms a channel region of the SiC MOSFET, so that by increasing the trench width or reducing the trench interval C, the conductive channel density of the SiC MOSFET device can be improved, and the total on-resistance of the SiC MOSFET device can be reduced.

[0170] Figure 10 Some schematic diagrams of the semiconductor device provided by the embodiments of the present application when generating on-current are shown, Figure 11 Some schematic diagrams of the semiconductor device provided by the embodiments of the present application when generating on-current are shown, Figure 10 Some schematic diagrams of the semiconductor device provided by the embodiments of the present application when generating on-current are shown, Figure 10 Some schematic diagrams of the semiconductor device provided by the embodiments of the present application when generating on-current are shown, Figure 11 The black straight line with an arrow represents the flow direction of the on-current when the SiC MOSFET is turned on. For example, when a positive voltage is loaded on the gate 11 of the SiC MOSFET, the MOSFET provided by the present application can be controlled to be turned on, and at this time, if different voltages are loaded on the source 13 and the drain 14 (for example, the voltage loaded on the source 13 is greater than the voltage loaded on the drain 14), the on-current flowing from the source 13 to the drain 14 will be generated between the source 13 and the drain 14, as shown in Figure 10 The black straight line with an arrow represents the flow direction of the on-current when the SiC MOSFET is turned on. For example, when a positive voltage is loaded on the gate 11 of the SiC MOSFET, the MOSFET provided by the present application can be controlled to be turned on, and at this time, if different voltages are loaded on the source 13 and the drain 14 (for example, the voltage loaded on the source 13 is greater than the voltage loaded on the drain 14), the on-current flowing from the source 13 to the drain 14 will be generated between the source 13 and the drain 14, as shown in Figure 11

[0171] Figure 12 Some flowcharts of the preparation method of the semiconductor device provided by the embodiments of the present application are shown. Referring to Figure 12 The structure shown in Figure 7 For example, in the preparation method, the following steps can be included:

[0172] S10, epitaxially growing a first epitaxial layer on the N-type semiconductor substrate.

[0173] For example, step S10 includes:

[0174] First, referring to Figure 13a ​A first epitaxial layer 100 is epitaxially grown on the N-type SiC semiconductor substrate 1 to a first set thickness DS1 (i.e. thickness in the third direction z).

[0175] Exemplarily, the SiC material doped with N-type impurities is epitaxially grown on the N-type SiC semiconductor substrate 1 by an epitaxial process to form the first epitaxial layer 100 to the first set thickness DS1.

[0176] The present application does not limit the specific value of the first set thickness DS1. In practical applications, the specific value of the first set thickness DS1 can be determined according to the requirements of the actual application environment.

[0177] Thereafter, referring to Figure 13b , the first epitaxial layer 100 is ion implanted by an ion implantation process to form the second P-type semiconductor region 8.

[0178] Exemplarily, the P-type impurities are doped in the first epitaxial layer 100 corresponding to the second P-type semiconductor region 8 to be formed by an ion implantation process to form the second P-type semiconductor region 8 in a planar region.

[0179] The present application does not limit the thickness (i.e. thickness in the third direction) of the second P-type semiconductor region 8. In practical applications, the specific value of the thickness of the second P-type semiconductor region 8 can be determined according to the requirements of the actual application environment.

[0180] Thereafter, referring to Figure 13c , the first epitaxial layer 100 on which the second P-type semiconductor region 8 is formed is continuously epitaxially grown until the first epitaxial layer 100 to a second set thickness DS2 is formed.

[0181] Exemplarily, the SiC material doped with N-type impurities is continuously epitaxially grown on the first epitaxial layer 100 on which the second P-type semiconductor region 8 is formed by an epitaxial process to form the first epitaxial layer 100 to the second set thickness DS2.

[0182] S20, ion implantation is performed in a part of the first epitaxial layer by an ion implantation process to form the second N-type semiconductor region, the first P-type semiconductor region and the source region, and the region of the first epitaxial layer in which ion implantation is not performed forms the first N-type semiconductor region.

[0183] Exemplarily, referring to Figure 13d, the ion implantation process is adopted to perform N-type impurity doping on the surface of the first epitaxial layer to form a second N-type semiconductor region 3. Then, the ion implantation process is adopted to perform P-type impurity doping on the surface of the first epitaxial layer to form a first P-type semiconductor region 4. Then, the ion implantation process is adopted to perform N-type impurity doping on the surface of the first epitaxial layer 100 to form a source region 6, and P-type impurity doping on the surface of the first epitaxial layer 100 at the first sidewall S1 and the second sidewall S2 of the gate trench 01 to form a fourth P-type semiconductor region 5 arranged in the same layer as the source region 6.

[0184] Therefore, after the ion implantation process, part of the first epitaxial layer 100 forms the second N-type semiconductor region 3, the first P-type semiconductor region 4, the source region 6, and the fourth P-type semiconductor region 5, and the part of the first epitaxial layer 100 which is not subjected to the ion implantation process forms the first N-type semiconductor region 2.

[0185] S30, etching the first epitaxial layer to the first N-type semiconductor region to form a plurality of gate trenches arranged at intervals in the first epitaxial layer.

[0186] For example, first, a trench mask (which can be a mask formed by photoresist or a hard mask plate) is formed on the first epitaxial layer, the region of the first epitaxial layer where the gate trench 01 is to be formed is exposed, and the region of the first epitaxial layer where the gate trench 01 is not to be formed is covered by the trench mask. Then, referring to Figure 13e An appropriate etching process is selected from the plasma etching process, ion sputtering etching process, and reactive ion etching process, and the like, and the region of the first epitaxial layer which is not covered by the trench mask is etched until the first N-type semiconductor region 2 is etched to and the second P-type semiconductor region 8 is exposed, and the etching is stopped, so as to form a plurality of gate trenches 01 extending along the first direction x and arranged along the second direction y in the first epitaxial layer.

[0187] S40, using an inclined ion implantation process, a third P-type semiconductor region in contact with the second P-type semiconductor region is formed on the first sidewall and the second sidewall of each gate trench along the first direction.

[0188] For example, referring to Figure 13f , using an inclined ion implantation process, P-type impurity doping is performed on the surface of the first sidewall S1 and the second sidewall S2 of each gate trench 01 to form a third P-type semiconductor region 9 in contact with the second P-type semiconductor region 8.

[0189] S50, forming a gate dielectric layer in the gate trench.

[0190] For example, referring to Figure 13gThe first epitaxial layer is oxidized to form a gate dielectric layer 10 on the surface of the first epitaxial layer. That is, the surface of each gate trench 01 is covered with the gate dielectric layer 10, and the side of the first epitaxial layer away from the semiconductor substrate 1 is also covered with the gate dielectric layer 10.

[0191] S60, a first gate electrode of the gate electrodes is formed in the gate trench covered with the gate dielectric layer, and a second gate electrode of the gate electrodes is formed on the first epitaxial layer and in contact with the first gate electrode.

[0192] For example, first, a deposition process is used to deposit a polysilicon material on the entire first epitaxial layer covered with the gate trench, and the polysilicon material fills the gate trench. After the gate trench is filled with the polysilicon material, a polysilicon film layer covers the entire first epitaxial layer. Then, a gate mask is formed on the first epitaxial layer. The gate mask can be a mask formed of photoresist or a hard mask plate. The gate mask covers the area where the second gate electrode is to be formed, and exposes the remaining area. Then, a suitable etching process is selected from plasma etching, ion sputtering etching, and reactive ion etching, and the exposed area of the polysilicon material is etched until the source region 6 and the fourth P-type semiconductor region 5 are exposed. Figure 13g A suitable etching process is selected from plasma etching, ion sputtering etching, and reactive ion etching, and the area of the polysilicon material not covered by the trench mask is etched until the source region 6 and the fourth P-type semiconductor region 5 are exposed, to form the first gate electrode 111 and the second gate electrode 112.

[0193] S70, an interlayer dielectric layer covering the entire first epitaxial layer is formed on the gate electrodes.

[0194] For example, first, a contact hole mask is formed on the first epitaxial layer. The contact hole mask can be a mask formed of photoresist or a hard mask plate. The contact hole mask covers the area where the contact hole 02 is not to be formed, and exposes the area where the contact hole 02 is to be formed. Then, a suitable etching process is selected from plasma etching, ion sputtering etching, and reactive ion etching, and the area of the interlayer dielectric layer 12 not covered by the contact hole 02 mask is etched to expose the portions of the source region 6 on both sides of the first gate electrode 111 in the first direction x and the portions of the fourth P-type semiconductor region 5 on both sides of the first gate electrode 111. Figure 13h A deposition process is used to deposit an interlayer dielectric layer 12 on the entire first epitaxial layer, and the interlayer dielectric layer 12 covers the entire first epitaxial layer.

[0195] S80, the interlayer dielectric layer is etched to form a contact hole extending in the second direction.

[0196] For example, first, a contact hole mask is formed on the first epitaxial layer. The contact hole mask can be a mask formed of photoresist or a hard mask plate. The contact hole mask covers the area where the contact hole 02 is not to be formed, and exposes the area where the contact hole 02 is to be formed. Then, a suitable etching process is selected from plasma etching, ion sputtering etching, and reactive ion etching, and the area of the interlayer dielectric layer 12 not covered by the contact hole 02 mask is etched to expose the portions of the source region 6 on both sides of the first gate electrode 111 in the first direction x and the portions of the fourth P-type semiconductor region 5 on both sides of the first gate electrode 111. Figure 13i

[0197] ​S90, a source electrode is formed on the side of the interlayer dielectric layer away from the semiconductor substrate, and the source electrode is in contact with the source region through the contact hole. And a drain electrode is formed on the side of the semiconductor substrate away from the first epitaxial layer.

[0198] The material of the source electrode and the drain electrode is not limited in the present application. For example, the material of the source electrode and the drain electrode can be a metal material. Exemplarily, the metal material can include W, Al, Ti, Cu, Mo or Pt.

[0199] Exemplarily, referring to Figure 13j , a deposition process is adopted to deposit a metal material on the side of the interlayer dielectric layer 12 away from the semiconductor substrate 1, thereby forming a source electrode 13. The source electrode 13 is in contact with the source region 6 through the metal material filled in the contact hole 02.

[0200] Exemplarily, referring to Figure 13j , a deposition process can be adopted to deposit a metal material on the side of the semiconductor substrate 1 away from the first epitaxial layer, thereby forming a drain electrode 14 when the source electrode 13 is formed. Alternatively, a deposition process can be adopted to deposit a metal material on the side of the semiconductor substrate 1 away from the first epitaxial layer, thereby forming a drain electrode 14 after the source electrode 13 is formed.

[0201] Figure 14 A perspective structural schematic diagram of a semiconductor device provided by another embodiment of the present application is shown. Figure 15 A perspective structural schematic diagram of a semiconductor device provided by another embodiment of the present application is shown. Figure 14 A structural schematic diagram of a gate trench in the semiconductor device is shown.

[0202] Referring to Figure 14 and Figure 15 , in some other embodiments provided by the present application, the semiconductor device includes: an N-type semiconductor substrate 1, a first epitaxial layer, a plurality of gate trenches 01 arranged at intervals, a gate electrode 11, an interlayer dielectric layer 12, a source electrode 13 and a drain electrode 14. And the first epitaxial layer includes: a first N-type semiconductor region 2, a second N-type semiconductor region 3, a first P-type semiconductor region 4, a source region 6, a second P-type semiconductor region 8, a third P-type semiconductor region 9 and a fourth P-type semiconductor region 5. The present embodiment is a variation of the implementation in the above-mentioned embodiments. Only the differences between the present embodiment and the above-mentioned embodiments are described below, and the same parts are not described herein.

[0203] Referring to Figure 14 and Figure 15In the embodiment, the second P-type semiconductor region 8 and the bottom end of the gate trench 01 have a spacing region 202. That is, the second P-type semiconductor region 8 at the bottom of the gate trench 01 is not in direct contact with the bottom of the gate trench 01, but is connected to the bottom of the gate trench 01 through the spacing region 202. Exemplarily, the spacing region 202 is an N-type semiconductor region, and the doping concentration of the spacing region 202 is the same as or similar to that of the first N-type semiconductor region 2. Alternatively, the spacing region 202 is part of the first N-type semiconductor region 2.

[0204] In the embodiment, the spacing region 202 can serve as a flow path of the on-current of the SiC MOSFET device, can increase the on-current area of the SiC MOSFET device, and further reduces the total on-resistance of the SiC MOSFET device.

[0205] In the embodiment, the spacing region 202 can serve as a flow path of the on-current of the SiC MOSFET device, can increase the on-current area of the SiC MOSFET device, and further reduces the total on-resistance of the SiC MOSFET device. Figure 14 The structure shown in the embodiment is taken as an example, and the flowchart of the corresponding preparation method can refer to Figure 12 . Wherein, steps S10-S20, S40-S90 can refer to the above description of the preparation method.

[0206] In the embodiment, step S30 is etching the first epitaxial layer to the first N-type semiconductor region, and forming a plurality of gate trenches 01 spaced from each other in the first epitaxial layer.

[0207] In some examples, first, a trench mask (which can be a mask formed by photoresist or a hard mask plate) is formed on the first epitaxial layer, the region of the first epitaxial layer where the gate trench is to be formed is exposed, and the region of the first epitaxial layer where the gate trench is not to be formed is covered by the trench mask. Then, referring to Figure 15 A suitable etching process is selected from plasma etching process, ion sputtering etching process and reactive ion etching process, and the region of the first epitaxial layer not covered by the trench mask is etched until the first N-type semiconductor region 2 is etched, and the etching is stopped when the second P-type semiconductor region 8 is not exposed, so that the part of the first N-type semiconductor region 2 remaining above the second P-type semiconductor region 8 forms the spacing region 202.

[0208] In other examples, first, a trench mask (which can be a mask formed by photoresist or a hard mask plate) is formed on the first epitaxial layer, the region of the first epitaxial layer where the gate trench is to be formed is exposed, and the region of the first epitaxial layer where the gate trench is not to be formed is covered by the trench mask. Then, referring to Figure 15From the etching processes such as plasma etching process, ion sputtering etching process and reactive ion etching process, a suitable etching process is selected to etch the region of the first epitaxial layer which is not covered by the trench mask, until the first N-type semiconductor region 2 is etched, however, the original design is to stop the etching process when the second P-type semiconductor region 8 is exposed, but due to the precision limitation of the etching process, the etching process may be stopped before the second P-type semiconductor region 8 is exposed, thereby leaving part of the first N-type semiconductor region 2 above the second P-type semiconductor region 8, and the remaining first N-type semiconductor region 2 forms the interval region 202.

[0209] Figure 16 A perspective structural schematic diagram of a semiconductor device provided by another embodiment of the application is shown. Figure 17 A perspective structural schematic diagram of a semiconductor device provided by another embodiment of the application is shown. Figure 16 A perspective structural schematic diagram of a semiconductor device provided by another embodiment of the application is shown, Figure 18 A perspective structural schematic diagram of a semiconductor device provided by another embodiment of the application is shown. Figure 16 A perspective structural schematic diagram of a semiconductor device provided by another embodiment of the application is shown.

[0210] Referring to Figures 16 to 18 In some other embodiments provided by the application, the semiconductor device provided by the embodiments of the application comprises an N-type semiconductor substrate 1, a first epitaxial layer, a plurality of gate trenches 01 arranged at intervals, a gate 11, an interlayer dielectric layer 12, a source 13 and a drain 14. Moreover, the first epitaxial layer comprises a first N-type semiconductor region 2, a second N-type semiconductor region 3, a first P-type semiconductor region 4, a source region 6, a second P-type semiconductor region 8, a third P-type semiconductor region 9 and a fourth P-type semiconductor region 5. The present embodiment is a variation of the implementation in the above-mentioned embodiments. Only the differences between the present embodiment and the above-mentioned embodiments will be described below, and the same parts will not be described herein.

[0211] Referring to Figures 16 to 18 In the present embodiment, a plurality of third P-type semiconductor regions 9 are provided, one third P-type semiconductor region 9 of the plurality of third P-type semiconductor regions 9 is arranged on the first side wall S1 of each gate trench 01, and the second side wall S2 of each gate trench 01 is not provided with a third P-type semiconductor region 9. That is, only the third P-type semiconductor regions 9 are arranged on the first side wall S1 of each gate trench 01, respectively. Moreover, the third P-type semiconductor regions 9 are in contact with the second P-type semiconductor region 8, so that the third P-type semiconductor regions 9 can be connected to the second P-type semiconductor region 8 for signal transmission, and the voltage of the third P-type semiconductor regions 9 is the same as that of the second P-type semiconductor region 8.

[0212] Exemplarily, referring to Figures 16 to 18The fourth P-type semiconductor region 5 is also provided with a plurality of fourth P-type semiconductor regions 5, which are in one-to-one correspondence with the plurality of third P-type semiconductor regions 9 and are in contact. Among them, the third P-type semiconductor region 9 provided on the first side wall S1 corresponds to one of the plurality of fourth P-type semiconductor regions 5, and the fourth P-type semiconductor region 5 is provided on the side of the third P-type semiconductor region 9 away from the first side wall S1 of the gate trench 01. Then the source 13 is connected to the second P-type semiconductor region 8 through the fourth P-type semiconductor region 5 and the third P-type semiconductor region 9 arranged in correspondence with each other in sequence, so that the voltage loaded on the source 13 is input to the second P-type semiconductor region 8 through the fourth P-type semiconductor region 5 and the third P-type semiconductor region 9 in sequence, so that the second P-type semiconductor region 8 has a voltage, thereby effectively shielding the gate dielectric layer electric field at the bottom of the gate trench 01, and further improving the robustness of the device.

[0213] Exemplarily, referring to Figures 16 to 18 The first epitaxial layer further comprises: a fifth P-type semiconductor region 15, the fifth P-type semiconductor region 15 and the source region 6 are provided in the same layer, the fifth P-type semiconductor region 15 is provided on the side of the second side wall S2 of the gate trench 01 away from the first side wall S1, and the fifth P-type semiconductor region 15 is in contact with the source 13 through the contact hole 02.

[0214] Exemplarily, the fifth P-type semiconductor region 15 is a plurality of fifth P-type semiconductor regions 15, which are in one-to-one correspondence with the second side walls of the plurality of gate trenches 01, that is, the second side wall S2 of one gate trench 01 corresponds to one fifth P-type semiconductor region 15. Alternatively, the plurality of source regions 6 and the plurality of fifth P-type semiconductor regions 15 on the second side wall S2 of the gate trench 01 are arranged alternately. That is, the plurality of source regions 6 and the plurality of fifth P-type semiconductor regions 15 on the same side wall of the gate trench 01 are arranged alternately along the second direction y.

[0215] Exemplarily, the source region is provided in a plurality of source regions 6, and the gate trench 01 and the plurality of source regions 6 are arranged alternately. That is, the gate trench 01 and the source region 6 are arranged alternately along the second direction y. That is, the plurality of source regions and the plurality of fifth P-type semiconductor regions 15 on the second side wall S2 of the gate trench 01 are arranged alternately.

[0216] Alternatively, the fifth P-type semiconductor region 15 can be formed by doping the first epitaxial layer through an ion implantation process. And the fifth P-type semiconductor region 15 is mainly doped with P-type impurities, such as boron (B), aluminum (Al) or gallium (Ga) and the like. Exemplarily, the doping concentration of the fifth P-type semiconductor region 15 is the same as or similar to the doping concentration of the fourth P-type semiconductor region 5.

[0217] In the embodiment of the present application, the third P-type semiconductor region 9 is provided at the first side wall S1 of the gate trench 01, and no channel is formed.

[0218] As shown in the structure, the flow chart of the corresponding preparation method can refer to Figure 16 Figure 12 Among them, steps S10-S30, S50-S90 can refer to the above description of the preparation method.

[0219] In this embodiment, step S40 is: using a tilted ion implantation process, on the first sidewall of each gate trench in the first direction, respectively forming a third P-type semiconductor region in contact with the second P-type semiconductor region.

[0220] For example, referring to Figure 18 , using a tilted ion implantation process, P-type impurity doping is performed on the surface of the first sidewall S1 of each gate trench 01, respectively forming a third P-type semiconductor region 9 in contact with the second P-type semiconductor region 8.

[0221] Figure 19 A three-dimensional structural schematic diagram of a semiconductor device provided by another embodiment of the application is shown. Figure 20 A three-dimensional structural schematic diagram of a semiconductor device provided by another embodiment of the application is shown. Figure 19 A three-dimensional structural schematic diagram of a semiconductor device provided by another embodiment of the application is shown. Figure 21 A three-dimensional structural schematic diagram of a semiconductor device provided by another embodiment of the application is shown. Figure 19 A three-dimensional structural schematic diagram of a semiconductor device provided by another embodiment of the application is shown.

[0222] For example, referring to Figures 19 to 21 In still some embodiments provided by the application, the semiconductor device includes: an N-type semiconductor substrate 1, a first epitaxial layer, a plurality of gate trenches 01 arranged at intervals, a gate 11, an interlayer dielectric layer 12, a source 13, and a drain 14. And the first epitaxial layer includes: a first N-type semiconductor region 2, a second N-type semiconductor region 3, a first P-type semiconductor region 4, a source region 6, a second P-type semiconductor region 8, a third P-type semiconductor region 9, and a fourth P-type semiconductor region 5. This embodiment is a variation of the implementation in the above embodiment. Only the differences between this embodiment and the above embodiment will be described below, and the same parts will not be described here.

[0223] For example, referring to Figures 19 to 21 ​​In the embodiment, a plurality of third P-type semiconductor regions 9 are provided, one of the plurality of third P-type semiconductor regions 9 is provided at the first sidewall S1 of each gate trench 01, and the second sidewall of each gate trench is not provided with a third P-type semiconductor region 9. That is, the third P-type semiconductor region 9 is only provided at the first sidewall S1 of each gate trench 01, respectively. And these third P-type semiconductor regions 9 are all in contact with the second P-type semiconductor region 8, so that the third P-type semiconductor region 9 can be connected with the second P-type semiconductor region 8 for signal transmission, and the voltage of the third P-type semiconductor region 9 is the same as that of the second P-type semiconductor region 8.

[0224] For example, referring to Figures 19 to 21 , a plurality of fourth P-type semiconductor regions 5 are also provided, which are one-to-one corresponding and in contact with the plurality of third P-type semiconductor regions 9. Among them, the third P-type semiconductor region 9 provided on the first sidewall S1 corresponds to one of the plurality of fourth P-type semiconductor regions 5, and the fourth P-type semiconductor region 5 is provided on the side of the third P-type semiconductor region 9 away from the first sidewall S1 of the gate trench 01. Then the source 13 is connected to the second P-type semiconductor region 8 through the fourth P-type semiconductor region 5 and the third P-type semiconductor region 9 provided in correspondence, so that the voltage loaded on the source 13 is input to the second P-type semiconductor region 8 through the fourth P-type semiconductor region 5 and the third P-type semiconductor region 9, so that the second P-type semiconductor region 8 has a voltage, thereby effectively shielding the gate dielectric layer electric field at the bottom of the gate trench 01, and further improving the robustness of the device operation.

[0225] For example, referring to Figures 19 to 21 , only the fourth P-type semiconductor region 5 is provided at the first sidewall S1 of the gate trench 01, and the source region 6 is provided at the second sidewall S2 of the gate trench 01. The first P-type semiconductor region 4 at the second sidewall S2 of the gate trench 01 can be controlled by the first gate 111 to form a channel, and the source region 6 is provided at the second sidewall S2 of the gate trench 01. The on-state current can be transmitted from the first P-type semiconductor region 4 at the second sidewall S2 of the gate trench 01 to the drain 14, further improving the flow path of the on-state current.

[0226] For example, referring to Figure 19 , the structure shown in the figure, the corresponding preparation method flow chart can refer to Figure 12 . Among them, steps S10, S30, S50-S90 can refer to the description of the preparation method above.

[0227] In the embodiment, the step S20 is: forming the second N-type semiconductor region, the first P-type semiconductor region and the source region by ion implantation in the partial region of the first epitaxial layer by using ion implantation process, and the first N-type semiconductor region is formed in the region of the first epitaxial layer which is not subjected to ion implantation.

[0228] For example, referring to Figure 21 , the second N-type semiconductor region 3 is formed by N-type impurity doping on the surface of the first epitaxial layer by using ion implantation process. Then, the first P-type semiconductor region 4 is formed by P-type impurity doping on the surface of the first epitaxial layer by using ion implantation process. Then, the source region 6 is formed by N-type impurity doping on the surface of the first epitaxial layer by using ion implantation process, and the fourth P-type semiconductor region 5 which is arranged in the same layer as the source region 6 is formed by P-type impurity doping on the surface of the first epitaxial layer at the first side wall S1 of the gate trench 01. Therefore, after the ion implantation process, the second N-type semiconductor region 3, the first P-type semiconductor region 4, the source region 6 and the fourth P-type semiconductor region 5 are formed in the partial region of the first epitaxial layer in the embodiment, and the first N-type semiconductor region 2 is formed in the region of the first epitaxial layer which is not subjected to ion implantation by using the ion implantation process.

[0229] In the embodiment, the step S40 is: forming the third P-type semiconductor region 9 which is in contact with the second P-type semiconductor region 8 on the first side wall S1 of each gate trench 01 along the first direction by using inclined ion implantation process.

[0230] For example, referring to Figure 21 , the third P-type semiconductor region 9 which is in contact with the second P-type semiconductor region 8 is formed by P-type impurity doping on the surface of the first side wall S1 of each gate trench 01 by using inclined ion implantation process.

[0231] Figure 22 A top view structural schematic diagram of a semiconductor device provided by another embodiment of the application is shown.

[0232] For example, referring to Figure 22 , in some other embodiments provided by the application, the semiconductor device comprises: an N-type semiconductor substrate 1, a first epitaxial layer, a plurality of gate trenches 01 which are arranged at intervals, a gate 11, an interlayer dielectric layer 12, a source 13 and a drain 14. The first epitaxial layer comprises: a first N-type semiconductor region 2, a second N-type semiconductor region 3, a first P-type semiconductor region 4, a source region 6, a second P-type semiconductor region 8, a third P-type semiconductor region 9 and a fourth P-type semiconductor region 5. The embodiment is a transformation of the implementation in the above-mentioned embodiments. Only the differences between the embodiment and the above-mentioned embodiments are described below, and the same parts are not described here.

[0233] For example, referring to Figure 22In at least a portion of the gate trenches 01 in two adjacent trench groups, the gate trenches 01 arranged along the first direction x are interconnected. For example, gate trench 01c1 in trench group GK1 and gate trench 01c2 in trench group GK2 are arranged along the first direction x, and gate trench 01c1 and gate trench 01c2 are interconnected. Gate trench 01d1 in trench group GK1 and gate trench 01d2 in trench group GK2 are arranged along the first direction x, and gate trench 01d1 and gate trench 01d2 are interconnected. Gate trench 01e1 in trench group GK1 and gate trench 01e2 in trench group GK2 are arranged along the first direction, and gate trench 01e1 and gate trench 01e2 are interconnected.

[0234] Exemplarily, in this application, the plurality of gate trenches includes a first gate trench and a second gate trench extending along a first direction x, wherein the first gate trench and the second gate trench are respectively located in two adjacent trench groups. That is, the first gate trench is located in one of the two adjacent trench groups, the second gate trench is located in the other trench group of the two adjacent trench groups, and the first gate trench and the second gate trench are interconnected. For example, refer to... Figure 22 In trench group GK1, gate trench 01c1 can serve as the first gate trench, and in trench group GK2, gate trench 01c2 can serve as the second gate trench. Gate trenches 01c1 and 01c2 in trench group GK1 and GK2 are interconnected. Similarly, gate trench 01d1 in trench group GK1 can serve as the first gate trench, and in trench group GK2, gate trench 01d2 can serve as the second gate trench. Gate trenches 01d1 and 01d2 in trench group GK1 and GK2 are interconnected. Finally, gate trench 01e1 in trench group GK1 can serve as the first gate trench, and in trench group GK2, gate trench 01e2 can serve as the second gate trench.

[0235] Reference Figure 22 The contact hole 02 includes a plurality of sub-contact holes spaced apart from each other, and at least one through gate trench 01 is provided between two adjacent sub-contact holes in the same contact hole 02. This application does not limit the number of sub-contact holes into which the contact hole 02 is divided; for example, it can be two, three, four, or more. Furthermore, this application does not limit the number of through gate trenches 01 provided between two adjacent sub-contact holes in the same contact hole 02; for example, it can be one, two, three, four, or more. This increases the design freedom of the contact hole 02 and improves the current uniformity of the SiC MOSFET device.

[0236] For example, refer to Figure 22The contact hole includes sub-contact holes 02a and 02b which are arranged at intervals. The sub-contact holes 02a and 02b are arranged with gate trenches 01d1 and 01d2 which are mutually penetrated.

[0237] Figure 23 A perspective structural schematic diagram of a semiconductor device provided by another embodiment of the present application is shown.

[0238] Referring to Figure 23 In some other embodiments provided by the present application, the semiconductor device includes an N-type semiconductor substrate 1, a first epitaxial layer, a second epitaxial layer 201, a plurality of gate trenches 01 arranged at intervals, a gate 11, an interlayer dielectric layer 12, a source 13, and a drain 14. The first epitaxial layer includes a first N-type semiconductor region 2, a second N-type semiconductor region 3, a first P-type semiconductor region 4, a source region 6, a second P-type semiconductor region 8, a third P-type semiconductor region 9, and a fourth P-type semiconductor region 5. The present embodiment is a variation of the implementation in the above-mentioned embodiments. Only the differences between the present embodiment and the above-mentioned embodiments are described below, and the same parts are not described again.

[0239] Referring to Figure 23 The second epitaxial layer 201 is arranged between the first epitaxial layer (for example, the first N-type semiconductor region 2) and the semiconductor substrate 1. Because the second epitaxial layer 201 is arranged, the thickness of the second P-type semiconductor region 8 in the first epitaxial layer 100 in the third direction z can be arranged to be relatively thick, for example, the thickness of the second P-type semiconductor region 8 in the third direction z can be arranged to be greater than 1 um.

[0240] Referring to Figure 23 In the present embodiment, the second epitaxial layer 201 is an N-type semiconductor region. For example, the second epitaxial layer 201 is SiC doped with an N-type impurity, such as nitrogen (N), phosphorus (P), or arsenic (As). For example, the doping concentration of the second epitaxial layer 201 is less than the doping concentration of the first N-type semiconductor region 2.

[0241] For example, referring to Figure 23 The flowchart of the corresponding preparation method can be referred to Figure 24 . Among them, steps S10-S90 can be referred to the description of the preparation method described above.

[0242] Before step S10, it further includes step S00: epitaxially growing a second epitaxial layer on the N-type semiconductor substrate 1.

[0243] For example, referring to Figure 23 On the N-type SiC semiconductor substrate 1, a SiC material doped with an N-type impurity is epitaxially grown on the N-type SiC semiconductor substrate 1 by using an epitaxial process to form the second epitaxial layer 201.

[0244] The embodiment of the present application further provides a power conversion circuit, which can be an AC-DC conversion circuit and / or a DC-DC conversion circuit. The power conversion circuit can comprise a circuit board and one or more semiconductor devices, and the semiconductor devices are connected with the circuit board. Since the semiconductor devices have good performance, the power conversion circuit comprising the semiconductor devices also has good performance. In addition, the power conversion circuit has similar problem-solving principles to the semiconductor devices, and thus the technical effects of the power conversion circuit can refer to those of the semiconductor devices, and the repeated parts will not be described herein.

[0245] The embodiment of the present application further provides a vehicle comprising the power conversion circuit provided by the embodiment of the present application. Since the power conversion circuit has good performance, the circuit of the vehicle comprising the power conversion circuit also has good performance. In addition, the vehicle has similar problem-solving principles to the power conversion circuit, and thus the technical effects of the vehicle can refer to those of the power conversion circuit, and the repeated parts will not be described herein.

[0246] Obviously, those skilled in the art can make various modifications and variations to the present application without departing from the scope of the present application. Thus, if these modifications and variations of the present application belong to the scope of the claims of the present application and their equivalent technologies, the present application is also intended to include these modifications and variations.

Claims

1. A semiconductor device, characterized in that, include: N-type semiconductor substrate; A first epitaxial layer is disposed on the semiconductor substrate; A plurality of gate trenches are spaced apart from each other, and the plurality of gate trenches extend upward along a third direction perpendicular to the plane of the semiconductor substrate into the first epitaxial layer; wherein, the plurality of gate trenches extend along a first direction parallel to the plane of the semiconductor substrate, and the plurality of gate trenches are arranged along a second direction parallel to the plane of the semiconductor substrate; the first direction, the second direction, and the third direction are intersecting each other; The gate includes a first gate and a second gate that are in contact with each other. The first gate is filled in the gate trench through a gate dielectric layer, and the second gate is disposed on the top of the first epitaxial layer through the gate dielectric layer. An interlayer dielectric layer covers the side of the gate away from the semiconductor substrate, and the interlayer dielectric layer has contact holes; wherein the contact holes extend along the second direction and penetrate the plurality of gate trenches, the orthographic projection of the contact holes on the semiconductor substrate does not overlap with the orthographic projection of the gate on the semiconductor substrate, and the contact holes expose a portion of the first epitaxial layer; The source electrode is disposed on the side of the interlayer dielectric layer away from the semiconductor substrate, and the source electrode contacts the first epitaxial layer exposed by the contact hole through the contact hole; The drain is disposed on the side of the semiconductor substrate away from the first epitaxial layer.

2. The semiconductor device as claimed in claim 1, characterized in that, The plurality of gate trenches are divided into at least one trench group; the contact holes are at least two; A groove group is provided between two adjacent contact holes, and the contact holes penetrate the groove group in the second direction.

3. The semiconductor device as described in claim 2, characterized in that, The number of gate trenches is the same in different trench groups.

4. The semiconductor device as described in claim 2, characterized in that, The plurality of gate trenches includes a first gate trench and a second gate trench that extend along the first direction, wherein the first gate trench and the second gate trench are respectively located in two adjacent trench groups; The contact hole includes a plurality of sub-contact holes spaced apart from each other, and at least one through gate trench is provided between two adjacent sub-contact holes in the same contact hole.

5. The semiconductor device according to any one of claims 1-4, characterized in that, The first epitaxial layer includes: a first N-type semiconductor region, a second N-type semiconductor region, a first P-type semiconductor region, and a source region. The first N-type semiconductor region is disposed between the second N-type semiconductor region and the semiconductor substrate. The first P-type semiconductor region is disposed on the side of the second N-type semiconductor region away from the semiconductor substrate. The source region is disposed on the side of the first P-type semiconductor region away from the semiconductor substrate. In a third direction perpendicular to the plane containing the semiconductor substrate, the gate trench extends into the first N-type semiconductor region; The contact hole exposes a portion of the source region.

6. The semiconductor device as claimed in claim 5, characterized in that, The first epitaxial layer further includes: The second P-type semiconductor region is disposed below the gate trench and is connected to the source.

7. The semiconductor device as claimed in claim 6, characterized in that, In the first direction, the gate trench has a first sidewall and a second sidewall disposed opposite to each other; The first epitaxial layer further includes: The third P-type semiconductor region is disposed on at least one first sidewall and / or second sidewall of the gate trench, and the third P-type semiconductor region is in contact with the second P-type semiconductor region. The fourth P-type semiconductor region is disposed on the same layer as the source region, and is located on the side of the third P-type semiconductor region away from the gate trench. The fourth P-type semiconductor region is in contact with the third P-type semiconductor region, and is in contact with the source through the contact hole.

8. The semiconductor device as claimed in claim 7, characterized in that, The first epitaxial layer further includes: The fifth P-type semiconductor region is disposed on the same layer as the source region. The fifth P-type semiconductor region is disposed on the side of the gate trench sidewall where the third P-type semiconductor region is not disposed, and the fifth P-type semiconductor region is in contact with the corresponding source electrode through the contact hole.

9. The semiconductor device as claimed in claim 8, characterized in that, There are multiple fifth P-type semiconductor regions, and each of the multiple fifth P-type semiconductor regions is provided in a one-to-one correspondence with the second sidewall of the multiple gate trenches; The source regions are multiple, and the gate trenches are alternately arranged with the multiple source regions.

10. The semiconductor device according to any one of claims 7-9, characterized in that, The orthogonal projection of the second P-type semiconductor region onto the semiconductor substrate covers the orthogonal projection of the gate trench onto the semiconductor substrate and the orthogonal projection of the third P-type semiconductor region onto the semiconductor substrate.

11. The semiconductor device as claimed in claim 10, characterized in that, The second P-type semiconductor region is a planar region extending along the second direction; The orthographic projection of the second P-type semiconductor region onto the semiconductor substrate also covers the gap between the orthographic projections of two adjacent gate trenches onto the semiconductor substrate.

12. The semiconductor device as claimed in claim 5, characterized in that, The semiconductor device further includes: The second epitaxial layer of the N-type semiconductor is disposed between the first epitaxial layer and the semiconductor substrate, and the doping concentration of the second epitaxial layer is less than the doping concentration of the first N-type semiconductor region. The thickness of the second epitaxial layer in the third direction is greater than 1 μm.

13. The semiconductor device as claimed in claim 12, characterized in that, The semiconductor substrate, the first epitaxial layer, and the second epitaxial layer are made of SiC.

14. A method for fabricating a semiconductor device, characterized in that, include: A first epitaxial layer is epitaxially grown on an N-type semiconductor substrate; The first epitaxial layer is etched to form a plurality of gate trenches that are spaced apart from each other and extend upward along a third direction perpendicular to the plane of the semiconductor substrate into the first epitaxial layer. The plurality of gate trenches extend along a first direction parallel to the plane of the semiconductor substrate and are arranged along a second direction parallel to the plane of the semiconductor substrate. The first direction, the second direction and the third direction are intersected with each other. A gate dielectric layer is formed in the gate trench; A first gate is formed in a gate trench in which a gate dielectric layer is formed, and a second gate is formed on top of the first epitaxial layer, and the first gate and the second gate are made to contact each other. An interlayer dielectric layer covering the entire first epitaxial layer is formed on the gate; The interlayer dielectric layer is etched to form a contact hole that extends along the second direction and penetrates the plurality of gate trenches. The contact hole exposes a portion of the first epitaxial layer, and the orthographic projection of the contact hole on the semiconductor substrate does not overlap with the orthographic projection of the gate on the semiconductor substrate. A source electrode is formed on the side of the interlayer dielectric layer away from the semiconductor substrate, and the source electrode is made to contact the first epitaxial layer exposed by the contact hole through the contact hole; and a drain electrode is formed on the side of the semiconductor substrate away from the first epitaxial layer.

15. The preparation method according to claim 14, characterized in that, After epitaxially growing the first epitaxial layer on an N-type semiconductor substrate, the fabrication method further includes: An ion implantation process is used to implant ions into a portion of the first epitaxial layer to form a second N-type semiconductor region, a first P-type semiconductor region, and a source region. The region in the first epitaxial layer that is not ion implanted forms the first N-type semiconductor region. The first N-type semiconductor region is disposed between the second N-type semiconductor region and the semiconductor substrate. The first P-type semiconductor region is disposed on the side of the first N-type semiconductor region away from the semiconductor substrate. The source region is disposed on the side of the first P-type semiconductor region away from the semiconductor substrate. The contact hole exposes a portion of the source region.

16. The preparation method according to claim 15, characterized in that, The epitaxial growth of the first epitaxial layer on the N-type semiconductor substrate includes: A first epitaxial layer of a first predetermined thickness is epitaxially grown on the N-type semiconductor substrate; The first epitaxial layer is ion implanted using an ion implantation process to form a second P-type semiconductor region. On the first epitaxial layer that forms the second P-type semiconductor region, epitaxial growth continues until a first epitaxial layer of a second predetermined thickness is formed.

17. The preparation method according to claim 16, characterized in that, The preparation method further includes: Before forming a gate dielectric layer in the gate trench, a tilted ion implantation process is used to form a third P-type semiconductor region that contacts the second P-type semiconductor region on at least one sidewall of the gate trench along the first direction. The preparation method further includes: When forming the source region, an ion implantation process is used to form a fourth P-type semiconductor region in the first epitaxial layer, which is disposed in the same layer as the source region. The fourth P-type semiconductor region is disposed in the same layer as the source region, and is located on the side of the third P-type semiconductor region away from the gate trench. The fourth P-type semiconductor region is in contact with the third P-type semiconductor region, and is in contact with the source electrode through the contact hole.

18. A power conversion circuit, characterized in that, It includes a circuit board and one or more semiconductor devices as described in any one of claims 1-13, wherein the semiconductor devices are connected to the circuit board.

19. A vehicle, characterized in that, Includes the power conversion circuit as described in claim 18, the power conversion circuit being used to convert AC and / or DC power to output DC power.

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