Test system and device for many-core chip array

Abstract

The present disclosure relates to a testing system and device for a many-core chip array, the device comprising: a control module; a chip array, comprising a plurality of many-core chips to be tested, the plurality of many-core chips to be tested forming a chip array of K rows and N columns; the control module is used to output a test instruction to each of the many-core chips to be tested, test each of the many-core chips to be tested, and read the returned data from each of the many-core chips to be tested, and determine the test result according to the returned data, wherein the test result includes at least one of whether the read and write functions of each of the many-core chips to be tested are normal, whether the connectivity between each of the many-core chips to be tested is normal, and whether the operation function of each of the many-core chips to be tested is normal. The embodiments of the present disclosure can realize batch testing of multiple many-core chips, and because the implementation of the device is relatively simple, it brings the advantages of low manufacturing cost and maintenance cost.

Description

Technical Field

[0001] The present disclosure relates to the field of testing technology, and in particular to a testing system and device for a many-core chip array. Background Art

[0002] A many-core chip refers to a processor chip that integrates dozens or even more processor cores on a single chip. Since a many-core chip has many processor cores integrated on it, the chip tester used in the related technology usually tests the many-core chips one by one and cannot achieve batch testing of multiple many-core chips. In addition, the manufacturing cost and maintenance cost of the chip tester used in the related technology are high, and the solution is relatively complicated. Summary of the invention

[0003] According to one aspect of the present disclosure, a testing device for a many-core chip array is provided, the device comprising:

[0004] Control module;

[0005] A chip array, comprising a plurality of many-core chips to be tested, wherein the plurality of many-core chips to be tested form a chip array of K rows and N columns, wherein the many-core chips to be tested in each row are connected in sequence, and the many-core chips to be tested in each column are connected in sequence, and each of the many-core chips to be tested in the first row, the Kth row, the first column, and the Nth column in the chip array are connected to the control module, and K and N are both positive integers;

[0006] The control module is used to output test instructions to each many-core chip to be tested, test each many-core chip to be tested, and read returned data from each many-core chip to be tested, and determine the test result according to the returned data, wherein the test result includes at least one of whether the read and write functions of each many-core chip to be tested are normal, whether the connectivity between each many-core chip to be tested is normal, and whether the computing function of each many-core chip to be tested is normal.

[0007] In a possible implementation manner, the test instruction includes a write instruction and a read instruction, and the control module is used to:

[0008] Data is written to each of the many-core chips to be tested through the write instruction, and data of each of the many-core chips to be tested is read through the read instruction to determine the test result.

[0009] In a possible implementation manner, the control module is used to:

[0010] When the data read from any of the many-core chips to be tested is the same as the data written into it, it is determined that the reading and writing of the many-core chip to be tested is normal; otherwise, it is determined that the reading and writing of the many-core chip to be tested is abnormal.

[0011] In a possible implementation manner, the control module is further used for:

[0012] When it is determined that the read and write of the many-core chip to be tested is normal, it can be determined that the connectivity of the corresponding read and write ports of the many-core chip to be tested is normal;

[0013] When it is determined that the read and write of the many-core chip to be tested is abnormal, the position of the many-core chip to be tested is switched, data is rewritten to the many-core chip to be tested after the switched position, and data is reread from the many-core chip to be tested. When it is determined that the read and write of the many-core chip to be tested is normal for M consecutive times, it can be determined that the connectivity of the corresponding read and write ports of the many-core chip to be tested is normal. Otherwise, it is determined that the connectivity of the corresponding read and write ports of the many-core chip to be tested is abnormal, wherein M is a positive integer, and the port from which data is read indicates that the connectivity of the port is normal.

[0014] In a possible implementation manner, when it is determined that the read and write of the many-core chip to be tested is normal, it can be determined that the connectivity of the corresponding read and write ports of the many-core chip to be tested is normal, including:

[0015] If the multi-core chip to be tested is read and written through the first path, and it is determined that the reading and writing of the multi-core chip to be tested is normal, then it is determined that the connectivity of each port on the first path is normal.

[0016] The first path is composed of the port of the control module, the port of the multi-core chip to be tested, and the corresponding port of the multi-core chip to be tested between the port of the control module and the port of the multi-core chip to be tested.

[0017] In a possible implementation manner, the normal connectivity between the multi-core chips to be tested means that line communication is normal and reading and writing are normal.

[0018] In a possible implementation manner, the control module is further used for:

[0019] Write the model parameters of the neural network to each multi-core chip to be tested through write instructions;

[0020] Writing initial data in a preset target scenario to each of the many-core chips to be tested through a write instruction, so that each of the many-core chips to be tested performs a neural network operation in the preset target scenario to obtain an operation result;

[0021] The operation results of each of the many-core chips to be tested are read through the read instruction, and whether the operation functions of each of the many-core chips to be tested are normal is determined according to the operation results.

[0022] In a possible implementation, the device further includes:

[0023] K power supply units, each power supply unit is used to supply power to each row of the multi-core chips to be tested in the chip array, each power supply unit has multiple power supply modes, each power supply mode has different power supply parameters, and each power supply mode corresponds to the working mode of each row of the multi-core chips to be tested.

[0024] In a possible implementation manner, the control module is further configured to determine the power consumption of each of the many-core chips to be tested in various power supply modes and working modes.

[0025] In a possible implementation, the control module includes a host computer and a programmable logic controller, the host computer includes a sending module, a receiving module, and a detection module, and the programmable logic controller includes a downlink processing module and an uplink processing module, wherein:

[0026] The input end of the uplink processing module and the output end of the downlink processing module are both connected to the chip array.

[0027] The output end of the sending module is connected to the input end of the downlink processing module, the sending module is used to send the test instruction, and the downlink processing module is used to process the test instruction and then send it to each multi-core chip to be tested.

[0028] The input end of the receiving module is connected to the output end of the uplink processing module, and the uplink processing module is used to process the data received from each multi-core chip to be tested and then send it to the receiving module.

[0029] The detection module is connected to the receiving module and is used to determine the test result according to the data transmitted by the receiving module.

[0030] According to another aspect of an embodiment of the present disclosure, a testing system for a many-core chip array is also provided. The system includes the testing device for the many-core chip array.

[0031] The disclosed embodiment forms a chip array of K rows and N columns by forming a plurality of many-core chips to be tested, uses a control module to output test instructions to each of the many-core chips to be tested, tests each of the many-core chips to be tested, reads returned data from each of the many-core chips to be tested, and determines the test result based on the returned data, thereby enabling batch testing of multiple many-core chips. Furthermore, since the implementation of the device is relatively simple, it has the advantages of lower manufacturing cost and maintenance cost.

[0032] It should be understood that the above general description and the following detailed description are exemplary and explanatory only and do not limit the present disclosure. Other features and aspects of the present disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The drawings herein are incorporated into the specification and constitute a part of the specification. These drawings illustrate embodiments consistent with the present disclosure and are used to illustrate the technical solutions of the present disclosure together with the specification.

[0034] Figure 1 A block diagram of a testing device for a many-core chip array according to an embodiment of the present disclosure is shown.

[0035] Figure 2 A logical block diagram of a testing device for a many-core chip array according to an embodiment of the present disclosure is shown.

[0036] Figure 3 A logical flow diagram of a testing device for a many-core chip array according to an embodiment of the present disclosure is shown.

[0037] Figure 4 A module block diagram of a testing device for a many-core chip array according to an embodiment of the present disclosure is shown.

[0038] Figure 5 A module block diagram of a testing device for a many-core chip array according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0039] Various exemplary embodiments, features and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise specified.

[0040] In the description of the present disclosure, it should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present disclosure.

[0041] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present disclosure, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0042] In the present disclosure, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.

[0043] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0044] The term "and / or" herein is only a description of the association relationship of the associated objects, indicating that there may be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the term "at least one" herein represents any combination of at least two of any one or more of a plurality of. For example, including at least one of A, B, and C can represent including any one or more elements selected from the set consisting of A, B, and C.

[0045] In addition, in order to better illustrate the present disclosure, numerous specific details are given in the following specific embodiments. It should be understood by those skilled in the art that the present disclosure can also be implemented without certain specific details. In some examples, methods, means, components and circuits well known to those skilled in the art are not described in detail in order to highlight the subject matter of the present disclosure.

[0046] See also Figure 1 , Figure 1 A block diagram of a testing device for a many-core chip array according to an embodiment of the present disclosure is shown.

[0047] like Figure 1 As shown, the device comprises:

[0048] Control module 10;

[0049] A chip array, comprising a plurality of many-core chips 20 to be tested, wherein the plurality of many-core chips 20 to be tested form a chip array of K rows and N columns, wherein the many-core chips 20 to be tested in each row are connected in sequence, and the many-core chips 20 to be tested in each column are connected in sequence, and each of the many-core chips 20 to be tested in the first row, the Kth row, the first column, and the Nth column in the chip array are all connected to the control module 10, and K and N are both positive integers;

[0050] The control module 10 is used to output test instructions to each of the many-core chips 20 to be tested, test each of the many-core chips 20 to be tested, and read the returned data from each of the many-core chips 20 to be tested, and determine the test result according to the returned data, wherein the test result includes at least one of whether the read and write functions of each of the many-core chips 20 to be tested are normal, whether the connectivity between each of the many-core chips to be tested is normal, and whether the computing function of each of the many-core chips to be tested is normal.

[0051] The disclosed embodiment forms a chip array of K rows and N columns by forming a plurality of many-core chips 20 to be tested, uses a control module 10 to output a test instruction to each of the many-core chips 20 to be tested, tests each of the many-core chips 20 to be tested, reads the returned data from each of the many-core chips 20 to be tested, and determines the test result according to the returned data, thereby enabling batch testing of multiple many-core chips. Furthermore, since the implementation of the device is relatively simple, it has the advantages of lower manufacturing cost and maintenance cost.

[0052] The embodiments of the present disclosure do not limit the specific sizes of the number of rows K and the number of columns N of the chips in the chip array. Those skilled in the art can set them according to actual conditions and needs. For example, K and N can both be 3.

[0053] The control module 10 of the disclosed embodiment uses a field programmable gate array (FPGA), i.e., a programmable logic controller. The disclosed embodiment does not limit the specific implementation of the control module 10, and those skilled in the art can set it according to actual conditions and needs. For example, the control module 10 may include a processing component, a terminal including a processing component, or a combination thereof.

[0054] Exemplarily, the processing component includes but is not limited to a separate processor, or a discrete component, or a combination of a processor and a discrete component. The processor may include a controller having an execution instruction function in an electronic device, and the processor may be implemented in any appropriate manner, for example, by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors or other electronic components. Inside the processor, the executable instructions may be executed by hardware circuits such as logic gates, switches, application-specific integrated circuits (ASICs), programmable logic controllers, and embedded microcontrollers.

[0055] Exemplarily, a terminal is also called a user equipment (UE), a mobile station (MS), a mobile terminal (MT), etc., and is a device that provides voice and / or data connectivity to a user, for example, a handheld device with a wireless connection function, a vehicle-mounted device, etc. At present, some examples of terminals are: mobile phones, tablet computers, laptop computers, PDAs, mobile Internet devices (MID), wearable devices, virtual reality (VR) devices, augmented reality (AR) devices, wireless terminals in industrial control (Industrial Control), wireless terminals in self-driving (Selfdriving), wireless terminals in remote medical surgery (Remote Medical Surgery), wireless terminals in smart grids (Smart Grid), wireless terminals in transportation safety (Transportation Safety), wireless terminals in smart cities (Smart City), wireless terminals in smart homes (Smart Home), wireless terminals in Internet of Vehicles, etc.

[0056] Exemplarily, the control module 10 may include a host computer and a programmable logic controller, and the host computer may include the aforementioned terminal.

[0057] The embodiments of the present disclosure do not limit the specific implementation method for determining the test results based on the returned data, and do not limit the test items. Those skilled in the art can set them according to actual conditions and needs. Exemplarily, the test items may include read-write tests, connectivity tests of various ports of the multi-core chip, and operation tests. Correspondingly, the test results include whether the read-write functions of each multi-core chip 20 to be tested are normal, whether the connectivity between each multi-core chip to be tested is normal, and whether the operation function of each multi-core chip to be tested is normal. The embodiments of the present disclosure do not limit the specific technical means for judging whether the read-write function is normal, whether the connectivity is normal, and whether the operation function of each multi-core chip to be tested is normal. Those skilled in the art can set them according to actual conditions and needs, and an exemplary introduction is given below.

[0058] The embodiment of the present disclosure does not limit the type of test instructions, and those skilled in the art may set the type according to actual conditions and needs. In a possible implementation, the test instructions may include write instructions and read instructions, and the control module 10 may be used to:

[0059] The data is written to each of the many-core chips 20 to be tested through the write instruction, and the data of each of the many-core chips 20 to be tested is read through the read instruction to determine the test result.

[0060] See also Figure 2 , Figure 3 , Figure 2 , Figure 3 A logical block diagram of a testing device for a many-core chip array according to an embodiment of the present disclosure is shown.

[0061] For example, Figure 2 As shown, in a possible implementation, the control module may include a host computer and a programmable logic controller. The embodiment of the present disclosure can send test instructions such as write instructions and read instructions to the interface of the programmable logic controller through the host computer, and the programmable logic controller processes the test instructions and sends them to each chip in the chip array.

[0062] The programmable logic controller of the disclosed embodiment acts as a controller to connect the host computer end with the chip array to form a path, thereby realizing the chip testing function. It is possible to test different multi-core chips in the chip array, and it is also possible to test different cores of the multi-core chip. The host computer can select one or more multi-core chips to be tested, or different cores of one or more multi-core chips for testing. By comparing the return data of the chip test with the correct value, it can be determined whether the test condition of the chip meets the requirements.

[0063] For example, Figure 3 As shown, in a possible implementation, the host computer may include a sending module, a receiving module, and a detection module, and the programmable logic controller includes a downlink processing module and an uplink processing module, wherein:

[0064] The input end of the uplink processing module and the output end of the downlink processing module are both connected to the chip array.

[0065] The output end of the sending module is connected to the input end of the downlink processing module, the sending module is used to send the test instruction, and the downlink processing module is used to process the test instruction and send it to each of the many-core chips 20 to be tested.

[0066] The input end of the receiving module is connected to the output end of the uplink processing module, and the uplink processing module is used to process the data received from each of the many-core chips 20 to be tested and then send the data to the receiving module.

[0067] The detection module is connected to the receiving module and is used to determine the test result according to the data transmitted by the receiving module.

[0068] The embodiments of the present disclosure do not limit the specific implementation methods of the sending module, the receiving module, the detection module, the downlink processing module, and the uplink processing module. Those skilled in the art may adopt appropriate technical implementations according to actual conditions and needs.

[0069] For example, the host computer can send instructions and receive information. The programmable logic controller processes the test instructions received from the host computer and then sends them to the chip. The chip array receives the instructions from the programmable logic array and processes them. After the chip processes, a piece of information (indicating the execution result of the instruction) is generated. This information is sent to the host computer through the programmable logic controller. The host computer receives and displays it, and a round of information interaction is completed.

[0070] The embodiments of the present disclosure do not limit the specific manner in which the downlink processing module and the test instructions are processed. Those skilled in the art may adopt a suitable processing manner according to actual conditions and needs. For example, the test instructions may be packaged and processed according to the protocol packet structure shown in Table 1, and the processed test instructions include protocol content, valid data, and check bits.

[0071] Table 1

[0072]

[0073] Among them, those skilled in the art of communication protocol can set it according to actual conditions and needs, and the embodiments of the present disclosure are not limited thereto. The valid data can be the test instruction and the data contained therein, and the check bit can be used for parity check or any other type of check.

[0074] The embodiments of the present disclosure do not limit the specific forms of the write instructions and the read instructions, and those skilled in the art may configure them according to actual conditions and needs.

[0075] Exemplarily, the write instruction may include a register selection instruction, a chip configuration write instruction, a control write instruction, a calculation instruction, and a data transmission instruction. The disclosed embodiment may control program jump calls, data calculations, and data transmissions through instructions to specify one or more cores in the multi-core chip to perform operations. The write instruction may be written by the host computer to the chip register through the programmable logic controller.

[0076] Exemplarily, the read instruction may include reading a value in a register of the chip (which may be an initial value or a written data value), a result value obtained by running test data, etc. The read instruction may be sent by the host computer to the chip through the programmable logic controller to obtain data returned by the multi-core chip to be tested, and then the programmable logic controller transmits the data to the host computer, thereby displaying the data obtained by the read instruction.

[0077] For example, a value of 1 can be written into the register 0 of the multi-core chip to be tested. The register 0 is input into the register control module of the host computer software, the value 1 is input into the value module, and the write data is clicked. This operation will generate a write instruction, which is sent by the host computer to the programmable logic controller, and then sent to the multi-core chip 20 to be tested after passing through the downlink processing module in the programmable logic controller. After the multi-core chip 20 to be tested processes, the value 1 can be written into the register 0. When reading the data of the register 0 of the multi-core chip to be tested, the identifier of the register 0 is input into the register control module of the host computer software, and the read data (register 0) is clicked. At this time, the host computer generates a read instruction and sends it to the programmable logic controller, which is sent by the programmable logic controller to the multi-core chip 20 to be tested to identify this instruction as the data to read the register 0, and returns this data to the programmable logic controller, which is then uploaded to the receiving module of the host computer by the programmable logic controller. Of course, the above-described process of writing and reading data in the register of the multi-core chip 20 to be tested is exemplary and should not be regarded as a limitation of the embodiments of the present disclosure.

[0078] The embodiments of the present disclosure can perform synchronous testing or asynchronous testing on each of the many-core chips 20 to be tested, and can select one or more rows, one or more columns for testing, or select the many-core chips 20 to be tested in a specific area (such as a regular rectangular area or an irregular area) for testing. The embodiments of the present disclosure can implement synchronous testing of multiple many-core chips 20 to be tested that constitute a chip array through write instructions and read instructions, which can improve test efficiency, reduce test costs, and can perform individual tests on specific chips to be tested, with high flexibility.

[0079] In a possible implementation, the control module 10 may be used to:

[0080] When the data read from any of the many-core chips 20 to be tested is the same as the data written thereto, it is determined that the reading and writing of the many-core chip 20 to be tested is normal; otherwise, it is determined that the reading and writing of the many-core chip 20 to be tested is abnormal.

[0081] Exemplarily, assuming that the written data is data 1 and the read data is data 2, if data 2 is determined to be the same as data 1 through comparison, then the reading and writing of the many-core chip 20 under test is determined to be normal, otherwise the reading and writing of the many-core chip 20 under test is determined to be abnormal.

[0082] In a possible implementation manner, the control module 10 may also be used for:

[0083] When it is determined that the read and write of the many-core chip 20 to be tested is normal, determining that the connectivity of the corresponding read and write ports of the many-core chip 20 to be tested is normal;

[0084] In the case where it is determined that the read and write of the many-core chip 20 to be tested is abnormal, the position of the many-core chip 20 to be tested is switched, data is rewritten to the many-core chip 20 to be tested after the switched position, and data is reread from the many-core chip 20 to be tested. If it is determined that the read and write of the many-core chip 20 to be tested is normal for M consecutive times, it can be determined that the connectivity of the corresponding read and write ports of the many-core chip 20 to be tested is normal, otherwise it is determined that the connectivity of the corresponding read and write ports of the many-core chip 20 to be tested is abnormal, where M is a positive integer. Specifically, which port reads data indicates which port has normal connectivity, and if all ports can read data, it indicates that the connectivity of all ports is normal.

[0085] In a possible implementation, normal connectivity between the multi-core chips to be tested may mean that line communication is normal and reading and writing are normal, and the multi-core chips to be tested can read and write normally and line communication is normal. In order to improve test efficiency, if it is determined that the multi-core chips to be tested can read and write normally, it can be regarded as normal connectivity.

[0086] In a possible implementation manner, when it is determined that the read and write of the many-core chip to be tested is normal, it can be determined that the connectivity of the corresponding read and write ports of the many-core chip to be tested is normal, which may include:

[0087] If the multi-core chip to be tested is read and written through the first path, and it is determined that the reading and writing of the multi-core chip to be tested is normal, then it is determined that the connectivity of each port on the first path is normal.

[0088] The first path is composed of the port of the control module, the port of the multi-core chip to be tested, and the corresponding port of the multi-core chip to be tested between the port of the control module and the port of the multi-core chip to be tested.

[0089] See also Figure 4 , Figure 4 A module block diagram of a testing device for a many-core chip array according to an embodiment of the present disclosure is shown.

[0090] For example, Figure 4 As shown, the chip array may include 9 many-core chips 20 to be tested, forming a 3×3 chip array. For ease of description, the many-core chips 20 to be tested in the chip array are marked as chip A0, chip A1, chip A2, chip B0, chip B1, chip B2, chip C0, chip C1, and chip C2, respectively. Figure 4 In the figure, each multi-core chip 20 to be tested has ports in four directions (which can be Serdes high-speed channels). Taking chip A0 as an example, the port marked with 1 is in the south direction, the port marked with 2 is in the north direction, the port marked with 3 is in the west direction, and the port marked with 4 is in the east direction. The other chips are similar and will not be repeated here.

[0091] For example, Figure 4 As shown, in the 3x3 chip array to be tested, the south end of the chips A0, B0, and C0 are connected to the programmable logic controller in the control module 10, and the chip B1 located in the center is connected to the chip B0, chip A1, chip B2, and chip C1 in four directions. Chip B1 can test the connectivity in four directions.

[0092] For example, Figure 4 As shown, in the 3x3 chip array to be tested, assuming that chip A0 (the multi-core chip to be tested) is read and written through the first path (the first path includes the port of the control module and the south port of chip A0, or the port of the control module and the west port of chip A0), and chip A0 is read and written normally, it can be said that the south and west paths of chip A0 are normal. Assuming that chip B0 is read and written through the first path (the first path includes the port of the control module and the south port of chip B0), and it is determined that chip B0 is read and written normally, it can be said that the south path of chip B0 is normal. Assuming that chip C0 is read and written through the first path (the first path includes the port of the control module and the south port of chip C0, or the port of the control module and the east port of chip C0), and chip C0 is read and written normally, it is shown that the south and east paths of the chip at the position of chip C0 are normal.

[0093] For example, Figure 4 As shown, assuming that reading and writing are performed from the south and north sides of the chip (i.e., reading and writing are performed via the south port and north port of the chip), for example, the first path corresponding to chip A1 includes the port of the control module, the south port of chip A0, the north port of chip A0, and the south port of chip A1. If chip A1 reads and writes normally, it can be explained that the south side of chip A1, the south side of chip A0, and the north side path are normal (i.e., the first path is normal). Chip B1 is similar to chip C1. If chip A2 reads and writes normally, it can be explained that the south side of chip A2, the south side of chip A0 and the north side paths of chip A1 are normal, and chip B2 is similar to chip C2.

[0094] For example, if reading and writing chip B0 from the west channel of chip A0 is normal (the first channel includes the port of the control module, the west port of chip A0, the east port of chip A0, and the west port of chip B0), it can be said that the channel composed of the port of the control module, the west port of chip A0, the east port of chip A0, and the west port of chip B0 is normal, and chip A1 is similar to chip A2.

[0095] For example, if the reading and writing of chip C0 from the west channel of chip A0 is normal, it can be explained that the west and east channels of chip A0 and chip B0 are normal, and chip C1 and chip C2 are similar.

[0096] For example, if the reading and writing of the chip in the four directions of east, south, west, and north are all normal, it proves that the four directional paths of the chip are normal.

[0097] For example, if chip A1 has abnormal reading and writing in the south direction, it can be switched, for example, to the position of chip A0, that is, the positions of chip A1 and chip A0 are interchanged. After multiple reading and writing, chip A1 is placed in the A0 position and the reading and writing in the south direction are normal. This means that chip A1 had abnormal reading and writing in the north direction or A1 had abnormal reading and writing in the south direction. Chip B1 is similar to chip C1.

[0098] The embodiments of the present disclosure can also perform functional tests when the chip path is normal. Different tests can be performed for multi-core test chips with different purposes to better understand the working status of the chip. Exemplarily, the basic part of the functional test includes chip read and write tests, and the application part may include the recognition of the chip under different algorithm tests. The embodiments of the present disclosure do not limit the specific content of the functional test, and those skilled in the art can set it according to actual conditions and needs.

[0099] For example, Figure 4 As shown, the disclosed embodiment can test the multi-core chip to be tested for inter-chip computing tasks and inter-chip communication tasks. As mentioned above, each multi-core chip to be tested has Serdes channels in four directions of east, south, west and north. Exemplarily, the Serdes channels in the four directions of chip B1 are respectively connected to chip A1, chip B2, chip C1 and chip B0 to realize the channel connection between chips. The Serdes channels in the four directions of chip B0 are respectively connected to chip A0, chip B1, chip C0 and programmable gate array controller to realize the channel connection between chips, and the other chips are similar. Then an array connection is formed to realize inter-chip communication and testing. Exemplarily, when performing a communication test on chip A2, the data of chip A2 can be read by inputting corresponding instructions in the host computer. Since this communication process passes through chip A0 and chip A1, the above is cross-chip communication between chips, that is, inter-chip communication. When performing a calculation test on chip B1, the corresponding instructions and test data are input in the host computer, and sent to chip B1 via chip B0 to realize the calculation test. Since this communication process passes through chip B0, the above is an inter-chip computing task. It can be seen that the embodiment of the present disclosure solves the problem that inter-chip computing tasks and inter-chip communication tasks in a multi-core chip can be efficiently executed and tested. The number and rate of the Serdes channel can be set and adjusted by changing the chip configuration.

[0100] In a possible implementation manner, the control module 10 may also be used for:

[0101] Writing the model parameters of the neural network into each of the many-core chips to be tested 20 through a write instruction;

[0102] Writing initial data under a preset target scenario to each of the many-core chips 20 to be tested through a write instruction, so that each of the many-core chips 20 to be tested performs a neural network operation under the preset target scenario to obtain an operation result;

[0103] The operation results of each of the many-core chips 20 to be tested are read through the read instruction, and whether the operation functions of each of the many-core chips to be tested are normal is determined according to the operation results.

[0104] Exemplarily, if the operation result is the same as the pre-prepared standard result, it can be determined that the operation function is normal, otherwise it can be determined that the operation function is abnormal. Of course, in order to improve the accuracy of the test, the embodiment of the present disclosure can set the number of comparisons M, where M is a positive integer. When the operation results of M neural network operations are the same as the standard results, it can be determined that the operation function is normal. If there is at least one neural network operation in the M neural network operations whose operation results are different from the standard results, it can be determined that the operation function is abnormal.

[0105] The embodiments of the present disclosure do not limit the specific type of neural network, nor the specific model parameters. Those skilled in the art may set them according to actual conditions and needs. For example, the neural network may include a pulse neural network SNN, a convolutional neural network CNN, etc.

[0106] Illustratively, through the above tests, the disclosed embodiment can test the working status of the multi-core chip 20 under different neural networks, can be operated by the host computer, and the programmable logic controller can write and read with the multi-core chip 20 under test, and finally feedback to the host computer.

[0107] Although the embodiments of the present disclosure have been illustratively introduced using neural network operations as an example to illustrate the operation test of the many-core chip 20 to be tested, the embodiments of the present disclosure are not limited to this. Those skilled in the art can select a corresponding operation method according to actual conditions and needs. The operation method may also include k-means operations, support vector machine operations, other neural network operations, and the like.

[0108] In a possible implementation, Figure 4 As shown, the device may also include:

[0109] K power supply units 30, each power supply unit 30 is used to supply power to each row of the multi-core chips 20 to be tested in the chip array, each power supply unit 30 has multiple power supply modes, each power supply mode has different power supply parameters, and each power supply mode corresponds to the working mode of each row of the multi-core chips 20 to be tested.

[0110] The embodiments of the present disclosure do not limit the implementation method of the power supply unit, the specific power supply parameters of the power supply mode, or the specific working mode, and those skilled in the art may set them according to actual conditions and needs.

[0111] Exemplarily, the power supply unit may include a battery pack, and the battery pack may include a lithium-ion battery, a lithium polymer battery, a direct current source, or other types of power supply methods. For example, the power supply unit may also include an AC / DC converter and a DC / DC converter. The AC / DC converter may be connected to various types of alternating current, that is, the embodiments of the present disclosure may be applied in various places around the world, for example, it may be connected to 220V (single phase) or 380V (three phase) with a frequency of 50Hz; it may be connected to 220V (single phase) or 380V (three phase) with a frequency of 50Hz; it may be connected to 110 / 220V (single phase) or 380 / 460V (three phase) with a frequency of 60Hz; it may be connected to 120 / 240V (single phase), 208 / 240V (three phase); it may be connected to 120 / 240V (single phase) or 208 / 240V (three phase) with a frequency of 60Hz, and so on. The specific implementation of the AC / DC converter and the DC / DC converter is not limited in the embodiments of the present disclosure, and those skilled in the art can configure them according to actual conditions and needs.

[0112] Exemplarily, the working mode may include a static working mode, a general working mode, and working modes under different working intensities (for example, a high-intensity working mode, an ultra-high-intensity working mode, etc., assuming that the working intensity corresponding to the general working mode is 1, then the working intensity corresponding to the static working mode is less than 1, the working intensity corresponding to the high-intensity working mode is, for example, 1 to 1.2, and the working intensity corresponding to the ultra-high-intensity working mode is, for example, 1.2 to 1.5), and the corresponding power supply mode may include a static power supply mode, a general power supply mode, and power supply modes under different working intensities (for example, a high-intensity power supply mode, an ultra-high-intensity power supply mode, etc.), and the corresponding relationship can be, for example, that the static power supply mode, the general power supply mode, the high-intensity power supply mode, and the ultra-high-intensity power supply mode correspond to the static working mode, the general working mode, the high-intensity working mode, and the ultra-high-intensity working mode, respectively.

[0113] Exemplarily, the power supply parameters include, for example, the power supply voltage, the power supply current, etc. Exemplarily, the power supply currents corresponding to the static power supply mode, the general power supply mode, the high-intensity power supply mode, and the ultra-high-intensity power supply mode increase in sequence, and the voltage remains constant.

[0114] In a possible implementation manner, the control module 10 is further configured to determine the power consumption of each of the many-core chips 20 to be tested in various power supply modes and working modes.

[0115] For example, when testing the power consumption of a chip, different power supply voltages can be connected to a current source for power supply, and the power consumption of the multi-core chip 20 to be tested can be measured when it is static, working, and under different working intensities (the power consumption is obtained by multiplying the current displayed by the current source by the power supply voltage). Figure 4 As shown, the three rows of the many-core chips 20 to be tested have three power supplies respectively, so that power supply independence can be achieved.

[0116] It should be noted that although the above Figure 4 An exemplary introduction is given in which a 3×3 chip array including three rows and three columns (the first row includes chip A0, chip A1, chip A2, the second row includes chip B0, chip B1, chip B2, the third row includes chip C0, chip C1, chip C2, the first column includes chip A0, chip B0, chip C0, the second column includes chip A1, chip B1, chip C1, and the third column includes chip A2, chip B2, chip C2) is given. However, the embodiments of the present disclosure are not limited to this and an exemplary introduction is given below.

[0117] See also Figure 5 , Figure 5 A module block diagram of a testing device for a many-core chip array according to an embodiment of the present disclosure is shown.

[0118] For example, Figure 5 As shown, the chip array may include K rows and n columns, the first row includes chip A0, chip A1, ... chip An, the second row includes chip B0, chip B1 ... chip Bn, the third row includes chip C0, chip C1 ... chip Cn ... the Kth row includes chip K0, chip K1 ... chip Kn, the first column includes chip A0, chip B0, chip C0 ... chip K0, the second column includes chip A1, chip B1, chip C1 ... chip K1, the third column includes chip A2, chip B2, chip C2 ... chip K2, ..., the nth column includes chip An, chip Bn, chip Cn ... chip Kn. Of course, the number of corresponding power supply units can be set adaptively.

[0119] In the embodiment of the present disclosure, the number of chips in each row, that is, the size of n, and the number of chips in each column, that is, the size of K, can be set according to actual conditions and needs.

[0120] The testing device for the many-core chip array according to the embodiment of the present disclosure may also include other components and modules, which are not limited to the examples of the present disclosure.

[0121] For example, the test device of the many-core chip array may further include a communication component, which may be configured to facilitate communication between modules within the test device of the many-core chip array or communication with other devices in a wired or wireless manner. The test device of the many-core chip array may be connected to a wired network or a wireless network (such as WiFi, 2G or 3G) based on a communication standard. In an exemplary embodiment, the communication component receives relevant information from the host computer via the UDP protocol. The communication component may also be at least one of a CAN communication unit, a UART communication unit, an SPI communication unit, an IIC communication unit, and the like.

[0122] For example, the testing device of the many-core chip array of the embodiment of the present disclosure may also include a temperature detection component for detecting the temperature of each many-core chip to be tested. The temperature detection component may include various types of temperature sensors, for example, may include at least one of a thermistor, a thermocouple, an IC temperature sensor, a platinum resistance temperature sensor, etc. The thermistor may be, for example, an NTC (Negative Temperature Coefficient) thermistor to improve the sensitivity, accuracy and wide working range of temperature acquisition.

[0123] For example, the testing device for the many-core chip array of the embodiment of the present disclosure may further include an alarm component for alarming when the temperature of the many-core chip to be tested exceeds a threshold value. The alarm component may include an audible and visual alarm.

[0124] For example, the test device of the multi-core chip array of the embodiment of the present disclosure may also include a protection circuit (such as a filtering circuit, a current limiting circuit, an electrostatic protection circuit, a balanced discharge circuit, etc.) for cutting off the power supply of the power supply unit or implementing other protection functions when the current or voltage in the device is abnormal, so as to improve the safety of the test.

[0125] Of course, in order to further improve the safety of the test, the embodiment of the present disclosure may also set a battery management system (BMS) to perform battery management on each power supply unit. Battery management includes but is not limited to collecting parameters of the batteries in the power supply unit (such as temperature, voltage, current, battery state of charge SOC, etc.), controlling the charging and discharging process, and achieving battery balancing.

[0126] For example, a cooling device may also be provided to dissipate heat for each module such as a battery module and a chip array. The heat dissipation technology of the cooling device includes air cooling technology (for example, including a fan, the airflow is generated by the operation of the fan to carry away the heat), liquid cooling technology (for example, including a coolant, immersing the battery pack in the coolant), phase change material technology (for example, including using phase change material as a cooling medium), etc.

[0127] The beneficial effects of the present invention include:

[0128] 1. It can interconnect the multi-core chips to form a multi-chip array, and at the same time interconnect with the programmable logic controller to realize information interaction and realize connectivity testing in all directions;

[0129] 2. It can realize cross-chip communication and communication status test in four directions;

[0130] 3. It can conduct multiple read and write communication tests on different chips in different directions, and test multiple chips at the same time, which can realize direct chip-to-chip interconnection and transit interconnection through programmable logic controller;

[0131] 4. It can test the power consumption of each multi-core chip under different supply voltages and working conditions;

[0132] 5. It can realize the operation test of a row (column) or a specific core in a multi-core chip;

[0133] 6. The internal test results of the multi-core chip under test for different test cases (CASE) can be realized, so as to better evaluate the chip usage;

[0134] 7. The host computer and programmable logic controller can perform CASE tests under different conditions for different application scenarios. That is, the programmable logic controller has strong functional reusability and can write different codes to achieve corresponding functions according to different needs.

[0135] The embodiments of the present disclosure have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or improvements to the technology in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A testing device for a many-core chip array, characterized in that: The device comprises: Control module; A chip array, comprising a plurality of many-core chips to be tested, wherein the plurality of many-core chips to be tested form a chip array of K rows and N columns, wherein the many-core chips to be tested in each row are connected in sequence, and the many-core chips to be tested in each column are connected in sequence, and each of the many-core chips to be tested in the first row, the Kth row, the first column, and the Nth column in the chip array are connected to the control module, and K and N are both positive integers; The control module is used to output a test instruction to each of the many-core chips to be tested, test each of the many-core chips to be tested, and read the returned data from each of the many-core chips to be tested, and determine the test result according to the returned data, wherein the test result includes at least one of whether the read and write functions of each of the many-core chips to be tested are normal, whether the connectivity between each of the many-core chips to be tested is normal, and whether the operation function of each of the many-core chips to be tested is normal. The test instructions include write instructions and read instructions, and the control module is used for: Data is written to each of the many-core chips to be tested through the write instruction, and data of each of the many-core chips to be tested is read through the read instruction to determine the test result.

2. The device according to claim 1, characterized in that The control module is used for: When the data read from any of the many-core chips to be tested is the same as the data written into it, it is determined that the reading and writing of the many-core chip to be tested is normal; otherwise, it is determined that the reading and writing of the many-core chip to be tested is abnormal.

3. The device according to claim 2, characterized in that The control module is also used for: When it is determined that the read and write of the many-core chip to be tested is normal, determining that the connectivity of the corresponding read and write ports of the many-core chip to be tested is normal; When it is determined that the read and write of the many-core chip to be tested is abnormal, the position of the many-core chip to be tested is switched, data is rewritten to the many-core chip to be tested after the switched position, and data is reread from the many-core chip to be tested. When it is determined that the read and write of the many-core chip to be tested is normal for M consecutive times, it is determined that the connectivity of the corresponding read and write ports of the many-core chip to be tested is normal. Otherwise, it is determined that the connectivity of the corresponding read and write ports of the many-core chip to be tested is abnormal, wherein M is a positive integer, and the port from which data is read indicates that the connectivity of the port is normal.

4. The device according to claim 3, characterized in that The method of determining that the read and write of the many-core chip to be tested is normal, and determining that the connectivity of the corresponding read and write ports of the many-core chip to be tested is normal, comprises: If the multi-core chip to be tested is read and written through the first path, and it is determined that the reading and writing of the multi-core chip to be tested is normal, then it is determined that the connectivity of each port on the first path is normal. The first path is composed of the port of the control module, the port of the multi-core chip to be tested, and the corresponding port of the multi-core chip to be tested between the port of the control module and the port of the multi-core chip to be tested.

5. The device according to claim 1, characterized in that The control module is also used for: Write the model parameters of the neural network to each multi-core chip to be tested through write instructions; Writing initial data in a preset target scenario to each of the many-core chips to be tested through a write instruction, so that each of the many-core chips to be tested performs a neural network operation in the preset target scenario to obtain an operation result; The operation results of each of the many-core chips to be tested are read through the read instruction, and whether the operation functions of each of the many-core chips to be tested are normal is determined according to the operation results.

6. The device according to claim 1, characterized in that The device also includes: K power supply units, each power supply unit is used to supply power to each row of the multi-core chips to be tested in the chip array, each power supply unit has multiple power supply modes, each power supply mode has different power supply parameters, and each power supply mode corresponds to the working mode of each row of the multi-core chips to be tested.

7. The device according to claim 6, characterized in that The control module is also used to determine the power consumption of each multi-core chip to be tested in various power supply modes and working modes.

8. The device according to claim 1, characterized in that The control module includes a host computer and a programmable logic controller, the host computer includes a sending module, a receiving module, and a detection module, and the programmable logic controller includes a downlink processing module and an uplink processing module, wherein: The input end of the uplink processing module and the output end of the downlink processing module are both connected to the chip array. The output end of the sending module is connected to the input end of the downlink processing module, the sending module is used to send the test instruction, and the downlink processing module is used to process the test instruction and then send it to each multi-core chip to be tested. The input end of the receiving module is connected to the output end of the uplink processing module, and the uplink processing module is used to process the data received from each multi-core chip to be tested and then send it to the receiving module. The detection module is connected to the receiving module and is used to determine the test result according to the data transmitted by the receiving module.

9. A test system for a many-core chip array, characterized in that: The system comprises the testing device for the many-core chip array according to any one of claims 1 to 8.

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