A hardware constraint-oriented pulse neural network training method, device and chip

Abstract

The application discloses a kind of hardware constraint-oriented pulse neural network training method, device and chip, training method includes: (1) for the ANN network before conversion is modified, according to hardware constraint condition reduces ANN network scale, quantifies weight and adjusts the layer structure that brain-computer computing chip does not support, so that ANN network adapts hardware constraint condition, obtains quantized ANN;(2) according to hardware constraint condition, adjust the neuron form of SNN, train and convert quantized ANN into IF neuron quantized SNN;(3) quantized ANN is converted to obtain the quantized SNN using signed IF neuron, and the quantized SNN is fine-tuned;(4) with quantized ANN and the quantized SNN using signed IF neuron in step (3) as standard, the quantized SNN using IF neuron obtained in step (2) is fine-tuned layer by layer.The application can solve the problem that the performance of SNN converted from ANN in the prior art is too much reduced to meet the hardware constraint condition.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of brain-like computing, and particularly relates to a hardware constraint-oriented spiking neural network training method and device and chip. BACKGROUND

[0002] Spiking Neural Network (SNN), also known as the third generation of neural network, has a network structure and operation mode that most closely mimics biological brain neurons from the perspective of biology and brain science, and uses time-discrete pulse signals to transmit information. When the neuron potential reaches the firing threshold, it will fire a pulse and transmit a signal, while resetting the potential. The spiking neural network is often sparsely connected, and since the neuron only fires a pulse when it exceeds the firing threshold, the spiking neural network has the characteristics of extremely low energy consumption and high operation efficiency. Based on this advantage and the approximation of its structure to biological neurons and the fitting of brain operation logic, the spiking neural network will certainly have great potential in the future.

[0003] The current training of the spiking neural network is mainly through direct training, which is converted into two ways from the trained artificial neural network.

[0004] The direct training method uses a surrogate gradient method, which uses a continuous function to replace the discrete pulse when the model is backpropagated. It also applies the method of Back Propagation Through Time (BPTT) originally applied in Artificial Neural Network (ANN) to directly optimize SNN. However, the direct training method cannot avoid the phenomenon of gradient explosion / gradient disappearance in the training process, which in turn affects the final result of the direct training method, especially in complex network structures or application scenarios.

[0005] The conversion method, i.e. ANN to SNN algorithm, first uses the conventional method of training ANN to train the ANN to obtain the trained weights. This training process is more stable and mature than the direct training method, and there are many excellent algorithms and hardware optimization methods that can be learned. After training an ANN model with excellent performance, the activation layer in the ANN model is directly replaced by the pulse firing layer in the spiking neural network, and the activation value is approximated as the probability of single-time-step firing pulse. This conversion process is stable and has less loss of accuracy. The main source of loss of accuracy is the loss of accuracy of converting the floating-point weights and activation values of ANN to the quantized weights and activation values of SNN with limited accuracy, and the cumulative error caused by the cumulative error in the conversion process. Although the performance of SNN is still difficult to surpass the ANN before conversion by optimizing the neuron form and the conversion process, the performance of SNN is still difficult to surpass the ANN before conversion by optimizing the neuron form and the conversion process.

[0006] In addition, the spiking neural network is not perfectly matched with the current general GPU, NPU, etc., and needs special support of computing chips to exert its own advantages and characteristics. The brain-like computing chips designed for spiking neural networks are in the initial stage of development worldwide, and different enterprises / colleges have developed brain-like computing chips to support spiking neural networks. The current brain-like computing chips often have small capacity, many restrictions on network forms, and limited performance in complex application scenarios. Due to the lagging nature of hardware development, brain-like computing chips cannot quickly support advanced theoretical research results in the academic field, such as some chips not supporting negative pulses for neurons. When deploying a spiking neural network on such chips, problems such as compilation process problems and actual deployable network size lower than the theoretical support size may occur. Similarly, various problems in the compilation process may impose additional restrictions on the number of channels and other issues in the network, posing additional challenges for spiking neural networks to function in various application scenarios. SUMMARY

[0007] The present application provides a hardware constraint-oriented spiking neural network training method, which can solve the problem of excessive performance degradation of ANN conversion to meet the hardware constraint condition in the prior art.

[0008] A hardware constraint-oriented spiking neural network training method, comprising the following steps:

[0009] (1) modifying the ANN network before conversion, reducing the ANN network size, quantizing the weight, and adjusting the layer structure not supported by the brain-like computing chip according to the hardware constraint condition, so that the ANN network adapts to the hardware constraint condition, and obtaining a quantized ANN;

[0010] (2) adjusting the neuron form of the SNN according to the hardware constraint condition, training and converting the quantized ANN into an IF neuron quantized SNN with precision and weight bit number meeting the hardware constraint condition;

[0011] (3) converting the quantized ANN to obtain a quantized SNN using signed IF neurons, and fine-tuning the quantized SNN; wherein the neuron form of the signed IF neuron is not restricted by the hardware condition;

[0012] (4) using the quantized ANN and the quantized SNN using signed IF neurons in step (3) as a standard, fine-tuning the quantized SNN using IF neurons obtained in step (2) layer by layer.

[0013] In the present application, the hardware constraint conditions include: limiting the total number of neurons and the total number of connections of the network; limiting the upper limit of the number of channels of a single layer network; limiting the form of neurons adopted; limiting the number of quantization bits and allowing only integer operations; and not implementing exponential operation and division.

[0014] In step (2), the number of neurons in the IF neuron quantized SNN meeting the hardware constraint conditions is constrained to within 200,000, the number of connections is constrained to within 2,000,000, and the number of channels of each layer is limited to within 128.

[0015] In step (2), the form of neurons is the IF neuron model, which can only emit a pulse when the neuron potential accumulation exceeds the threshold value and subtract the threshold value from the potential, and does not support firing negative pulses.

[0016] In step (3), the form of neurons is the signed IF neuron model, which judges that the previously emitted pulse is an over-fired pulse that should not have been fired when the neuron internal potential accumulation is negative at a certain time step after the pulse has been fired, and at this time, a positive threshold value is added to the potential to restore the potential and emit a negative pulse to offset the previous over-fired pulse, thereby eliminating the error caused by the previous over-fired pulse.

[0017] In step (4), the specific process of layer-by-layer fine-tuning is as follows:

[0018] For the quantized ANN, the pulse firing frequency of the IF neuron quantized SNN output meeting the hardware constraint conditions and the ANN activation value atlas are taken, and the Euclidean distance between the two is gradually reduced layer by layer, so that the pulse frequency of the IF neuron quantized SNN output is close to the activation value of the ANN before conversion;

[0019] For the quantized SNN using signed IF neurons and the IF neuron quantized SNN meeting the hardware constraint conditions, the same layer-by-layer adjustment method is adopted, and for the two SNNs, the total number of pulses fired at each time step in the layer is taken, the loss is calculated according to their Euclidean distance, and the weight of the IF neuron quantized SNN is fine-tuned step by step to reduce the difference between the two SNNs in the gradual firing of pulses;

[0020] Comprehensive above two forms, take certain weight ratio to meet the hardware constraint condition IF neuron quantization SNN from the second layer to the last layer in the training set of corresponding data set is adjusted layer by layer;Each layer input takes the current hardware constraint IF neuron quantization SNN layer input, to quantize ANN, signed IF neuron quantization SNN and IF neuron quantization SNN three respective outputs and the pulse accumulation of the two quantization SNNs in the layer at each time step and the final remaining membrane potential are calculated, the distance between the hardware constraint IF neuron quantization SNN layer and the remaining two is reduced, and the corresponding layer weight of the hardware constraint IF neuron quantization SNN is updated, and the updated weight is applied to the fine tuning of the subsequent layer.

[0021] The application further provides a hardware constraint-oriented spiking neural network training device, comprising a memory and one or more processors, wherein the memory stores executable code, and the one or more processors execute the executable code to implement the above-mentioned spiking neural network training method.

[0022] The application further provides a brain-like chip, which is deployed with a spiking neural network SNN, wherein the spiking neural network SNN is trained by using the above-mentioned spiking neural network training method.

[0023] Compared with the prior art, the application has the following beneficial effects:

[0024] The application trains a hardware constraint IF neuron quantization SNN network with relatively good performance, which can be deployed on a specified brain-like computing chip, by training a hardware constraint quantization ANN and through conversion and layer-by-layer fine tuning. BRIEF DESCRIPTION OF DRAWINGS

[0025] Figure 1 It is a hardware constraint-oriented spiking neural network training method.

[0026] Figure 2 It is an activation value function diagram in a quantization ANN and the corresponding mapping relationship of the IF neuron pulse emission frequency in an IF neuron quantization SNN.

[0027] Figure 3 It is the mapping relationship between the full-precision weight value before and after quantization by the aPot quantization method and the quantized weight.

[0028] Figure 4 It is the pseudo code of the fine tuning method in the original FastSNN.

[0029] Figure 5 The pseudo code of the hardware constraint pulse neural network fine-tuning method in the application.

[0030] Figure 6 The number of neurons and connections of each layer and the sum of the number of neurons and connections of the entire network of the AlexNet network structure adopted after adjusting the network structure without hardware constraints.

[0031] Figure 7 The number of neurons and connections of each layer and the sum of the number of neurons and connections of the entire network of the AlexNetSlim network structure adopted after adjusting the network structure with hardware constraints. DETAILED DESCRIPTION

[0032] The application will be further described in detail below in combination with the drawings and examples, and it should be pointed out that the following examples are intended to facilitate the understanding of the application and do not limit the application in any way.

[0033] As shown in Figure 1 , the hardware constraint-oriented pulse neural network training method in the embodiment mainly includes the following steps:

[0034] (1) By modifying the ANN network, replacing the layers not supported by hardware with the layers supported by hardware, simplifying the form of setting the quantized weight, and adjusting the network size to make the number of neurons and connections of the converted IF neuron quantized SNN network meet the conditions of hardware constraints;

[0035] The modified quantized ANN is trained to obtain a quantized ANN model with excellent performance.

[0036] (2) The quantized ANN is converted to obtain a hardware-constrained IF neuron quantized SNN. Verify its feasibility of being deployed to a specified brain-like computing chip.

[0037] (3) The quantized ANN is converted to obtain a signed IF neuron quantized SNN, and the weights of the SNN are fine-tuned layer by layer by means of the quantized ANN before conversion to optimize its performance.

[0038] (4) The signed IF neuron quantized SNN and the quantized ANN are used to fine-tune the IF neuron quantized SNN layer by layer, and an IF neuron quantized SNN model with performance not much lower than the quantized ANN and which can be deployed to hardware is obtained.

[0039] (5) The performance of the IF neuron quantized SNN obtained in the previous step is verified using a test set.

[0040] In step (1), the hardware constraints include weight bit width and arithmetic operation bit width, the former can be selected as 2, 4, 6, 8, 16 bits, and the latter is fixed as 16 bits. All numerical values and arithmetic operations on the hardware are based on integers, and floating-point numbers are not supported. Therefore, a quantization method is used to modify the network originally with floating-point precision. The chip requires that the neuron cannot be too complex, and it is difficult to implement division and exponential operation. The chip itself supports the upper limit size of the network to be 2 million neurons and 200 million connections, and at the same time, the upper limit of the number of channels of a single-layer neural network is preferably controlled within 128, otherwise it will greatly affect the network running rate. Due to the current problems in hardware compilation and other aspects, the performance of the chip cannot be fully utilized. It can be regarded as ensuring that the operation of the spiking neural network can be realized in real time and stably, and the current size of the spiking neural network is controlled within 200,000 neurons and 2 million connections. The specific method of implementing the hardware constraint condition is:

[0041] Through actual operation, the connection number and neuron size of the pruned model are cut to the size that can be actually deployed on the hardware. In the adjustment process, the overall size of the network needs to be modified to meet the size in the hardware constraint. Taking the convolutional layer as an example, assuming that the channel number of the layer is n, and the size of the image input feature in the layer is a*a, then the number of neurons of the image in the layer is n*a 2 . Since it is a convolutional layer, when the convolution kernel size is 3*3, each neuron is connected with 9 neurons in the upper layer, and the connection number of the layer is 9*n*a 2 . For a fully connected layer, the size of the kth layer neuron is the channel number n k of the kth layer, and the connection number is the total number of connections between the neurons of the layer and the neurons of the previous layer, i.e., the k-1th layer, which is n k *n k-1 . The network size is proportional to the size of the input image, and the size of each layer is proportional to the size of the input feature in the layer. By adjusting the network structure and the size of the image, an optimal performance solution is obtained between pruning the network channel number and compressing the original input image. An optimal performance solution is obtained between when the image feature is compressed in the network and the control of the network channel number.

[0042] For each layer of the network, the channel number is limited to 128 to meet the hardware requirement for the channel number.

[0043] The convolution weight is quantized by aPot quantization method, and the Relu weight is quantized by uniform quantization method to a specified number of bits. The network after quantization can be deployed on the chip to perform integer operation instead of floating-point operation.

[0044] In step (2), the hardware is specifically Darwin No. 3 chip, and the neuron form is fixed as IF neuron model, which can only emit a pulse when the neuron potential accumulation exceeds the threshold value and subtract the threshold value from the potential, and does not support firing of negative pulses. In the chip, the corresponding time step T = 2 n -1 step.

[0045] In step (3), the neuron structure is a signed IF neuron model. For the signed IF neuron, the model determines that the previously emitted pulse is an over-fired pulse that should not have been fired when the neuron internal potential accumulation is negative at a certain time step after the pulse has been fired, at which time a positive threshold recovery potential is added to the potential and a negative pulse is emitted to offset the previous over-fired pulse, thereby eliminating the error caused by the previous over-fired pulse. The hardware-supported IF neuron cannot have such a mechanism, and thus may not be able to compensate for the erroneously fired pulse, resulting in accumulation of errors.

[0046] In step (4), for the quantized ANN, the pulse firing frequency of the hardware-constrained SNN layer output and the ANN activation value atlas are taken, and the Euclidean distance between the two is gradually reduced layer by layer, so that the SNN output pulse frequency is as close as possible to the activation value of the ANN before conversion; for the quantized SNN using the signed IF neuron model and the hardware-constrained IF neuron quantized SNN, a step-by-step adjustment method is adopted, and for the two SNNs, the total number of cumulative pulses fired at each time step inside the layer and the remaining amount of membrane potential at the last step are compared and referenced, and the hardware-constrained IF neuron quantized SNN weight is fine-tuned to reduce the difference between the two in the cumulative pulse firing step by step. Since the SNN relies on the accumulation of pulses to gradually approach the output of the ANN, and there are negative pulses in the signed IF neuron, the hardware-constrained IF neuron quantized SNN required in the present application cannot use negative pulses, which may cause too large a difference in single-step pulse firing. Therefore, the cumulative firing of pulses at each time step is adopted.

[0047] For quantized ANNs and quantized SNNs using signed IF neuron models, a combination of these two fine-tuning methods is employed. A certain weight ratio is used to adjust the hardware-constrained IF neuron quantized SNN layer by layer from layer 2 to the last classification layer on the corresponding training set. The input to each layer is taken from the current hardware-constrained IF neuron quantized SNN layer. The calculation is performed using the outputs of the three layers, as well as the impulse firing patterns at each time step within that layer of the signed IF neuron quantized SNN (not constrained by hardware) and the hardware-constrained IF neuron quantized SNN. This reduces the distance between the hardware-constrained IF neuron quantized SNN and the other two, and updates the corresponding layer weights of the hardware-constrained IF neuron quantized SNN. These updated weights are then applied to the fine-tuning of subsequent layers until the last layer is reached. After layer-by-layer fine-tuning, the performance of the hardware-constrained IF neuron quantized SNN after fine-tuning is tested on the test set.

[0048] In this embodiment of the invention, the aPot quantization method is used to quantize the layers storing weights, such as convolutional layers and fully connected layers, in the ANN, while uniform quantization is used to quantize the ReLU layers. The quantized ANN is then directly converted to obtain an SNN with the same quantization form. For any neuron in the activation layer, the uniform quantization formula is:

[0049]

[0050] Where s is the pruning threshold, representing the weights to be pruned to the range [-s, s], and b is the quantization bit depth, corresponding to the possible range of the emitted pulse in the SNN being [0, 2]. b Integers within the range of -1]. X is the original unquantized full-precision activation value. The Round function will... The function performs rounding and returns an integer. The Clip function then constrains this integer to [2]. b The integer returned is within the range of [-1]. After rounding and constraint, it is scaled back to the range of [0,1].

[0051] The ANN model used, the training conversion method, and the method of using only quantized ANN to fine-tune the signed IF neuron are all from the literature "Hu, Yangfan, et al. Fast-snn: Fast spiking neural network by converting quantized ann." IEEE Transactions on Pattern Analysis and Machine Intelligence (2023). In the network, the method of using direct encoding and IF neurons and soft reset is used, the first layer directly inputs direct current, the neuron will not emit negative pulses, and the neuron potential will not flow with time. The neuron will receive the pulse of the connected neuron in the last layer and accumulate the membrane potential, and when the membrane potential exceeds the firing threshold, it will emit a pulse, and through soft reset, the membrane potential is reduced by an amount of firing threshold.

[0052] Unlike the fine-tuning method in this literature, the fine-tuning method used in this application includes using quantized SNN with signed IF neurons not supported by hardware as the learning object, and further refining the learning object by layer to the cumulative value map of the step-by-step firing of the pulse neural network, making full use of the characteristics of the pulse neural network in the time dimension. At the same time, by fine-tuning SNN, SNN is more practical and feasible.

[0053] Figure 2 In the following, it is assumed that the quantization bit number is b bit. The conversion formula of the pulse neural network and the quantization bit number is:

[0054] T = 2 b -1

[0055] Where T is the time step in the pulse neural network, and b is the quantization bit number of the ANN before conversion and the SNN after conversion. In Figure 2 In the following, b = 2 is taken to show the specific situation after quantization.

[0056] In the ANN, the aPot quantization method is used to quantize the convolution layer, and the uniform quantization method is used to quantize the Relu function.

[0057] Figure 3The comparison of the full-precision values before and after and the quantized values after is quantized by the aPot quantization method. The aPot quantization method is from the literature "Li, Yuhang, Xin Dong, and Wei Wang. Additive Powers-of-Two Quantization: An Efficient Non-uniform Discretization for Neural Networks. International Conference on Learning Representations. 2019.", which is a non-uniform quantization method. By limiting all quantized values to several powers of two, aPoT quantization is beneficial to improve computational efficiency and well match the weight distribution. For example, the quantized values for bit = 3 are [0, 0.0625, 0.125, 0.1875, 0.25, 0.375, 0.5, 0.625], and after scaling to [0, 1] they are [0, 0.1, 0.2, 0.30, 0.4, 0.6, 0.8, 1.0]. For a floating-point number that needs to be quantized, the quantization is performed to make it the nearest quantized value.

[0058] Figure 4 The method in the method can be used for various forms of neurons, but the common IF neuron supported by hardware cannot be well fitted to the ANN output due to the lack of negative pulse compensation error correction mechanism, and thus even if the quantized ANN is used for fine-tuning, it will inevitably cause errors, and the performance loss after fine-tuning is still large. Since fine-tuning itself is equivalent to adjusting the generated quantized SNN weight, it is similar to retraining the quantized SNN, and cannot guarantee the optimality of the fine-tuning result. Therefore, the present application uses the quantized SNN of the signed IF neuron which is not affected by the hardware constraint to further fine-tune the quantized SNN of the IF neuron which is affected by the hardware constraint, fully utilizes the characteristics of the spiking neural network in the time dimension to help improve the performance of the IF neuron SNN which meets the hardware constraint condition, so that the pulse firing condition of the latter is closer to the actual performance of the former, and the performance of the brain-like operation chip in dealing with real application scenarios is truly improved.

[0059] Figure 5 is the fine-tuning process of the hardware-constrained IF neuron quantized SNN in the present application, and in the present application, the pulse neural network using the quantized signed IF neuron which cannot be deployed to hardware is used to learn and fine-tune the pulse neural network using the quantized IF neuron which can be deployed to hardware layer by layer and time step by time step, and then the timing characteristics of the pulse neural network are used to reduce the performance loss caused by the modification of the pulse neural network for deployment to hardware.

[0060] Figure 6For the AlexNet network model that has not been adjusted in size, the image input size is 32*32 when CIFAR10 is used as the data set. The Dropout layer has been removed and replaced with a convolution layer that sets the step size for convolution operation to compress image features.

[0061] Figure 7 For the AlexNetSlim network model that has been adjusted in size, the model adjusts the number of channels of each layer on the basis of removing the Dropout layer and replacing the pooling layer with a convolution layer that sets the step size for convolution operation to compress image features. Since the image size in the CIFAR10 data set is already 32*32, there is no space for further compression. The AlexNetSlim network mainly adjusts the number of channels of each layer, especially the fully connected layer, to reduce the total number of neurons and the number of connections after the network is converted into an SNN. And the number of channels is compressed to below 128 to help the compiler pass. Without affecting the performance, the convolution layer that compresses the image features can be moved forward. Further, the number of neurons and the number of connections of the subsequent network layers are reduced.

[0062] For application scenarios such as target recognition, the VOC0712 data set often uses an image training size of 640*640 and a verification size of 416*416. Target recognition itself has more requirements for network performance, and excessively compressing the image is easy to lose important features, which greatly limits the space for adjusting the network itself. Therefore, it is more difficult to use a brain-like computing chip to deal with target recognition than image classification.

[0063] Based on the same inventive concept, the embodiment of the present application also provides a hardware constraint-oriented pulse neural network training device, which comprises a memory and one or more processors, the memory stores executable code, and the one or more processors execute the executable code to implement the pulse neural network training method.

[0064] Based on the same inventive concept, the embodiment of the present application also provides a brain-like chip, which is deployed with a pulse neural network SNN, and the pulse neural network SNN is trained by using the pulse neural network training method.

[0065] The above embodiments have described the technical solutions and beneficial effects of the present application in detail. It should be understood that the above description is only a specific embodiment of the present application and is not used to limit the present application. Any modification, supplement and equivalent replacement made within the principle range of the present application should be included in the protection range of the present application.

Claims

1. A hardware constraint oriented pulse neural network training method, characterized in that, The method comprises the following steps: (1) modifying the ANN network before conversion, reducing the ANN network size according to the hardware constraint condition, quantizing the weight and adjusting the layer structure not supported by the brain-like computing chip, so that the ANN network is adapted to the hardware constraint condition, and a quantized ANN is obtained; (2) adjusting the neuron form of the SNN according to the hardware constraint condition, training the quantized ANN and converting the IF neuron quantized SNN meeting the hardware constraint condition; (3) converting the quantized ANN to obtain a quantized SNN using signed IF neurons, and fine-tuning the quantized SNN; wherein the neuron form of the signed IF neuron is not constrained by the hardware condition; (4) using the quantized ANN and the quantized SNN using signed IF neurons in step (3) as a standard, fine-tuning the quantized SNN using IF neurons obtained in step (2) layer by layer.

2. The hardware constraint oriented pulse neural network training method according to claim 1, characterized in that, The hardware constraint condition comprises: limiting the total number of neurons and the total number of connections of the network; limiting the upper limit of the channel number of a single layer network; limiting the neuron form; limiting the quantization bit number and allowing only integer operations; and not supporting exponential operation and division.

3. The hardware constraint oriented pulse neural network training method according to claim 1, wherein, In step (2), the IF neuron quantized SNN meeting the hardware constraint condition is constrained to within 200,000 in scale and within 2,000,000 in connection number, and the channel number of each layer is limited to within 128.

4. The hardware constraint oriented pulse neural network training method according to claim 1, characterized in that, In step (2), the neuron form is an IF neuron model, which can only emit a pulse when the neuron potential accumulation exceeds the threshold value and subtract the threshold value from the potential, and does not support negative pulse emission.

5. The hardware constraint oriented pulse neural network training method according to claim 1, wherein, In step (3), the neuron form is a signed IF neuron model, which judges the previously emitted pulse as an over-emitted pulse that should not have been emitted when the neuron internal potential accumulation is negative at a certain time step after the pulse has been emitted, and at this time, a positive threshold value is added to the potential to restore the potential and emit a negative pulse to offset the previous over-emitted pulse, so as to eliminate the error caused by the previous over-emitted pulse.

6. The hardware constraint oriented pulse neural network training method according to claim 1, wherein, In step (4), the specific process of layer-by-layer fine-tuning is as follows: For the quantized ANN, take the pulse emission frequency of the IF neuron quantized SNN output meeting the hardware constraint condition and the ANN activation value atlas, and gradually reduce the Euclidean distance between the two, so that the pulse emission frequency of the SNN using the IF neuron quantization is close to the activation value of the ANN before conversion; For the quantized SNN using signed IF neurons and the IF neuron quantized SNN meeting the hardware constraint condition, the same layer-by-layer adjustment method is adopted, and for the two SNNs, the total number of cumulative pulse emissions at each time step in the layer is taken, the loss is calculated according to the Euclidean distance, the weight of the SNN using the IF neuron quantization is fine-tuned step by step, and the difference between the two gradually emitted pulses is reduced. Comprehensive above two forms, take certain weight ratio to the IF neuron quantization SNN which satisfies the hardware constraint condition from the second layer to the last layer to carry out the layer-by-layer adjustment to the training set of the corresponding data set;The input of each layer takes the input of the current IF neuron quantization SNN layer that satisfies the hardware constraint, to calculate the output of the quantization ANN, the output of the signed IF neuron quantization SNN and the output of the IF neuron quantization SNN, and the pulse cumulative emission situation and the final remaining membrane potential of each time step in the layer of the two quantization SNN, reduce the distance between the hardware constraint IF neuron quantization SNN layer and the remaining two, and update the corresponding layer weight of the hardware constraint IF neuron quantization SNN, to update the post-weight and apply it to the fine-tuning of the subsequent layer.

7. A hardware constraint oriented pulse neural network training apparatus, characterized by, The pulse neural network training method of any one of claims 1-6 is implemented by using one or more processors and a memory having stored executable code.

8. A brain-like chip deployed with a spiking neural network (SNN), characterized in that, The pulse neural network SNN is trained by using the pulse neural network training method of any one of claims 1-6.

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