Solar cells, modules and systems

Abstract

The present application discloses a solar cell, a component and a system. The solar cell includes: a silicon substrate, a tunneling dielectric layer and a doped polysilicon layer are stacked on a first surface of the silicon substrate背离 the silicon substrate bottom layer; a homojunction, the homojunction is located on a side of the silicon substrate with the tunneling dielectric layer, and the homojunction diffuses from the surface of the silicon substrate into the silicon substrate; the doping concentration of the homojunction is 1×10<supgt;15< / supgt; cm<supgt;‑3< / supgt> to 5×10<supgt;18< / supgt> cm<supgt;‑3< / supgt>, and the junction depth of the homojunction is greater than or equal to 500 nm and less than or equal to the thickness of the silicon substrate. The solar cell of the present application optimizes the doping concentration and the junction depth of the homojunction, which is beneficial to reducing the influence of Auger recombination and increasing the extraction and separation depth of carriers in the silicon substrate, while enhancing the concentration difference between the doped polysilicon layer and the silicon substrate, thereby enhancing the built-in electric field at the heterojunction silicon substrate interface, and further improving the conversion efficiency of the solar cell. It should be noted that there is an incorrect expression "硅基底的第一表面背离所述硅基底层叠设置有隧穿介电层和掺杂多晶硅层" in the original text. I translated it according to the literal meaning, but it may need to be further verified in the context to ensure the accuracy of the technical content.

Description

Technical Field

[0001] The present invention generally relates to the field of photovoltaic technology, and more particularly to a solar cell, a component and a system. Background Art

[0002] TOPCon (tunneling oxide passivated contact) cells usually prepare an ultra-thin tunneling oxide layer on the back of the silicon wafer, and then deposit a doped polysilicon layer on the surface of the tunneling oxide layer to form a passivated contact structure; this structure provides good surface chemical passivation and field passivation for the back of the silicon wafer. The tunneling oxide layer mainly plays the role of passivating the dangling bonds on the surface of the crystalline silicon, reducing the surface defect state density, and allowing carrier transmission. The deposited doped polysilicon layer forms a strong built-in electric field, which promotes the asymmetric selection and transmission of carriers and significantly reduces the reverse saturation current density. At the same time, the highly doped degenerate or nearly degenerate polysilicon layer has good lateral conductivity, which effectively reduces the square resistance and contact resistance. In addition, the introduction of the tunneling oxygen / doped polysilicon layer isolates the metal from the silicon substrate, which can significantly reduce the contact recombination loss. These characteristics together determine that the TOPCon cell has a higher open circuit voltage (V OC ) and fill factor (FF), which ultimately manifests in higher photoelectric conversion efficiency. This structural advantage can be more fully reflected in TOPCon-BC (back contact) cells, while integrating the advantages of high short-circuit current density of BC cells, achieving higher photoelectric conversion efficiency.

[0003] However, when the TOPCon cell in the related art prepares the heavily doped polysilicon layer at high temperature, the thickness of the tunneling oxide layer is too thin to effectively shield the impurity atoms. The impurities diffuse into the silicon substrate material through the tunneling oxide layer, forming a homojunction with high doping concentration and shallow electric field influence depth. The doping concentration on the surface of the silicon substrate is too high, causing serious Auger recombination losses. In addition, the high doping concentration on the surface of the silicon substrate will reduce the difference in doping concentration on both sides of the heterojunction between the silicon substrate and the doped polysilicon, reduce the intensity and depth of the induced electric field at the heterojunction on the surface of the silicon substrate, and narrow the depth of action of the induced electric field at the heterojunction of the silicon substrate, resulting in a weakened heterojunction passivation effect and an impact on the carrier extraction ability and extraction depth of the silicon substrate, thereby affecting V OC and FF enhancement. Summary of the invention

[0004] In view of the above-mentioned defects or deficiencies in the prior art, it is desired to provide a solar cell, a component and a system that can effectively solve the problem of serious Auger recombination losses caused by the high doping concentration on the surface of the silicon substrate, improve the concentration difference between the doped polysilicon layer and the silicon substrate, enhance the heterojunction induced electric field on the surface of the silicon substrate, and thereby improve the efficiency of the solar cell.

[0005] In a first aspect, the present invention provides a solar cell, comprising:

[0006] A silicon substrate, wherein a tunnel dielectric layer and a doped polysilicon layer are stacked on a first surface of the silicon substrate away from the silicon substrate;

[0007] A homojunction, wherein the homojunction is located on the side of the silicon substrate having the tunnel dielectric layer, and the homojunction diffuses from the surface of the silicon substrate to the inside of the silicon substrate;

[0008] The surface doping concentration of the homojunction is 1×10 15 cm -3 ~5×10 18 cm -3 The junction depth of the homojunction is greater than or equal to 500nm and less than or equal to the thickness of the silicon substrate.

[0009] As an alternative, the surface doping concentration of the homojunction is 1×10 16 cm -3 ~3×10 18 cm -3 .

[0010] As an optional solution, the junction depth of the homojunction is 1000nm~2000nm.

[0011] As an optional solution, the doping concentration of the doped polysilicon layer is 1×10 19 cm -3 ~1×10 21 cm -3 .

[0012] As an optional solution, based on the projection on the surface of the silicon substrate, the projection of the doped polysilicon layer is located within the projection range of the homojunction.

[0013] As an alternative, the tunnel dielectric layer is selected from at least one of oxide, nitride, oxynitride, carbide, oxycarbide or halide.

[0014] As an optional solution, it also includes: a passivation anti-reflection layer located on the surface of the doped polysilicon layer;

[0015] and a metal electrode, wherein the metal electrode passes through the passivation anti-reflection layer and contacts the doped polysilicon layer.

[0016] As an optional solution, based on the projection on the surface of the silicon substrate, the projection of the metal electrode is located within the projection range of the homojunction.

[0017] As an optional solution, the silicon substrate further includes a second surface opposite to the first surface, and the second surface includes a selective emitter.

[0018] As an optional solution, the first surface of the silicon substrate includes a plurality of first regions and a plurality of second regions that are spaced apart from each other;

[0019] The homojunction is located within the surface of the first region.

[0020] As an optional solution, the second region includes a P-type doping layer, and the doping type of the homojunction is different from the doping type of the P-type doping layer.

[0021] In a second aspect, the present invention provides a method for preparing a solar cell, which specifically comprises the following steps:

[0022] Forming a doping source layer on the first surface of the silicon substrate, the doping source layer comprising a first pre-doping layer and PSG formed on the first surface of the silicon substrate, or the doping source layer comprising a second pre-doping layer and BSG formed on the first surface of the silicon substrate;

[0023] removing PSG or BSG from the first surface of the silicon substrate;

[0024] Diffusion treatment is performed by means of finite source diffusion;

[0025] forming a tunneling dielectric layer on the first surface of the silicon substrate;

[0026] preparing a doped polysilicon layer on the tunnel dielectric layer;

[0027] A homojunction is formed in the first surface of the silicon substrate, and the surface doping concentration of the homojunction is 1×10 15 cm -3 ~5×10 18 cm -3 The junction depth of the homojunction is greater than or equal to 500nm and less than or equal to the thickness of the silicon substrate.

[0028] In a third aspect, the present invention provides a method for preparing a solar cell, comprising the following steps:

[0029] Preparing a dielectric layer on a first surface of a silicon substrate;

[0030] Preparing a first doped polysilicon layer on the dielectric layer to form an inner extension layer in the first surface of the silicon substrate;

[0031] removing the first doped polysilicon layer;

[0032] Diffusion of the inner expansion layer into the silicon substrate by limited source diffusion;

[0033] forming a tunnel dielectric layer and a second doped polysilicon layer on the first surface of the silicon substrate;

[0034] A homojunction is formed in the first surface of the silicon substrate, and the surface doping concentration of the homojunction is 1×10 15 cm -3 ~5×10 18 cm -3 The junction depth of the homojunction is greater than or equal to 500nm and less than or equal to the thickness of the silicon substrate.

[0035] In a fourth aspect, the present invention provides a solar cell assembly, comprising a solar cell according to the first aspect.

[0036] In a fifth aspect, the present invention provides a solar cell system, comprising a solar cell assembly according to the fourth aspect.

[0037] The solar cell of the present invention is provided with a low-doped homojunction with a deep electric field depth on the surface of the silicon substrate near the tunnel dielectric layer and the doped polycrystalline silicon, that is, the doping concentration on the surface of the homojunction is 1×10 15 cm -3 ~5×10 18 cm -3 , the homojunction electric field depth is greater than or equal to 500nm and less than or equal to the thickness of the silicon substrate. On the one hand, the homojunction doping concentration and electric field depth of the present application are conducive to improving the carrier separation and extraction capabilities inside the silicon substrate while reducing the influence of Auger recombination; on the other hand, the doping concentration of the homojunction of the present application can enhance the doping concentration difference between the doped polysilicon layer and the silicon substrate, thereby improving the heterojunction induced electric field strength and action depth on the surface of the heterojunction silicon substrate, which is of great help to the carrier separation near the interface, and effectively improves the V OC and FF, thereby improving the photoelectric conversion efficiency of solar cells. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Other features, objects and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings:

[0039] Figure 1 A schematic diagram of a homojunction stacked tunneling dielectric layer and a doped polysilicon layer in a solar cell according to an embodiment of the present application;

[0040] Figure 2 is a schematic structural diagram of a solar cell according to Example 1;

[0041] Figure 3 A schematic diagram of the structure of a solar cell of Comparative Example 1;

[0042] Figure 4 It is a doping concentration curve diagram of the solar cell of the present invention and the traditional TOPCon cell;

[0043] Figure 5 Schematic diagram of the structure of the solar cell of Example 2.

[0044] In the figure,

[0045] 10. Silicon substrate;

[0046] 20. Homojunction;

[0047] 111, a first passivation anti-reflection layer, 112, a second passivation anti-reflection layer, 113, an aluminum oxide layer, 114, a silicon nitride layer;

[0048] 40. a first metal electrode, 50. a second metal electrode;

[0049] 60. Selective emitter, 70. Light extension region, 80. Tunneling dielectric layer, 90. Doped polysilicon layer. DETAILED DESCRIPTION

[0050] The present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the relevant invention, rather than to limit the invention. It is also necessary to explain that, for ease of description, only the parts related to the invention are shown in the accompanying drawings.

[0051] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0052] TOPCon cells belong to heterojunction technology, which forms a heterojunction structure by doping polysilicon layer / tunneling silicon oxide / silicon substrate. However, due to the high-temperature preparation of poly-Si technology, there is a process in which poly-Si doped atoms diffuse into the silicon substrate. Impurities that diffuse into the silicon substrate through the tunneling silicon oxide form a highly doped inner expansion area on the surface of the silicon substrate. TOPCon (tunneling oxide passivation contact) cells usually prepare an ultra-thin tunneling oxide layer on the back of the silicon wafer, and then deposit a doped polysilicon layer on the surface of the tunneling oxide layer to form a passivation contact structure; this structure provides good surface chemical passivation and field passivation for the back of the silicon wafer. The tunneling oxide layer mainly plays a role in passivating the dangling bonds on the surface of the crystalline silicon, reducing the surface defect state density, and allowing carrier transmission. The deposition of the doped polysilicon layer forms a strong built-in electric field, which promotes the asymmetric selection and transmission of carriers and significantly reduces the reverse saturation current density. At the same time, the highly doped degenerate or nearly degenerate polysilicon layer has good lateral conductivity, which effectively reduces the square resistance and contact resistance. In addition, the introduction of the tunneling oxygen layer / doped polysilicon layer isolates the metal and silicon substrate, which can significantly reduce the contact recombination loss. These characteristics together determine that the TOPCon battery has a higher open circuit voltage (V OC ) and fill factor (FF), which ultimately manifests in higher photoelectric conversion efficiency. This structural advantage can be more fully reflected in TOPCon-BC (back contact) cells, while integrating the advantages of high short-circuit current density of BC cells, achieving higher photoelectric conversion efficiency.

[0053] However, when the TOPCon cell in the related art prepares the heavily doped polysilicon layer at high temperature, the thickness of the tunneling oxide layer is too thin to effectively mask the impurity atoms. The impurities diffuse into the silicon substrate material through the tunneling oxide layer, forming a highly doped inner expansion area, forming a homojunction with a high doping concentration and a shallow electric field influence depth, making the doping concentration on the surface of the silicon substrate too high, thereby causing serious Auger recombination; and the high surface doping of the silicon substrate will reduce the difference in doping concentration on both sides of the heterojunction between the silicon substrate and the doped polysilicon, reduce the induced electric field strength of the heterojunction on the surface of the silicon substrate, and narrow the action depth of the induced electric field of the heterojunction of the silicon substrate, resulting in the silicon substrate The carrier extraction ability and extraction depth are affected, and then the V OC and FF enhancement.

[0054] Based on the above problems, an embodiment of the present application provides a solar cell, such as Figure 1 As shown, including:

[0055] A silicon substrate 10, wherein a tunnel dielectric layer 80 and a doped polysilicon layer 90 are stacked on a first surface of the silicon substrate 10 and are away from the silicon substrate 10;

[0056] A homojunction 20, the homojunction 20 is located on a side of the silicon substrate 10 having the tunnel dielectric layer 80 and the homojunction 20 diffuses from the surface of the silicon substrate 10 to the inside of the silicon substrate 10;

[0057] The surface doping concentration of the homojunction 20 is 1×10 15 cm -3 ~5×10 18 cm -3 , the junction depth of the homojunction 20 is greater than or equal to 500 nm and less than or equal to the thickness of the silicon substrate 10 .

[0058] It should be noted that the homojunction 20 can be a pn junction formed on the silicon substrate 10, or it can be an electric field formed by the conductivity type of the external doping element and the conductivity type of the doping element in the silicon substrate being the same but the doping concentration of the external doping element and the doping concentration of the doping element in the silicon substrate being different (also called a high-low junction); the heterojunction refers to a pn junction formed between heterogeneous materials, or it can be an electric field formed by the same conductivity type but different doping concentrations (also called a high-low junction); wherein the heterojunction in the embodiments of the present application can be understood as a heterojunction of a doped polysilicon layer / tunneling dielectric layer / silicon substrate.

[0059] It is understandable that, for a double-sided contact cell, both the front side of the silicon substrate 10 and the back side of the silicon substrate 10 can be used as light-receiving surfaces to absorb incident light. The silicon substrate 10 contains doping elements, and the doping element type is N-type or P-type. The N-type element can be a V group element such as phosphorus, bismuth, antimony or arsenic, and the P-type element can be a III group element such as boron, aluminum, gallium or indium. A lower doping concentration of the silicon substrate 10 is conducive to forming a wide space charge region, but it will also significantly increase the series resistance and affect FF. In the embodiment of the present application, the doping concentration of the silicon substrate 10 is characterized by the resistivity of the silicon substrate 10, and the resistivity of the silicon substrate 10 can be 0.3 –2×10 5 Ωcm, preferably the resistivity of the silicon substrate 10 is 0.7-6 Ωcm.

[0060] The silicon substrate 10 is a region that absorbs incident photons and generates photogenerated carriers. In some embodiments, illustratively, the silicon substrate 10 in the embodiments of the present application is a single crystal silicon substrate 10;

[0061] In the embodiments of the present application, the light-receiving surface of the silicon substrate is referred to as the front surface of the silicon substrate, and the backlight surface of the silicon substrate is referred to as the back surface of the silicon substrate.

[0062] The tunneling dielectric layer 80 allows the majority carriers to tunnel into the doped polysilicon layer 90, and then the majority carriers are laterally transmitted in the doped polysilicon layer 90 and collected by the metal electrode, thereby greatly reducing the contact recombination current between the metal electrode and the doped polysilicon layer 90, and improving the open circuit voltage and short circuit current of the solar cell. Increasing the thickness of the tunneling dielectric layer 80 helps to improve the passivation effect and suppress the inward expansion on the silicon substrate 10, but an overly thick tunneling dielectric layer 80 will affect the tunneling transmission effect, and an overly thin tunneling dielectric layer 80 will reduce the passivation effect and increase the inward expansion. Therefore, by optimizing the thickness and material of the tunneling dielectric layer 80, the tunneling dielectric layer 80 can ensure the passivation effect and the tunneling transmission effect while suppressing the inward expansion.

[0063] The doped polysilicon layer 90 can also be N-type doped or P-type doped. The doping concentration of the doped polysilicon layer 90 is selected to be saturated or close to saturated (i.e., polysilicon is a degenerate semiconductor or close to a degenerate semiconductor, i.e., the doping concentration is too high, and the impurity atoms cannot be completely ionized / activated). The higher the doping concentration, the smaller the resistance and contact recombination loss, and the stronger the electric field; the moderate thickness of the doped polysilicon layer 90 can ensure that the optical loss of the doped polysilicon layer 90 is small and the interface passivation effect of the tunneling dielectric layer 80 is good, and avoid increasing the lateral transmission resistance, thereby improving the battery efficiency.

[0064] It can also be understood that the doping type of the homojunction 20 is the same as the doping type of the doped polysilicon layer 90; for example: when the doping element type of the silicon substrate 10 is an N-type doping element, the doping element type of the doped polysilicon layer 90 is an N-type doping element, and the doping element type of the homojunction 20 is an N-type doping element.

[0065] The surface doping concentration of the homojunction 20 refers to the doping concentration of the homojunction 20 on the surface of the silicon substrate 10, and the junction depth of the homojunction 20 refers to the depth at which the doping concentration of the homojunction 20 inside the silicon substrate 10 is equal to the intrinsic doping concentration of the silicon substrate; the surface doping concentration of the homojunction 20 in the embodiment of the present application can be, but is not limited to, 1×10 15 cm -3 , 2×10 15 cm -3 , 2×10 18 cm -3 , 3×10 18 cm -3 , 4×10 18 cm -3 or 5×10 18 cm -3 etc.; the junction depth of the homojunction 20 can be but not limited to 500nm, 100nm, 1500nm, 2000nm, 5000nm, 10μm, 50μm, 100μm, 150μm or 200μm, etc. The surface doping concentration and junction depth of the homojunction 20 of the present application, on the one hand, are conducive to reducing the influence of Auger recombination while ensuring the strengthening of the built-in electric field of the homojunction 20, thereby improving the carrier separation and extraction capabilities; on the other hand, the surface doping concentration and junction depth of the homojunction 20 of the present application can enhance the concentration difference between the doped polysilicon layer 90 and the silicon substrate 10, thereby enhancing the built-in electric field on the surface of the heterojunction silicon substrate 10, which is of great help to the separation of carriers near the interface, effectively improving the VOC and FF of the solar cell, and then improving the conversion efficiency of the solar cell.

[0066] It should be noted that the solar cell can be a front junction cell or a back junction cell, the light-facing side and the back-facing side of the silicon substrate can both be textured surfaces or light-facing textured surface and back-facing polished surface, the silicon substrate can be p-type or n-type, the cell can be double-sided electrode or back contact, single-sided cell or double-sided cell, non-selective emitter or selective emitter structure, etc. A homogeneous pn junction superimposed with a heterogeneous high-low junction, or a homogeneous high-low junction superimposed with a heterogeneous high-low junction, or a heterogeneous pn junction superimposed with a homogeneous high-low junction can be formed by a composite junction. The embodiments of the present application do not specifically limit this.

[0067] For example, the solar cell of the present application can be a TOPCon cell or a BC (back contact) cell; in some embodiments, taking a TOPCon cell with a P-type silicon substrate 10 as an example, the back side of the silicon substrate 10 includes a homojunction 20, a tunneling dielectric layer 80, an N-type doped polysilicon layer 90, a first passivation anti-reflection layer 111 and a first metal electrode 40; the front side of the silicon substrate 10 is provided with a selective emitter 60, a second passivation anti-reflection layer and a second metal electrode 50 in sequence from the inside to the outside; in some other embodiments, taking a BC cell with a P-type silicon substrate 10 as an example, the back side of the silicon substrate 10 includes a plurality of first regions and a plurality of second regions arranged at intervals, the first region includes a homojunction 20, a tunneling dielectric layer 80, an N-type doped polysilicon layer 90, a first passivation anti-reflection layer 111 and a first metal electrode 40, and the second region includes a first passivation anti-reflection layer 111 and a second metal electrode 50 arranged on the surface of the silicon substrate 10, and the second metal electrode 50 is an aluminum electrode.

[0068] The first metal electrode 40 and the second metal electrode 50 may each be a single-layer structure or a stacked-layer structure.

[0069] The solar cell of the embodiment of the present application solves the problem that the homojunction in the prior art TOPCon cell has a high concentration on the surface of the silicon substrate 10 and a shallow junction depth. The embodiment of the present application sets a homojunction with a low doping depth of the electric field on the surface of the silicon substrate near the tunnel dielectric layer and the doped polysilicon, that is, the doping concentration on the surface of the homojunction is 1×10 15 cm -3 ~5×10 18 cm -3 , the homojunction electric field depth is greater than or equal to 500nm and less than or equal to the thickness of the silicon substrate. On the one hand, the homojunction doping concentration and electric field depth of the present application are conducive to improving the carrier separation and extraction capabilities inside the silicon substrate while reducing the influence of Auger recombination; on the other hand, the doping concentration of the homojunction of the present application can enhance the doping concentration difference between the doped polysilicon layer and the silicon substrate, thereby improving the heterojunction induced electric field strength and action depth on the surface of the heterojunction silicon substrate, which is of great help to the carrier separation near the interface, and effectively improves the V OC and FF, thereby improving the photoelectric conversion efficiency of solar cells.

[0070] In a preferred embodiment, the surface doping concentration of the homojunction 20 is 1×10 16 cm -3 ~3×10 18 cm -3 The doping concentration of the homojunction 20 of this embodiment is beneficial to reducing Auger recombination, and is beneficial to the transfer of the heterojunction electric field to the silicon substrate, thereby increasing the induced electric field strength and depth of the heterojunction in the silicon substrate.

[0071] In a preferred embodiment, the junction depth of the homojunction 20 is 1000nm~2000nm. The junction depth of the homojunction 20 of this embodiment can meet the internal electric field strength of the high-low junction, so that the minority carriers drift to the surface of the doped polysilicon layer 90, shorten the path of the carriers generated by the silicon substrate 10 drifting to the PN junction, which is conducive to reducing the risk of recombination of the minority carriers before reaching the doped polysilicon layer 90. In addition, the junction depth of the homojunction 20 is less than the thickness of the silicon substrate 10, that is, it penetrates the silicon substrate 10, which is conducive to the diffusion of the doping elements in the homojunction 20 to the front or heavily doped area of ​​the silicon substrate 10, which is conducive to improving the open circuit voltage of the solar cell and the photoelectric conversion efficiency of the solar cell.

[0072] As an optional solution, the doping concentration of the doped polysilicon layer 90 is 1×10 17 cm -3 ~1×10 22 cm -3 Specifically, the doping concentration of the doped polysilicon layer 90 may be, but is not limited to, 1×10 17 cm -3 , 2×10 17 cm -3 , 1×10 18 cm -3 , 1×10 19 cm -3 , 3×10 19 cm -3 , 5×10 19 cm -3 , 1×10 20 cm -3 , 6×10 20 cm -3 , 1×10 21 cm -3 ,7×10 21 cm -3 or 1×10 22 cm -3 wait.

[0073] The doping concentration of the doped polysilicon layer 90 in this embodiment is higher than the doping concentration of the homojunction 20, and a high-low junction is formed between the homojunction 20 and the doped polysilicon layer 90, thereby forming a built-in electric field between the homojunction 20 and the doped polysilicon layer 90, so that the doping elements in the silicon substrate 10 can easily drift to the highly doped doped polysilicon layer, which is beneficial to increase the output current of the battery.

[0074] In a preferred embodiment, the doping concentration of the doped polysilicon layer 90 is 1×10 19 cm -3 ~1×10 21 cm-3 .

[0075] As an implementable manner, the tunnel dielectric layer 80 is selected from at least one of oxide, nitride, oxynitride, carbide, oxycarbide or halide.

[0076] In some embodiments, based on the projection on the surface of the silicon substrate 10 , the projection of the doped polysilicon layer 90 is located within the projection range of the homojunction 20 .

[0077] As an achievable manner, the solar cell includes a passivation anti-reflection layer located on the surface of the doped polysilicon layer 90;

[0078] and a metal electrode, wherein the metal electrode passes through the passivation anti-reflection layer and contacts the doped polysilicon layer 90 .

[0079] In some embodiments, based on the projection on the surface of the silicon substrate 10 , the projection of the metal electrode is located within the projection range of the homojunction 20 .

[0080] As an implementable manner, the passivation anti-reflection layer includes a first passivation anti-reflection layer 111 and a second passivation anti-reflection layer 112 , and the first passivation anti-reflection layer 111 and the second passivation anti-reflection layer 112 each include an aluminum oxide layer 113 and a silicon nitride layer 114 that are stacked.

[0081] Among them, aluminum oxide and silicon nitride can both play a passivation role, and the anti-reflection effect mainly depends on silicon nitride; in a preferred embodiment, a multi-layer anti-reflection structure is set up, and silicon nitride can be set as a multi-layer silicon nitride layer with different refractive indexes; other anti-reflection layers, such as magnesium fluoride, can also be set on the silicon nitride surface.

[0082] In addition, silicon nitride may also be oxygen-doped or carbon-doped or both-doped silicon nitride, that is, silicon oxynitride, silicon carbide nitride, silicon carbon nitride oxynitride, and the like.

[0083] In some embodiments, aluminum oxide may be replaced by intrinsic or doped amorphous silicon, nanocrystalline silicon, microcrystalline silicon, microcrystalline silicon oxide, nanocrystalline silicon oxide, amorphous silicon oxide, phosphorus oxide, boron oxide, hafnium oxide, silicon carbide, titanium oxide, gallium oxide, zinc oxide, or tantalum oxide.

[0084] In some embodiments, Figure 2 As shown, the silicon substrate 10 further includes a second surface opposite to the first surface, and the second surface includes a selective emitter 60 .

[0085] In other embodiments, Figure 5 As shown, the first surface of the silicon substrate 10 includes a plurality of first regions and a plurality of second regions that are spaced apart from each other, and the homojunction 20 is located in the surface of the first region.

[0086] It can be understood that the structures of all the first regions can be the same or different, for example, a part of the first region is provided with a homojunction, and the remaining part of the first region is not provided with a homojunction; the corresponding second region is similar; wherein the second region can be any structure, including but not limited to an aluminum back field structure, a passivation selective contact structure or an amorphous silicon heterojunction structure; wherein the passivation selective contact structure includes a passivation layer and a selective transport layer, and the selective transport layer includes an electron selective transport layer or a hole selective transport layer; and the amorphous silicon heterojunction structure includes an intrinsic amorphous silicon layer and a doped semiconductor layer.

[0087] As an achievable manner, the hole selective transport layer includes a hole selective layer, or a hole selective layer and a transport layer stacked and arranged away from the silicon substrate surface; the electron selective transport layer includes an electron selective layer, or an electron selective layer and a transport layer stacked and arranged away from the silicon substrate surface.

[0088] Among them, the hole selection layer and the transport layer are made of high work function materials, and there is a work function difference between the two materials. The hole selection layer is mainly used to form an electric field to repel electrons, and the transport layer is used to improve the contact performance of the metal electrode. For the local structure, when the projection area of ​​the hole selection layer is not larger than the projection area of ​​the metal electrode, the transport layer can be omitted; the same is true for the electron selection layer and the transport layer.

[0089] In some embodiments, the hole selection layer is selected from materials with a work function greater than 4.8 eV and a valence band gap ΔE V A material with a V of less than 0.5 eV, or a monomolecular layer material; the transport layer is selected from at least one of oxides, nitrides, oxynitrides, chalcogenides, halides, thiocyanates and organic conductive polymers;

[0090] The electron selective layer is selected from materials with a work function less than 4.2 eV and a conduction band gap ΔE C A material with a FET of less than 0.5 eV, or an organic conductive polymer; the transport layer is selected from at least one of doped or intrinsic oxides, nitrides, carbides, oxynitrides, carbon oxides, carbonitride oxides, chalcogenides, halides, or organic conductive polymers.

[0091] Specifically, the hole selection layer is selected from at least one of doped or intrinsic molybdenum oxide, vanadium oxide, tungsten oxide, chromium oxide, titanium oxide, copper oxide, nickel oxide, cobalt oxide, rhenium oxide, copper iodide, PEDOT:PSS, silicon carbide and a phosphate group monolayer;

[0092] The electron selective layer is selected from at least one of doped or intrinsic lithium fluoride, magnesium fluoride, potassium fluoride, rubidium fluoride, cesium fluoride, calcium fluoride, strontium fluoride, barium fluoride, cerium fluoride, europium fluoride, tantalum oxide, zinc oxide, indium oxide, titanium oxide, magnesium oxide, zinc oxide, tin oxide, cesium oxide, niobium oxide, barium oxide, tantalum nitride, titanium nitride, titanium oxynitride, silicon carbide, cesium chloride, cesium bromide, cesium iodide, cesium carbonate, potassium carbonate, rubidium carbonate, calcium carbonate, strontium carbonate, barium carbonate, zinc sulfide, cadmium sulfide, indium sulfide, fullerene derivatives and bathocuproine.

[0093] Furthermore, the thickness of the hole selective transport layer is 0.1 nm-700 nm, and the thickness of the passivation anti-reflection layer is 0 nm-525 nm.

[0094] In some embodiments, the electron selective transport layer has a thickness of 0.1 nm to 700 nm.

[0095] In a preferred embodiment, the thickness of the hole selective transport layer is 0.5 nm-340 nm.

[0096] In a preferred embodiment, the thickness of the electron selective transport layer is 0.5 nm-340 nm.

[0097] In a preferred embodiment, the thickness of the passivation anti-reflection layer is 30 nm-300 nm.

[0098] In some embodiments, the thickness of the electron selective layer is 0.1 nm-100 nm, preferably 0.5 nm-40 nm; the thickness of the transport layer is 0 nm-600 nm, preferably 0 nm-300 nm.

[0099] It can also be understood that due to the provision of the hole selective transport layer and the electron selective transport layer, the metal electrode can be made of low-cost metal, which is beneficial to greatly reduce the cost of metallization materials.

[0100] As an achievable manner, one or more anti-reflection layers, such as magnesium fluoride, may be further disposed on the outer surfaces of the hole selective transport layer, the electron selective transport layer, and the passivation anti-reflection layer. Specifically, if the hole selective transport layer is located at the outermost side, an anti-reflection layer is disposed on the outer surface of the hole selective transport layer; if the electron selective transport layer is located at the outermost side, an anti-reflection layer is disposed on the outer surface of the electron selective transport layer; if the passivation anti-reflection layer is located at the outermost side, an anti-reflection layer is disposed on the outer surface of the passivation anti-reflection layer.

[0101] In some embodiments, the second region includes a P-type doped layer, and the doping type of the homojunction is different from the doping type of the P-type doped layer.

[0102] It can be understood that the P-type doped layer can be a doped layer (P+ layer) formed when the second metal electrode 50 is aluminum and an aluminum electrode is formed on the surface of the silicon substrate; that is, the second region adopts aluminum back field technology; specifically, the second region includes a passivation anti-reflection layer and an aluminum electrode, and the aluminum electrode contacts the silicon substrate through the passivation anti-reflection layer.

[0103] In summary, the solar cell of the embodiment of the present application is provided with a low-doped deep electric field depth homojunction on the surface of the silicon substrate near the tunnel dielectric layer and the doped polysilicon, that is, the homojunction surface doping concentration is 1×10 15 cm -3 ~5×10 18 cm -3 , the homojunction electric field depth is greater than or equal to 500nm and less than or equal to the thickness of the silicon substrate. On the one hand, the homojunction doping concentration and electric field depth of the present application are conducive to improving the carrier separation and extraction capabilities inside the silicon substrate while reducing the influence of Auger recombination; on the other hand, the doping concentration of the homojunction of the present application can enhance the doping concentration difference between the doped polysilicon layer and the silicon substrate, thereby improving the heterojunction induced electric field strength and action depth on the surface of the heterojunction silicon substrate, which is of great help to the carrier separation near the interface, and effectively improves the V OC and FF, thereby improving the photoelectric conversion efficiency of solar cells.

[0104] In a second aspect, the present invention provides a method for preparing a solar cell, which specifically comprises the following steps:

[0105] S1, forming a doping source layer on the first surface of the silicon substrate, the doping source layer comprising a first pre-doping layer and PSG formed on the first surface of the silicon substrate, or a second pre-doping layer and BSG formed on the first surface of the silicon substrate;

[0106] S2, removing PSG or BSG on the first surface of the silicon substrate;

[0107] S3, diffusion processing by means of finite source diffusion;

[0108] S4, preparing a tunneling dielectric layer on the first surface of the silicon substrate;

[0109] S5, preparing a doped polysilicon layer on the surface of the tunneling dielectric layer;

[0110] Finally, a homojunction is formed in the first surface of the silicon substrate, and the surface doping concentration of the homojunction is 1×10 15 cm -3 ~5×10 18 cm -3 The junction depth of the homojunction is greater than or equal to 500nm and less than or equal to the thickness of the silicon substrate.

[0111] In step S1, a doping source layer is formed on the surface of the silicon substrate to form a first pre-doping layer and PSG, or a second pre-doping layer and BSG on the surface of the silicon substrate. The first pre-doping layer and the second pre-doping layer can be understood as areas with high doping concentration and shallow doping depth on the surface of the silicon substrate; the silicon substrate can be a polished surface or a textured surface; the process for preparing the doping source layer can be, but is not limited to, thermal diffusion (e.g., tube furnace thermal diffusion, silicon ink diffusion), laser doping (e.g., laser doping, spin-coating phosphorus source doping, laser chemical doping), or ion implantation, etc.

[0112] For example, taking a P-type silicon substrate as an example, LPCVD and PECVD can be used for thermal diffusion with limited phosphorus source.

[0113] In step S2, the surface PSG and BSG can be removed by conventional processes;

[0114] In step S3, the limited source diffusion is performed to reduce the surface doping concentration of the first pre-doped layer or the second pre-doped layer and push the doping elements into the silicon substrate; wherein the limited source is to remove the PSG or BSG rich in doping elements and use the first pre-doped layer or the second pre-doped layer as a limited diffusion source; the limited source diffusion can adopt the same process as step S1, but different process parameters such as temperature, pressure and time can be adjusted according to the doping curve, which are determined according to actual processing needs;

[0115] In step S4, a tunneling dielectric layer is prepared on the first surface of the silicon substrate. The tunneling dielectric layer has a certain passivation and masking effect to avoid the problem of Fermi level pinning caused by the high density of interface defect states. At the same time, the material needs to provide masking ability. It is necessary to have a wide bandgap, high resistance, the properties of chemical passivation and field effect passivation, and a dense structure, which can achieve effective masking ability for phosphorus or boron and prevent internal expansion. The materials of the tunneling dielectric layer include but are not limited to some oxides, nitrides, nitrogen oxides, carbides, carbon oxides, etc.; the embodiments of the present application utilize a dense and appropriately thick tunneling dielectric layer, combined with an optimized process for doped polysilicon layers, to strictly control the internal expansion accompanying the formation of doped polysilicon layers and suppress the formation of highly doped homojunctions.

[0116] The method for preparing the tunnel dielectric layer includes but is not limited to:

[0117] Thermal oxidation growth method:

[0118] CVD: Ozone gas oxidation (OGO), plasma-assisted nitrous oxide oxidation (PANO), APCVD, LPCVD, UHVCVD, LCVD, photo-CVD, PECVD, HDPCVD, MPCVD, HTCVD, MTCVD, ICPCVD, MOCVD, HWCVD, VPE, ThermalALD, PEALD

[0119] PVD: thermal evaporation, electron beam evaporation, magnetron sputtering, reactive sputtering, DC sputtering, RF sputtering, ion beam sputtering, ion plating, ion beam deposition, ion assisted deposition (IAD), MBE, LPE, HWE, close space sublimation (CSS);

[0120] Solution method: nitric acid oxidation (NAOS), spin coating, spray coating, drop coating, meniscus coating, dipping, CBD, SILAR, electroplating, chemical plating, anodic reaction deposition

[0121] Two-step oxidation (TSO).

[0122] In step S5, a doped polysilicon layer is prepared to form a degenerate semiconductor with a high doping concentration. Thermal diffusion requires high temperature and diffusion source flow. During the preparation process, attention should be paid to the influence on the doping concentration and junction depth of the homojunction. The following methods can be used: (1) Combine the doping crystallization process of the doped polysilicon layer and the thermal diffusion process of the internal diffusion to achieve the optimization of the doping curve, that is, the diffusion process of step S1 does not need to achieve the optimal doping curve, which can be achieved through the doping crystallization process of the doped polysilicon layer in step S5; (2) Take other routes to prepare the doped polysilicon layer, such as the low-temperature route.

[0123] In a preferred embodiment, a doped polysilicon layer is prepared on the surface of the tunnel dielectric layer using a low temperature process. The low temperature process used in this embodiment is beneficial to suppress the diffusion of doping elements into the substrate when preparing the doped polysilicon layer, and the low temperature process operation is safe and reliable.

[0124] As a feasible approach, for cells with different structures, other passivation anti-reflection layers are prepared on the surface of the doped polysilicon layer.

[0125] For example, taking an N-type battery as an example, the front side is a boron diffusion junction of an SE structure, the back side is an n++ passivation contact structure, and the composite junction is arranged on the back side. The preparation method includes the following steps:

[0126] (1) Cleaning of silicon substrate and texturing of the front side of silicon substrate;

[0127] (2) Boron diffusion is performed on the silicon substrate to form SE;

[0128] (3) Backside etching of the silicon substrate to remove BSG and the boron expansion area;

[0129] (4) Diffusion of phosphorus on silicon substrate;

[0130] (5) preparing a passivation layer and amorphous silicon deposition on the back side of the silicon substrate;

[0131] (6) Phosphorus diffusion;

[0132] (7) Etching the front side of the silicon substrate to remove the phosphorus diffusion residue and PSG;

[0133] (8) Forming aluminum oxide on both sides of the silicon substrate by ALD;

[0134] (9) Forming silicon nitride on both sides of the silicon substrate by PECVD;

[0135] (10) Grooving;

[0136] (11) Low-temperature metallization treatment of the front and back sides of the silicon substrate;

[0137] (12) Contact optimization by laser enhancement and light injection.

[0138] In a third aspect, an embodiment of the present application provides another method for preparing a solar cell, comprising the following steps:

[0139] S1, preparing a dielectric layer on a first surface of a silicon substrate;

[0140] S2, preparing a first doped polysilicon layer on the dielectric layer to form an inner extension layer in the first surface of the silicon substrate;

[0141] S3, removing the first doped polysilicon layer;

[0142] S4, diffusing the inner expansion layer into the silicon substrate by limited source diffusion;

[0143] S5, forming a tunneling dielectric layer and a second doped polysilicon layer on the first surface of the silicon substrate;

[0144] Finally, a homojunction is formed in the first surface of the silicon substrate, and the surface doping concentration of the homojunction is 1×10 15 cm -3 ~5×10 18 cm -3 , the junction depth of the homojunction is greater than or equal to 500 nm and less than or equal to the thickness of the silicon substrate.

[0145] It can be understood that the preparation of the first doped polysilicon layer in step S2 includes:

[0146] Depositing intrinsic amorphous silicon;

[0147] The intrinsic amorphous silicon is crystallized to form a first doped polysilicon layer and the inner diffusion layer.

[0148] Doped amorphous silicon can be first prepared by in-situ doping, and then crystallized through a high-temperature process to form doped amorphous silicon and an inner diffusion layer.

[0149] In step S2, during the process of preparing the first doped polysilicon layer, the doping elements diffuse into the silicon substrate through the dielectric layer to form a high-concentration diffusion layer on the surface of the silicon substrate;

[0150] After removing the first doped polysilicon layer, the inner expansion layer is used as a limited diffusion source to push the inner expansion layer into the silicon substrate by further diffusion;

[0151] In step S3, removing the first doped polysilicon may also include removing the dielectric layer;

[0152] In step S4, further diffusion is performed using the inner diffusion layer as a limited diffusion source;

[0153] In step S5, the tunnel dielectric layer and the second doped polysilicon may be formed in the same manner as in the second aspect of the present invention.

[0154] In a fourth aspect, the present invention provides a solar cell assembly, including a solar cell according to the first aspect. It is understandable that the solar cell assembly has all the features and advantages of the above solar cells, which will not be described in detail here. In general, the solar cell assembly has a high cell efficiency.

[0155] In a fifth aspect, the present invention provides a solar cell system, including a solar cell assembly according to the fourth aspect. It is understood that the solar cell system has all the features and advantages of the above-mentioned solar cells, which will not be described in detail here. In general, the solar cell system has a higher cell efficiency.

[0156] The solar cell of the embodiment of the present application is described in detail below with reference to a specific embodiment.

[0157] Example 1

[0158] like Figure 2 As shown, taking a double-sided contact cell with a P-type silicon substrate as an example, the back side of the silicon substrate 10 includes a homojunction 20, a tunneling dielectric layer 80, a P-type doped polysilicon layer 90, a first passivation anti-reflection layer 111 and a first metal electrode 40; the front side of the silicon substrate 10 includes a selective emitter 60 (n++), a light expansion region 70, a second passivation anti-reflection layer 112 and a second metal electrode 50.

[0159] Comparative Example 1

[0160] Different from Example 1, Figure 3As shown, the comparative example is a traditional TOPCon cell structure without the homojunction in Example 1; wherein, when forming the doped polysilicon layer, the traditional TOPCon cell forms an inner expansion layer of the same doping type inside the silicon substrate, and the doping concentration of the inner expansion layer is high and the depth is shallow;

[0161] Figure 4 The comparison of the doping curves of the embodiment of the present invention and the traditional TOPCon is shown. Among them, the "biased doping polysilicon / tunneling dielectric / silicon substrate optimization strategy" and the "biased homojunction optimization strategy" are two different optimization methods of the present invention. Compared with the "biased doping polysilicon / tunneling dielectric / silicon substrate optimization strategy" and the "biased homojunction optimization strategy", the "biased doping polysilicon / tunneling dielectric / silicon substrate optimization strategy" sets the doping concentration on the surface of the silicon substrate to be slightly lower, and the concentration difference between polysilicon and the substrate is large, which is beneficial to the electric field effect of the heterojunction, but will weaken the homojunction electric field enhancement to a certain extent. The "biased homojunction optimization strategy" sets the silicon substrate surface concentration to be slightly higher, and the concentration difference between polysilicon and the substrate is small, and the homojunction electric field is enhanced, which is beneficial to the effect of the homojunction, but weakens the electric field effect of the heterojunction to a certain extent. Compared with traditional TOPCon cells, the junction depth of the homojunction inside the silicon substrate of the present invention is deeper, reaching 1200nm; and the doping concentration of the homojunction on the surface of the silicon substrate of the present invention is much lower than that of traditional TOPCon cells. As the junction depth of the homojunction inside the silicon substrate increases, the doping concentration changes slowly and approaches the doping concentration of the intrinsic silicon substrate.

[0162] Example 2

[0163] like Figure 5 As shown, taking a back contact cell of a P-type silicon substrate as an example, the back side of the silicon substrate 10 includes a plurality of first regions and second regions arranged at intervals, each first region includes a homojunction 20, a tunneling dielectric layer 80, an N-type doped polysilicon layer 90, a first passivation anti-reflection layer 111 and a first metal electrode 40 stacked sequentially from the inside to the outside on the surface of the silicon substrate, and the first metal electrode 40 passes through the first passivation anti-reflection layer 111 and contacts with the N-type doped polysilicon layer 90;

[0164] Each second region includes a first passivation anti-reflection layer 111 and a second metal electrode 50 disposed on the back side of the silicon substrate. The second metal electrode 50 passes through the first passivation anti-reflection layer 111 and contacts the silicon substrate 10. The second metal electrode 50 may be an aluminum electrode.

[0165] A second passivation anti-reflection layer 112 is disposed on the front surface of the silicon substrate.

[0166] It should be understood that the terms "center", "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like used above to indicate orientations or positional relationships are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, unless otherwise specified, "multiple" means two or more.

[0167] The above description is only a preferred embodiment of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of the invention involved in the present application is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the inventive concept. For example, the above features are replaced with (but not limited to) technical features with similar functions disclosed in the present application.

Claims

1. A solar cell, characterized in that: include: A silicon substrate, wherein a tunnel dielectric layer and a doped polysilicon layer are stacked on a first surface of the silicon substrate away from the silicon substrate; A homojunction, the homojunction is located on a side of the silicon substrate having the tunnel dielectric layer, and the homojunction diffuses from the surface of the silicon substrate to the inside of the silicon substrate; The surface doping concentration of the homojunction is 1×10 15 cm -3 ~5×10 18 cm -3 , the junction depth of the homojunction is greater than or equal to 500nm and less than or equal to the thickness of the silicon substrate; wherein the surface doping concentration of the homojunction refers to the doping concentration of the homojunction located on the surface of the silicon substrate, and the junction depth of the homojunction refers to the depth at which the doping concentration of the homojunction inside the silicon substrate is equal to the intrinsic doping concentration of the silicon substrate; A passivation anti-reflection layer located on the surface of the doped polysilicon layer; and a metal electrode, wherein the metal electrode passes through the passivation anti-reflection layer and contacts the doped polysilicon layer.

2. The solar cell according to claim 1, characterized in that: The surface doping concentration of the homojunction is 1×10 16 cm -3 ~3×10 18 cm -3 .

3. The solar cell according to claim 1, characterized in that The junction depth of the homojunction is 1000nm~2000nm.

4. The solar cell according to claim 1, characterized in that The doping concentration of the doped polysilicon layer is 1×10 19 cm -3 ~1×10 21 cm -3 .

5. The solar cell according to claim 1, characterized in that: Based on the projection on the surface of the silicon substrate, the projection of the doped polysilicon layer is located within the projection range of the homojunction.

6. The solar cell according to any one of claims 1 to 5, characterized in that: The tunnel dielectric layer is selected from at least one of oxide, nitride, oxynitride, carbide, oxycarbide or halide.

7. The solar cell according to any one of claims 1 to 5, characterized in that: Based on the projection on the surface of the silicon substrate, the projection of the metal electrode is located within the projection range of the homojunction.

8. The solar cell according to any one of claims 1 to 5, characterized in that: The silicon substrate further includes a second surface opposite to the first surface, the second surface including a selective emitter.

9. The solar cell according to any one of claims 1 to 5, characterized in that: The first surface of the silicon substrate includes a plurality of first regions and a plurality of second regions that are spaced apart from each other; The homojunction is located within a surface of the first region.

10. The solar cell according to claim 9, characterized in that: The second region includes a P-type doping layer, and a doping type of the homojunction is different from a doping type of the P-type doping layer.

11. A method for preparing a solar cell, characterized in that: The steps include: Forming a doping source layer on the first surface of the silicon substrate, wherein the doping source layer includes a first pre-doping layer and PSG formed on the first surface of the silicon substrate, or the doping source layer includes a second pre-doping layer and BSG formed on the first surface of the silicon substrate; removing PSG or BSG on the first surface of the silicon substrate; Diffusion treatment is performed by means of finite source diffusion; Preparing a tunneling dielectric layer on the first surface of the silicon substrate; preparing a doped polysilicon layer on the tunnel dielectric layer; A homojunction is formed in the first surface of the silicon substrate, and the surface doping concentration of the homojunction is 1×10 15 cm -3 ~5×10 18 cm -3 , the junction depth of the homojunction is greater than or equal to 500nm and less than or equal to the thickness of the silicon substrate; wherein the surface doping concentration of the homojunction refers to the doping concentration of the homojunction located on the surface of the silicon substrate, and the junction depth of the homojunction refers to the depth at which the doping concentration of the homojunction inside the silicon substrate is equal to the intrinsic doping concentration of the silicon substrate.

12. A method for preparing a solar cell, characterized in that: The steps include: Preparing a dielectric layer on a first surface of a silicon substrate; Preparing a first doped polysilicon layer on the dielectric layer to form an inner extension layer in the first surface of the silicon substrate; removing the first doped polysilicon layer; Diffusion of the inner diffusion layer into the silicon substrate by limited source diffusion; forming a tunneling dielectric layer and a second doped polysilicon layer on the first surface of the silicon substrate; A homojunction is formed in the first surface of the silicon substrate, and the surface doping concentration of the homojunction is 1×10 15 cm -3 ~5×10 18 cm -3 , the junction depth of the homojunction is greater than or equal to 500nm and less than or equal to the thickness of the silicon substrate; wherein the surface doping concentration of the homojunction refers to the doping concentration of the homojunction located on the surface of the silicon substrate, and the junction depth of the homojunction refers to the depth at which the doping concentration of the homojunction inside the silicon substrate is equal to the intrinsic doping concentration of the silicon substrate.

13. A solar cell module, characterized in that: A solar cell comprising the solar cell according to any one of claims 1 to 10.

14. A solar cell system, characterized in that: A solar cell module comprising the solar cell module as claimed in claim 13.

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