Phase-shifted memristive chaotic oscillator with controllable amplitude and bias

Abstract

The present invention discloses a phase-shifted memristor chaotic oscillator with controllable amplitude and bias, belonging to the technical fields of electronics, communications, and information engineering. A phase-shifted chaotic oscillator is constructed by introducing a memristor. The introduced memristor can change the frequency selection network of the oscillation circuit while also maintaining a constant amplification factor. The oscillator has two independent bias control voltages, which can effectively control the voltage values on two capacitors through bias cancellation. The op amp supply voltage and the memristor change rate in the oscillation circuit change in the same proportion, which can also scale the output voltages on all capacitors in the same proportion. Finally, a memristor equivalent circuit is designed, which uses AD633 feedback to implement division operations, significantly reducing component usage and lowering costs. The present invention has a simple circuit structure, a wide range of chaos control parameters, and a relatively stable system. It can be widely used in instruments and signal generators, and can also be used for secure communications, information encryption, and pseudo-random number generation.

Description

Technical Field

[0001] The present invention belongs to the technical field of electronics, communications and information engineering, and particularly relates to a phase-shifted memristive chaotic oscillator with controllable amplitude and bias. Background Art

[0002] Chaotic signals, due to their initial value sensitivity and quasi-randomness, have found widespread application in secure communications, neural stimulation, and weak signal detection. However, in practical engineering, the bias and amplitude of chaotic signals often need to be adjusted to meet system requirements. Amplitude modulation is often a necessary step in signal conditioning. Due to the broadband nature of chaotic signals, the design of conditioning circuits that match them is currently relatively complex. Therefore, finding a signal conditioning method based on the internal structure of chaotic systems is of great significance for engineering applications. Memristors, as a new type of nonlinear element, have become a common circuit component in chaotic systems due to their introduction of nonlinear feedback. Many circuits incorporate memristors to generate chaos. In recent years, with the advancement of memristor research, some classical systems have been successfully transformed into chaotic memristor systems by combining memristors with them. However, the design process from system to circuit often results in complex circuits.

[0003] Regarding the amplitude control and bias adjustment of chaotic signals, the implementation solutions of relevant patents were consulted. For example, patent [application number CN202010199862.7] proposes a dual-scroll memristor super-chaotic signal source circuit, but the signal source circuit cannot be amplitude-controlled; patent [authorization number ZL201210395656.9] gives a four-wing chaotic signal source circuit, which realizes nonlinearity through cross-product terms, outputs complex four-wing chaotic phase orbits, and realizes local amplitude control by adjusting the feedback strength of the cross-product terms, but there is no bias adjustment; patent [authorization number ZL201910561036.X] uses three multipliers and a memristor to realize nonlinear action to construct chaos. By adjusting the weight value of the memristor, different chaotic signals or periodic signals can be generated. However, this patent cannot achieve the adjustment of signal polarity and bias; patent [application number CN202310308615.X] proposes a simplified Jerk-like adjustable amplitude and frequency chaotic oscillator and its control method, but the circuit structure is not compact and relatively complex. The present invention realizes amplitude control by jointly controlling the parameters of the memristor and the power supply voltage of the main operational amplifier, and realizes bias control of the chaotic signal by a direct current voltage source. Summary of the Invention

[0004] Purpose of the Invention: To address the above issues, the present invention proposes a phase-shifted memristor chaotic oscillator with controllable amplitude and bias. By introducing a memristor into the classic phase-shifted sinusoidal oscillator structure and designing a controlled memristor to maintain a constant amplification factor, the circuit generates chaotic oscillations. This circuit achieves amplitude control by combining memristor parameters with the main op amp power supply voltage, and bias control of the chaotic signal via a DC voltage source. Because bias and amplitude are controlled by internal parameters, the main op amp power supply voltage, and the DC voltage source, the hardware cost is relatively low.

[0005] Technical solution: To achieve the purpose of the present invention, the technical solution adopted by the present invention is: an amplitude and bias controllable phase-shifted memristor chaotic oscillator, comprising a phase-shifted oscillation circuit, a memristor M and a controlled memristor M f .

[0006] The phase-shift oscillator circuit has a loop structure.

[0007] The output of the main operational amplifier U1 is connected to one end of the capacitor C1; the other end of the capacitor C1 is connected to one end of the capacitor C2, and the connection point leads to the first branch; the other end of the capacitor C2 is connected to one end of the capacitor C3, and the connection point leads to the second branch; the other end of the capacitor C3 is connected to the reverse input of the main operational amplifier U1; the controlled memristor M f One end is denoted as V + Connected to the reverse input terminal of the main op amp U1, the other end is recorded as V - Connected to the output terminal of the main operational amplifier U1; the non-inverting input terminal of the main operational amplifier U1 is grounded; in the first branch, starting from the connection point, it is connected to the resistor R1 through the DC voltage source V1 and then grounded; in the second branch, starting from the connection point, it is connected to the memristor M through the connection terminal VM through the DC voltage source V2 and then grounded.

[0008] The amplitude- and bias-controllable phase-shifted memristor chaotic oscillator includes a memristor M, which consists of three modules and two voltage followers. The first module is the memristor internal variable control module, the second module is the memristor current output module, and the third module is the memristor window function module.

[0009] The four input terminals of the above-mentioned memristor internal variable control module are respectively connected to the output terminal VRR of the memristor current output module, the output terminal VMM of the first voltage follower, the output terminal VFS of the memristor window function module and the negative power supply VN of the main operational amplifier U1; the output terminal VS-5 of the memristor internal variable control module is connected to an input terminal of the memristor window function module.

[0010] The three input terminals of the above-mentioned memristor current output module are respectively connected to the first voltage follower input terminal VM, the first voltage follower output terminal VMM and the second voltage follower output terminal P10V; the output terminal VRR of the memristor current output module is connected to an input terminal of the memristor internal variable control module.

[0011] The three input terminals of the above-mentioned memristor window function module are respectively connected to the first voltage follower output terminal VMM, the memristor internal variable control module output terminal VS-5 and the second voltage follower output terminal P10V; the output terminal VFS of the memristor window function module is connected to an input terminal of the memristor internal variable control module.

[0012] The first voltage follower is connected to the first voltage follower input terminal VM via the non-inverting input terminal of the operational amplifier U2 and is connected to the first voltage follower output terminal VMM via the inverting input terminal of the operational amplifier U2.

[0013] The second voltage follower above connects the DC voltage source +15V through the resistor R 35 With op amp U 23 The non-inverting input terminal is connected to the op amp U 23 The non-inverting input is connected through the resistor R 36 Grounded at the back; op amp U 23 The inverting input terminal is connected to the output terminal, and the operational amplifier U 23 The output end of is the second voltage follower output end P10V.

[0014] The above-mentioned memristor internal variable control module includes resistors R2, R3, R4, R5, R6, R7, R8, R9, R 10, operational amplifiers U4, U5, U7, U8, U9, and multipliers U3, U6; this module contains four input terminals, which are respectively connected to the output terminal VRR of the memristor current output module, the output terminal VMM of the first voltage follower, the output terminal VFS of the memristor window function and the negative power supply VN of the main operational amplifier U1; one output terminal: the output terminal VS-5 of the memristor internal variable control module. Three of the input terminals are on the multiplier U3; the multiplicand X non-inverting input terminal X1 of the multiplier U3 is connected to the output terminal VRR of the memristor current output module, the multiplicand X inverting input terminal X2 is connected to the output terminal VMM of the first voltage follower, the multiplicand Y non-inverting input terminal Y1 is connected to the output terminal VFS of the memristor window function module, the multiplicand Y inverting input terminal Y2 is grounded, the summing input terminal Z is grounded, and its product output terminal W is connected to the inverting input terminal of the operational amplifier U5 through the resistor R3; the non-inverting input terminal of the operational amplifier U5 is grounded, and the output terminal is connected to the multiplicand Y inverting input terminal Y2 of the multiplier U6; one end of the resistor R4 is connected to the inverting input terminal of the operational amplifier U5, and the other end is connected to the product output terminal W of the multiplier U6; the multiplicand X non-inverting input terminal X1, the multiplicand Y non-inverting input terminal Y1 and the summing input terminal Z of the multiplier U6 are grounded; the DC voltage source +5V is connected to the resistor R 10 Connected to the non-inverting input of the operational amplifier U9; the non-inverting input of the operational amplifier U9 is grounded after passing through the sliding variable resistor PR2, and the inverting input of the operational amplifier U9 is connected to the output; one end of the resistor R6 is connected to the output of the operational amplifier U9, and the other end is connected to the inverting input of the operational amplifier U7; the negative power supply VN of the main operational amplifier U1 is connected to the inverting input of the operational amplifier U7 through the resistor R5; one end of the resistor R7 is connected to the inverting input of the operational amplifier U7, and the other end is connected to the output of the operational amplifier U7; the non-inverting input of the operational amplifier U7 is grounded, and the output is connected to the inverting input Y2 of the multiplicand Y of the multiplier U6; the resistor R8 One end of is connected to the inverting input terminal X2 of the multiplicand X of the multiplier U6, and the other end is connected to the inverting input terminal of the operational amplifier U8; one end of the resistor R9 is connected to the inverting input terminal of the operational amplifier U8, and the other end is connected to the output terminal of the operational amplifier U8; the non-inverting input terminal of the operational amplifier U8 is grounded; the output terminal of the operational amplifier U8 is connected to the inverting input terminal of the operational amplifier U4 through the resistor R2; one end of the capacitor C4 is connected to the inverting input terminal of the operational amplifier U4, and the other end is connected to the output terminal of the operational amplifier U4; the non-inverting input terminal of the operational amplifier U4 is grounded, and its output terminal is the output terminal VS-5 of the internal variable control module of the memristor.

[0015] The above-mentioned memristor current output module includes a resistor R 11 、R 12 、R 13 、R 14 、R 15 、R 16 、R 17 、R 18 、R 19 、R 20 , op amp U 10 、U12 、U 13 , and the multiplier U 11 This module includes three input terminals, which are connected to the first voltage follower input terminal VM, the first voltage follower output terminal VMM and the second voltage follower output terminal P10V respectively; one output terminal: the memristor current output module output terminal VRR. The first voltage follower output terminal VMM is connected to the resistor R 11 With op amp U 10 The inverting input terminal of the operational amplifier U 10 The non-inverting input terminal is grounded and the output terminal is connected to the multiplier U 11 The multiplicand Y is the non-inverting input terminal Y1; the resistor R 12 One end is connected to the op amp U 10 The other end is connected to the inverting input of the multiplier U 11 The product output terminal W of the multiplier U 11 The multiplicand X is connected to the non-inverting input terminal X1 and the summing input terminal Z. The resistor R 13 One end is connected to the output terminal VRR of the memristor current output module, and the other end is connected to the first voltage follower input terminal VM; the output terminal VS-5 of the memristor internal variable control module is connected to the output terminal VRR of the memristor current output module, and the other end is connected to the first voltage follower input terminal VM; 15 With op amp U 12 The inverting input terminal is connected to the DC voltage source +5V through the resistor R 14 With op amp U 12 The inverting input terminal is connected to the resistor R 16 One end and op amp U 12 The other end is connected to the inverting input of the op amp U 12 The output end is connected to the resistor R 17 One end and op amp U 12 The inverting input terminal is connected to the op amp U 12 The output end of the op amp U 12 The non-inverting input terminal is grounded; the resistor R 18 One end and op amp U 12 The output end is connected to the op amp U 13 The second voltage follower output terminal P10V is connected to the inverting input terminal of 19 With op amp U 13 The inverting input terminal is connected to the resistor R 20 One end and op amp U 13 The other end is connected to the inverting input of the op amp U 13 The output end of the op amp U 13 The non-inverting input terminal is grounded, and the output terminal is connected to the multiplier U 11 The multiplicand X is inverting input terminal X2.

[0016] The above-mentioned memristor window function module includes a resistor R 21, op amp U 14 , and the multiplier U 15 、U 16 This module includes three input terminals, which are connected to the first voltage follower output terminal VMM, the memristor internal variable control module output terminal VS-5, and the second voltage follower output terminal P10V; one output terminal: the memristor window function output terminal VFS. The first voltage follower output terminal VMM is connected to the memristor window function through the resistor R 21 With op amp U 14 The inverting input terminal of the operational amplifier U 14 The non-inverting input terminal is grounded, and the output terminal is connected to the multiplier U 15 The inverting input terminal X2 of the multiplicand X is connected to the inverting input terminal Y2 of the multiplicand Y; the output terminal VS-5 of the internal variable control module of the memristor is connected to the multiplier U 15 The multiplicand X non-inverting input terminal X1 and the multiplicand Y non-inverting input terminal Y1 are connected; the multiplier U 15 The summing input Z is grounded, and the multiplier U 15 The product output W is connected to the multiplier U 16 The multiplicand X inverting input terminal X2 and the multiplicand Y non-inverting input terminal Y1; multiplier U 16 The multiplicand X's non-inverting input terminal X1 and the multiplicand Y's inverting input terminal Y2 are grounded, and the multiplier U 16 The product output terminal W is the output terminal VFS of the memristor window function module, and the multiplier U 16 The summing input terminal Z is connected to the second voltage follower output terminal P10V.

[0017] The amplitude and bias controllable phase-shifted memristor chaotic oscillator includes a controlled memristor M f , controlled memristor M f Including resistor R 22 、R 23 、R 24 、R 25 、R 26 、R 27 、R 28 、R 29 、R 30 、R 31 、R 32 、R 33 、R 34 , op amp U 17 、U 18 、U 19 、U 21 、U 22 , and the multiplier U 20 ; Contains three input terminals, connected to the controlled memristor V + End, controlled memristor V -The controlled memristor V + Terminal and op amp U 17 The non-inverting input terminal of the operational amplifier U 17 The inverting input terminal is connected to the output terminal, and the operational amplifier U 17 The output terminal is connected through the resistor R 22 With op amp U 18 The non-inverting input terminal is connected to the resistor R 23 One end and op amp U 18 The non-inverting input terminal is connected and the other end is grounded; the controlled memristor V - The resistor R 24 With op amp U 18 The inverting input terminal is connected to the resistor R 25 One end and op amp U 18 The other end is connected to the inverting input of the op amp U 18 The output end of the op amp U 18 The output terminal is connected through the resistor R 26 With op amp U 19 The inverting input terminal of the operational amplifier U 19 The non-inverting input terminal is grounded and the output terminal is connected to the multiplier U 20 The multiplicand Y is the non-inverting input terminal Y1; the resistor R 27 One end is connected to the op amp U 19 The other end is connected to the inverting input of the multiplier U 20 The product output terminal W of the multiplier U 20 The multiplicand X's non-inverting input terminal X1 and the summing input terminal Z are grounded; one end of the sliding resistor PR1 is connected to the operational amplifier U 19 The other end is connected to the output of the multiplier U 20 The multiplicand Y is the inverting input terminal Y2; the multiplier U 20 The multiplicand Y is input to the inverting terminal Y2 of the memristor V + The output terminal VS-5 of the internal variable control module of the memristor is connected to the resistor R 29 With op amp U 21 The inverting input terminal is connected to the DC voltage source +5V through the resistor R 28 With op amp U 21 The inverting input terminal is connected to the resistor R 30 One end and op amp U 21 The other end is connected to the inverting input of the op amp U 21 The output end is connected to the resistor R 31 One end and op amp U 21 The other end is connected to the inverting input of the op amp U 21 The output end of the op amp U 21 The non-inverting input terminal is grounded; the resistor R32 One end and op amp U 21 The output end is connected to the op amp U 22 The second voltage follower output terminal P10V is connected to the inverting input terminal of 33 With op amp U 22 The inverting input terminal is connected to the resistor R 34 One end and op amp U 22 The other end is connected to the inverting input of the op amp U 22 The output end of the op amp U 22 The non-inverting input terminal is grounded, and the output terminal is connected to the multiplier U 20 The multiplicand X is inverting input terminal X2.

[0018] Beneficial effects: Compared with the prior art, the technical solution of the present invention has the following beneficial technical effects:

[0019] A phase-shifted memristor chaotic oscillator with controllable amplitude and bias is designed based on the phase-shifted oscillator circuit framework. By introducing a memristor and a controlled memristor and designing an equivalent circuit, it outputs a chaotic signal with controllable bias and adjustable amplitude. The adjustable DC voltage source in the circuit effectively controls the bias of the chaotic signal. The phase-shifted memristor chaotic oscillator with controllable amplitude and bias has two independent bias control inputs, while the memristor parameters associated with the power supply voltage and the main op amp power supply voltage enable amplitude control of the chaotic signal. The designed oscillator offers flexibility in chaotic signal control, reduces the difficulty of circuit implementation and debugging, and facilitates the application of chaotic signals in electronics and information engineering. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 This is the schematic diagram of a phase-shifted memristive chaotic oscillator with controllable amplitude and bias.

[0021] Figure 2 It is the projection of the phase trajectory of the amplitude and bias controllable phase-shifted memristive chaotic oscillator on the phase plane.

[0022] Figure 3 It is the timing waveform of a phase-shifted memristive chaotic oscillator with controllable amplitude and bias.

[0023] Figure 4 It is the amplitude control of a phase-shifted memristive chaotic oscillator with controllable amplitude and bias.

[0024] Figure 5 It is the bias control of a phase-shifted memristive chaotic oscillator with controllable amplitude and bias.

[0025] Figure 6 The physical PCB layout of the amplitude and bias controllable phase-shifted memristive chaotic oscillator is compared with the actual oscilloscope. DETAILED DESCRIPTION

[0026] The technical solution of the present invention will be further described below with reference to the accompanying drawings and embodiments.

[0027] 1. Dynamic equations of a phase-shifted memristive chaotic oscillator with controllable amplitude and bias.

[0028] This system can be realized by using an equivalent circuit, such as Figure 1 As shown, (a) is the basic framework diagram, (b) is the equivalent circuit of the memristor M, and (c) is the controlled memristor M. f Equivalent circuit. For the sake of regularity, (b) and (c) both include a voltage follower. Let the voltages on the three capacitors C1, C2, and C3 be u1, u2, and u3, and the voltage at the output of the op amp be V, with an amplitude of ±V amp , then:

[0029]

[0030] When the parameters of the amplitude modulation and bias power supply are ignored and R1 is regarded as R, the specific circuit equation is converted into:

[0031]

[0032] The memristor model here is the HP memristor:

[0033]

[0034] The window function here is expressed as:

[0035]

[0036] Where a is a coefficient, the theoretical value is positive infinity, here it is 10 6 .

[0037] For a more general description, dimensionless normalization is performed here.

[0038] remember

[0039]

[0040] The memristance M is expressed as:

[0041] M=R on m(s) (6)

[0042] The controlled memristor M f Expressed as:

[0043] M f =R on m f (s) (7)

[0044] where m(s) is:

[0045] m(s)=s+α(1-s) (8)

[0046] where m f (s) is:

[0047] m f (s)=β+m(s) (9)

[0048] remember For unit voltage, multiply the first equation of equation group (2) by Multiply the second equation Multiply the third equation The fourth equation is multiplied by R off C3. The equation is as follows:

[0049]

[0050] Note that the parameter t0 = R off C3, ρ=k s v0C1.

[0051] Note variables

[0052] Remember Function

[0053]

[0054] Since tanh(ax) is used to determine polarity and the coefficient a is large enough, F1(s) can be rewritten as F2(s):

[0055]

[0056] Then the dimensionless equation of the system is:

[0057]

[0058] Where h is the formula (11), m(s) is the formula (8), and m f (s) is formula (9), and F2(s) is formula (12).

[0059] Select parameter a=10 6 , k s =10 4 , p=2, R on =100Ω, R off =10000Ω, C1=C2=C3=10 -4 F, V m=15V. Then α=100,β=10,γ=100,σ=100,ρ=5.625,v0=5.625V,t0=1s. When the bifurcation parameter is k=16 and the initial value is (1,0,0,0), the corresponding Les of the system is: (0.085,0.001,-1.578,8.382), D ky =2.055. The chaotic attractor output by the system is as follows: Figure 2 As shown: (a) is the y-(-z) plane diagram, (b) is the x-(-y) plane diagram; the corresponding time domain waveform is as follows Figure 3 shown.

[0060] Although from Figure 2 It is not difficult to find the elliptical periodic phase orbit of the traditional phase-shifted sine oscillator in the phase orbit diagram, but it is still affected by the memristor. The constant change of the oscillation frequency leads to the appearance of strange time domain waveforms and attractors. Figure 3 As can be seen, the system is highly sensitive to changes in the memristor. Changes in the slope, and particularly the polarity, of the internal variable s in the memristor cause sudden changes in the voltages of the three capacitors, resulting in spike-like oscillation behavior. Because this system is based on an oscillator, it is insensitive to initial values. If the initial value is too large, the limited output voltage of the op amp will cause the voltage to decay to the oscillation range. If the initial value is too small, the controlled memristor maintains a constant amplification factor, which will eventually amplify the voltage to the oscillation range.

[0061] 2. Amplitude and bias control.

[0062] When considering the amplitude modulation and bias power supply, the circuit equation is as follows:

[0063]

[0064] The window function F3(s) here is expressed as:

[0065]

[0066] in:

[0067]

[0068] Then V1 and V2 realize independent bias control, and V3 realizes global amplitude modulation. V1 and V2 are equivalent to adding DC current to the resistance R and memristor M of the circuit, such as Figure 1 As shown in (a); V3 is equivalent to changing the maximum output of the op amp while changing the rate of change of the memristor.

[0069] Normalize as above:

[0070]

[0071] in:

[0072]

[0073] Here m(s) is the formula (8), m f (s) is formula (9).

[0074] The window function F4(s) here is expressed as:

[0075]

[0076] The remaining constants are the same as above.

[0077] The relationship between parameters d1, d2, d3 and circuit power supply is: Then d1 and d2 realize independent bias control, and d3 realizes global amplitude modulation.

[0078] This example provides the following proof:

[0079] (1) Bias control of d1.

[0080] Let x→x-d1, y→y+d1, d2=0, d3=1, then system (17) becomes system (13), which means that the parameter d1 does not change the dynamic behavior of the system, but causes the variables x and y to be offset.

[0081] (2) Bias control of d2.

[0082] Let y→y-d2, z→z+d2, d1=0, d3=1, then system (17) becomes system (13), which means that the parameter d2 does not change the dynamic behavior of the system, but causes a bias in the variables y and z.

[0083] (3) Global amplitude modulation of d3.

[0084] Let x→x·d3, y→y·d3, z→z·d3, d1=0, d2=0, then system (17) becomes system (13), which means that the parameter d3 does not change the dynamic behavior of the system, but makes the amplitudes of variables x, y, and z change simultaneously and proportionally.

[0085] (4) Co-regulation of d1, d2 and d3.

[0086] Let x→x·d3-d1, y→y·d3+d1-d2, z→z·d3+d2, then system (17) becomes system (13), which means that the three parameters d1, d2, and d3 do not affect each other and can act simultaneously.

[0087] It's worth noting that in function h, parameter d3 and bifurcation parameter k are multiplicative. This means that for a given product, the value of parameter d3 is affected by the bifurcation parameter k. For ease of understanding, the bifurcation parameter k remains unchanged throughout the above proof, taking the value k = 16.

[0088] In order to better express the bias and amplitude modulation phenomena, the initial values of the system must also change accordingly when the parameters are changed.

[0089] like Figure 4 As shown, the left side is the xyz three-dimensional stereogram and the right side is the timing diagram x(t).

[0090] When the initial value is [d3,0,0,0], Figure 4 The two figures show how the parameter d3 scales the variables x, y, and z simultaneously. For reference, when d3 is 1: When d3 is 0.5, the 3D phase trajectory converges inward, halving the x-amplitude; when d3 is 2, the 3D phase trajectory expands outward, doubling the x-amplitude.

[0091] Figure 4 It shows the global amplitude modulation capability of the system.

[0092] like Figure 5 As shown, the upper left is x-(-y), the upper right is x(t); the lower left is y-(-z), and the lower right is y(t).

[0093] When the initial value is [1-d1,d1,0,0], Figure 5 The two figures above show how the parameter d1 shifts the x and y variables in opposite directions. For reference, when d1 is 0, a d1 of -5 shifts the x-(-y) phase trajectory upward and to the right, with the x magnitude shifting upward. A d1 of 5 shifts the x-(-y) phase trajectory downward and to the left, with the x magnitude shifting downward.

[0094] When the initial value is [1,-d2,d2,0], Figure 5 The two figures below demonstrate how the parameter d2 shifts the variables y and z in opposite directions. For reference, when d2 is 0, a d2 of -1 shifts the y-z phase trajectory upward and to the right, with the y magnitude shifting upward. A d2 of 1 shifts the y-z phase trajectory downward and to the left, with the y magnitude shifting downward.

[0095] Figure 5 It demonstrates the bias control capability of the system.

[0096] 3. Circuit implementation of a phase-shifted memristive chaotic oscillator with controllable amplitude and bias.

[0097] The physical PCB layout of the amplitude and bias controllable phase-shifted memristor chaotic oscillator is shown in the figure below. Figure 6As shown, (a1) is a real shot of the front side of the PCB, (a2) is a real shot of the back side of the PCB, (b1) is the y-(-z) phase trajectory diagram displayed by the actual oscilloscope, and (b2) is the x-(-y) diagram displayed by the actual oscilloscope.

[0098] The amplitude and bias controllable phase-shifted memristor chaotic oscillator is based on a phase-shifted oscillation circuit and introduces a memristor M and a controlled memristor M. f And realize.

[0099] The above-mentioned phase-shift oscillator circuit has a loop structure. The output of the main op amp U1 is connected to one end of the capacitor C1; the other end of the capacitor C1 is connected to one end of the capacitor C2, and the connection point leads to the first branch; the other end of the capacitor C2 is connected to one end of the capacitor C3, and the connection point leads to the second branch; the other end of the capacitor C3 is connected to the reverse input of the main op amp U1; the controlled memristor M f One end is denoted as V + Connected to the reverse input terminal of the main op amp U1, the other end is recorded as V - Connected to the output terminal of the main operational amplifier U1; the non-inverting input terminal of the main operational amplifier U1 is grounded; in the first branch, starting from the connection point, it is connected to the resistor R1 through the DC voltage source V1 and then grounded; in the second branch, starting from the connection point, it is connected to the memristor M through the connection terminal VM through the DC voltage source V2 and then grounded.

[0100] The amplitude- and bias-controllable phase-shifted memristor chaotic oscillator includes a memristor M, which consists of three modules and two voltage followers. The first module is the memristor internal variable control module; the second module is the memristor current output module; and the third module is the memristor window function module.

[0101] The four input terminals of the above-mentioned memristor internal variable control module are respectively connected to the output terminal VRR of the memristor current output module, the output terminal VMM of the first voltage follower, the output terminal VFS of the memristor window function module and the negative power supply VN of the main operational amplifier U1; the output terminal VS-5 of the memristor internal variable control module is connected to an input terminal of the memristor window function module.

[0102] The three input terminals of the above-mentioned memristor current output module are respectively connected to the first voltage follower input terminal VM, the first voltage follower output terminal VMM and the second voltage follower output terminal P10V; the output terminal VRR of the memristor current output module is connected to an input terminal of the memristor internal variable control module.

[0103] The three input terminals of the above-mentioned memristor window function module are respectively connected to the first voltage follower output terminal VMM, the memristor internal variable control module output terminal VS-5, and the second voltage follower output terminal P10V; the output terminal VFS of the memristor window function module is connected to an input terminal of the memristor internal variable control module.

[0104] The first voltage follower is connected to the first voltage follower input terminal VM via the non-inverting input terminal of the operational amplifier U2 and is connected to the first voltage follower output terminal VMM via the inverting input terminal of the operational amplifier U2.

[0105] The second voltage follower above connects the DC voltage source +15V through the resistor R 35 With op amp U 23 The non-inverting input terminal is connected to the op amp U 23 The non-inverting input is connected through the resistor R 36 Grounded at the back; op amp U 23 The inverting input terminal is connected to the output terminal, and the operational amplifier U 23 The output end of is the second voltage follower output end P10V.

[0106] The above-mentioned memristor internal variable control module includes resistors R2, R3, R4, R5, R6, R7, R8, R9, R 10 , operational amplifiers U4, U5, U7, U8, U9, and multipliers U3, U6; this module contains four input terminals, which are respectively connected to the output terminal VRR of the memristor current output module, the output terminal VMM of the first voltage follower, the output terminal VFS of the memristor window function and the negative power supply VN of the main operational amplifier U1, and one output terminal: the output terminal VS-5 of the memristor internal variable control module. Three of the input terminals are on the multiplier U3; the multiplicand X non-inverting input terminal X1 of the multiplier U3 is connected to the output terminal VRR of the memristor current output module, the multiplicand X inverting input terminal X2 is connected to the output terminal VMM of the first voltage follower, the multiplicand Y non-inverting input terminal Y1 is connected to the output terminal VFS of the memristor window function module, the multiplicand Y inverting input terminal Y2 is grounded, the summing input terminal Z is grounded, and its product output terminal W is connected to the inverting input terminal of the operational amplifier U5 through the resistor R3; the non-inverting input terminal of the operational amplifier U5 is grounded, and the output terminal is connected to the multiplicand Y inverting input terminal Y2 of the multiplier U6; one end of the resistor R4 is connected to the inverting input terminal of the operational amplifier U5, and the other end is connected to the product output terminal W of the multiplier U6; the multiplicand X non-inverting input terminal X1, the multiplicand Y non-inverting input terminal Y1 and the summing input terminal Z of the multiplier U6 are grounded; the DC voltage source +5V is connected to the resistor R 10Connected to the non-inverting input of the operational amplifier U9; the non-inverting input of the operational amplifier U9 is grounded after passing through the sliding variable resistor PR2, and the inverting input of the operational amplifier U9 is connected to the output; one end of the resistor R6 is connected to the output of the operational amplifier U9, and the other end is connected to the inverting input of the operational amplifier U7; the negative power supply VN of the main operational amplifier U1 is connected to the inverting input of the operational amplifier U7 through the resistor R5; one end of the resistor R7 is connected to the inverting input of the operational amplifier U7, and the other end is connected to the output of the operational amplifier U7; the non-inverting input of the operational amplifier U7 is grounded, and the output is connected to the inverting input Y2 of the multiplicand Y of the multiplier U6; the resistor R8 One end of is connected to the inverting input terminal X2 of the multiplicand X of the multiplier U6, and the other end is connected to the inverting input terminal of the operational amplifier U8; one end of the resistor R9 is connected to the inverting input terminal of the operational amplifier U8, and the other end is connected to the output terminal of the operational amplifier U8; the non-inverting input terminal of the operational amplifier U8 is grounded; the output terminal of the operational amplifier U8 is connected to the inverting input terminal of the operational amplifier U4 through the resistor R2; one end of the capacitor C4 is connected to the inverting input terminal of the operational amplifier U4, and the other end is connected to the output terminal of the operational amplifier U4; the non-inverting input terminal of the operational amplifier U4 is grounded, and its output terminal is the output terminal VS-5 of the internal variable control module of the memristor.

[0107] The above-mentioned memristor current output module includes a resistor R 11 、R 12 、R 13 、R 14 、R 15 、R 16 、R 17 、R 18 、R 19 、R 20 , op amp U 10 、U 12 、U 13 , and the multiplier U 11 ; It includes three input terminals, which are respectively connected to the first voltage follower input terminal VM, the first voltage follower output terminal VMM and the second voltage follower output terminal P10V; one output terminal: the memristor current output module output terminal VRR. The first voltage follower output terminal VMM is connected to the resistor R 11 With op amp U 10 The inverting input terminal of the operational amplifier U 10 The non-inverting input terminal is grounded and the output terminal is connected to the multiplier U 11 The multiplicand Y is the non-inverting input terminal Y1; the resistor R 12 One end is connected to the op amp U 10 The other end is connected to the inverting input of the multiplier U 11 The product output terminal W of the multiplier U 11 The multiplicand X is connected to the non-inverting input terminal X1 and the summing input terminal Z. The resistor R 13One end is connected to the output terminal VRR of the memristor current output module, and the other end is connected to the first voltage follower input terminal VM; the output terminal VS-5 of the memristor internal variable control module is connected to the output terminal VRR of the memristor current output module, and the other end is connected to the first voltage follower input terminal VM; 15 With op amp U 12 The inverting input terminal is connected to the DC voltage source +5V through the resistor R 14 With op amp U 12 The inverting input terminal is connected to the resistor R 16 One end and op amp U 12 The other end is connected to the inverting input of the op amp U 12 The output end is connected to the resistor R 17 One end and op amp U 12 The other end is connected to the inverting input of the op amp U 12 The output end of the op amp U 12 The non-inverting input terminal is grounded; the resistor R 18 One end and op amp U 12 The output end is connected to the op amp U 13 The second voltage follower output terminal P10V is connected to the inverting input terminal of 19 With op amp U 13 The inverting input terminal is connected to the resistor R 20 One end and op amp U 13 The other end is connected to the inverting input of the op amp U 13 The output end of the op amp U 13 The non-inverting input terminal is grounded, and the output terminal is connected to the multiplier U 11 The multiplicand X is inverting input terminal X2.

[0108] The above-mentioned memristor window function module includes a resistor R 21 , op amp U 14 , and the multiplier U 15 、U 16 This module includes three input terminals, which are connected to the first voltage follower output terminal VMM, the memristor internal variable control module output terminal VS-5, and the second voltage follower output terminal P10V; one output terminal: the memristor window function output terminal VFS. The first voltage follower output terminal VMM is connected to the memristor window function through the resistor R 21 With op amp U 14 The inverting input terminal of the operational amplifier U 14 The non-inverting input terminal is grounded, and the output terminal is connected to the multiplier U 15 The inverting input terminal X2 of the multiplicand X is connected to the inverting input terminal Y2 of the multiplicand Y; the output terminal VS-5 of the internal variable control module of the memristor is connected to the multiplier U 15 The multiplicand X non-inverting input terminal X1 and the multiplicand Y non-inverting input terminal Y1 are connected; the multiplier U 15 The summing input Z is grounded, and the multiplier U 15The product output W is connected to the multiplier U 16 The multiplicand X inverting input terminal X2 and the multiplicand Y non-inverting input terminal Y1; multiplier U 16 The multiplicand X's non-inverting input terminal X1 and the multiplicand Y's inverting input terminal Y2 are grounded, and the multiplier U 16 The product output terminal W is the output terminal VFS of the memristor window function module, and the multiplier U 16 The summing input terminal Z is connected to the second voltage follower output terminal P10V.

[0109] The amplitude and bias controllable phase-shifted memristor chaotic oscillator includes a controlled memristor M f , controlled memristor M f Including resistor R 22 、R 23 、R 24 、R 25 、R 26 、R 27 、R 28 、R 29 、R 30 、R 31 、R 32 、R 33 、R 34 , op amp U 17 、U 18 、U 19 、U 21 、U 22 , and the multiplier U 20 ; Contains three input terminals, connected to the controlled memristor V + End, controlled memristor V - The controlled memristor V + Terminal and op amp U 17 The non-inverting input terminal of the operational amplifier U 17 The inverting input terminal is connected to the output terminal, and the operational amplifier U 17 The output terminal is connected through the resistor R 22 With op amp U 18 The non-inverting input terminal is connected to the resistor R 23 One end and op amp U 18 The non-inverting input terminal is connected and the other end is grounded; the controlled memristor V - The resistor R 24 With op amp U 18 The inverting input terminal is connected to the resistor R 25 One end and op amp U 18 The other end is connected to the inverting input of the op amp U 18 The output end of the op amp U 18 The output terminal is connected through the resistor R26 With op amp U 19 The inverting input terminal of the operational amplifier U 19 The non-inverting input terminal is grounded and the output terminal is connected to the multiplier U 20 The multiplicand Y is the non-inverting input terminal Y1; the resistor R 27 One end is connected to the op amp U 19 The other end is connected to the inverting input of the multiplier U 20 The product output terminal W of the multiplier U 20 The multiplicand X's non-inverting input terminal X1 and the summing input terminal Z are grounded; one end of the sliding resistor PR1 is connected to the operational amplifier U 19 The other end is connected to the output of the multiplier U 20 The multiplicand Y is the inverting input terminal Y2; the multiplier U 20 The multiplicand Y is input to the inverting terminal Y2 of the memristor V + The output terminal VS-5 of the internal variable control module of the memristor is connected to the resistor R 29 With op amp U 21 The inverting input terminal is connected to the DC voltage source +5V through the resistor R 28 With op amp U 21 The inverting input terminal is connected to the resistor R 30 One end and op amp U 21 The other end is connected to the inverting input of the op amp U 21 The output end is connected to the resistor R 31 One end and op amp U 21 The other end is connected to the inverting input of the op amp U 21 The output end of the op amp U 21 The non-inverting input terminal is grounded; the resistor R 32 One end and op amp U 21 The output end is connected to the op amp U 22 The second voltage follower output terminal P10V is connected to the inverting input terminal of 33 With op amp U 22 The inverting input terminal is connected to the resistor R 34 One end and op amp U 22 The other end is connected to the inverting input of the op amp U 22 The output end of the op amp U 22 The non-inverting input terminal is grounded, and the output terminal is connected to the multiplier U 20 The multiplicand X is inverting input terminal X2.

[0110] Special note, op amp U4 and U 14The op amp is powered by ±5V. There are no specific requirements for the other components. In this embodiment, the ±5V op amp is the OP262, the other op amps are the ±15V ADA4000, and the multiplier is the AD633. Other similar components can be substituted; component selection is not essential.

Claims

1. A phase-shifted memristive chaotic oscillator with controllable amplitude and bias, characterized by: The oscillator comprises a phase-shift oscillation circuit, an equivalent memristor M and a controlled memristor M f ; The phase-shift oscillator circuit has a loop circuit structure; Among them, the output end of the main operational amplifier U1 is connected to one end of the capacitor C1; the other end of the capacitor C1 is connected to one end of the capacitor C2, and the connection point leads to the first branch; the other end of the capacitor C2 is connected to one end of the capacitor C3, and the connection point leads to the second branch; the other end of the capacitor C3 is connected to the reverse input end of the main operational amplifier U1; The controlled memristor M f One end is denoted as V + Connected to the reverse input terminal of the main op amp U1, the other end is recorded as V - Connected to the output terminal of the main operational amplifier U1; the same-direction input terminal of the main operational amplifier U1 is grounded; In the first branch, starting from the connection point, a DC voltage source V1 is connected to the resistor R1 and then to ground. In the second branch, starting from the connection point, a DC voltage source V2 is connected to the equivalent memristor M via the connection terminal VM and then to ground. The equivalent memristor M comprises an equivalent memristor internal variable control module, a memristor current output module, an equivalent memristor window function module and two voltage followers; The four input terminals of the equivalent memristor internal variable control module are respectively connected to the output terminal VRR of the memristor current output module, the output terminal VMM of the first voltage follower, the output terminal VFS of the equivalent memristor window function module and the negative power supply VN of the main operational amplifier U1; the output terminal VS-5 of the equivalent memristor internal variable control module is connected to an input terminal of the equivalent memristor window function module; The three input terminals of the memristor current output module are respectively connected to the first voltage follower input terminal VM, the first voltage follower output terminal VMM and the second voltage follower output terminal P10V; the output terminal VRR of the memristor current output module is connected to an input terminal of the equivalent memristor internal variable control module; The three input terminals of the equivalent memristor window function module are respectively connected to the first voltage follower output terminal VMM, the output terminal VS-5 of the equivalent memristor internal variable control module, and the second voltage follower output terminal P10V; the output terminal VFS of the equivalent memristor window function module is connected to an input terminal of the equivalent memristor internal variable control module; The first voltage follower is connected to the first voltage follower input terminal VM through the non-inverting input terminal of the operational amplifier U2, and is connected to the first voltage follower output terminal VMM through the inverting input terminal of the operational amplifier U2; The second voltage follower connects the DC voltage source +15V through the resistor R 35 With op amp U 23 The non-inverting input terminal is connected to the op amp U 23 The non-inverting input is connected through the resistor R 36 Grounded at the back; op amp U 23 The inverting input terminal is connected to the output terminal, and the operational amplifier U 23 The output end is the second voltage follower output end P10V; The equivalent memristor internal variable control module includes resistors R2, R3, R4, R5, R6, R7, R8, R9, R 10 , op amps U4, U5, U7, U8, U9, and multipliers U3, U6; The multiplicand X non-inverting input terminal X1 of the multiplier U3 is connected to the output terminal VRR of the memristor current output module, the multiplicand X inverting input terminal X2 is connected to the output terminal VMM of the first voltage follower, the multiplicand Y non-inverting input terminal Y1 is connected to the output terminal VFS of the equivalent memristor window function module, the multiplicand Y inverting input terminal Y2 is grounded, the summation input terminal Z is grounded, and the product output terminal W is connected to the inverting input terminal of the operational amplifier U5 through the resistor R3; The non-inverting input terminal of the operational amplifier U5 is grounded, and the output terminal is connected to the inverting input terminal Y2 of the multiplicand Y of the multiplier U6; one end of the resistor R4 is connected to the inverting input terminal of the operational amplifier U5, and the other end is connected to the product output terminal W of the multiplier U6; the non-inverting input terminal X1 of the multiplicand X, the non-inverting input terminal Y1 of the multiplicand Y, and the summing input terminal Z of the multiplier U6 are grounded; A DC voltage source of +5V is applied through the resistor R 10 Connected to the non-inverting input terminal of the operational amplifier U9; the non-inverting input terminal of the operational amplifier U9 is grounded after passing through the sliding variable resistor PR2, and the inverting input terminal of the operational amplifier U9 is connected to the output terminal; One end of the resistor R6 is connected to the output terminal of the operational amplifier U9, and the other end is connected to the inverting input terminal of the operational amplifier U7; the negative power supply VN of the main operational amplifier U1 is connected to the inverting input terminal of the operational amplifier U7 through the resistor R5; One end of the resistor R7 is connected to the inverting input terminal of the operational amplifier U7, and the other end is connected to the output terminal of the operational amplifier U7; the non-inverting input terminal of the operational amplifier U7 is grounded, and the output terminal is connected to the inverting input terminal Y2 of the multiplicand Y of the multiplier U6; One end of the resistor R8 is connected to the inverting input terminal X2 of the multiplicand X of the multiplier U6, and the other end is connected to the inverting input terminal of the operational amplifier U8; one end of the resistor R9 is connected to the inverting input terminal of the operational amplifier U8, and the other end is connected to the output terminal of the operational amplifier U8; The non-inverting input terminal of the operational amplifier U8 is grounded; the output terminal of the operational amplifier U8 is connected to the inverting input terminal of the operational amplifier U4 through the resistor R2; one end of the capacitor C4 is connected to the inverting input terminal of the operational amplifier U4, and the other end is connected to the output terminal of the operational amplifier U4; The non-inverting input terminal of the operational amplifier U4 is grounded, and its output terminal is the output terminal VS-5 of the equivalent memristor internal variable control module; The memristor current output module includes a resistor R 11 、R 12 、R 13 、R 14 、R 15 、R 16 、R 17 、R 18 、R 19 、R 20 , op amp U 10 、U 12 、U 13 , and the multiplier U 11 ; The first voltage follower output terminal VMM is connected to the resistor R 11 With op amp U 10 The inverting input terminal of the operational amplifier U 10 The non-inverting input terminal is grounded and the output terminal is connected to the multiplier U 11 The multiplicand Y is at the non-inverting input terminal Y1; Resistor R 12 One end is connected to the op amp U 10 The other end is connected to the inverting input of the multiplier U 11 The product output terminal W of the multiplier U 11 The multiplicand X is connected to the non-inverting input terminal X1 and the summing input terminal Z. The resistor R 13 One end is connected to the output terminal VRR of the memristor current output module, and the other end is connected to the input terminal VM of the first voltage follower; The output terminal VS-5 of the equivalent memristor internal variable control module is connected to the resistor R 15 With op amp U 12 The inverting input terminal is connected to the DC voltage source +5V through the resistor R 14 With op amp U 12 The inverting input terminal is connected to the resistor R 16 One end and op amp U 12 The other end is connected to the inverting input of the op amp U 12 The output end is connected to the resistor R 17 One end and op amp U 12 The other end is connected to the inverting input of the op amp U 12 The output end of the op amp U 12 The non-inverting input terminal is grounded; Resistor R 18 One end and op amp U 12 The output end is connected to the op amp U 13 The second voltage follower output terminal P10V is connected to the inverting input terminal of the resistor R 19 With op amp U 13 The inverting input terminal is connected to the resistor R 20 One end and op amp U 13 The other end is connected to the inverting input of the op amp U 13 The output end of the op amp U 13 The non-inverting input terminal is grounded, and the output terminal is connected to the multiplier U 11 The multiplicand X is the inverting input terminal X2; The equivalent memristor window function module includes a resistor R 21 , op amp U 14 , and the multiplier U 15 、U 16 ; The first voltage follower output terminal VMM is connected to the resistor R 21 With op amp U 14 The inverting input terminal of the operational amplifier U 14 The non-inverting input terminal is grounded, and the output terminal is connected to the multiplier U 15 The multiplicand X inverting input terminal X2 is connected to the multiplicand Y inverting input terminal Y2; The output terminal VS-5 of the equivalent memristor internal variable control module and the multiplier U 15 The multiplicand X non-inverting input terminal X1 and the multiplicand Y non-inverting input terminal Y1 are connected; Multiplier U 15 The summing input Z is grounded, and the multiplier U 15 The product output W is connected to the multiplier U 16 The multiplicand X inverting input terminal X2 and the multiplicand Y non-inverting input terminal Y1; Multiplier U 16 The multiplicand X's non-inverting input terminal X1 and the multiplicand Y's inverting input terminal Y2 are grounded, and the multiplier U 16 The product output terminal W is the output terminal VFS of the equivalent memristor window function module, and the multiplier U 16 The summing input terminal Z is connected to the second voltage follower output terminal P10V; The controlled memristor M f Including resistor R 22 、R 23 、R 24 、R 25 、R 26 、R 27 、R 28 、R 29 、R 30 、R 31 、R 32 、R 33 、R 34 , op amp U 17 、U 18 、U 19 、U 21 、U 22 , and the multiplier U 20 ; The equivalent memristor M is expressed as: M = R on m(s), m(s)=s+α(1-s), Controlled Memristor M f Expressed as: M f =R on m f (s), m f (s)=β+m(s), R=R1, Controlled Memristor V + Terminal and op amp U 17 The non-inverting input terminal of the operational amplifier U 17 The inverting input terminal is connected to the output terminal, and the operational amplifier U 17 The output terminal is connected through the resistor R 22 With op amp U 18 The non-inverting input terminal of Resistor R 23 One end and op amp U 18 The non-inverting input terminal is connected and the other end is grounded; the controlled memristor V - The resistor R 24 With op amp U 18 The inverting input terminal of is connected; Resistor R 25 One end and op amp U 18 The other end is connected to the inverting input of the op amp U 18 The output end of the op amp U 18 The output terminal is connected through the resistor R 26 With op amp U 19 The inverting input terminal of is connected; Op amp U 19 The non-inverting input terminal is grounded and the output terminal is connected to the multiplier U 20 The multiplicand Y is the non-inverting input terminal Y1; the resistor R 27 One end is connected to the op amp U 19 The other end is connected to the inverting input of the multiplier U 20 The product output terminal W of the multiplier U 20 The multiplicand X's non-inverting input terminal X1 and the summing input terminal Z are grounded; One end of the sliding resistor PR1 is connected to the op amp U 19 The other end is connected to the output of the multiplier U 20 The multiplicand Y is the inverting input terminal Y2; the multiplier U 20 The multiplicand Y is input to the inverting terminal Y2 of the memristor V + end; The output terminal VS-5 of the equivalent memristor internal variable control module is connected to the resistor R 29 With op amp U 21 The inverting input terminal is connected to the DC voltage source +5V through the resistor R 28 With op amp U 21 The inverting input terminal of is connected; Resistor R 30 One end and op amp U 21 The other end is connected to the inverting input of the op amp U 21 The output end is connected to the resistor R 31 One end and op amp U 21 The other end is connected to the inverting input of the op amp U 21 The output end of the op amp U 21 The non-inverting input terminal is grounded; Resistor R 32 One end and op amp U 21 The output end is connected to the op amp U 22 The second voltage follower output terminal P10V is connected to the inverting input terminal of the resistor R 33 With op amp U 22 The inverting input terminal is connected to the resistor R 34 One end and op amp U 22 The other end is connected to the inverting input of the op amp U 22 The output terminal is connected to Op amp U 22 The non-inverting input terminal is grounded, and the output terminal is connected to the multiplier U 20 The multiplicand X is inverting input terminal X2.

Images