High reliability one-way transmission method, device, equipment and storage medium

Abstract

The present invention discloses a high-reliability unidirectional transmission method, device, equipment and storage medium, the method comprising: when the target data is obtained through the PCIE interface, sending a data storage instruction to the DDR memory based on the FPGA master control; creating a storage queue in the DDR memory according to the data storage instruction, and putting the target data into the storage queue; verifying the target data in the storage queue according to a preset method to generate a check value; after encapsulating the check value and the target data in the storage queue, obtaining the encapsulated data, and sending the encapsulated data to a receiving device through a SATA interface, the receiving device verifies the received encapsulated data, obtains the target check value, and judges whether the data verification is successful according to the check value and the target check value. Since the present invention realizes the sending and receiving verification of data unidirectional transmission, compared with the prior art, the present invention effectively improves the security and reliability of unidirectional transmission.

Description

Technical Field

[0001] The present invention relates to the technical field of data transmission, and in particular to a high-reliability one-way transmission method, device, equipment and storage medium. Background Art

[0002] The network unidirectional import product is generally composed of dual hosts plus unidirectional transmission components, namely, data sending processing unit, data receiving processing unit and unidirectional transmission component. The network unidirectional import product is deployed between two different security domains. Among them, the network interface of the data sending processing unit is connected to the information sender security domain A, and the network interface of the data receiving processing unit is connected to the information receiver security domain B. The information flow flows unidirectionally from the security domain A that sends data to the security domain B that receives data. The unidirectional transmission component uses the physical characteristics of unidirectional transmission to establish the only unidirectional transmission channel between the two security domains. In this channel, data can only be transmitted unidirectionally from the data sending processing unit to the data receiving processing unit. The unidirectional transmission component consists of a pair of unidirectional receiving components and a unidirectional sending component. The unidirectional sending component is installed in the data sending processing unit, and the unidirectional receiving component is installed in the data receiving processing unit. The unidirectional physical transmission characteristics of the unidirectional transmission component are fixed and cannot be modified. Any software configuration, physical jumper, etc. cannot change the unidirectional transmission characteristics and transmission direction of its components, thereby achieving the reliability of unidirectional data import.

[0003] Currently, one-way import components are generally completed using fiber optic network cards that physically shield the receiving or sending channels. However, the use of general network chips has the disadvantages of being unable to implement data verification in one-way transmission scenarios, being unreliable, and being unable to guarantee security.

[0004] Therefore, there is an urgent need for a high-reliability one-way transmission method that can effectively solve the technical problem of how to improve the security and reliability of one-way transmission. Summary of the invention

[0005] The main purpose of the present invention is to provide a high-reliability one-way transmission method, device, equipment and storage medium, aiming to solve the technical problem of how to improve the security and reliability of one-way transmission.

[0006] To achieve the above object, the present invention provides a high-reliability unidirectional transmission method, which is applied to a sending device, wherein the sending device includes: a PCIE interface, an FPGA master control, a DDR memory, and a SATA interface. The high-reliability unidirectional transmission method includes:

[0007] When the target data is acquired through the PCIE interface, a data storage instruction is sent to the DDR memory based on the FPGA master control;

[0008] Creating a storage queue in the DDR memory according to the data storage instruction, and placing the target data into the storage queue;

[0009] Verify the target data in the storage queue according to a preset method to generate a verification value;

[0010] After encapsulating the check value and the target data in the storage queue, the encapsulated data is obtained, and the encapsulated data is sent to a receiving device through the SATA interface. The receiving device verifies the received encapsulated data to obtain a target check value, and determines whether the data verification is successful based on the check value and the target check value.

[0011] Optionally, the storage queue is a circular first-in-first-out queue, and the step of creating a storage queue in the DDR memory according to the data storage instruction and placing the target data into the storage queue includes:

[0012] Creating a circular first-in-first-out queue in the DDR memory according to the data storage instruction, wherein each queue block in the circular first-in-first-out queue stores data of preset bytes;

[0013] The target data is sequentially placed into each queue block of the circular first-in-first-out queue according to preset bytes.

[0014] Optionally, the step of verifying the target data in the storage queue according to a preset method to generate a verification value includes:

[0015] Divide the target data in the circular FIFO queue according to a preset division rule to obtain target sub-data;

[0016] Verifying the target sub-data in sequence according to a preset method to obtain verification values ​​corresponding to each target sub-data;

[0017] Correspondingly, the step of obtaining encapsulated data after encapsulating the check value and the target data in the storage queue includes:

[0018] Each queue block corresponding to each target sub-data is sequentially encapsulated with the check value corresponding to each target sub-data to obtain encapsulated data.

[0019] In addition, to achieve the above-mentioned purpose, the present invention also provides a high-reliability unidirectional transmission method, which is applied to a receiving device, wherein the receiving device includes a PCIE interface, an FPGA master control, a DDR memory, and a SATA interface. The high-reliability unidirectional transmission method includes:

[0020] When receiving preset target data sent by a sending device through the SATA interface, sending a data storage instruction to the DDR memory based on the FPGA master control, the preset target data includes data information and a check value corresponding to the data information;

[0021] Creating a storage queue in the DDR memory according to the data storage instruction, and placing the preset target data into the storage queue in sequence;

[0022] Verify the preset target data in the storage queue according to a preset method to generate a target verification value;

[0023] Determining whether the data verification is successful according to the target verification value and the verification value;

[0024] If the data verification is successful, the preset target data is uploaded to the upper layer application through the PCIE interface.

[0025] Optionally, the step of creating a storage queue in the DDR memory according to the data storage instruction and sequentially placing the preset target data into the storage queue includes:

[0026] Creating a storage queue in the DDR memory according to the data storage instruction, wherein the storage queue is a circular first-in-first-out queue, and the circular first-in-first-out queue includes a plurality of queue blocks;

[0027] Putting the preset target data into the queue blocks of the storage queue in sequence;

[0028] Correspondingly, the step of verifying the preset target data in the storage queue according to a preset method to generate a target verification value includes:

[0029] When the preset target data of the preset threshold is received, the preset target data of the preset threshold in the storage queue is verified to obtain a target verification value.

[0030] Optionally, after judging whether the data verification is successful according to the target verification value and the verification value, the method further includes:

[0031] If the data verification fails, the verification failure information is fed back to the sending device through the FPGA master control, so that the sending device sends a subsequent message according to the verification failure information.

[0032] In addition, to achieve the above-mentioned purpose, the present invention further proposes a high-reliability unidirectional transmission device, which is applied to a sending device, and the sending device includes: a PCIE interface, an FPGA master control, a DDR memory and a SATA interface, and the high-reliability unidirectional transmission device includes:

[0033] A data acquisition module, configured to send a data storage instruction to the DDR memory based on the FPGA master control when the target data is acquired through the PCIE interface;

[0034] A data storage module, used for creating a storage queue in the DDR memory according to the data storage instruction, and putting the target data into the storage queue;

[0035] A data verification module, used to verify the target data in the storage queue according to a preset method and generate a verification value;

[0036] A data sending module is used to encapsulate the check value and the target data in the storage queue to obtain encapsulated data, and send the encapsulated data to a receiving device through the SATA interface. The receiving device verifies the received encapsulated data to obtain a target check value, and determines whether the data verification is successful based on the check value and the target check value.

[0037] In addition, to achieve the above-mentioned purpose, the present invention further proposes a high-reliability unidirectional transmission device, which is applied to a receiving device, and the receiving device includes a PCIE interface, an FPGA master control, a DDR memory and a SATA interface, and the high-reliability unidirectional transmission device includes:

[0038] A data receiving module, configured to send a data storage instruction to the DDR memory based on the FPGA master control when receiving preset target data sent by the sending device through the SATA interface, wherein the preset target data includes data information and a check value corresponding to the data information;

[0039] A data storage module, used for creating a storage queue in the DDR memory according to the data storage instruction, and placing the preset target data into the storage queue in sequence;

[0040] A data verification module, used to verify the preset target data in the storage queue according to a preset method and generate a target verification value;

[0041] A verification judgment module, used to judge whether the data verification is successful according to the target verification value and the verification value;

[0042] The data upload module is used to upload the preset target data to the upper layer application through the PCIE interface if the data verification is successful.

[0043] In addition, to achieve the above-mentioned objectives, the present invention also proposes a high-reliability unidirectional transmission device, which includes: a memory, a processor, and a high-reliability unidirectional transmission program stored in the memory and executable on the processor, wherein the high-reliability unidirectional transmission program is configured to implement the steps of the high-reliability unidirectional transmission method described above.

[0044] In addition, to achieve the above objectives, the present invention also proposes a storage medium, on which a high-reliability one-way transmission program is stored, and when the high-reliability one-way transmission program is executed by a processor, the steps of the high-reliability one-way transmission method described above are implemented.

[0045] The present invention discloses a high-reliability unidirectional transmission method, device, equipment and storage medium, the method comprising: when the target data is obtained through the PCIE interface, sending a data storage instruction to the DDR memory based on the FPGA master control; creating a storage queue in the DDR memory according to the data storage instruction, and putting the target data into the storage queue; verifying the target data in the storage queue according to a preset method to generate a check value; after encapsulating the check value and the target data in the storage queue, obtaining encapsulated data, and sending the encapsulated data to a receiving device through the SATA interface, the receiving device verifies the received encapsulated data to obtain a target check value, and judges whether the data verification is successful according to the check value and the target check value. Since the present invention puts the target data into the storage queue, then verifies the target data in the storage queue according to a preset method to generate a check value, then encapsulates the check value and the target data in the storage queue to obtain encapsulated data, and sends the encapsulated data to the receiving device through the SATA interface, compared with the prior art, the present invention realizes the sending and receiving verification of data unidirectional transmission, and improves the security and reliability of unidirectional transmission. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 It is a structural schematic diagram of a high-reliability unidirectional transmission device in a hardware operating environment involved in an embodiment of the present invention;

[0047] Figure 2 It is a flowchart of a first embodiment of a high reliability one-way transmission method of the present invention;

[0048] Figure 3 It is a flowchart of a second embodiment of a high reliability one-way transmission method of the present invention;

[0049] Figure 4 This is a schematic diagram of a specific implementation scenario of the high-reliability one-way transmission method of the present invention;

[0050] Figure 5It is a schematic diagram of the overall process of the high-reliability one-way transmission method of the present invention;

[0051] Figure 6 It is a structural block diagram of a first embodiment of a high reliability one-way transmission device of the present invention;

[0052] Figure 7 It is a structural block diagram of the second embodiment of the high reliability unidirectional transmission device of the present invention.

[0053] The realization of the purpose, functional features and advantages of the present invention will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0054] It should be understood that the specific embodiments described herein are only used to explain the present invention, and are not used to limit the present invention.

[0055] Reference Figure 1 , Figure 1 It is a schematic diagram of the structure of a high-reliability unidirectional transmission device in the hardware operating environment involved in the embodiment of the present invention.

[0056] like Figure 1 As shown, the high-reliability unidirectional transmission device may include: a processor 1001, such as a central processing unit (CPU), a communication bus 1002, a user interface 1003, a network interface 1004, and a memory 1005. Among them, the communication bus 1002 is used to realize the connection and communication between these components. The user interface 1003 may include a display screen (Display), an input unit such as a keyboard (Keyboard), and the optional user interface 1003 may also include a standard wired interface and a wireless interface. The network interface 1004 may optionally include a standard wired interface and a wireless interface (such as a wireless fidelity (Wireless-Fidelity, WI-FI) interface). The memory 1005 may be a high-speed random access memory (Random Access Memory, RAM), or a stable non-volatile memory (Non-Volatile Memory, NVM), such as a disk storage. The memory 1005 may also be a storage device independent of the aforementioned processor 1001.

[0057] Those skilled in the art will understand that Figure 1 The structure shown in the figure does not constitute a limitation on the high-reliability unidirectional transmission device, and may include more or less components than those shown in the figure, or combine certain components, or arrange the components differently.

[0058] like Figure 1As shown, the memory 1005 as a storage medium may include an operating system, a network communication module, a user interface module, and a high-reliability one-way transmission program.

[0059] exist Figure 1 In the high-reliability unidirectional transmission device shown, the network interface 1004 is mainly used for data communication with the network server; the user interface 1003 is mainly used for data interaction with the user; the processor 1001 and the memory 1005 in the high-reliability unidirectional transmission device of the present invention can be set in the high-reliability unidirectional transmission device, and the high-reliability unidirectional transmission device calls the high-reliability unidirectional transmission program stored in the memory 1005 through the processor 1001, and executes the high-reliability unidirectional transmission method provided by the embodiment of the present invention.

[0060] The embodiment of the present invention provides a high reliability one-way transmission method, referring to Figure 2 , Figure 2 FIG. 4 is a flow chart of a first embodiment of a high-reliability unidirectional transmission method according to the present invention.

[0061] In this embodiment, the high-reliability unidirectional transmission method is applied to a sending device, the sending device includes: a PCIE interface, an FPGA master control, a DDR memory and a SATA interface, and the high-reliability unidirectional transmission method includes the following steps:

[0062] Step S10: When the target data is acquired through the PCIE interface, a data storage instruction is sent to the DDR memory based on the FPGA master control.

[0063] It should be noted that the execution subject of this embodiment may be a sending device in a one-way data transmission scenario. The one-way data transmission scenario includes a sending device and a receiving device.

[0064] It should be understood that the PCIE interface uses different physical channels and data lines to transmit data, wherein each channel can support multiple data lines, thereby achieving higher bandwidth.

[0065] FPGA (Field-Programmable Gate Array) is a product that is further developed on the basis of programmable devices such as PAL, GAL, CPLD, etc. It is a semi-customized circuit in the field of application-specific integrated circuits (ASICs), which not only solves the shortcomings of customized circuits, but also overcomes the shortcomings of the limited number of gate circuits of the original programmable devices. Users can develop skill circuits with unique functions based on their own needs and apply them.

[0066] The SATA interface uses serial data transmission technology, in which data is transmitted bit by bit through a pair of differential signal lines. The SATA interface provides a unified connection standard, making hard disk drives and solid-state drives compatible in different computer systems.

[0067] DDR (Double Data Rate Synchronous Dynamic Random-Access Memory) memory is a type of computer memory. It is a relatively common type of memory used to store and run data and programs in computers. Compared with the earlier SDRAM (Synchronous Dynamic Random-Access Memory), DDR memory has a higher data transmission speed and bandwidth. DDR memory can transmit data twice in one clock cycle.

[0068] Step S20: creating a storage queue in the DDR memory according to the data storage instruction, and placing the target data into the storage queue.

[0069] It should be noted that the storage queue is a circular first-in-first-out queue. Step S20 includes: creating a circular first-in-first-out queue in the DDR memory according to the data storage instruction, each queue block in the circular first-in-first-out queue storing data of preset bytes; and placing the target data into each queue block of the circular first-in-first-out queue in sequence according to the preset bytes.

[0070] It is understandable that the above-mentioned preset bytes can be user-defined settings, can be set according to the data volume of the target data, or can be set by other methods, for example, 8K Byte, 10K Byte or 16K Byte, etc. This embodiment and the following embodiments are described using 8K Byte as the preset byte.

[0071] Step S30: verifying the target data in the storage queue according to a preset method to generate a verification value.

[0072] It should be noted that the above step S30 includes: dividing the target data in the circular FIFO queue according to a preset division rule to obtain target sub-data; verifying the target sub-data in turn according to a preset method to obtain the verification value corresponding to each target sub-data.

[0073] It should be explained that the above-mentioned preset method can be CRC check, MD5 check, or other check methods. This embodiment and the following embodiments are described with CRC check as the preset method. Therefore, the above-mentioned check value is the CRC value obtained by CRC check. The above-mentioned preset division rule can be that every 16 queue blocks of data in the above-mentioned circular first-in-first-out queue are regarded as a target sub-data.

[0074] In a specific implementation, the above target data is stored in each queue block of 8K Byte, and a CRC check is performed every 16 queue blocks to obtain a CRC value.

[0075] Step S40: After encapsulating the check value and the target data in the storage queue, the encapsulated data is obtained, and the encapsulated data is sent to the receiving device through the SATA interface. The receiving device verifies the received encapsulated data to obtain the target check value, and determines whether the data verification is successful based on the check value and the target check value.

[0076] It should be noted that each queue block corresponding to each target sub-data may be encapsulated in sequence with the check value corresponding to each target sub-data to obtain encapsulated data, that is, each encapsulated data includes an 8K Byte queue block and a CRC value.

[0077] When the target data is acquired through the PCIE interface, the present embodiment sends a data storage instruction to the DDR memory based on the FPGA master control; creates a storage queue in the DDR memory according to the data storage instruction, and puts the target data into the storage queue; verifies the target data in the storage queue according to a preset method to generate a verification value; after encapsulating the verification value and the target data in the storage queue, obtains the encapsulated data, and sends the encapsulated data to the receiving device through the SATA interface, and the receiving device verifies the received encapsulated data to obtain the target verification value, and determines whether the data verification is successful according to the verification value and the target verification value. Since the present embodiment puts the target data into the storage queue, then verifies the target data in the storage queue according to a preset method to generate a verification value, and then encapsulates the verification value and the target data in the storage queue to obtain the encapsulated data, and sends the encapsulated data to the receiving device through the SATA interface, compared with the prior art, the present embodiment realizes the sending and receiving verification of unidirectional data transmission, and improves the security and reliability of unidirectional transmission.

[0078] refer to Figure 3 , Figure 3 This is a flow chart of the second embodiment of the high reliability one-way transmission method of the present invention. Figure 2The illustrated embodiment provides a second embodiment of the high-reliability unidirectional transmission method of the present invention.

[0079] In this embodiment, a high-reliability unidirectional transmission method is applied to a receiving device, wherein the receiving device includes a PCIE interface, an FPGA master control, a DDR memory, and a SATA interface. The high-reliability unidirectional transmission method includes the following steps:

[0080] Step S50: When the preset target data sent by the sending device is received through the SATA interface, a data storage instruction is sent to the DDR memory based on the FPGA master control, and the preset target data includes data information and a check value corresponding to the data information.

[0081] It should be noted that the above-mentioned preset target data are multiple encapsulated data sent by the sending device, each encapsulated data includes an 8K Byte queue block and a CRC value, that is, the preset target data includes data information and a check value corresponding to the data information.

[0082] Step S60: creating a storage queue in the DDR memory according to the data storage instruction, and placing the preset target data into the storage queue in sequence.

[0083] It should be noted that a storage queue is created in the DDR memory according to the data storage instruction, the storage queue is a circular first-in-first-out queue, and the circular first-in-first-out queue includes multiple queue blocks; the preset target data is placed in the queue blocks of the storage queue in sequence.

[0084] Step S70: verifying the preset target data in the storage queue according to a preset method to generate a target verification value.

[0085] It should be noted that, when preset target data of a preset threshold is received, the preset target data of the preset threshold in the storage queue is verified to obtain a target verification value.

[0086] It should be explained that the above preset threshold is set by the preset rule of the sending device. Since the preset division rule corresponding to the sending device is to treat every 16 queue blocks of data in the circular first-in-first-out queue as a target sub-data, where each queue block contains 8K Byte. Therefore, the preset threshold in this embodiment is 16 8K Byte queue blocks.

[0087] In the specific implementation, every time 16 8K Byte queue blocks are received, a CRC check is performed to obtain a target check value.

[0088] Step S80: judging whether the data verification is successful according to the target verification value and the verification value.

[0089] The target check value and the check value corresponding to the 16 8K Byte queue blocks are compared, and whether the data check is successful is determined based on the comparison result.

[0090] Step S90: If the data verification is successful, the preset target data is uploaded to the upper layer application through the PCIE interface.

[0091] It should be noted that if the data verification fails, the verification failure information is fed back to the sending device through the FPGA master control, so that the sending device sends a subsequent message according to the verification failure information.

[0092] It should be explained that the above subsequent messages include 16 queue blocks corresponding to data verification failure and subsequent queue blocks.

[0093] In a specific implementation, if the data verification fails, the FPGA master sends a 1-Byte data message to feedback the verification failure to the sending device. After receiving the message, the FPGA master of the sending device resends the corresponding 16 blocks of data and subsequent queue blocks.

[0094] For example, refer to Figure 4 , Figure 4 The unidirectional transmission method with high reliability is shown in the figure below: The unidirectional transmission system uses a sending device A for the transmission side and a receiving device B for the reception side. The transmission side sends data through the sending device A, and the reception side receives data through the receiving device B.

[0095] For example, refer to Figure 5 , Figure 5The overall flow diagram of the high-reliability unidirectional transmission method of the present invention is shown. The sending side sends data to the DDR memory corresponding to the FPGA master control through the PCIE interface provided by the sending device, that is, the FPGA of the sending side receives data to the onboard DDR memory of the sending device through the CIE interface; the onboard memory data of the FPGA card is reorganized into 8K Byte data blocks, a CRC is calculated for every 16 data blocks, and data is sent according to the 8K Byte data blocks. The data structure encapsulated in each data block includes a CRC value. If the sending is successful and the return message is not received, the data memory corresponding to the last sent message is cleared; the FPGA card corresponding to the receiving device of the receiving side receives the data sent by the sending device through the SATA interface, and stores it in the onboard DDR. Every time 16 8K Byte data blocks are received, a CRC value is calculated, and the CRC value of the sending side is checked. If the check is successful, continue to receive. If the check fails, send 1Byte data feedback to the sending device (the receiving device sends 1Byte data feedback to indicate that the check fails, and notifies the sending device to resend the corresponding 16 blocks of data and subsequent data). The data of the receiving device corresponding to the receiving side is successfully checked, and the FPGA uploads the data to the application layer through the PCIE interface.

[0096] When receiving the preset target data sent by the sending device through the SATA interface, the present embodiment sends a data storage instruction to the DDR memory based on the FPGA master control, and the preset target data includes data information and a check value corresponding to the data information; creates a storage queue in the DDR memory according to the data storage instruction, and puts the preset target data into the storage queue in sequence; verifies the preset target data in the storage queue according to a preset method to generate a target check value; determines whether the data check is successful according to the target check value and the check value; if the data check is successful, uploads the preset target data to the upper layer application through the PCIE interface. Since the present embodiment puts the preset target data into the storage queue in sequence; verifies the preset target data in the storage queue according to a preset method to generate a target check value; determines whether the data check is successful according to the target check value and the check value; if the data check is successful, uploads the preset target data to the upper layer application through the PCIE interface, compared with the prior art, the present embodiment further improves the security and reliability of one-way transmission.

[0097] In addition, an embodiment of the present invention further provides a storage medium on which a high-reliability one-way transmission program is stored. When the high-reliability one-way transmission program is executed by a processor, the steps of the high-reliability one-way transmission method described above are implemented.

[0098] Reference Figure 6 , Figure 6 It is a structural block diagram of the first embodiment of the high reliability unidirectional transmission device of the present invention.

[0099] like Figure 6 As shown, the high-reliability unidirectional transmission device proposed in an embodiment of the present invention is applied to a sending device, and the sending device includes: a PCIE interface, an FPGA master control, a DDR memory and a SATA interface. The high-reliability unidirectional transmission device includes: a data acquisition module 601, a data storage module 602, a data verification module 603 and a data sending module 604.

[0100] The data acquisition module 601 is used to send a data storage instruction to the DDR memory based on the FPGA master control when the target data is acquired through the PCIE interface.

[0101] The data storage module 602 is used to create a storage queue in the DDR memory according to the data storage instruction and put the target data into the storage queue.

[0102] The data verification module 603 is used to verify the target data in the storage queue according to a preset method and generate a verification value.

[0103] The data sending module 604 is used to encapsulate the check value and the target data in the storage queue to obtain encapsulated data, and send the encapsulated data to the receiving device through the SATA interface. The receiving device verifies the received encapsulated data to obtain the target check value, and determines whether the data verification is successful based on the check value and the target check value.

[0104] The data storage module 602 is also used to create a circular first-in-first-out queue in the DDR memory according to the data storage instruction, and each queue block in the circular first-in-first-out queue stores data of preset bytes; and put the target data into each queue block of the circular first-in-first-out queue in sequence according to the preset bytes.

[0105] The data verification module 603 is also used to divide the target data in the circular FIFO queue according to a preset division rule to obtain target sub-data; and to verify the target sub-data in turn according to a preset method to obtain a verification value corresponding to each target sub-data.

[0106] The data sending module 604 is further used to encapsulate each queue block corresponding to each target sub-data in sequence with the check value corresponding to each target sub-data to obtain encapsulated data.

[0107] When the target data is acquired through the PCIE interface, the present embodiment sends a data storage instruction to the DDR memory based on the FPGA master control; creates a storage queue in the DDR memory according to the data storage instruction, and puts the target data into the storage queue; verifies the target data in the storage queue according to a preset method to generate a verification value; after encapsulating the verification value and the target data in the storage queue, obtains the encapsulated data, and sends the encapsulated data to the receiving device through the SATA interface, and the receiving device verifies the received encapsulated data to obtain the target verification value, and determines whether the data verification is successful according to the verification value and the target verification value. Since the present embodiment puts the target data into the storage queue, then verifies the target data in the storage queue according to a preset method to generate a verification value, and then encapsulates the verification value and the target data in the storage queue to obtain the encapsulated data, and sends the encapsulated data to the receiving device through the SATA interface, compared with the prior art, the present embodiment realizes the sending and receiving verification of unidirectional data transmission, and improves the security and reliability of unidirectional transmission.

[0108] Based on the first embodiment of the high reliability one-way transmission device of the present invention, a second embodiment of the high reliability one-way transmission device of the present invention is proposed. Figure 7 , Figure 7 A structural block diagram of a second embodiment of a high reliability unidirectional transmission device according to the present invention.

[0109] like Figure 7 As shown, the high-reliability unidirectional transmission device proposed in an embodiment of the present invention is applied to a receiving device, and the receiving device includes a PCIE interface, an FPGA master control, a DDR memory and a SATA interface. The high-reliability unidirectional transmission device includes: a data receiving module 701, a data storage module 702, a data verification module 703, a verification judgment module 704 and a data upload module 705.

[0110] The data receiving module 701 is used to send a data storage instruction to the DDR memory based on the FPGA master control when receiving preset target data sent by the sending device through the SATA interface. The preset target data includes data information and a check value corresponding to the data information.

[0111] The data storage module 702 is used to create a storage queue in the DDR memory according to the data storage instruction, and put the preset target data into the storage queue in sequence.

[0112] The data verification module 703 is used to verify the preset target data in the storage queue according to a preset method to generate a target verification value.

[0113] The verification judgment module 704 is used to judge whether the data verification is successful according to the target verification value and the verification value.

[0114] The data uploading module 705 is used to upload the preset target data to the upper layer application through the PCIE interface if the data verification is successful.

[0115] The data storage module 702 is also used to create a storage queue in the DDR memory according to the data storage instruction, and the storage queue is a circular first-in-first-out queue, and the circular first-in-first-out queue includes multiple queue blocks; the preset target data is placed in the queue blocks of the storage queue in sequence.

[0116] The data verification module 703 is further configured to verify the preset target data of the preset threshold in the storage queue to obtain a target verification value when the preset target data of the preset threshold is received.

[0117] The data upload module 705 is also used to feed back verification failure information to the sending device through the FPGA master control if the data verification fails, so that the sending device sends a subsequent message according to the verification failure information.

[0118] When receiving the preset target data sent by the sending device through the SATA interface, the present embodiment sends a data storage instruction to the DDR memory based on the FPGA master control, and the preset target data includes data information and a check value corresponding to the data information; creates a storage queue in the DDR memory according to the data storage instruction, and puts the preset target data into the storage queue in sequence; verifies the preset target data in the storage queue according to a preset method to generate a target check value; determines whether the data check is successful according to the target check value and the check value; if the data check is successful, uploads the preset target data to the upper layer application through the PCIE interface. Since the present embodiment puts the preset target data into the storage queue in sequence; verifies the preset target data in the storage queue according to a preset method to generate a target check value; determines whether the data check is successful according to the target check value and the check value; if the data check is successful, uploads the preset target data to the upper layer application through the PCIE interface, compared with the prior art, the present embodiment further improves the security and reliability of one-way transmission.

[0119] Other embodiments or specific implementations of the high-reliability unidirectional transmission device of the present invention can refer to the above-mentioned method embodiments and will not be described in detail here.

[0120] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or system including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or system. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or system including the element.

[0121] The serial numbers of the above embodiments of the present invention are only for description and do not represent the advantages or disadvantages of the embodiments.

[0122] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course can also be implemented by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as a read-only memory / random access memory, a magnetic disk, or an optical disk), and includes a number of instructions for a terminal device (which can be a mobile phone, a computer, a server, an air conditioner, or a network device, etc.) to execute the methods described in each embodiment of the present invention.

[0123] The above are only preferred embodiments of the present invention, and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A high reliability one-way transmission method, characterized in that: The method is applied to a sending device, the sending device includes: a PCIE interface, an FPGA master control, a DDR memory and a SATA interface, and the high-reliability unidirectional transmission method includes: When the target data is acquired through the PCIE interface, a data storage instruction is sent to the DDR memory based on the FPGA master control; Creating a storage queue in the DDR memory according to the data storage instruction, and putting the target data into the storage queue, wherein the storage queue is a circular first-in-first-out queue; Verify the target data in the storage queue according to a preset method to generate a verification value; After encapsulating the check value and the target data in the storage queue, encapsulated data is obtained, and the encapsulated data is sent to a receiving device through the SATA interface, the receiving device verifies the received encapsulated data to obtain a target check value, and determines whether the data verification is successful according to the check value and the target check value, each encapsulated data includes a queue block and a check value; The step of creating a storage queue in the DDR memory according to the data storage instruction and placing the target data into the storage queue comprises: Creating a circular first-in-first-out queue in the DDR memory according to the data storage instruction, wherein each queue block in the circular first-in-first-out queue stores data of preset bytes; Putting the target data into each queue block of the circular first-in-first-out queue in sequence according to preset bytes; The step of verifying the target data in the storage queue according to a preset method to generate a verification value includes: Divide the target data in the circular FIFO queue according to a preset division rule to obtain target sub-data, wherein the target sub-data includes a plurality of queue blocks; Verifying the target sub-data in sequence according to a preset method to obtain verification values ​​corresponding to each target sub-data; Correspondingly, the step of obtaining encapsulated data after encapsulating the check value and the target data in the storage queue includes: Encapsulating each queue block corresponding to each target sub-data with the check value corresponding to each target sub-data in sequence to obtain encapsulated data; The method further comprises: When the verification failure information corresponding to the target sub-data is received by the receiving device, the corresponding target sub-data and subsequent data corresponding to the target sub-data are sent.

2. A high reliability one-way transmission method, characterized in that: The method is applied to a receiving device, the receiving device includes a PCIE interface, an FPGA master control, a DDR memory and a SATA interface, and the high-reliability unidirectional transmission method includes: When receiving preset target data sent by a sending device through the SATA interface, sending a data storage instruction to the DDR memory based on the FPGA master control, the preset target data includes data information and a check value corresponding to the data information; Creating a storage queue in the DDR memory according to the data storage instruction, and placing the preset target data into the storage queue in sequence; Verify the preset target data in the storage queue according to a preset method to generate a target verification value; Determining whether the data verification is successful according to the target verification value and the verification value; If the data verification is successful, the preset target data is uploaded to the upper layer application through the PCIE interface; The step of creating a storage queue in the DDR memory according to the data storage instruction and sequentially placing the preset target data into the storage queue comprises: Creating a storage queue in the DDR memory according to the data storage instruction, wherein the storage queue is a circular first-in-first-out queue, and the circular first-in-first-out queue includes a plurality of queue blocks; Putting the preset target data into the queue blocks of the storage queue in sequence; Correspondingly, the step of verifying the preset target data in the storage queue according to a preset method to generate a target verification value includes: When the preset target data of the preset threshold is received, the preset target data of the preset threshold in the storage queue is verified to obtain a target verification value; After judging whether the data verification is successful according to the target verification value and the verification value, the method further includes: If the data verification fails, the verification failure information is fed back to the sending device through the FPGA master control, so that the sending device sends a subsequent message according to the verification failure information.

3. A high reliability one-way transmission device, characterized in that: The high-reliability unidirectional transmission device is applied to a sending device, the sending device includes: a PCIE interface, an FPGA master control, a DDR memory and a SATA interface, and the high-reliability unidirectional transmission device includes: A data acquisition module, configured to send a data storage instruction to the DDR memory based on the FPGA master control when the target data is acquired through the PCIE interface; A data storage module, used for creating a storage queue in the DDR memory according to the data storage instruction, and putting the target data into the storage queue, wherein the storage queue is a circular first-in-first-out queue; A data verification module, used to verify the target data in the storage queue according to a preset method and generate a verification value; a data sending module, configured to encapsulate the check value and the target data in the storage queue to obtain encapsulated data, and send the encapsulated data to a receiving device through the SATA interface, wherein the receiving device verifies the received encapsulated data to obtain a target check value, and determines whether the data verification is successful according to the check value and the target check value, wherein each encapsulated data includes a queue block and a check value; The data storage module is further used to create a circular first-in-first-out queue in the DDR memory according to the data storage instruction, each queue block in the circular first-in-first-out queue stores data of preset bytes; and put the target data into each queue block of the circular first-in-first-out queue in sequence according to the preset bytes; The data verification module is further used to divide the target data in the circular FIFO queue according to a preset division rule to obtain target sub-data, wherein the target sub-data includes a plurality of queue blocks; and to verify the target sub-data in sequence according to a preset method to obtain a verification value corresponding to each target sub-data; The data sending module is further used to encapsulate each queue block corresponding to each target sub-data with the check value corresponding to each target sub-data in sequence to obtain encapsulated data; The high-reliability one-way transmission device is further used to send the corresponding target sub-data and subsequent data corresponding to the target sub-data when receiving the verification failure information corresponding to the target sub-data from the receiving device.

4. A high reliability one-way transmission device, characterized in that: The high-reliability unidirectional transmission device is applied to a receiving device, the receiving device includes a PCIE interface, an FPGA master control, a DDR memory and a SATA interface, and the high-reliability unidirectional transmission device includes: A data receiving module, configured to send a data storage instruction to the DDR memory based on the FPGA master control when receiving preset target data sent by the sending device through the SATA interface, wherein the preset target data includes data information and a check value corresponding to the data information; A data storage module, used for creating a storage queue in the DDR memory according to the data storage instruction, and placing the preset target data into the storage queue in sequence; A data verification module, used to verify the preset target data in the storage queue according to a preset method and generate a target verification value; A verification judgment module, used to judge whether the data verification is successful according to the target verification value and the verification value; A data uploading module, configured to upload the preset target data to an upper layer application through the PCIE interface if the data verification succeeds; The data storage module is further used to create a storage queue in the DDR memory according to the data storage instruction, wherein the storage queue is a circular first-in-first-out queue, and the circular first-in-first-out queue includes a plurality of queue blocks; and the preset target data is sequentially placed in the queue blocks of the storage queue; The data verification module is further configured to verify the preset target data of the preset threshold in the storage queue to obtain a target verification value when receiving the preset target data of the preset threshold; The verification judgment module is also used to feedback verification failure information to the sending device through the FPGA master control if the data verification fails, so that the sending device sends a subsequent message according to the verification failure information.

5. A high reliability one-way transmission device, characterized in that: The device comprises: a memory, a processor, and a high-reliability one-way transmission program stored in the memory and executable on the processor, wherein the high-reliability one-way transmission program is configured to implement the steps of the high-reliability one-way transmission method according to any one of claims 1 or 2.

6. A storage medium, characterized in that: The storage medium stores a high-reliability one-way transmission program, and when the high-reliability one-way transmission program is executed by the processor, the steps of the high-reliability one-way transmission method according to any one of claims 1 or 2 are implemented.

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