Semiconductor devices

Abstract

The present invention discloses a semiconductor device, which includes: a contact layer, including a first contact layer, the first contact layer includes a plurality of sub-contact layers; an interlayer insulating film, the interlayer insulating film is arranged above the first cooking surface and includes the first interlayer insulating film, the first interlayer insulating film is arranged in the fast recovery diode region, the first interlayer insulating film is provided with a first contact hole, in a top view, the first contact hole extends in the first direction and is a plurality of, the plurality of first contact holes are arranged at intervals in the second direction, each first contact hole includes a plurality of sub-contact holes, the plurality of sub-contact holes are arranged at intervals in the first direction and correspond one to one with the plurality of sub-contact layers in the up and down directions. Thus, by arranging a plurality of sub-contact holes arranged at intervals in the first direction on the first interlayer insulating film in the fast recovery diode region, the reverse recovery current and reverse recovery loss of the semiconductor device can be reduced, and the soft recovery characteristics of the semiconductor device can be achieved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device. Background Art

[0002] Traditional insulated gate bipolar transistors cannot achieve reverse conduction. In inverter applications, they need to be sealed together with anti-parallel fast recovery diodes, which increases the cost and volume of the system. Based on this, reverse conducting insulated gate bipolar transistors came into being. Insulated gate bipolar transistors and fast recovery diodes are integrated on the same chip. With its small chip area, high power density, low cost and high reliability, it has attracted extensive research. Optimizing and balancing the characteristics of insulated gate bipolar transistors and fast recovery diodes is a difficult and important topic.

[0003] In the prior art, in a reverse conducting insulated gate bipolar transistor, when a fast recovery diode switches from an on state to an off state, unbalanced carriers stored inside the diode are released, thereby generating a large reverse recovery current and causing large switching losses. Summary of the invention

[0004] The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, one object of the present invention is to provide a semiconductor device that can reduce reverse recovery current and reverse recovery loss.

[0005] According to an embodiment of the present invention, a semiconductor device comprises: a substrate, the substrate having a first main surface and a second main surface opposite to the first main surface; a drift layer of a first conductivity type, the drift layer being arranged on the substrate and located between the first main surface and the second main surface; a base layer of a second conductivity type, the base layer of the second conductivity type being arranged on a side of the drift layer facing the first main surface, and the upper surface of the base layer constituting a part of the first main surface; a first trench, the first trench penetrating the base layer from the first main surface in the thickness direction to reach the drift layer, the first trench being located in a fast recovery diode region of the semiconductor device and extending in a length direction in the first direction of the semiconductor device, the first trench being a plurality of trenches, and the plurality of the first trenches being arranged at intervals in the second direction of the semiconductor device; a contact layer of a second conductivity type, the contact layer being arranged on the base layer and the upper surface constituting a part of the first main surface, the contact layer comprising a first contact layer, the first contact layer being located in the fast recovery diode region and extending in a length direction in the first direction, the first contact layer being a plurality of trenches, and the plurality of the first trenches being arranged at intervals in the second direction of the semiconductor device. The first contact layers are arranged at intervals in the second direction, one first contact layer is arranged between two adjacent first grooves, one first contact layer includes multiple sub-contact layers, and the multiple sub-contact layers are arranged at intervals in the first direction; an interlayer insulating film, the interlayer insulating film is arranged above the first main surface and includes a first interlayer insulating film, the first interlayer insulating film is arranged in the fast recovery diode region, the first interlayer insulating film is provided with a first contact hole, in a top view, the first contact hole extends in the first direction and is multiple, the multiple first contact holes are arranged at intervals in the second direction, each of the first contact holes includes multiple sub-contact holes, the multiple sub-contact holes are arranged at intervals in the first direction and correspond to the multiple sub-contact layers in the upper and lower directions, wherein the first direction and the second direction are perpendicular to each other; an emitter metal layer, the emitter metal layer is arranged above the interlayer insulating film, the portion of the emitter metal layer corresponding to the fast recovery diode region is provided with a first contact protrusion, the first contact protrusion passes through the sub-contact hole and contacts the sub-contact layer.

[0006] Therefore, by setting a plurality of sub-contact holes spaced apart in a first direction on the first interlayer insulating film in the fast recovery diode region, the injection channel area of ​​the emitter metal layer in the fast recovery diode region in the semiconductor device can be directly reduced, thereby reducing the reverse recovery current and reverse recovery loss of the semiconductor device, and realizing the soft recovery characteristics of the semiconductor device.

[0007] In some examples of the present invention, the length of the sub-contact hole in the first direction is W1, the spacing distance between two adjacent sub-contact holes in each of the first contact holes is W2, and W1 and W2 satisfy the relationship: W2≤W1.

[0008] In some examples of the present invention, two adjacent first contact holes are set to be a first adjacent contact hole and a second adjacent contact hole, respectively, and in the second direction, projections of the multiple sub-contact holes in the first adjacent contact hole overlap with projections of the multiple sub-contact holes in the second adjacent contact hole in a one-to-one correspondence.

[0009] In some examples of the present invention, two adjacent first contact holes are set to be a first adjacent contact hole and a second adjacent contact hole, respectively, and in the second direction, projections of the multiple sub-contact holes in the first adjacent contact hole and projections of the multiple sub-contact holes in the second adjacent contact hole are alternately arranged in sequence in the first direction.

[0010] In some examples of the present invention, the length of the sub-contact hole in the first direction is W1, the spacing distance between two adjacent sub-contact holes in each of the first contact holes is W2, and W1 and W2 satisfy the relationship: W2>W1.

[0011] In some examples of the present invention, two adjacent first contact holes are set to be a first adjacent contact hole and a second adjacent contact hole, respectively, and in the second direction, projections of the multiple sub-contact holes in the first adjacent contact hole overlap with projections of the multiple sub-contact holes in the second adjacent contact hole in a one-to-one correspondence.

[0012] In some examples of the present invention, two adjacent first contact holes are set to be a first adjacent contact hole and a second adjacent contact hole, respectively, and in the second direction, projections of the multiple sub-contact holes in the first adjacent contact hole and projections of the multiple sub-contact holes in the second adjacent contact hole are alternately arranged in sequence in the first direction.

[0013] In some examples of the present invention, the first trench is a virtual trench, a virtual gate electrode is arranged in the virtual trench, the virtual gate electrode is electrically connected to the emitter metal layer of the semiconductor device, the virtual gate electrode is spaced apart from the inner wall of the virtual trench, a virtual gate insulating film is arranged between the virtual gate electrode and the virtual trench, and the virtual gate electrode is arranged opposite to the base layer and the drift layer via the virtual gate insulating film.

[0014] In some examples of the present invention, the semiconductor device also includes a second trench and an emitter layer, the second trench penetrates the emitter layer and the base layer from the first main surface in the thickness direction to reach the drift layer, the second trench is located in the insulated gate bipolar transistor region of the semiconductor device and extends in the first direction in length, there are multiple second trenches, and the multiple second trenches are spaced apart in the second direction of the semiconductor device; the contact layer includes a second contact layer, the second contact layer is located in the insulated gate bipolar transistor region and extends in the first direction in length, there are multiple second contact layers, and the multiple second contact layers are spaced apart in the second direction. The second contact layer is arranged upwardly with a spacing therebetween, and a second contact layer is arranged between two adjacent second grooves; the interlayer insulating film includes a second interlayer insulating film, the second interlayer insulating film is arranged on the insulated gate bipolar transistor, the second interlayer insulating film is provided with a second contact hole, and from a top-down perspective, the second contact holes extend in a first direction and are multiple, and the multiple second contact holes are spaced apart in the second direction, the second contact holes correspond to the second contact layer in the up and down directions, and the emitter metal layer is provided with a second contact protrusion on a portion corresponding to the insulated gate bipolar transistor region, and the second contact protrusion passes through the second contact hole and contacts the second contact layer.

[0015] In some examples of the present invention, the insulated gate bipolar transistor region and the fast recovery diode region are spaced apart to form a transition region, the transition region is provided with a connecting groove, the connecting groove penetrates the base layer from the first main surface in the thickness direction to reach the drift layer, the connecting groove extends in the second direction in the length direction and connects one end of multiple first grooves, the semiconductor device does not have the contact layer corresponding to the transition region, the interlayer insulating film includes a third interlayer insulating film, the third interlayer insulating film is provided with a third contact hole, in a top view, the third contact hole extends in the second direction and corresponds to at least part of the connecting groove up and down, the emitter metal layer is provided with a third contact protrusion in the part corresponding to the transition region, the third contact protrusion penetrates the third contact hole and contacts the virtual gate electrode of the connecting groove.

[0016] In some examples of the present invention, the third contact hole is spaced apart from the first contact hole and the second contact hole respectively.

[0017] In some examples of the present invention, the second trench is an active trench, an active gate electrode is arranged in the active trench, the active gate electrode is connected to the gate pad electrode of the semiconductor device, the active gate electrode is spaced apart from the inner wall of the active trench, an active gate insulating film is arranged between the active gate electrode and the active trench, the active gate electrode is separated from the emitter layer by the active gate insulating film, the base layer and the drift layer are arranged relatively.

[0018] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0020] Figure 1 is a schematic diagram of a semiconductor device according to an embodiment of the present invention;

[0021] Figure 2 is a partial schematic diagram of a semiconductor device according to an embodiment of the present invention;

[0022] Figure 3 is a partial schematic diagram of a substrate according to an embodiment of the present invention;

[0023] Figure 4 is a partial schematic diagram of a semiconductor device according to an embodiment of the present invention;

[0024] Figure 5 is a partial schematic diagram of a semiconductor device according to some other embodiments of the present invention;

[0025] Figure 6 is a partial schematic diagram of a semiconductor device according to some other embodiments of the present invention;

[0026] Figure 7 is a partial schematic diagram of a semiconductor device according to some further embodiments of the present invention;

[0027] Figure 8 is a partial schematic diagram of a semiconductor device according to some further embodiments of the present invention;

[0028] Fig. 9 for Figure 2 A1-A1 direction, Figure 5 A5-A5 direction and Figure 7 A cross-sectional view along the A9-A9 direction;

[0029] Fig.10 for Figure 4 Middle A3-A3 direction, Figure 6 A7-A7 direction and Figure 8 Cross-sectional view along the A11-A11 direction;

[0030] Fig.11 for Figure 2 A2-A2 direction and Figure 4 A cross-sectional view along the A4-A4 direction;

[0031] Fig.12 for Figure 5 A6-A6 direction and Figure 6 A cross-sectional view along the A8-A8 direction;

[0032] Fig.13 for Figure 7 A10-A10 direction and Figure 8 A cross-sectional view along the A12-A12 direction;

[0033] Fig.14 is a partial schematic diagram of a semiconductor device according to an embodiment of the present invention;

[0034] Fig.15 is a partial schematic diagram of a semiconductor device according to an embodiment of the present invention;

[0035] Fig.16 is a partial schematic diagram of a semiconductor device according to an embodiment of the present invention;

[0036] Fig.17 is a partial schematic diagram of a semiconductor device according to an embodiment of the present invention;

[0037] Fig.18 is a partial schematic diagram of a semiconductor device according to an embodiment of the present invention;

[0038] Fig.19 is a partial schematic diagram of a semiconductor device according to an embodiment of the present invention;

[0039] Fig. 20 is a partial schematic diagram of a semiconductor device according to an embodiment of the present invention;

[0040] Fig.21 is a partial schematic diagram of a semiconductor device according to an embodiment of the present invention;

[0041] Fig. 22 is a schematic diagram of a semiconductor device according to an embodiment of the present invention;

[0042] Fig.23 is a flow chart of manufacturing a semiconductor device according to an embodiment of the present invention.

[0043] Reference numerals:

[0044] 100. Semiconductor devices;

[0045] 1. substrate; 101. first main surface; 102. second main surface;

[0046] 2. Drift layer; 3. Base layer;

[0047] 4. fast recovery diode region; 401. first trench; 4011. virtual gate insulating film; 402. virtual gate electrode;

[0048] 5. contact layer; 501. first contact layer; 5011. sub-contact layer; 502. second contact layer;

[0049] 6. interlayer insulating film; 601. first interlayer insulating film; 6011. first contact hole; 60111. sub-contact hole; 60112. first adjacent contact hole; 60113. second adjacent contact hole; 602. second interlayer insulating film; 6021. second contact hole; 603. third interlayer insulating film; 6031. third contact hole;

[0050] 7. emitter metal layer; 701. first contact protrusion; 702. second contact protrusion; 703. emitter metal body; 704. third contact protrusion;

[0051] 8. Insulated gate bipolar transistor region; 801. Second trench; 8011. Active gate insulating film; 802. Emitter layer; 803. Active gate electrode;

[0052] 9. Transition area; 901. Connecting groove;

[0053] 10. Terminal region; 11. Gate pad; 12. Carrier storage layer; 13. Field stop layer; 14. Collector layer; 15. Collector metal layer; 16. Cathode layer; 17. Gate trench; 18. Gate oxide layer; 20. Contact hole. DETAILED DESCRIPTION

[0054] Embodiments of the present invention are described in detail below. The embodiments described with reference to the accompanying drawings are exemplary. Embodiments of the present invention are described in detail below.

[0055] Reference below Figure 1-Figure 22 A semiconductor device 100 according to an embodiment of the present invention is described. The semiconductor device 100 is, for example, a reverse conducting insulated gate bipolar transistor. In the following description, N and P represent the conductivity type of the semiconductor. In the present invention, the first conductivity type is set to N type and the second conductivity type is set to P type for description.

[0056] Combination Figure 1-Figure 3As shown, the semiconductor device 100 according to the present invention may mainly include: a substrate 1, a drift layer 2 of a first conductivity type, a base layer 3 of a second conductivity type, a first trench 401, a contact layer 5 of a second conductivity type, an interlayer insulating film 6 and an emitter metal layer 7, wherein the substrate 1 has a first main surface 101 and a second main surface 102 on the opposite side of the first main surface 101, which can provide a stable and reliable setting position for other structures on the semiconductor device 100. The drift layer 2 of the first conductivity type is arranged on the substrate 1 and is located between the first main surface 101 and the second main surface 102, and the base layer 3 of the second conductivity type is arranged on the side of the drift layer 2 facing the first main surface 101, and the upper surface of the base layer 3 constitutes a part of the first main surface 101, so that the basic structure of the semiconductor device 100 can be formed, and the normal operation of the semiconductor device 100 can be ensured.

[0057] Further, the semiconductor device 100 is provided with a first trench 401 in the fast recovery diode region 4, the length direction of the first trench 401 extends in the first direction of the semiconductor device 100, and the first trench 401 penetrates the base layer 3 from the first main surface 101 to reach the drift layer 2 in the thickness direction. The first trench 401 is a virtual trench, and a virtual gate electrode 402 is provided in the virtual trench. The virtual trench can make the virtual gate electrode 402 of the fast recovery diode region 4 extend from the first main surface 101 to the drift layer 2, and the virtual gate electrode 402 is electrically connected to the emitter metal layer 7 of the semiconductor device 100, so that the virtual gate electrode 402 and the emitter metal layer 7 have the same potential. The virtual gate electrode 402 is spaced apart from the inner wall of the virtual trench, and a virtual gate insulating film 4011 is provided between the virtual gate electrode 402 and the virtual trench. The virtual gate electrode 402 is arranged opposite to the base layer 3 and the drift layer 2 through the virtual gate insulating film 4011, so that the function of the semiconductor device 100 can be guaranteed to operate normally.

[0058] There are multiple first trenches 401 , and the multiple first trenches 401 are spaced apart in the second direction of the semiconductor device 100 , so that the fast recovery diode region 4 can match different types of insulated gate bipolar transistors to form a reverse conducting insulated gate bipolar transistor.

[0059] Furthermore, a contact layer 5 of the second conductive type is arranged on the base layer 3, and the upper surface constitutes a part of the first main surface 101, and a first contact layer 501 is arranged in the fast recovery diode region 4, and the length direction of the first contact layer 501 extends in the first direction of the semiconductor device 100, and multiple first contact layers 501 are arranged at intervals in the second direction of the semiconductor device 100, and a first contact layer 501 is arranged between two adjacent first grooves 401, so that a fast recovery diode region 4 with a complete structure can be formed on the semiconductor device 100 to realize reverse conduction of the semiconductor device 100.

[0060] In an embodiment of the present invention, a first contact layer 501 disposed between two adjacent first trenches 401 includes a plurality of sub-contact layers 5011, and the plurality of sub-contact layers 5011 are disposed at intervals in the first direction. Compared with a first contact layer 501 disposed between two adjacent first trenches 401 in the prior art and continuously disposed in the first direction of the semiconductor device 100, the embodiment of the present invention can reduce the occupied area of ​​the first contact layer 501 between two adjacent first trenches 401 in the fast recovery diode region 4 in the fast recovery diode region 4, which is equivalent to directly reducing the injection channel area of ​​the emitter metal layer 7 in the fast recovery diode region 4 in the semiconductor device 100 on the one hand, and on the other hand, reducing the area of ​​the first contact layer 501 in the fast recovery diode region 4 can reduce the hole injection efficiency of the first contact hole 6011 and reduce the number of injected holes, thereby reducing the reverse recovery current of the semiconductor device 100, making the reverse recovery characteristics of the semiconductor device 100 softer, thereby reducing the reverse recovery loss of the semiconductor device 100, and facilitating a better balance between the on-state voltage drop and the reverse recovery characteristics of the semiconductor device 100. In addition, reducing the reverse recovery loss of the semiconductor device 100 is beneficial to reducing the heat generation of the semiconductor device 100 , thereby enhancing the robustness of the semiconductor device 100 .

[0061] Further, the interlayer insulating film 6 is disposed above the first main surface 101 and includes a first interlayer insulating film 601, the first interlayer insulating film 601 is disposed in the fast recovery diode region 4, and the first interlayer insulating film 601 is provided with a first contact hole 6011, and in a top view, the first contact hole 6011 extends in a first direction, and there are a plurality of them. Specifically, the interlayer insulating film 6 is made of an insulating material, and the interlayer insulating film 6 is disposed above the first main surface 101, so that only the area corresponding to the contact hole 20 in the first main surface 101 of the semiconductor device 100 can be connected to other external structures, so as to ensure the connection reliability when the chip is integrated in the semiconductor device 100. The interlayer insulating film 6 includes a first interlayer insulating film 601 arranged in the fast recovery diode region 4, and a first contact hole 6011 is arranged in the first interlayer insulating film 601. The first contact hole 6011 can expose a local position on the first main surface 101 to the interlayer insulating film 6, so that other structures can be connected to the local position on the first main surface 101. By setting the position of the first contact hole 6011 on the first interlayer insulating film 601, accurate connection between the first main surface 101 and other structures can be achieved, thereby ensuring the connection reliability within the semiconductor device 100.

[0062] Further, in a top view, a plurality of first contact holes 6011 are arranged on the interlayer insulating film 6, and the plurality of first contact holes 6011 extend in the first direction. In addition, the plurality of first contact holes 6011 are arranged at intervals in the second direction, and each first contact hole 6011 includes a plurality of sub-contact holes 60111, and the plurality of sub-contact holes 60111 are arranged at intervals in the first direction, which can reduce the hole injection efficiency, reduce the amount of hole injection, and further reduce the reverse recovery current, so that the reverse recovery characteristics of the fast recovery diode region 4 in the semiconductor are softer, the reverse recovery loss is reduced, the heat is reduced, and the robustness of the device is enhanced.

[0063] In addition, the plurality of sub-contact holes 60111 correspond to the plurality of sub-contact layers 5011 in the vertical direction, wherein the first direction and the second direction are perpendicular to each other, so that the plurality of first contact holes 6011 correspond to the plurality of first contact layers 501 on the first main surface 101 in a one-to-one manner, so that the plurality of first contact layers 501 can be exposed to the interlayer insulating film 6 through the plurality of first contact holes 6011, so that other structures can be connected to the plurality of first contact layers 501 through the plurality of first contact holes 6011. It should also be noted that the top view in the embodiment of the present invention is perpendicular to Figure 2 The perspective of the paper direction.

[0064] Further, the emitter metal layer 7 is arranged above the interlayer insulating film 6, and the portion of the emitter metal layer 7 corresponding to the fast recovery diode region 4 is provided with a first contact protrusion 701, and the first contact protrusion 701 passes through the sub-contact hole 60111 and contacts the sub-contact layer 5011 to achieve electrical connection between the two. Specifically, in the embodiment of the present invention, the emitter metal layer 7 arranged above the interlayer insulating film 6 is the emitter metal body 703 of the semiconductor device 100, and the portion of the emitter metal layer 7 corresponding to the fast recovery diode region 4 is provided with a first contact protrusion 701, and the first contact protrusion 701 can pass through a plurality of sub-contact holes 60111 in the first interlayer insulating film 601, so that the first contact protrusion 701 can contact the corresponding sub-contact below the sub-contact hole 60111, so that the first contact layer 501 can be connected to the emitter metal layer 7 to ensure the normal operation of the semiconductor device 100.

[0065] Therefore, by setting a plurality of sub-contact holes 60111 spaced apart in the first direction on the first interlayer insulating film 601 of the fast recovery diode region 4, the injection channel area of ​​the emitter metal layer 7 of the fast recovery diode region 4 in the semiconductor device 100 can be directly reduced, thereby reducing the reverse recovery current and reverse recovery loss of the semiconductor device 100, thereby realizing the soft recovery characteristics of the semiconductor device 100.

[0066] According to an embodiment of the present invention, Figure 2 and Figure 4 As shown, the length of the sub-contact hole 60111 in the first direction is W1, and the spacing distance between two adjacent sub-contact holes 60111 in each first contact hole 6011 is W2, and W1 and W2 satisfy the relationship: W2≤W1. Specifically, when multiple sub-contact holes 60111 are spaced in the first direction, in each first contact hole 6011, the spacing distance between two adjacent sub-contact holes 60111 is set not to exceed the length of the sub-contact hole 60111 in the first direction. In this way, the reverse recovery loss of the semiconductor device 100 can be reduced while ensuring that the on-state voltage drop of the semiconductor device 100 is not too large, which is conducive to balancing the relationship between the on-state voltage drop and the reverse recovery characteristics of the semiconductor device 100, and is conducive to improving the performance balance of the semiconductor device 100.

[0067] In some embodiments of the present invention, Figure 2 , Figure 5 and Figure 7 As shown, two adjacent first contact holes 6011 are set to be a first adjacent contact hole 60112 and a second adjacent contact hole 60113. In the second direction, the projections of the multiple sub-contact holes 60111 in the first adjacent contact hole 60112 overlap with the projections of the multiple sub-contact holes 60111 in the second adjacent contact hole 60113. Such an arrangement can make the arrangement of the multiple sub-contact holes 60111 in the fast recovery diode region 4 in this embodiment simpler, and can facilitate the processing and manufacturing of the semiconductor device 100.

[0068] In other embodiments of the present invention, Figure 4 , Figure 6 and Figure 8 As shown, two adjacent first contact holes 6011 are respectively set as a first adjacent contact hole 60112 and a second adjacent contact hole 60113. In the second direction, the projections of the multiple sub-contact holes 60111 in the first adjacent contact hole 60112 and the projections of the multiple sub-contact holes 60111 in the second adjacent contact hole 60113 are alternately arranged in sequence in the first direction. In this way, the ions injected into the fast recovery diode region 4 through the multiple sub-contact holes 60111 in this embodiment can be more uniform, the distribution of the ions in the semiconductor device 100 can be more uniform, and the heat generation during operation of the semiconductor device 100 can be more uniform, which is conducive to improving the robustness of the semiconductor device 100.

[0069] According to some further embodiments of the present invention, Figure 7 and Figure 8As shown, the length of the sub-contact hole 60111 in the first direction is W1, and the spacing distance between two adjacent sub-contact holes 60111 in each first contact hole 6011 is W2, and W1 and W2 satisfy the relationship: W2>W1. Specifically, when multiple sub-contact holes 60111 are spaced in the first direction, in each first contact hole 6011, the spacing distance between two adjacent sub-contact holes 60111 is set to exceed the length of the sub-contact hole 60111 in the first direction, which will increase the on-state voltage drop of the semiconductor device 100 and reduce the on-state current, sacrificing the on-state current and on-state voltage drop of the semiconductor device 100, so as to further reduce the reverse recovery loss of the semiconductor device 100, reduce heat generation, and enhance the robustness of the device.

[0070] In some embodiments of the present invention, Figure 7 , Fig. 9 and Fig.13 As shown, two adjacent first contact holes 6011 are set to be a first adjacent contact hole 60112 and a second adjacent contact hole 60113. In the second direction, the projections of the multiple sub-contact holes 60111 in the first adjacent contact hole 60112 overlap with the projections of the multiple sub-contact holes 60111 in the second adjacent contact hole 60113. Such an arrangement can make the structure of the multiple sub-contact holes 60111 in the fast recovery diode region 4 in this embodiment simpler, and can facilitate the processing and manufacturing of the semiconductor device 100.

[0071] In other embodiments of the present invention, Figure 8 , Fig.10 and Fig.13 As shown, two adjacent first contact holes 6011 are respectively set as a first adjacent contact hole 60112 and a second adjacent contact hole 60113. In the second direction, the projections of the multiple sub-contact holes 60111 in the first adjacent contact hole 60112 and the projections of the multiple sub-contact holes 60111 in the second adjacent contact hole 60113 are alternately arranged in sequence in the first direction. In this way, the ions injected into the fast recovery diode region 4 through the multiple sub-contact holes 60111 in this embodiment can be more uniform, the distribution of the ions in the semiconductor device 100 can be more uniform, and the heat generation during operation of the semiconductor device 100 can be more uniform, which is conducive to improving the robustness of the semiconductor device 100.

[0072] According to an embodiment of the present invention, when the projections of the multiple sub-contact holes 60111 in the first adjacent contact hole 60112 in the second direction overlap with the projections of the multiple sub-contact holes 60111 in the second adjacent contact hole 60113 in a one-to-one correspondence, the area of ​​the fast recovery diode region 4 is equal to the area of ​​the fast recovery diode region 4 when the projections of the multiple sub-contact holes 60111 in the first adjacent contact hole 60112 in the second direction and the projections of the multiple sub-contact holes 60111 in the second adjacent contact hole 60113 are alternately arranged in the first direction, and when the second direction The length of the sub-contact holes 60111 in the first direction when the projections of the multiple sub-contact holes 60111 in the first adjacent contact hole 60112 and the projections of the multiple sub-contact holes 60111 in the second adjacent contact hole 60113 overlap in a one-to-one correspondence is the same as the length of the sub-contact holes 60111 in the first direction when the projections of the multiple sub-contact holes 60111 in the first adjacent contact hole 60112 and the projections of the multiple sub-contact holes 60111 in the second adjacent contact hole 60113 are alternately arranged in the first direction. The spacing distance between two adjacent sub-contact holes 60111 in each first contact hole 6011 in the case where the projections of the multiple sub-contact holes 60111 in the adjacent contact hole 60112 and the projections of the multiple sub-contact holes 60111 in the second adjacent contact hole 60113 correspond to each other in a one-to-one correspondence, and the spacing distance between two adjacent sub-contact holes 60111 in each first contact hole 6011 in the case where the projections of the multiple sub-contact holes 60111 in the first adjacent contact hole 60112 and the projections of the multiple sub-contact holes 60111 in the second adjacent contact hole 60113 are alternately arranged in the first direction. When the spacing distances between holes 60111 are the same, the total area of ​​the first contact hole 6011 when the projections of multiple sub-contact holes 60111 in the first adjacent contact hole 60112 in the second direction and the projections of multiple sub-contact holes 60111 in the second adjacent contact hole 60113 overlap one by one is greater than the total area of ​​the first contact hole 6011 when the projections of multiple sub-contact holes 60111 in the first adjacent contact hole 60112 in the second direction and the projections of multiple sub-contact holes 60111 in the second adjacent contact hole 60113 are alternately arranged in the first direction.

[0073] Combination Fig. 9 and Fig.10 As shown, the semiconductor device 100 also includes a second trench 801 and an emitter layer 802. The second trench 801 penetrates the emitter layer 802 and the base layer 3 from the first main surface 101 in the thickness direction to reach the drift layer 2. The second trench 801 is located in the insulated gate bipolar transistor region 8 of the semiconductor device 100, and the length direction extends in the first direction. There are multiple second trenches 801, and the multiple second trenches 801 are spaced apart in the second direction of the semiconductor device 100.

[0074] Specifically, an insulated gate bipolar transistor region 8 is also provided in the semiconductor device 100, and a second trench 801 is provided on the insulated gate bipolar transistor region 8. The length direction of the second trench 801 extends in the first direction of the semiconductor device 100, and penetrates the emitter layer 802 and the base layer 3 from the first main surface 101 in the thickness direction to reach the drift layer 2. The second trench 801 is an active trench, and an active gate electrode 803 is provided in the active trench. The active trench can extend the active gate electrode 803 of the insulated gate bipolar transistor region 8 from the first main surface 101 to the drift layer 2. The active gate electrode 803 is electrically connected to the gate pad 11 of the semiconductor device 100, so that the active gate electrode 803 and the gate pad 11 can have the same potential. The active gate electrode 803 is spaced apart from the inner wall of the active trench, an active gate insulating film 8011 is disposed between the active gate electrode 803 and the active trench, and the active gate electrode 803 is disposed opposite to the emitter layer 802, the base layer 3 and the drift layer 2 via the active gate insulating film 8011. In addition, a carrier storage layer 12 is further disposed in the insulated gate bipolar transistor region 8, the carrier storage layer 12 is disposed between the base layer 3 and the drift layer 2, and the active trench penetrates the carrier storage layer 12 to reach the drift layer 2, so that the function of the semiconductor device 100 can be guaranteed to operate normally.

[0075] When a voltage is applied to the active gate electrode 803, an electric field is generated and transmitted to the base layer 3 through the active gate insulating film 8011 to affect the free charge carriers in the base layer 3 and form a channel. There are multiple second trenches 801, and the multiple second trenches 801 are spaced apart in the second direction of the semiconductor device 100, so that the performance of the insulated gate bipolar transistor region 8 can meet the working requirements of the semiconductor device 100.

[0076] Further, the contact layer 5 includes a second contact layer 502, which is located in the insulated gate bipolar transistor region 8 and has a length direction extending in the first direction. There are multiple second contact layers 502, and the multiple second contact layers 502 are spaced apart in the second direction, and one second contact layer 502 is disposed between two adjacent second trenches 801. Specifically, the insulated gate bipolar transistor region 8 is provided with the second contact layer 502 to constitute a part of the first main surface 101 in the insulated gate bipolar transistor region 8, there are multiple second contact layers 502, and the multiple second contact layers 502 are spaced apart in the second direction, which can constitute the contact layer 5 region of the insulated gate bipolar transistor region 8, and one second contact layer 502 is disposed between two adjacent second trenches 801, so as to constitute the basic structure of the insulated gate bipolar transistor region 8 of the semiconductor device 100.

[0077] In the embodiment of the present invention, the second contact layer 502 is of the second conductivity type, and the emitter layer 802 is of the first conductivity type. During the preparation of the semiconductor device 100, the concentration of the second conductivity type impurities in the second contact layer 502 is lower than the concentration of the first conductivity type impurities in the emitter layer 802. Therefore, in the insulated gate bipolar transistor region 8, the second contact layer 502 formed in the emitter layer 802 is covered by the emitter layer 802. Fig. 9 and Fig.10 In FIG. 8 , the second contact layer 502 formed in the emitter layer 802 is covered by the emitter layer 802 , so the second contact layer 502 is not shown in the emitter layer 802 .

[0078] Further, the interlayer insulating film 6 includes a second interlayer insulating film 602, which is disposed on the insulated gate bipolar transistor. The second interlayer insulating film 602 is provided with a second contact hole 6021. In a top view, the second contact hole 6021 extends in the first direction, and there are a plurality of second contact holes 6021, which are arranged at intervals in the second direction, and the second contact holes 6021 correspond to the second contact layer 502 in the vertical direction. Specifically, the interlayer insulating film 6 is made of an insulating material, and the interlayer insulating film 6 is disposed above the first main surface 101, so that only the area corresponding to the contact hole 20 in the first main surface 101 of the semiconductor device 100 can be connected to other external structures, so as to ensure the connection reliability when the chip is integrated in the semiconductor device 100. The interlayer insulating film 6 also includes a second interlayer insulating film 602 arranged in the insulated gate bipolar transistor region 8, and a second contact hole 6021 is arranged in the second interlayer insulating film 602. The second contact hole 6021 can expose the second contact layer 502 to the second interlayer insulating film 602, and other structures can pass through the second contact hole 6021 and contact the second contact layer 502, so that the contact layer 5 in the insulated gate bipolar transistor region 8 can be accurately connected with other structures to ensure the connection reliability within the semiconductor device 100.

[0079] Furthermore, a second contact protrusion 702 is provided on a portion of the emitter metal layer 7 corresponding to the insulated gate bipolar transistor region 8. The second contact protrusion 702 passes through a second contact hole 6021 and contacts the second contact layer 502 to achieve electrical connection between the two. This ensures that the emitter metal layer 7 is accurately connected to the second contact layer 502 of the insulated gate bipolar transistor region 8 through the second contact hole 6021.

[0080] Combination Figure 1 , Fig. 9 and Fig.10As shown, the insulated gate bipolar transistor region 8 and the fast recovery diode region 4 are arranged at intervals to form a transition region 9, and the transition region 9 is provided with a connecting groove 901, and the connecting groove 901 penetrates the base layer 3 from the first main surface 101 in the thickness direction to reach the drift layer 2, and the connecting groove 901 extends in the second direction in the length direction, and connects one end of multiple first grooves 401, and the semiconductor device 100 is not provided with a contact layer 5 corresponding to the transition region 9, and the interlayer insulating film 6 includes a third interlayer insulating film 603, and the third interlayer insulating film 603 is provided with a third contact hole 6031. In a top view, the third contact hole 6031 extends in the second direction and corresponds to at least a part of the connecting groove 901 up and down.

[0081] Specifically, the insulated gate bipolar transistor region 8 and the fast recovery diode region 4 are arranged at intervals on the semiconductor device 100, which can ensure the working reliability of the insulated gate bipolar transistor and the fast recovery diode devices on the semiconductor device 100. A transition region 9 is provided between the insulated gate bipolar transistor region 8 and the fast recovery diode region 4 to reduce the mutual influence between the insulated gate bipolar transistor region 8 and the fast recovery diode region 4 in the semiconductor device 100.

[0082] Furthermore, combined with Figure 2 , Figure 4 , Figure 5 , Figure 6 , Figure 7 and Figure 8 As shown, a connection groove 901 is provided in the transition region 9. The connection groove 901 penetrates the base layer 3 from the first main surface 101 in the thickness direction to reach the drift layer 2. The length direction of the connection groove 901 extends in the second direction and connects one end of the plurality of first grooves 401. The connection groove 901 and the first groove 401 are both virtual grooves. A virtual gate electrode 402 is provided in the connection groove 901 through a virtual gate insulating film 4011. The semiconductor device 100 does not have a contact layer 5 corresponding to the transition region 9 to ensure the transition effect of the transition region 9 between the insulated gate bipolar transistor region 8 and the fast recovery diode region 4. The interlayer insulating film 6 also includes a third interlayer insulating film 603, which is provided in the transition region 9, and a third contact hole 6031 is provided on the third interlayer insulating film 603, so that the emitter metal layer 7 is connected to the virtual gate electrode 402 in the connection groove 901 through the third contact hole 6031.

[0083] Furthermore, combined with Fig.11 , Fig.12 and Fig.13As shown, in a top-down perspective, the third contact hole 6031 on the third interlayer insulating film 603 extends in the second direction and corresponds at least partially to the connecting groove 901 up and down, and a third contact protrusion 704 is provided on the portion of the emitter metal layer 7 corresponding to the transition region 9. The third contact protrusion 704 passes through the third contact hole 6031 and contacts the virtual gate electrode 402 of the connecting groove 901. This can ensure that the virtual gate electrode 402 in the connecting groove 901 is exposed to the third interlayer insulating film 603 through the third contact hole 6031, and can ensure that the emitter metal layer 7 in the semiconductor device 100 is reliably electrically connected to the virtual gate electrode 402 in the connecting groove 901 through the third contact hole 6031.

[0084] Combination Figure 2 and Figure 4 As shown, the third contact hole 6031 is spaced apart from the first contact hole 6011 and the second contact hole 6021, respectively. This not only allows the first contact protrusion 701, the second contact protrusion 702 and the third contact protrusion 704 on the emitter metal layer 7 to be spaced apart in the semiconductor device 100 to prevent the spacing between multiple first contact protrusions 701 from being too small, and to prevent the spacing between multiple second contact protrusions 702 from being too small, thereby improving the convenience of the production process of the semiconductor device 100, but also prevents the emitter metal layers 7 in different areas of the semiconductor device 100 from being incorrectly connected to cause a short circuit, thereby ensuring the structural reliability of the semiconductor device 100.

[0085] According to an embodiment of the present invention, Figure 14-Figure 22 As shown, the structure of the semiconductor device 100 mainly includes: an emitter metal layer 7, an interlayer insulating film 6, an emitter layer 802 of the first conductivity type, a base layer 3 of the second conductivity type, a contact layer 5 of the second conductivity type, a carrier storage layer 12, a drift layer 2 of the first conductivity type, a field stop layer 13, a collector layer 14 of the second conductivity type, a cathode layer 16 of the first conductivity type, a collector metal layer 15 and an insulating layer. Figure 14-Figure 23 The manufacturing process of the semiconductor device 100 is described as follows:

[0086] S1, providing a semiconductor substrate formed by a collector layer 14 of the second conductivity type, a field stop layer 13 of the first conductivity type, a drift layer 2 of the first conductivity type, a carrier storage layer 12 of the first conductivity type, and a base layer 3 of the second conductivity type, which is structure 1;

[0087] S2, on the basis of structure one, a gate trench 17 is formed by photolithography and etching of the semiconductor substrate, including an active trench and a dummy trench, the gate trench 17 starts from the first main surface 101, and penetrates the second conductive type base layer 3 and the carrier storage layer 12 to reach the drift layer 2, which is structure two;

[0088] S3, growing a gate oxide layer 18 on the basis of structure 2, which is structure 3;

[0089] S4, on the basis of structure three, depositing in-situ doped polysilicon to form an active gate electrode 803 and a virtual gate electrode 402, which is structure four;

[0090] S5. Based on the structure 4, using a mask plate for photolithography, first conductivity type impurities are implanted to form a first conductivity type emitter layer 802. This structure is the structure 5.

[0091] S6, on the basis of structure five, depositing an interlayer insulating film 6 to form structure six;

[0092] S7, on the basis of structure 6, forming a contact hole 20 by photolithography and etching to form structure 7;

[0093] S8, on the basis of structure seven, implanting a contact layer 5 of the second conductivity type, and then sequentially filling in a tungsten plug and titanium or tin to form structure eight;

[0094] S9, based on structure eight, sputter the top metal, photolithography etch the top metal, and deposit the passivation layer, and photolithography etch the passivation layer. Subsequently, under the shielding of the mask, the first conductivity type impurities are injected to form the first conductivity type cathode layer 16, and finally the back metal is deposited, so that a reverse conducting insulated gate bipolar transistor device structure is formed;

[0095] Figure 1 The figure shows a commonly used reverse conducting insulated gate bipolar transistor chip, which mainly includes an insulated gate bipolar transistor region 8, a fast recovery diode region 4, a fast recovery diode-insulated gate bipolar transistor transition region, an active region-terminal region 10 transition region, a terminal region 10 and a gate pad 11.

[0096] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "circumferential", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0097] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example.

[0098] Although the embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.

Claims

1. A semiconductor device, characterized in that: include: A substrate (1), the substrate (1) having a first main surface (101) and a second main surface (102) opposite to the first main surface (101); A drift layer (2) of a first conductivity type, the drift layer (2) being arranged on the substrate (1) and located between the first main surface (101) and the second main surface (102); a base layer (3) of a second conductivity type, the base layer (3) of the second conductivity type being arranged on a side of the drift layer (2) facing the first main surface (101), the upper surface of the base layer (3) constituting a part of the first main surface (101); a first trench (401), the first trench (401) penetrating the base layer (3) from the first main surface (101) in the thickness direction to reach the drift layer (2); in a top view: the first trench (401) is located in the fast recovery diode region (4) of the semiconductor device (100) and the length direction extends in the first direction of the semiconductor device (100); there are a plurality of first trenches (401), and the plurality of first trenches (401) are arranged at intervals in the second direction of the semiconductor device (100); a contact layer (5) of a second conductive type, the contact layer (5) being arranged on the base layer (3) and the upper surface constituting a part of the first main surface (101), the contact layer (5) comprising a first contact layer (501), the first contact layer (501) being located in the fast recovery diode region (4) and the length direction extending in the first direction, the first contact layer (501) being multiple, the multiple first contact layers (501) being arranged at intervals in the second direction, one first contact layer (501) being arranged between two adjacent first grooves (401), one first contact layer (501) comprising multiple sub-contact layers (5011), the multiple sub-contact layers (5011) being arranged at intervals in the first direction; An interlayer insulating film (6), the interlayer insulating film (6) being arranged above the first main surface (101) and comprising a first interlayer insulating film (601), the first interlayer insulating film (601) being arranged in the fast recovery diode region (4), the first interlayer insulating film (601) being provided with a first contact hole (6011), the first contact hole (6011) extending in a first direction and being a plurality of the first contact holes (6011) being arranged at intervals in the second direction, each of the first contact holes (6011) comprising a plurality of sub-contact holes (60111), the plurality of sub-contact holes (60111) being arranged at intervals in the first direction and corresponding one-to-one with the plurality of sub-contact layers (5011) in the up-down direction, wherein the first direction and the second direction are perpendicular to each other; An emitter metal layer (7), the emitter metal layer (7) being arranged above the interlayer insulating film (6), a portion of the emitter metal layer (7) corresponding to the fast recovery diode region (4) being provided with a first contact protrusion (701), the first contact protrusion (701) passing through the sub-contact hole (60111) and contacting the sub-contact layer (5011).

2. The semiconductor device according to claim 1, wherein: The length of the sub-contact hole (60111) in the first direction is W1, the spacing distance between two adjacent sub-contact holes (60111) in each of the first contact holes (6011) is W2, and W1 and W2 satisfy the relationship: W2≤W1.

3. The semiconductor device according to claim 2, wherein: The two adjacent first contact holes (6011) are respectively set to be a first adjacent contact hole (60112) and a second adjacent contact hole (60113). In the second direction, the projections of the multiple sub-contact holes (60111) in the first adjacent contact hole (60112) overlap with the projections of the multiple sub-contact holes (60111) in the second adjacent contact hole (60113) in a one-to-one correspondence.

4. The semiconductor device according to claim 2, wherein: The two adjacent first contact holes (6011) are respectively set as a first adjacent contact hole (60112) and a second adjacent contact hole (60113). In the second direction, the projections of the multiple sub-contact holes (60111) in the first adjacent contact hole (60112) and the projections of the multiple sub-contact holes (60111) in the second adjacent contact hole (60113) are alternately arranged in sequence in the first direction.

5. The semiconductor device according to claim 1, wherein: The length of the sub-contact hole (60111) in the first direction is W1, the spacing distance between two adjacent sub-contact holes (60111) in each of the first contact holes (6011) is W2, and W1 and W2 satisfy the relationship: W2>W1.

6. The semiconductor device according to claim 5, wherein: The two adjacent first contact holes (6011) are respectively set to be a first adjacent contact hole (60112) and a second adjacent contact hole (60113). In the second direction, the projections of the multiple sub-contact holes (60111) in the first adjacent contact hole (60112) overlap with the projections of the multiple sub-contact holes (60111) in the second adjacent contact hole (60113) in a one-to-one correspondence.

7. The semiconductor device according to claim 5, wherein: The two adjacent first contact holes (6011) are respectively set as a first adjacent contact hole (60112) and a second adjacent contact hole (60113). In the second direction, the projections of the multiple sub-contact holes (60111) in the first adjacent contact hole (60112) and the projections of the multiple sub-contact holes (60111) in the second adjacent contact hole (60113) are alternately arranged in sequence in the first direction.

8. The semiconductor device according to claim 1, wherein: The first groove (401) is a virtual groove, a virtual gate electrode (402) is arranged in the virtual groove, the virtual gate electrode (402) is electrically connected to the emitter metal layer (7) of the semiconductor device (100), the virtual gate electrode (402) is spaced apart from the inner wall of the virtual groove, a virtual gate insulating film (4011) is arranged between the virtual gate electrode (402) and the virtual groove, and the virtual gate electrode (402) is arranged relative to the base layer (3) and the drift layer (2) via the virtual gate insulating film (4011).

9. The semiconductor device according to claim 1, wherein: It also comprises a second trench (801) and an emitter layer (802); the second trench (801) penetrates the emitter layer (802) and the base layer (3) from the first main surface (101) in the thickness direction to reach the drift layer (2); the second trench (801) is located in the insulated gate bipolar transistor region (8) of the semiconductor device (100) and extends in the first direction in the length direction; there are a plurality of second trenches (801), and the plurality of second trenches (801) are arranged at intervals in the second direction of the semiconductor device (100); The contact layer (5) comprises a second contact layer (502), the second contact layer (502) is located in the insulated gate bipolar transistor region (8) and the length direction extends in the first direction, there are a plurality of second contact layers (502), the plurality of second contact layers (502) are arranged at intervals in the second direction, and one second contact layer (502) is arranged between two adjacent second grooves (801); the interlayer insulating film (6) comprises a second interlayer insulating film (602), the second interlayer insulating film (602) is arranged in the insulated gate bipolar transistor, and the second interlayer insulating film ( The emitter metal layer (7) is provided with a second contact hole (6021), and in a top view, the second contact hole (6021) extends in a first direction and is a plurality of the second contact holes (6021), and the plurality of second contact holes (6021) are arranged at intervals in the second direction, and the second contact hole (6021) corresponds to the second contact layer (502) in the vertical direction, and a second contact protrusion (702) is provided on a portion of the emitter metal layer (7) corresponding to the insulated gate bipolar transistor region (8), and the second contact protrusion (702) passes through the second contact hole (6021) and contacts the second contact layer (502).

10. The semiconductor device according to claim 9, wherein: The insulated gate bipolar transistor region (8) and the fast recovery diode region (4) are arranged at intervals to form a transition region (9); the transition region (9) is provided with a connection groove (901); the connection groove (901) penetrates the base layer (3) from the first main surface (101) in the thickness direction to reach the drift layer (2); the connection groove (901) extends in the second direction in the length direction and connects one end of a plurality of the first grooves (401); the semiconductor device (100) is not provided with the contact layer (5) corresponding to the transition region (9); The interlayer insulating film (6) comprises a third interlayer insulating film (603), a third contact hole (6031) is arranged on the third interlayer insulating film (603), and in a top view, the third contact hole (6031) extends in the second direction and corresponds to at least part of the connecting groove (901) in the upper and lower directions, and a third contact protrusion (704) is arranged on the part of the emitter metal layer (7) corresponding to the transition region (9), and the third contact protrusion (704) penetrates the third contact hole (6031) and contacts the virtual gate electrode (402) of the connecting groove (901).

11. The semiconductor device according to claim 10, wherein: The third contact hole (6031) is spaced apart from the first contact hole (6011) and the second contact hole (6021) respectively.

12. The semiconductor device according to claim 9, wherein: The second groove (801) is an active groove, an active gate electrode (803) is arranged in the active groove, the active gate electrode (803) is electrically connected to the gate pad (11) of the semiconductor device (100), the active gate electrode (803) is arranged with an interval from the inner wall of the active groove, an active gate insulating film (8011) is arranged between the active gate electrode (803) and the active groove, and the active gate electrode (803) is arranged relative to the emitter layer (802), the base layer (3) and the drift layer (2) via the active gate insulating film (8011).

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