Power-down discharge circuit, power-down discharge method, and display panel

Abstract

The application discloses a power-off discharging circuit, a power-off discharging method and a display panel, and relates to the technical field of display. The power-off discharging circuit comprises a signal module and a discharging module. The signal module comprises a high-level signal line and a signal output unit. The signal output unit is connected with a power supply system through the high-level signal line. The discharging module is connected with the high-level signal line. The signal output unit is connected with a gate driving unit. The gate driving unit comprises a maintaining unit and a to-be-released unit. The high-level signal line provides a high-level voltage of a preset signal for the signal output unit. The signal output unit outputs the preset signal to the gate driving unit. The discharging module adjusts the high-level voltage and discharges the to-be-released unit when power-off. In the above manner, the GOA unit in the plane is discharged, the abnormal display of a picture during power-off of switching on and off is avoided, and the display effect is improved.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to a power-down discharge circuit, a power-down discharge method, and a display panel. Background Technology

[0002] Currently, in the display panel, the Gate on Array (GOA) unit, during power-on and power-off, all input level signals at time point W1 (reference)... Figure 1 When the signal is simultaneously pulled high, the TFT (Thin Film Transistor) controlling the horizontal switch will be turned on, discharging the TFT and the bootstrap capacitor. However, due to the simultaneous change of the signal, the TFT in the discharge circuit cannot reach the voltage difference condition and cannot be turned on, so the TFT and bootstrap capacitor that need to be discharged cannot be completely discharged, resulting in residual charge, causing abnormal switching on and off, and abnormal display on the display panel. Summary of the Invention

[0003] The main objective of this invention is to provide a power-down discharge circuit, a power-down discharge method, and a display panel, aiming to solve the technical problem in the prior art where the TFT and bootstrap capacitor of the GOA unit cannot be completely discharged when the power is turned on or off, resulting in residual charge and abnormal screen display.

[0004] To achieve the above objectives, the present invention proposes a power-down discharge circuit, which includes a signal module and a discharge module. The signal module includes a high-level signal line and a signal output unit. The signal output unit is connected to a power supply system through the high-level signal line. The discharge module is connected to the high-level signal line. The signal output unit is connected to a gate driving unit. The gate driving unit includes a sustaining unit and a release unit. The release unit includes a bootstrap capacitor, a first thin-film transistor, and a second thin-film transistor. The first terminal of the bootstrap capacitor is connected to the gate terminal of the first thin-film transistor and the source terminal of the second thin-film transistor, respectively. The second terminal of the bootstrap capacitor is connected to the drain terminal of the first thin-film transistor. A clock signal is connected to the source terminal of the first thin-film transistor, and a low-level signal is connected to the drain terminal of the second thin-film transistor. The gate terminal of the second thin-film transistor is connected to the sustaining unit.

[0005] The high-level signal line is used to provide a high-level voltage of a preset signal to the signal output unit, and the preset signal includes at least the clock signal and the input signal of the sustaining unit;

[0006] The signal output unit is used to output the preset signal to the gate driving unit;

[0007] The discharge module is used to adjust the high-level voltage when the power is off, so as to turn on the second thin-film transistor and discharge the unit to be released.

[0008] Optionally, the discharge module includes a first discharge module and a second discharge module, the high-level signal line includes a first high-level signal line and a second high-level signal line, the first discharge module is connected to the first high-level signal line and the signal output unit respectively, and the second discharge module is connected to the second high-level signal line and the signal output unit respectively;

[0009] The first high-level signal line is used to provide a first high-level voltage for the input signal of the sustaining unit;

[0010] The first discharge module is used to adjust the first high-level voltage so that the voltage at the gate terminal of the second thin-film transistor is adjusted.

[0011] The second high-level signal line is used to provide a second high-level voltage for the clock signal;

[0012] The second discharge module is used to adjust the second high-level voltage so that the voltage at the source terminal of the second thin-film transistor is adjusted.

[0013] Optionally, the first discharge module includes a first switching unit and a first discharge adjustment unit connected together. The first switching unit is connected to the first high-level signal line, and the first discharge adjustment unit is connected to the signal output unit. The second discharge module includes a second discharge adjustment unit, which is connected to the second high-level signal line and the signal output unit respectively. The first switching unit is open when powered off and closed when not powered off.

[0014] Optionally, the first discharge adjustment unit includes a first sustaining capacitor, a second sustaining capacitor, a third sustaining capacitor, and a first grounding resistor connected in parallel. The first switching unit is connected to the first terminal of the first sustaining capacitor, and the second terminal of the first grounding resistor is grounded.

[0015] The second discharge adjustment unit includes a fourth sustaining capacitor, a fifth sustaining capacitor, a sixth sustaining capacitor, and a second grounding resistor connected in parallel. The second terminal of the second grounding resistor is grounded. The first sustaining capacitor, the second sustaining capacitor, and the third sustaining capacitor are larger than the fourth sustaining capacitor, the fifth sustaining capacitor, and the sixth sustaining capacitor. The first grounding resistor is larger than the second grounding resistor.

[0016] Optionally, the first discharge module includes a first switch unit, a first discharge adjustment unit, and a second switch unit connected in sequence. The first switch unit is connected to the first high-level signal line, and the second switch unit is connected to the signal output unit. The second discharge module includes a second discharge adjustment unit, which is connected to the second high-level signal line and the signal output unit respectively. The first switch unit and the second switch unit are disconnected when powered off, and the first switch unit and the second switch unit are closed when not powered off.

[0017] Optionally, the first discharge adjustment unit includes a first sustaining capacitor, a second sustaining capacitor, a third sustaining capacitor, and a first grounding resistor connected in parallel. The first terminal of the first sustaining capacitor is connected to the first switching unit and the second switching unit, respectively, and the second terminal of the first grounding resistor is grounded.

[0018] The second discharge adjustment unit includes a fourth sustaining capacitor, a fifth sustaining capacitor, a sixth sustaining capacitor, and a second grounding resistor connected in parallel, with the second end of the second grounding resistor grounded.

[0019] Optionally, the discharge module includes a discharge unit and a switching unit. The discharge unit is connected to the high-level signal line, and the discharge unit is connected to the low-level signal line and the signal output unit respectively through the switching unit.

[0020] The switching unit is used to close when the power is off, so as to discharge the pixel capacitor in the gate driving unit;

[0021] The switching unit is also used to turn off after the pixel capacitor has discharged, so as to turn on the second thin-film transistor.

[0022] Optionally, the discharge unit includes a holding capacitor and a grounding resistor connected in parallel, with the first end of the grounding resistor connected to the switching unit and the second end of the grounding resistor grounded.

[0023] To achieve the above objectives, the present invention also proposes a power-off discharge method, the power-off discharge method comprising:

[0024] The high-level signal line provides a high-level voltage of a preset signal to the signal output unit. The preset signal includes at least a clock signal and an input signal of the sustaining unit in the gate drive unit.

[0025] The signal output unit outputs the preset signal to the gate driving unit;

[0026] When the discharge unit is powered off, it adjusts the high-level voltage to discharge the unit to be released in the gate driving unit.

[0027] To achieve the above objectives, the present invention also proposes a display panel, including the power-down discharge circuit described above, and applying the steps of the power-down discharge method described above.

[0028] In this invention, the power-down discharge circuit includes a signal module and a discharge module. The signal module includes a high-level signal line and a signal output unit. The signal output unit is connected to the power supply system via the high-level signal line. The discharge module is connected to the high-level signal line and the signal output unit is connected to the gate driving unit. The gate driving unit includes a sustaining unit and a release unit. The release unit includes a bootstrap capacitor, a first thin-film transistor, and a second thin-film transistor. The first terminal of the bootstrap capacitor is connected to the gate terminal of the first thin-film transistor and the source terminal of the second thin-film transistor, respectively. The second terminal of the bootstrap capacitor is connected to the drain terminal of the first thin-film transistor. A clock signal is connected to the source terminal of the first thin-film transistor, and a low-level signal is connected to the drain terminal of the second thin-film transistor. The gate terminal of the second thin-film transistor is connected to the sustaining unit. The high-level signal line provides a high-level voltage of a preset signal to the signal output unit. The signal output unit outputs the preset signal to the gate driving unit. When the power is off, the discharge module adjusts the high-level voltage to turn on the second thin-film transistor and discharge the release unit. Because the TFT and bootstrap capacitor of the GOA unit cannot be completely discharged when the power is turned on or off, residual charge is caused, resulting in abnormal screen display. This invention sets up a discharge module to adjust the voltage of the input signal of the in-plane GOA unit, turn on the second thin film transistor, realize the discharge of residual charge in the GOA unit, avoid screen display abnormalities caused by false triggering when the power is turned on or off, and improve the display effect. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0030] Figure 1 A schematic diagram of the power-down timing of one embodiment of the power-down discharge circuit of the present invention;

[0031] Figure 2 This is a schematic diagram of the structure of the first embodiment of the power-off discharge circuit of the present invention;

[0032] Figure 3 This is a schematic diagram of the gate driving unit of one embodiment of the power-down discharge circuit of the present invention.

[0033] Figure 4 This is a schematic diagram of the second embodiment of the power-down discharge circuit of the present invention;

[0034] Figure 5 This is a schematic diagram of the third embodiment of the electric discharge circuit of the present invention;

[0035] Figure 6 This is a detailed structural diagram of a discharge module that controls the power-down speed through capacitors and resistors, according to one embodiment of the power-down discharge circuit of the present invention.

[0036] Figure 7 This is a schematic diagram of the VGH power-down timing of one embodiment of the power-down discharge circuit of the present invention;

[0037] Figure 8 This is a schematic diagram of the fourth embodiment of the power-down discharge circuit of the present invention;

[0038] Figure 9 This is a detailed structural diagram of a discharge module whose output voltage is adjusted by a switch, according to one embodiment of the power-down discharge circuit of the present invention.

[0039] Figure 10 This is a schematic diagram of the fifth embodiment of the electric discharge circuit of the present invention;

[0040] Figure 11 This is a detailed structural diagram of a single discharge module in the first embodiment of the power-down discharge circuit of the present invention.

[0041] Figure 12 This is a schematic flowchart of the first embodiment of the electric discharge method of the present invention.

[0042] Explanation of icon numbers:

[0043] label name label name 10 signal module 203 Discharge unit 20 Discharge module 204 Switching unit 30 Power System 401 Maintenance unit 40 Gate drive unit 402 Units to be released 101 high-level signal line 2011 First Switching Unit 102 Signal output unit 2012 First Discharge Adjustment Unit 201 First discharge module 2013 Second switching unit 202 Second discharge module 2021 Second Discharge Adjustment Unit

[0044] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0045] It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0046] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0047] It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present invention are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indication will also change accordingly.

[0048] Furthermore, the use of terms such as "first" and "second" in this invention is for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of that feature. Additionally, the technical solutions of the various embodiments can be combined with each other, but only on the basis of being achievable by those skilled in the art. When the combination of technical solutions is contradictory or impossible to implement, such a combination of technical solutions should be considered non-existent and not within the scope of protection claimed by this invention.

[0049] Example 1

[0050] Reference Figure 2 , Figure 2 This is a schematic diagram of the first embodiment of the power-down discharge circuit of the present invention. The present invention proposes a first embodiment of the power-down discharge circuit.

[0051] In this embodiment, the power-down discharge circuit includes a signal module 10 and a discharge module 20. The signal module 10 includes a high-level signal line 101 and a signal output unit 102. The signal output unit 102 is connected to the power supply system 30 through the high-level signal line 101. The discharge module 20 is connected to the high-level signal line 101. The signal output unit 102 is connected to the gate driving unit 40.

[0052] It should be noted that the gate driving unit 40 is the GOA unit in the display panel. In this embodiment, the gate driving unit includes a sustaining unit 401 and a release unit 402. The release unit 402 includes a bootstrap capacitor C, a first thin-film transistor T1, and a second thin-film transistor T2. The first end of the bootstrap capacitor C is connected to the gate end of the first thin-film transistor T1 and the source end of the second thin-film transistor T2, respectively. The second end of the bootstrap capacitor C is connected to the drain end of the first thin-film transistor T1. The source end of the first thin-film transistor T1 is connected to a clock signal, and the drain end of the second thin-film transistor T2 is connected to a low-level signal. The gate end of the second thin-film transistor is connected to the sustaining unit 401.

[0053] It is understood that the high-level signal line 101 is used to provide a high-level voltage of a preset signal to the signal output unit 102. The preset signal includes at least a clock signal and an input signal to the sustain unit 401. The signal output unit 102 is used to output the preset signal to the gate drive unit 40. The sustain unit 401 is the LC sustain unit.

[0054] It should be understood that the power supply system 30 can provide voltages for all signals to the signal output unit 102, which can be either high-level voltages or low-level voltages. In this embodiment, the high-level signal line 101, i.e., the VGH signal line, can provide the required high-level voltage (VGH voltage) to the signal transmission unit 102. The preset signal is the signal that receives the VGH voltage in this embodiment, such as: clock signal (CK signal), input signal of the sustaining unit (LC signal), STV signal, etc. This embodiment does not limit this.

[0055] It should be noted that the discharge module 20 is used to adjust the high-level voltage when the power is off so that the second thin-film transistor T2 is turned on to discharge the release unit 402.

[0056] Understandably, this refers to the row switch of the control panel of the first thin-film transistor T1. (Reference) Figure 1 When the power is switched on or off, all input level signals are simultaneously pulled high at time point W1. The first thin-film transistor T1 and other TFTs are turned on, discharging with the bootstrap capacitor. However, due to the simultaneous change of the input signals, the second thin-film transistor T2 in the release unit 402 cannot reach the voltage difference condition and cannot be turned on. This results in the first thin-film transistor T1 and other TFTs and the bootstrap capacitor not being able to completely discharge, leading to residual charge and causing abnormal power-on / off display, resulting in abnormal image display on the display panel. The charge at point PU (gate terminal of the first thin-film transistor T1) can be released by connecting to the low-level signal line (VGL signal line) through the second thin-film transistor T2. Therefore, this embodiment uses the second thin-film transistor T2 to control charge release. The second thin-film transistor T2 can be controlled by the sustaining unit 401. By adjusting the voltage of the input signal of the sustaining unit 401 and the voltage of the input signal (CK signal) of the first thin-film transistor T1, the second thin-film transistor T2 is turned on, and the residual charge is released.

[0057] It should be understood that when the second thin-film transistor T2 is turned on, the difference between the gate voltage and the source voltage needs to be greater than the turn-on voltage (VGS) of the second thin-film transistor T2. The turn-on voltage of the second thin-film transistor T2 is usually 2V to 6V, which needs to be determined according to the actual situation.

[0058] like Figure 3The schematic diagram of the gate driving unit shown illustrates a 10T1C architecture for gate driving unit 40 (a sustaining unit 401 is only required with an architecture of 7T1C or higher). During power-down, at time W1, all input GOA unit signals are pulled high, and T1, T3, and T4 are turned on, discharging the TFT and bootstrap capacitor C. At time W2, the input VGH voltage drops to the threshold voltage of the TFT device, and T1, T3, and T4 are turned off. Since the input signals are simultaneously pulled high during power-down, T2 does not reach the voltage difference condition and cannot be turned on, preventing the TFT and bootstrap capacitor from discharging. Therefore, by turning on T2, the charge at point PU can be released through T2 connected to the VGL signal line, avoiding display abnormalities caused by residual charge. Other suitable architectures can also be used for the gate driving unit; this embodiment does not limit this.

[0059] It should be noted that if only one sustaining unit 401 is set, the second thin-film transistor T2 will always remain in the conducting state, which is prone to wear and tear. Therefore, two sustaining units 401 can be set in the gate driving unit 40. One sustaining unit 401 is input with VGH voltage to realize the conduction of the second thin-film transistor T2, and the other sustaining unit 401 is input with VGL voltage to realize the turn-off of the second thin-film transistor T2, thereby increasing reliability.

[0060] It is understood that the thin-film transistor used in this embodiment may be an indium gallium zinc oxide (IGZO) TFT, and correspondingly, the display panel may be an IGZO panel. This embodiment does not limit this.

[0061] In this embodiment, the gate driving unit 40 is the GOA unit in the display panel. In this embodiment, the gate driving unit includes a sustaining unit 401 and a release unit 402. The release unit 402 includes a bootstrap capacitor C, a first thin-film transistor T1, and a second thin-film transistor T2. The first end of the bootstrap capacitor C is connected to the gate end of the first thin-film transistor T1 and the source end of the second thin-film transistor T2, respectively. The second end of the bootstrap capacitor C is connected to the drain end of the first thin-film transistor T1. The source end of the first thin-film transistor T1 is connected to a clock signal, and the drain end of the second thin-film transistor T2 is connected to a low-level signal. The gate end of the second thin-film transistor is connected to the sustaining unit 401. The high-level signal line 101 is used to provide a high-level voltage of a preset signal to the signal output unit 102. The preset signal includes at least a clock signal and an input signal of the sustaining unit 401. The signal output unit 102 is used to output the preset signal to the gate driving unit 40. The discharge module 20 is used to adjust the high-level voltage when the power is off so that the second thin-film transistor T2 is turned on to discharge the release unit 402. In this embodiment, a discharge module is set to adjust the voltage of the input signal of the in-plane GOA unit, turn on the second thin-film transistor T2, realize the discharge of residual charge in the GOA unit, avoid abnormal screen display caused by residual charge when powering on and off, and improve the display effect.

[0062] Example 2

[0063] Reference Figure 4 , Figure 4 This is a schematic diagram of the first embodiment of the power-down discharge circuit of the present invention. The present invention proposes a second embodiment of the power-down discharge circuit.

[0064] Based on the first embodiment described above, in this embodiment, the discharge module 20 includes a first discharge module 201 and a second discharge module 202, and the high-level signal line 101 includes a first high-level signal line (VGH1 signal line) and a second high-level signal line (VGH2 signal line). The first discharge module 201 is connected to the first high-level signal line VGH1 and the signal output unit 102, respectively, and the second discharge module 202 is connected to the second high-level signal line VGH2 and the signal output unit 102, respectively.

[0065] It should be noted that in this embodiment, the output unit 102 is provided with VGH voltage through two high-level signal lines, and each high-level signal line 101 is equipped with a discharge module.

[0066] Understandably, the first high-level signal line is used to provide a first high-level voltage to the input signal of the sustaining unit 401; the first discharge module 201 is used to adjust the first high-level voltage so that the voltage at the gate terminal of the second thin-film transistor T2 is adjusted; the second high-level signal line is used to provide a second high-level voltage to the clock signal; and the second discharge module 202 is used to adjust the second high-level voltage so that the voltage at the source terminal of the second thin-film transistor T2 is adjusted.

[0067] It should be understood that, in addition to the input signal of the maintenance unit 401, the first high-level signal line can also provide a first high-level voltage for other signals, such as the STV signal.

[0068] It should be noted that the first discharge module 201 and the second discharge module 202 can adjust the voltage at the gate and source terminals of the second thin-film transistor T2, respectively, so that the second thin-film transistor T2 can be turned on, thereby pulling down the voltage at the gate terminal of the first thin-film transistor T1, releasing the residual charge, and avoiding display abnormalities.

[0069] In this embodiment, the discharge module 20 includes a first discharge module 201 and a second discharge module 202. The high-level signal line 101 includes a first high-level signal line (VGH1 signal line) and a second high-level signal line (VGH2 signal line). The first discharge module 201 is connected to the first high-level signal line VGH1 and the signal output unit 102, respectively. The second discharge module 202 is connected to the second high-level signal line VGH2 and the signal output unit 102, respectively. The first high-level signal line is used to provide a first high-level voltage for the input signal of the sustaining unit 401. The first discharge module 201 is used to adjust the first high-level voltage so that the voltage at the gate terminal of the second thin-film transistor T2 is adjusted. The second high-level signal line is used to provide a second high-level voltage for the clock signal. The second discharge module 202 is used to adjust the second high-level voltage so that the voltage at the source terminal of the second thin-film transistor T2 is adjusted. This embodiment sets up two VGH channels and sets up discharge modules for each channel. The voltage at the gate and source terminals of the second thin-film transistor T2 can be adjusted to make it conduct, thereby discharging the residual charge in the GOA unit and avoiding abnormal screen display caused by residual charge when the power is turned on or off, thus improving the display effect.

[0070] Example 3

[0071] Reference Figure 5 , Figure 5 This is a schematic diagram of the third embodiment of the power-down discharge circuit of the present invention. The present invention proposes a third embodiment of the power-down discharge circuit.

[0072] Based on the second embodiment described above, in this embodiment, the first discharge module 201 includes a first switch unit 2011 and a first discharge adjustment unit 2012 connected together. The first switch unit 2011 is connected to a first high-level signal line, and the first discharge adjustment unit 2012 is connected to a signal output unit 102. The second discharge module 202 includes a second discharge adjustment unit 2021, which is connected to a second high-level signal line and a signal output unit 102 respectively. The first switch unit 2011 is open when powered off and closed when not powered off.

[0073] It should be noted that during normal display, the first switch unit 2011 is closed, and the first discharge module 201 and the second discharge module 202 normally provide the preset signal VGH voltage. Upon power-down, the first switch unit 2011 is open. In order to turn on the second thin-film transistor T2, the VGH voltage provided by the first discharge module 201 needs to be greater than the VGH voltage provided by the second discharge module 202. In other words, the first discharge module 201 needs to power down slower than the second discharge module 202.

[0074] It is understood that the first switching unit 2011 can be a switching element or a unidirectional diode, and this embodiment does not limit it.

[0075] Furthermore, such as Figure 6 As shown, the first discharge adjustment unit 2012 includes a first sustaining capacitor C1, a second sustaining capacitor C2, a third sustaining capacitor C3 and a first grounding resistor R1 connected in parallel. The first switching unit 2011 is connected to the first terminal of the first sustaining capacitor C1, and the second terminal of the first grounding resistor R1 is grounded. The second discharge adjustment unit 2021 includes a fourth sustaining capacitor C4, a fifth sustaining capacitor C5, a sixth sustaining capacitor C6 and a second grounding resistor R2 connected in parallel. The second terminal of the second grounding resistor R2 is grounded. The first sustaining capacitor C1, the second sustaining capacitor C2 and the third sustaining capacitor C3 are greater than the fourth sustaining capacitor C4, the fifth sustaining capacitor C5 and the sixth sustaining capacitor C6. The first grounding resistor R1 is greater than the second grounding resistor R2.

[0076] It should be understood that the power-off speed of the first discharge module 201 and the second discharge module 202 can be controlled by adjusting the size of the sustaining capacitor and the grounding resistor. In this embodiment, the first sustaining capacitor C1, the second sustaining capacitor C2, and the third sustaining capacitor C3 of the first discharge module 201 are larger than the fourth sustaining capacitor C4, the fifth sustaining capacitor C5, and the sixth sustaining capacitor C6 of the second discharge module 202, and the first grounding resistor R1 of the first discharge module 201 is larger than the second grounding resistor R2 of the second discharge module 202.

[0077] It should be noted that since different TFTs have different VGS voltages (typically in the range of 2V to 6V), the size of the holding capacitor and the grounding resistor need to be adjusted according to the actual VGS voltage, so that the first discharge module 201 powers down slower than the second discharge module 202. Assuming the TFT's VGS voltage is 2V and the VGH voltage is 25V... Figure 7 This is a schematic diagram of the VGH power-down timing. VGH1 and VGH2 represent the voltages input to the display panel by the first discharge module 201 and the second discharge module 202, respectively. Ignoring the impedance and capacitive reactance of the display panel, according to the RC discharge formulas Vt = VGH(et / RC) and T = RCln(Vgh / Vt), the complete discharge time of the display panel, i.e., VGH2 (25V) dropping to 5V, needs to be greater than 10ms. Substituting these values ​​into the formulas, the RC of VGH2 is 0.0062. Therefore, the second grounding resistor R2 can be taken as 6.2KΩ, and the fourth sustaining capacitor C4, the fifth sustaining capacitor C5, and the sixth sustaining capacitor C6 can be taken as 1uF. Figure 6 In the power-down sequence, both VGH1 and VGH2 initially start from 25V. At 1ms, the voltage of VGH1 is 2V higher than that of VGH2, so the voltage of VGH2 is 21.3V and the voltage of VGH1 is 23.3V. Substituting into the RC discharge formula, the RC of VGH1 is 0.0093. Therefore, the first grounding resistor R2 can be taken as 4.65KΩ, and the first holding capacitor C1, the second holding capacitor C2, and the third holding capacitor C3 can be taken as 2uF.

[0078] In this embodiment, the first discharge module 201 includes a first switch unit 2011 and a first discharge adjustment unit 2012 connected together. The first switch unit 2011 is connected to a first high-level signal line, and the first discharge adjustment unit 2012 is connected to a signal output unit 102. The second discharge module 202 includes a second discharge adjustment unit 2021, which is connected to a second high-level signal line and a signal output unit 102 respectively. The first switch unit 2011 is open when powered off and closed when not powered off. In this embodiment, by adjusting the size of the maintaining capacitor and the grounding resistor in the first discharge module 201 and the second discharge module 202, the first discharge module 201 discharges slower than the second discharge module 202, so that the second thin-film transistor T2 can be turned on, realizing the discharge of residual charge in the GOA unit, avoiding abnormal screen display caused by residual charge during power-on and power-off, and improving the display effect.

[0079] Example 4

[0080] Reference Figure 8 , Figure 8 This is a schematic diagram of the fourth embodiment of the power-down discharge circuit of the present invention. The present invention proposes a fourth embodiment of the power-down discharge circuit.

[0081] Based on the second embodiment described above, in this embodiment, the first discharge module 201 includes a first switch unit 2011, a first discharge adjustment unit 2012, and a second switch unit 2013 connected in sequence. The first switch unit 2011 is connected to a first high-level signal line, and the second switch unit 2013 is connected to a signal output unit 102. The second discharge module 202 includes a second discharge adjustment unit 2021, which is connected to a second high-level signal line and a signal output unit 102, respectively. The first switch unit 2011 and the second switch unit 2013 are disconnected when powered off, and the first switch unit 2011 and the second switch unit 2013 are closed when not powered off.

[0082] It should be noted that this embodiment includes a first switching unit 2011 and a second switching unit 2013. During normal display, both the first switching unit 2011 and the second switching unit 2013 are closed, providing the preset signal VGH voltage. During power-down, both the first switching unit 2011 and the second switching unit 2013 are open. In order to turn on the second thin-film transistor T2, the VGH voltage provided by the first discharge module 201 needs to be greater than the VGH voltage provided by the second discharge module 202.

[0083] It is understandable that in the third embodiment described above, the power-down speed is controlled by adjusting the size of the holding capacitor and the grounding resistor, thereby adjusting the VGH voltage provided by the first discharge module 201 and the second discharge module 202 to turn on the second thin film transistor T2. However, the size of the holding capacitor and the grounding resistor need to be adjusted according to the actual situation, which is quite cumbersome. This embodiment achieves this through switch control, reducing the complexity of operation.

[0084] Furthermore, such as Figure 9 As shown, the first discharge adjustment unit 2012 includes a first sustaining capacitor C1, a second sustaining capacitor C2, a third sustaining capacitor C3 and a first grounding resistor R1 connected in parallel. The first terminal of the first sustaining capacitor C1 is connected to the first switching unit 2011 and the second switching unit 2013 respectively, and the second terminal of the first grounding resistor R1 is grounded. The second discharge adjustment unit 2021 includes a fourth sustaining capacitor C4, a fifth sustaining capacitor C5 and a sixth sustaining capacitor C6 connected in parallel, and a second grounding resistor R2. The second terminal of the second grounding resistor is grounded.

[0085] It should be understood that the first switching unit 2011 can be a switching element or a unidirectional diode, and this embodiment is not limited in this respect. The second switching unit 2013 can be a bipolar transistor, such as a PNP transistor, see reference. Figure 9The base of the bipolar transistor is connected to the second high-level signal line, the emitter of the bipolar transistor is connected to the first end of the first grounding resistor R1, and the collector of the bipolar transistor is connected to the signal output module 102.

[0086] It should be noted that the base voltage of the bipolar transistor is the VGH2 voltage provided by the second discharge adjustment unit 2021. When the VGH1 voltage of the emitter is greater than the VGH2 voltage, the difference reaches the turn-on voltage of the bipolar transistor, and the second switching unit 2013 is turned off. At this time, the VGH1 voltage value output by the first discharge adjustment unit 2012 through the second switching unit 2013 will be greater than the VGH2 voltage value output by the second discharge adjustment unit 2021, so that the second thin film transistor T2 can be turned on.

[0087] In this embodiment, the first discharge module 201 includes a first switch unit 2011, a first discharge adjustment unit 2012, and a second switch unit 2013 connected in sequence. The first switch unit 2011 is connected to a first high-level signal line, and the second switch unit 2013 is connected to a signal output unit 102. The second discharge module 202 includes a second discharge adjustment unit 2021, which is connected to a second high-level signal line and a signal output unit 102. The first switch unit 2011 and the second switch unit 2013 are disconnected when powered off, and closed when not powered off. This embodiment uses switch control to ensure that, when powered off, the voltage output by the first discharge module 201 is greater than the voltage output by the second discharge module 202, allowing the second thin-film transistor T2 to conduct. This discharges residual charge in the GOA unit, preventing abnormal screen display caused by residual charge during power-on / off, improving display quality, and reducing the complexity of power-off operations.

[0088] Example 5

[0089] Reference Figure 10 , Figure 10 This is a schematic diagram of the fifth embodiment of the power-down discharge circuit of the present invention. The present invention proposes a fifth embodiment of the power-down discharge circuit.

[0090] Based on the first embodiment described above, in this embodiment, the discharge module 20 includes a discharge unit 203 and a switch unit 204. The discharge unit 203 is connected to a high-level signal line, and the discharge unit 203 is connected to a low-level signal line and a signal output unit 102 respectively through the switch unit 204.

[0091] It should be noted that the switching unit 204 is used to close when the power is off so that the pixel capacitor in the gate driving unit 40 can be discharged; the switching unit 204 is also used to turn off after the pixel capacitor has finished discharging so that the second thin film transistor T2 can be turned on.

[0092] It is understood that in this embodiment, a high-level signal line is provided to supply VGH voltage to the output unit 102. The discharge unit 203 is connected to the VGL signal line through the switching unit 204.

[0093] Furthermore, such as Figure 11 As shown, the discharge unit 203 includes a holding capacitor and a grounding resistor R3 connected in parallel. The first end of the grounding resistor is connected to the switching unit, and the second end of the grounding resistor is grounded.

[0094] It should be understood that multiple sustaining capacitors can be provided in the discharge unit 203; in this embodiment, three sustaining capacitors C7, C8, and C9 are provided. A resistor R4 is provided on the low-level signal line.

[0095] It should be noted that when power is off, the charge release includes the charge release of the pixel capacitor and the charge release of the GOA unit. Currently, the pixel capacitor release first turns on the TFTs (such as the first thin film transistor T1) that control the pixel capacitors of all GOA units in the plane.

[0096] Understandably, in this embodiment, when the panel is displaying normally, the switch unit 204 is open, and the VGL signal line outputs a normal negative voltage to the panel. When powered off, the switch unit 204 is closed, pulling up the voltage output by the VGL signal line, and the pixel capacitor begins to discharge. After the pixel capacitor has finished discharging its charge, the switch unit 204 is open, pulling the VGL voltage provided by the VGL signal line down again, so that the second thin-film transistor T2 is turned on, and the PU point charge can begin to discharge.

[0097] In this embodiment, the discharge module 20 includes a discharge unit 203 and a switching unit 204. The discharge unit 203 is connected to a high-level signal line, and the discharge unit 203 is connected to a low-level signal line and a signal output unit 102 via the switching unit 204. The switching unit 204 is used to close when the power is off, so that the pixel capacitor in the gate driving unit 40 can be discharged. The switching unit 204 is also used to turn off after the pixel capacitor has finished discharging, so that the second thin-film transistor T2 can be turned on. This embodiment sets up a discharge unit on the basis of the original VGH voltage output, so that the second thin-film transistor T2 can be turned on after the pixel capacitor has finished discharging, thereby discharging the residual charge in the GOA unit, avoiding abnormal screen display caused by residual charge when the power is turned on and off, and improving the display effect.

[0098] Example 6

[0099] Reference Figure 12 , Figure 12 This is a schematic flowchart of the first embodiment of the electric discharge method of the present invention. The present invention proposes a first embodiment of the electric discharge method.

[0100] In this embodiment, the power-down discharge method includes:

[0101] Step S10: The high-level signal line provides a high-level voltage of a preset signal to the signal output unit. The preset signal includes at least a clock signal and an input signal of the sustaining unit in the gate drive unit.

[0102] It should be noted that this embodiment is applied to the above-mentioned power-down discharge circuit. The power-down discharge circuit includes a signal module and a discharge module. The signal module includes a high-level signal line and a signal output unit. The signal output unit is connected to the power supply system through the high-level signal line. The discharge module is connected to the high-level signal line, and the signal output unit is connected to the gate drive unit. For the specific structure, please refer to [reference needed]. Figures 1 to 10 .

[0103] It is understood that the power supply system can provide voltages for all signals to the signal output unit, which can be either high-level or low-level voltages. In this embodiment, the high-level signal line, namely the VGH signal line, can provide the required VGH voltage to the signal transmission unit. The preset signal is the signal that receives the VGH voltage in this embodiment, such as: clock signal (CK signal), input signal of the sustaining unit (LC signal), STV signal, etc. This embodiment does not limit this.

[0104] Step S20: The signal output unit outputs the preset signal to the gate driving unit.

[0105] In step S30, when the discharge unit is powered off, it adjusts the high-level voltage to discharge the unit to be released in the gate driving unit.

[0106] It should be understood that the release unit includes a bootstrap capacitor, a first thin-film transistor (TFT), and a second TFT. When the power is turned on or off, the input signal is simultaneously pulled high, preventing the second TFT in the release unit from reaching the voltage difference condition and thus preventing it from conducting. This results in the first TFT and bootstrap capacitor not fully discharging, leaving residual charge and causing abnormal image display on the power-on / off screen. The charge at the PU point (gate terminal of the first TFT) can be released by connecting the second TFT to a low-level signal line (VGL signal line). Therefore, this embodiment uses the second TFT to control charge release. By adjusting the voltage of the holding unit input signal and the voltage of the first TFT input signal (CK signal), the second TFT is turned on to release the residual charge, thereby preventing abnormal image display.

[0107] In this embodiment, the high-level signal line provides a high-level voltage of a preset signal to the signal output unit. The signal output unit outputs the preset signal to the gate driving unit. When the power is off, the discharge module adjusts the high-level voltage to discharge the unit to be released, thereby turning on the second thin-film transistor, reducing the voltage at the gate of the first thin-film transistor, and keeping the first thin-film transistor off. Since the TFT and bootstrap capacitor of the GOA unit cannot be completely discharged when the power is turned on and off, residual charge results in abnormal screen display. In this embodiment, the discharge module adjusts the voltage of the input signal of the in-plane GOA unit to turn on the second thin-film transistor, thereby discharging the residual charge in the GOA unit, avoiding abnormal screen display caused by residual charge when the power is turned on and off, and improving the display effect.

[0108] Furthermore, embodiments of the present invention also propose a display panel, the display panel including the power-down discharge circuit described above, and applying the steps of the power-down discharge circuit described above.

[0109] The above are merely preferred embodiments of the present invention and do not limit the scope of the patent. Any equivalent structural or procedural transformations made based on the description and drawings of the present invention, or direct or indirect applications in other related technical fields, are similarly included within the scope of patent protection of the present invention.

Claims

1. A power-down discharge circuit, characterized in that, The power-down discharge circuit includes a signal module and a discharge module. The signal module includes a high-level signal line and a signal output unit. The signal output unit is connected to the power supply system through the high-level signal line. The discharge module is connected to the high-level signal line. The signal output unit is connected to the gate driving unit. The gate driving unit includes a sustaining unit and a release unit. The release unit includes a bootstrap capacitor, a first thin-film transistor, and a second thin-film transistor. The first terminal of the bootstrap capacitor is connected to the gate terminal of the first thin-film transistor and the source terminal of the second thin-film transistor, respectively. The second terminal of the bootstrap capacitor is connected to the drain terminal of the first thin-film transistor. The source terminal of the first thin-film transistor is connected to a clock signal, and the drain terminal of the second thin-film transistor is connected to a low-level signal. The gate terminal of the second thin-film transistor is connected to the sustaining unit. The high-level signal line is used to provide a high-level voltage of a preset signal to the signal output unit, and the preset signal includes at least the clock signal and the input signal of the sustaining unit; The signal output unit is used to output the preset signal to the gate driving unit; The discharge module is used to adjust the high-level voltage when the power is off, so as to turn on the second thin-film transistor and discharge the unit to be released.

2. The power-down discharge circuit as described in claim 1, characterized in that, The discharge module includes a first discharge module and a second discharge module. The high-level signal line includes a first high-level signal line and a second high-level signal line. The first discharge module is connected to the first high-level signal line and the signal output unit, respectively. The second discharge module is connected to the second high-level signal line and the signal output unit, respectively. The first high-level signal line is used to provide a first high-level voltage for the input signal of the sustaining unit; The first discharge module is used to adjust the first high-level voltage so that the voltage at the gate terminal of the second thin-film transistor is adjusted. The second high-level signal line is used to provide a second high-level voltage for the clock signal; The second discharge module is used to adjust the second high-level voltage so that the voltage at the source terminal of the second thin-film transistor is adjusted.

3. The power-down discharge circuit as described in claim 2, characterized in that, The first discharge module includes a first switch unit and a first discharge adjustment unit connected together. The first switch unit is connected to the first high-level signal line, and the first discharge adjustment unit is connected to the signal output unit. The second discharge module includes a second discharge adjustment unit, which is connected to the second high-level signal line and the signal output unit respectively. The first switch unit is open when powered off and closed when not powered off.

4. The power-down discharge circuit as described in claim 3, characterized in that, The first discharge adjustment unit includes a first sustaining capacitor, a second sustaining capacitor, a third sustaining capacitor, and a first grounding resistor connected in parallel. The first switching unit is connected to the first terminal of the first sustaining capacitor, and the second terminal of the first grounding resistor is grounded. The second discharge adjustment unit includes a fourth sustaining capacitor, a fifth sustaining capacitor, a sixth sustaining capacitor, and a second grounding resistor connected in parallel. The second terminal of the second grounding resistor is grounded. The first sustaining capacitor, the second sustaining capacitor, and the third sustaining capacitor are larger than the fourth sustaining capacitor, the fifth sustaining capacitor, and the sixth sustaining capacitor. The first grounding resistor is larger than the second grounding resistor.

5. The power-down discharge circuit as described in claim 2, characterized in that, The first discharge module includes a first switch unit, a first discharge adjustment unit, and a second switch unit connected in sequence. The first switch unit is connected to the first high-level signal line, and the second switch unit is connected to the signal output unit. The second discharge module includes a second discharge adjustment unit, which is connected to the second high-level signal line and the signal output unit respectively. The first switch unit and the second switch unit are disconnected when powered off, and the first switch unit and the second switch unit are closed when not powered off.

6. The power-down discharge circuit as described in claim 5, characterized in that, The first discharge adjustment unit includes a first sustaining capacitor, a second sustaining capacitor, a third sustaining capacitor, and a first grounding resistor connected in parallel. The first terminal of the first sustaining capacitor is connected to the first switching unit and the second switching unit, respectively, and the second terminal of the first grounding resistor is grounded. The second discharge adjustment unit includes a fourth sustaining capacitor, a fifth sustaining capacitor, a sixth sustaining capacitor, and a second grounding resistor connected in parallel, with the second end of the second grounding resistor grounded.

7. The power-down discharge circuit as described in claim 1, characterized in that, The discharge module includes a discharge unit and a switching unit. The discharge unit is connected to the high-level signal line, and the discharge unit is connected to the low-level signal line and the signal output unit through the switching unit. The switching unit is used to close when the power is off, so as to discharge the pixel capacitor in the gate driving unit; The switching unit is also used to turn off after the pixel capacitor has discharged, so as to turn on the second thin-film transistor.

8. The power-down discharge circuit as described in claim 7, characterized in that, The discharge unit includes a holding capacitor and a ground resistor connected in parallel. The first end of the ground resistor is connected to the switching unit, and the second end of the ground resistor is grounded.

9. A method for discharging electricity under power-off conditions, characterized in that, The power-down discharge method is applied to the power-down discharge circuit as described in any one of claims 1 to 8, and the power-down discharge method includes: The high-level signal line provides a high-level voltage of a preset signal to the signal output unit. The preset signal includes at least a clock signal and an input signal of the sustaining unit in the gate drive unit. The signal output unit outputs the preset signal to the gate driving unit; When the discharge unit is powered off, it adjusts the high-level voltage to discharge the unit to be released in the gate driving unit.

10. A display panel, characterized in that, The display panel includes a power-down discharge circuit as described in any one of claims 1-8, and applies the power-down discharge method as described in claim 9.

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