A high-density storage array

Abstract

The present invention discloses a high-density storage array, belonging to the technical field of memory and CMOS hybrid integrated circuit. The array is composed of K high-density storage units arranged in parallel, each storage unit includes N selected pass transistors, N*M two-terminal storage devices, a source line, a word line and N*M bit lines, the N select transistors form a drain-source series structure by connecting the drain end of the previous select transistor to the source end of the next select transistor, the gate ends are all connected to the word line, the source end of the first select transistor in the drain-source series structure is connected to the source line, M parallel two-terminal storage devices form a group, a total of N groups correspond to N select transistors, in each group, one end of the M two-terminal storage devices is connected to each other and to the drain end of the corresponding select transistor, and the other end is respectively connected to M bit lines; the array storage units share N*M bit lines. The present invention reduces the area of ​​the storage unit, improves the integration density of the storage array, and has broad application prospects.

Description

Technical Field

[0001] The invention belongs to the technical field of memory and CMOS hybrid integrated circuit, and in particular relates to a high-density storage array. Background Art

[0002] The rapid increase in the amount of information data in modern society has put forward higher requirements on existing memory. The current mainstream non-volatile memory is based on NAND structure FLASH, but FLASH memory has problems such as high operating voltage and difficulty in scaling down. In order to cope with the expected storage problems, a variety of non-volatile memories have been proposed, such as resistive random access memory (RRAM), phase change memory (PRAM), magnetoresistive memory (MRAM) and ferroelectric memory (FeRAM).

[0003] Among various new non-volatile memories, two-terminal non-volatile memories have attracted extensive attention and research due to their higher theoretical density and lower process cost brought by simple structure. In practical applications, two-terminal memories need to form a storage array to achieve high-density structure and high-speed reading and writing. The existing methods mainly form a one-transistor-one-memory (1T1R) array by forming a transistor gate. Figure 1 An array composed of 1T1R memory cells is shown, which can be regarded as 1T1R memory cells shown in 101 arranged in the horizontal and vertical directions, and each memory cell is composed of a selection transistor N and a memory device R. When reading, the transistor of the corresponding column device can be turned on by the WL signal, and at this time, the state of the corresponding memory device can be read by applying a read voltage through the BL signal and detecting the corresponding read current on the SL; when writing, the transistor of the corresponding column is turned on by applying a signal on the WL, and then the memory device R can be written to the required resistance value by applying a write voltage on the BL or SL.

[0004] However, Figure 1 The density of the conventional 1T1R array shown is limited by the area occupied by the transistors, which is mainly limited by the 102 part. On the one hand, each transistor is only connected to one storage device. On the other hand, the source end of the lower transistor needs to be connected to the source line SL, so the source end of the lower transistor needs to be isolated from the drain end of the upper transistor, which brings additional area overhead. The above two factors together limit the further improvement of the density of the storage array. Therefore, it is of great significance to study a high-density storage array. Summary of the invention

[0005] In view of the above problems existing in the prior art, the present invention proposes a high-density two-terminal memory cell and array structure.

[0006] The technical solution of the present invention is as follows:

[0007] A high-density storage array, characterized in that the array is composed of K high-density storage units arranged in parallel, the high-density storage unit includes N selection transistors, N*M two-terminal storage devices, a source line, a word line and N*M bit lines, wherein the N selection transistors are connected to the source end of the next selection transistor by connecting the drain end of the previous selection transistor to the source end of the next selection transistor to form a drain-source series structure, and the gate ends of the N selection transistors are connected to the word line, the source end of the first selection transistor in the drain-source series structure is connected to the source line, and the M parallel two-terminal storage devices are a There are N groups in total, corresponding to N selection transistors, in each group, one ends of M two-terminal storage devices are connected to each other and to the drain end of the corresponding selection transistor, and the other ends are respectively connected to M bit lines; K high-density storage units of the high-density storage array share N*M common bit lines, that is, the M*N bit lines of each high-density storage unit are respectively connected to M*N common bit lines, and the high-density storage array includes N*K selection transistors, N*M*K two-terminal storage devices, K source lines, K word lines, and N*M bit lines.

[0008] Furthermore, the two-terminal memory device has at least two variable states to store data, and a new two-terminal resistive memory is selected: resistance random access memory RRAM, spin transfer torque magnetoresistive random access memory STT-MRAM, phase change memory PRAM.

[0009] Furthermore, the gate transistor is a MOSFET of advanced process node.

[0010] Furthermore, among the K high-density storage units, K is at least 2.

[0011] Furthermore, when performing a read operation on the high-density storage array, the voltage of the word line is controlled to turn on N selection transistors of the storage unit to be read, and then a read signal is applied to the corresponding bit line and the corresponding source line current is read to read the resistance state of the storage device; when performing a write operation, the voltage of the word line is controlled to turn on N selection transistors of the storage unit to be written, and then a write signal is applied to the bit line or source line to change the resistance of the storage device, thereby writing the storage device to the desired state.

[0012] The technical effects of the present invention are as follows:

[0013] The present invention discloses a high-density storage array, which is suitable for advanced two-terminal storage devices, such as resistance random access memory RRAM, spin transfer torque magnetoresistive random access memory (STT-MRAM), phase change memory (PRAM), etc. The present invention connects a gating transistor to multiple storage devices, and eliminates the area overhead of connecting the gating transistor to an external source line by utilizing a structure in which the gating transistors are connected in series. In terms of storage density, the high-density storage array proposed by the present invention is larger than the existing 1T1R array, which is conducive to reducing the area of ​​the storage unit, improving the integration density of the storage array, and reducing the cost of manufacturing the memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 It is a schematic diagram of the structure of a traditional 1T1R array in the background technology of the present invention;

[0015] Figure 2 A schematic diagram of a high-density storage array structure proposed by the present invention;

[0016] Figure 3 This is a schematic diagram of an array structure of Example 1 in a specific implementation manner of the present invention;

[0017] Figure 4 For the corresponding Figure 3 A schematic diagram of an operation method;

[0018] Figure 5 This is a schematic diagram of an array structure of Example 2 in a specific implementation manner of the present invention;

[0019] Figure 6 For the corresponding Figure 5 A schematic diagram of an operation method. DETAILED DESCRIPTION

[0020] The present invention will be further clearly and completely described below through specific embodiments in conjunction with the accompanying drawings.

[0021] The present invention provides a high-density storage array, such as Figure 2 As shown, the high-density storage array circuit is composed of K high-density storage units arranged in parallel, and 201 is one of the high-density storage units. Figure 2 K source lines SL and K word lines WL corresponding to K high-density memory cells are marked in FIG. All memory cells share M*N bit lines BL, that is, the M*N bit lines of each memory cell are respectively connected to M*N common bit lines. Figure 2 The corresponding M*N bit lines BL are marked in FIG.

[0022] Figure 2The circuit structure of the storage unit 201 includes: N gate transistors, M*N two-terminal storage devices, a source line SL, a word line WL and M*N bit lines BL. The N gate transistors form a drain-source series structure by connecting the drain of the previous gate transistor to the source of the next gate transistor, and their gate terminals are all connected to the word line WL. The source terminal of the first gate transistor in the drain-source series structure is connected to the source line SL. Each M storage device is a group, one end of which is connected to each other and to the drain of a gate transistor, and the other end is connected to the respective bit lines. In this way, the M*N storage devices and the N gate transistors form a high-density storage unit.

[0023] When the high-density storage array proposed in the present invention is read, the voltage of the control word line WL can turn on the N selection transistors of the storage unit to be read, and then the resistance state of the storage device can be read by applying a read signal to the corresponding bit line BL and reading the corresponding source line current; when the write operation is performed, the voltage of the control word line WL can turn on the N selection transistors of the storage unit to be written, and then the resistance of the storage device can be changed by applying a write signal to the bit line or source line, thereby writing the storage device to the desired state.

[0024] Embodiment 1

[0025] Figure 3 The array in can be regarded as being composed of two high-density storage units as shown in 301, K=2, each storage unit uses M=2, N=2, that is, each storage unit includes 2 selection transistors, 4 memories and source line SL, word line WL and 4 bit lines BL, wherein the source of the lower selection transistor is connected to the drain of the upper selection transistor, and the two selection transistors form a source-drain series structure, and their gate terminals are connected to the word line WL, and the source of the upper selection transistor is connected to the source line SL. One end of each two memories is connected to each other and to the drain of a selection transistor. In this way, the four memories are connected to the drain of the two transistors, and the other ends of the four memories are connected to their respective bit lines BL. The memory selected in this embodiment is a resistive random access memory RRAM.

[0026] Assume that the resistance states of the two devices corresponding to BL3 need to be read out, that is, Figure 4 The states of the two devices corresponding to 401 in the figure are as follows: Figure 4 At this time, WL1 and WL2 are both connected to VDD, all transistors are in the on state, BL3 is connected to the read voltage Vread, the remaining BLs are connected to GND, and all SLs are connected to GND. By reading the current on SL1 and SL2, the resistance state of the two devices corresponding to BL3 can be obtained, thereby reading the stored information.

[0027] Embodiment 2

[0028] Figure 5 Another specific embodiment of the structure of the present invention is given. Figure 5 The array in can be regarded as composed of three high-density storage units as shown in 501, K=3, each storage unit uses M=4, N=2, that is, each storage unit includes two selection transistors, 8 memories and source line SL, word line WL and 8 bit lines BL, wherein the source of the lower selection transistor is connected to the drain of the upper selection transistor, and the two selection transistors form a source-drain series structure, and their gate terminals are connected to the word line WL, and the source of the upper selection transistor is connected to the source line SL. One end of each of the four memories is connected to each other and to the drain of a selection transistor. In this way, the eight memories are connected to the drain of the two transistors, and the other ends of the eight memories are connected to their respective bit lines BL. The memory selected in this embodiment is a phase change memory (PRAM).

[0029] Assuming that the device 502 corresponding to BL5 and SL3 needs to be written from a low resistance state to a high resistance state without affecting the states of other devices, the corresponding operation voltage application method is as follows: Figure 6 At this time, WL3 is connected to VDD, the corresponding transistor is in the on state, SL3 is connected to the write voltage Vwrite0 required for writing 0, BL5 and all other ports not marked are connected to GND, and the current flows through the corresponding device 502, and the device state is written to 0, thereby completing the writing of information.

[0030] The above explains the method of operating a single storage cell in an array at a time, and only one row and one column are selected at a time. Those with ordinary knowledge in the technical field should understand that the operation method can be easily extended to the selection of multiple rows and columns, so that the cells of multiple rows and columns can be read and written in parallel, increasing the data throughput of the array.

[0031] It should be noted that in the memory cell structure proposed by the present invention, the number of memories connected to each selection transistor can be different. Similarly, the array structure proposed by the present invention can be composed of memory cells proposed by the present invention with different lengths. The above changes do not affect the corresponding features and beneficial effects of the present invention, and do not change the essential connotation of the present invention.

[0032] Finally, it should be noted that the purpose of publishing the embodiments is to help further understand the present invention, but those skilled in the art can understand that various substitutions and modifications are possible without departing from the spirit and scope of the present invention and the appended claims. Therefore, the present invention should not be limited to the contents disclosed in the embodiments, and the scope of protection claimed by the present invention shall be subject to the scope defined in the claims.

Claims

1. A high-density storage array, characterized in that: The array is composed of K high-density storage units arranged in parallel, wherein the high-density storage unit includes N selection transistors, N*M two-terminal storage devices, a source line, a word line and N*M bit lines, wherein the N selection transistors form a drain-source series structure by connecting the drain end of the previous selection transistor to the source end of the next selection transistor, and the gate ends thereof are all connected to the word line, and the M parallel two-terminal storage devices form a group, and there are N groups in total, corresponding to the N selection transistors, and in each group, one end of the M two-terminal storage devices is connected to each other. The high-density storage array is characterized in that the first gate transistor has a drain end connected to the drain end of the gate transistor and the other end is connected to M bit lines respectively; wherein only the source end of the first gate transistor in the drain-source series structure is connected to the source line; the K high-density storage cells of the high-density storage array share N*M common bit lines, that is, the M*N bit lines of each high-density storage cell are respectively connected to the M*N common bit lines, and the high-density storage array includes N*K gate transistors, N*M*K two-terminal storage devices, K source lines, K word lines, and N*M bit lines.

2. A high-density storage array as claimed in claim 1, characterized in that: The two-terminal memory device has at least two variable states to store data, and a new two-terminal resistance type memory is selected: resistance random access memory RRAM, spin transfer torque magnetoresistive random access memory STT-MRAM, phase change memory PRAM.

3. A high-density storage array as claimed in claim 1, characterized in that: The gate transistor is a MOSFET of an advanced process node.

4. A high-density storage array as claimed in claim 1, characterized in that: The K high-density storage units, K is at least 2.

5. A high-density storage array as claimed in claim 1, characterized in that: When performing a read operation on the high-density storage array, the voltage of the control word line turns on the N selection transistors of the storage unit to be read, and then a read signal is applied to the corresponding bit line and the corresponding source line current is read to read the resistance state of the storage device; when performing a write operation, the voltage of the control word line turns on the N selection transistors of the storage unit to be written, and then a write signal is applied to the bit line or source line to change the resistance of the storage device, thereby writing the storage device to the desired state.

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