A power semiconductor module and a package assembly with double-sided heat dissipation

Abstract

The application provides a power semiconductor module and packaging assembly with double-sided heat dissipation, comprising a first substrate and a second substrate, the first substrate and the second substrate each comprising a connecting copper layer, an insulating medium layer and an outer copper layer arranged in a manner of adhesion; the connecting copper layer of the first substrate is opposite to the connecting copper layer of the second substrate; an upper bridge arm chip is arranged on the connecting copper layer of the first substrate, the connecting copper layer of the first substrate is connected to the soldering point surface of the upper bridge arm chip, and the connecting copper layer of the second substrate is connected to the upper surface of the upper bridge arm chip; a lower bridge arm chip is arranged on the connecting copper layer of the second substrate, the connecting copper layer of the second substrate is connected to the soldering point surface of the lower bridge arm chip, and the connecting copper layer of the first substrate is connected to the upper surface of the lower bridge arm chip; signal terminals and power terminals are arranged on both sides between the connecting copper layer of the first substrate and the connecting copper layer of the second substrate. After the technical scheme is adopted, the power semiconductor module and packaging assembly realize double-sided heat dissipation and have small size and high power density.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor devices, in particular to a double-sided heat dissipation power semiconductor module and packaging assembly. BACKGROUND

[0002] Power semiconductor modules are widely used in industrial frequency conversion, current converters, automobile electrode controllers and other scenes that need to convert electrical energy. Moreover, the traditional power semiconductor module adopts a single-sided cooling structure, and the heat generated by the power chip loss is conducted to the heat sink in a single direction through the DBC and the substrate. However, for high-integration or high-power power semiconductors, due to the large amount of heat generated by the chip, the single-sided heat dissipation has poor heat dissipation efficiency, and it is difficult to solve the heat dissipation demand of high heat, so the demand for double-sided heat dissipation solutions is becoming more and more urgent.

[0003] The existing double-sided heat dissipation solution has the problems of complex manufacturing process, high implementation difficulty and large module space occupation, and in vehicle modules, there are high requirements for volume and power density. Therefore, a double-sided heat dissipation power semiconductor module with small overall size and high power density is needed. SUMMARY

[0004] In order to overcome the above technical defects, the purpose of the present application is to provide a double-sided heat dissipation power semiconductor module and packaging assembly, which can dissipate heat on both sides, has a small thickness and lateral size, and has a high power density.

[0005] The present application discloses a double-sided heat dissipation power semiconductor module,

[0006] The first substrate and the second substrate each include a connecting copper layer, an insulating dielectric layer and an outer copper layer arranged in close contact, and the insulating dielectric layer is arranged between the connecting copper layer and the outer copper layer;

[0007] The first substrate and the second substrate are spaced apart and vertically coincident, so that the connecting copper layer of the first substrate is opposite to the connecting copper layer of the second substrate;

[0008] The connecting copper layer of the first substrate is provided with an upper bridge arm chip, the connecting copper layer of the first substrate is connected to the solder joint surface of the upper bridge arm chip, and the connecting copper layer of the second substrate is connected to the upper surface of the upper bridge arm chip;

[0009] The connecting copper layer of the second substrate is provided with a lower bridge arm chip, the connecting copper layer of the second substrate is connected to the solder joint surface of the lower bridge arm chip, and the connecting copper layer of the first substrate is connected to the upper surface of the lower bridge arm chip;

[0010] The signal terminal and the power terminal are respectively exposed to the two sides of the insulating shell along the horizontal direction.

[0011] Preferably, a first conductive pad is arranged between the connecting copper layer of the first substrate and the upper bridge arm chip, the bottom surface of the first conductive pad is connected with the connecting copper layer of the first substrate, and the top surface of the first conductive pad is connected with the solder surface of the upper bridge arm chip, so that the height of the upper surface of the upper bridge arm chip is equal to the height of the upper surface of the signal terminal.

[0012] A second conductive pad is arranged between the connecting copper layer of the second substrate and the lower bridge arm chip, so that the bottom surface of the second conductive pad is connected with the connecting copper layer of the second substrate, and the top surface of the second conductive pad is connected with the solder surface of the lower bridge arm chip, so that the height of the upper surface of the lower bridge arm chip is equal to the height of the lower surface of the signal terminal.

[0013] Preferably, the first substrate and the second substrate are spaced apart and installed in an insulating shell and vertically coincide, so that the connecting copper layer of the first substrate is opposite to the connecting copper layer of the second substrate, and the outer copper layer of the first substrate and the outer copper layer of the second substrate are opposite and respectively exposed to the outside of the insulating shell.

[0014] The signal terminal and the power terminal are respectively exposed to the two sides of the insulating shell along the horizontal direction.

[0015] Preferably, a positioning groove is arranged on the side of the insulating shell close to the signal terminal and deviated from the center line of the insulating shell.

[0016] Preferably, the connecting copper layer of the first substrate comprises a first main copper foil, a second main copper foil and a third main copper foil which are insulated from each other, and the connecting copper layer of the second substrate comprises a fourth main copper foil, a fifth main copper foil and a sixth main copper foil which are insulated from each other.

[0017] The first main copper foil is connected with the solder surface of the upper bridge arm chip, the second main copper foil is connected with the upper surface of the lower bridge arm chip, and the sixth main copper foil is connected with the solder surface of the lower bridge arm chip and the upper surface of the upper bridge arm chip.

[0018] The power terminal comprises a direct current positive terminal, a direct current negative terminal and an alternating current terminal, the direct current positive terminal is connected with the first main copper foil and the fourth main copper foil, the direct current negative terminal is connected with the second main copper foil and the fifth main copper foil, and the alternating current terminal is connected with the third main copper foil and the sixth main copper foil.

[0019] The commutation loop current enters the first main copper foil from the DC positive terminal, flows through the upper bridge arm chip, enters the sixth main copper foil, flows through the AC terminal and the lower bridge arm chip, and then enters the second main copper foil, and flows out of the power semiconductor module from the DC negative terminal.

[0020] Preferably, the connecting copper layer of the first substrate further comprises a first auxiliary copper foil, a second auxiliary copper foil, a third auxiliary copper foil, a fourth auxiliary copper foil and a fifth auxiliary copper foil, which are insulated from each other, and the third auxiliary copper foil and the fourth auxiliary copper foil are respectively connected to the upper surface of the lower bridge arm chip.

[0021] The connecting copper layer of the second substrate further comprises a sixth auxiliary copper foil, a seventh auxiliary copper foil, an eighth auxiliary copper foil, a ninth auxiliary copper foil and a tenth auxiliary copper foil, which are insulated from each other, and the seventh auxiliary copper foil and the eighth auxiliary copper foil are respectively connected to the upper surface of the upper bridge arm chip.

[0022] The signal terminal comprises a first collector signal terminal, a second collector signal terminal, a first emitter signal terminal, a second emitter signal terminal, a first gate signal terminal and a second gate signal terminal.

[0023] The first collector signal terminal connects the first main copper foil and the sixth auxiliary copper foil, the first emitter signal terminal connects the first auxiliary copper foil and the seventh auxiliary copper foil, the first gate signal terminal connects the second auxiliary copper foil and the eighth auxiliary copper foil, the second collector signal terminal connects the fifth auxiliary copper foil and the sixth main copper foil, the second emitter signal terminal connects the fourth auxiliary copper foil and the tenth auxiliary copper foil, and the second gate signal terminal connects the third auxiliary copper foil and the ninth auxiliary copper foil.

[0024] The commutation loop current enters the first main copper foil from the DC positive terminal, flows through the first collector signal terminal and the upper bridge arm chip, enters the sixth main copper foil, the seventh auxiliary copper foil and the eighth auxiliary copper foil, respectively flows through the first emitter signal terminal, the first gate signal terminal, the AC terminal, the second collector signal terminal and the lower bridge arm chip, and then enters the second main copper foil, the third auxiliary copper foil and the fourth auxiliary copper foil, flows through the second emitter signal terminal, the second gate signal terminal, and flows out of the power semiconductor module from the DC negative terminal.

[0025] Preferably, the upper bridge arm chip comprises an upper bridge arm IGBT chip and an upper bridge arm diode chip, and the lower bridge arm chip comprises a lower bridge arm IGBT chip and a lower bridge arm diode chip.

[0026] Preferably, the copper layer of the first substrate is connected to the solder joint surface of the upper bridge arm chip via vacuum reflow soldering, and the copper layer of the second substrate is connected to the upper surface of the upper bridge arm chip via vacuum reflow soldering.

[0027] The connecting copper layer of the second substrate is connected to the solder joint surface of the lower bridge arm chip via vacuum reflow soldering, and the connecting copper layer of the first substrate is connected to the upper surface of the lower bridge arm chip via vacuum reflow soldering.

[0028] Preferably, the materials of the first conductive pad and the second conductive pad include aluminum silicon carbide, molybdenum copper alloy, or copper.

[0029] The present invention also discloses a power semiconductor packaging assembly, comprising at least three power semiconductor modules as described above, wherein each of the power semiconductor modules is arranged in the same direction and in parallel.

[0030] Heat sinks are connected to the outer copper layer of the first substrate and the outer copper layer of the second substrate of each of the power semiconductor modules.

[0031] Compared with the prior art, the above technical solution has the following advantages: By using flip-chip technology, the solder joints of the chip are directly connected to the connecting copper layer, reducing the vertical dimension of the power semiconductor module; by mounting the upper bridge arm chip and the lower bridge arm chip in opposite directions on the first and second substrates, the pads connecting the first and second substrates can be reduced, thus reducing the lateral dimension of the power semiconductor module; and by setting an exposed outer copper layer, the power semiconductor module can achieve double-sided heat dissipation. Attached Figure Description

[0032] Figure 1 This is a schematic diagram of the structure of a power semiconductor module according to the present invention;

[0033] Figure 2 This is a three-dimensional assembly schematic diagram of a power semiconductor module according to the present invention;

[0034] Figure 3 This is a cross-sectional schematic diagram of a power semiconductor module according to the present invention;

[0035] Figure 4 This is a schematic diagram of the structure of a power semiconductor module according to the present invention;

[0036] Figure 5 This is a schematic diagram of the structure of the first substrate of the present invention;

[0037] Figure 6 This is a schematic diagram of the structure of the second substrate of the present invention;

[0038] Figure 7 This is a schematic diagram of the circuit topology of the present invention.

[0039] Reference numerals: 1-First substrate; 11-Connecting copper layer of the first substrate; 12-Insulating dielectric layer of the first substrate; 13-Outer copper layer of the first substrate; 2-Second substrate; 21-Connecting copper layer of the second substrate; 22-Insulating dielectric layer of the second substrate; 23-Outer copper layer of the second substrate; 3-Upper bridge arm chip; 4-Lower bridge arm chip; 5-Power terminal; 6-Signal terminal; 7-Insulating shell; 71-Positioning groove; 111-First main copper foil; 112-Second main copper foil Foil; 113 - Third main copper foil; 211 - Fourth main copper foil; 212 - Fifth main copper foil; 213 - Sixth main copper foil; 1110 - First auxiliary copper foil; 1120 - Second auxiliary copper foil; 1130 - Third auxiliary copper foil; 1140 - Fourth auxiliary copper foil; 1150 - Fifth auxiliary copper foil; 2110 - Sixth auxiliary copper foil; 2120 - Seventh auxiliary copper foil; 2130 - Eighth auxiliary copper foil; 2140 - Ninth auxiliary copper foil; 2150 - Tenth auxiliary copper foil. Detailed Implementation

[0040] The advantages of the present invention will be further illustrated below with reference to the accompanying drawings and specific embodiments.

[0041] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this disclosure as detailed in the appended claims.

[0042] The terminology used in this disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. The singular forms “a,” “the,” and “the” as used in this disclosure and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any and all possible combinations of one or more of the associated listed items.

[0043] It should be understood that although the terms first, second, third, etc., may be used in this disclosure to describe various information, such information should not be limited to these terms. These terms are used only to distinguish information of the same type from one another. For example, without departing from the scope of this disclosure, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to determination."

[0044] In the description of the present application, it needs to be understood that the terms "longitudinal", "transverse", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application.

[0045] In the description of the present application, unless otherwise specified and limited, it needs to be explained that the terms "mounting", "connecting", "connecting" should be understood broadly, for example, it can be mechanical connection or electrical connection, it can be the communication inside two elements, it can be direct connection, or indirect connection through intermediate medium, and the specific meaning of the above terms can be understood by those skilled in the art according to the specific circumstances.

[0046] In the subsequent description, the suffix such as "module", "component" or "unit" used to represent the element is only for the convenience of the description of the present application, and has no specific meaning. Therefore, "module" and "component" can be used mixedly.

[0047] As Figures 1-6 shown, the present application discloses a double-sided heat dissipation power semiconductor module,

[0048] including a first substrate 1 and a second substrate 2, the first substrate 1 and the second substrate 2 both include a connecting copper layer, an insulating medium layer and an outer copper layer arranged in close contact, the insulating medium layer is arranged between the connecting copper layer and the outer copper layer. The first substrate 1 and the second substrate 2 are spaced apart and vertically coincident, so that the connecting copper layer 11 of the first substrate and the connecting copper layer 21 of the second substrate are opposite. The connecting copper layer 11 of the first substrate is provided with an upper bridge arm chip 3, so that the connecting copper layer 11 of the first substrate is connected with the solder point surface of the upper bridge arm chip 3, and the connecting copper layer 21 of the second substrate is connected with the upper surface of the upper bridge arm chip 3. The connecting copper layer 21 of the second substrate is provided with a lower bridge arm chip 4, the connecting copper layer 21 of the second substrate is connected with the solder point surface of the lower bridge arm chip 4, and the connecting copper layer 11 of the first substrate is connected with the upper surface of the lower bridge arm chip 4. The signal terminal 6 and the power terminal 5 are arranged on both sides between the connecting copper layer 11 of the first substrate and the connecting copper layer 21 of the second substrate.

[0049] Specifically, the first substrate 1 and the second substrate 2 are both three-layer structures, including a connecting copper layer, an insulating medium layer and an outer copper layer arranged in sequence. The first substrate 1 and the second substrate 2 are arranged in a spaced and opposite manner. It can be understood that the size of the first substrate 1 and the second substrate 2 is exactly the same, so that the first substrate 1 and the second substrate 2 coincide in the vertical direction. After the connecting copper layer 11 of the first substrate and the connecting copper layer 21 of the second substrate are opposite, the connecting copper layer 11 of the first substrate and the connecting copper layer 21 of the second substrate can be electrically connected through chips and terminals, so that a commutation loop can be formed when the power semiconductor module is powered on. The outer copper layer 13 of the first substrate and the outer copper layer 23 of the second substrate are opposite, which can transfer the heat of the power semiconductor to the outside from two directions, so that the power semiconductor module can realize the effect of double-sided heat dissipation. Further, heat dissipation equipment can be connected to the outer copper layer 13 of the first substrate and the outer copper layer 23 of the second substrate, respectively, such as arranging a heat dissipation waterway on the outer copper layer 13 of the first substrate and the outer copper layer 23 of the second substrate, respectively, to improve the efficiency of double-sided heat dissipation of the power semiconductor module.

[0050] The insulating medium layer is arranged between the connecting copper layer and the outer copper layer to form insulation between the connecting copper layer and the outer copper layer, avoiding interference between the commutation function of the connecting copper layer and the heat dissipation function of the outer copper layer. The insulating medium layer can be made of zirconia toughened alumina ceramic, silicon nitride ceramic, aluminum nitride ceramic, etc.

[0051] Preferably, the thickness of the connecting copper layer, the insulating medium layer and the outer copper layer can be set as 0.3mm, 0.32mm and 0.4mm, respectively.

[0052] The signal terminal 6 is arranged in a strip-shaped metal, which can be connected to the drive board through welding, connector and the like, and is used to lead out signals at different positions of the commutation circuit of the power semiconductor module. The power terminal 5 is arranged in a sheet-shaped metal, which can be connected to the capacitor through laser welding and the like, and is used to input direct current to the power semiconductor module and lead out alternating current.

[0053] In the present application, the solder point surface of the chip refers to the surface obtained by depositing the protruding solder points on the IO unit side of the chip, and the upper surface of the chip refers to the other surface of the chip opposite to the solder point surface. The connecting copper layer 11 of the first substrate is connected to the solder point surface of the upper bridge arm chip 3, and the connecting copper layer 21 of the second substrate is connected to the solder point surface of the lower bridge arm chip 4, that is, the upper bridge arm chip 3 is connected to the connecting copper layer 11 of the first substrate in a flip chip manner, and the lower bridge arm chip 4 is connected to the connecting copper layer 21 of the second substrate in a flip chip manner, so that the upper bridge arm chip 3 and the lower bridge arm chip 4 are respectively flip-chip mounted on the two opposite connecting copper layers in opposite directions. And the connecting copper layer 21 of the second substrate is connected to the upper surface of the upper bridge arm chip 3, and the connecting copper layer 11 of the first substrate is connected to the upper surface of the lower bridge arm chip 4, so that the current can flow between the connecting copper layer 11 of the first substrate and the connecting copper layer 21 of the second substrate through the upper bridge arm chip 3 and the lower bridge arm chip 4, and a commutation loop is formed between the first substrate and the second substrate.

[0054] Since the flip chip manner is to directly connect the chip to the substrate, carrier or circuit board through the solder point surface of the chip, the vertical size is smaller than that of the wire bonding manner. And since the upper bridge arm chip 3 and the lower bridge arm chip 4 are respectively mounted on the connecting copper layer 11 of the first substrate and the connecting copper layer 21 of the second substrate in opposite directions, the commutation loop can be formed without the need of connecting conductive pads between the connecting copper layer 11 of the first substrate and the connecting copper layer 21 of the second substrate, which can reduce the use of components and reduce the lateral size of the power semiconductor module.

[0055] It can be understood that since the connecting copper layer 21 of the second substrate is connected to the upper surface of the upper bridge arm chip 3, and the connecting copper layer 11 of the first substrate is connected to the upper surface of the lower bridge arm chip 4, the signal terminal 6 and the power terminal 5 are respectively arranged on the two sides between the connecting copper layer 11 of the first substrate and the connecting copper layer 21 of the second substrate, therefore, after the above components complete their respective connection relationship, the distance between the first substrate 1 and the second substrate 2, the thickness of the upper bridge arm chip 3, the thickness of the lower bridge arm chip 4, the thickness of the signal terminal 6 and the thickness of the power terminal 5 are all equal.

[0056] When the above components are connected by soldering, a solder layer will be formed on the surface of any component connected to other components, so that the distance between the first substrate 1 and the second substrate 2, the thickness of the upper bridge arm chip 3 and its two solder layers, the thickness of the lower bridge arm chip 4 and its two solder layers, the thickness of the signal terminal 6 and its two solder layers, and the thickness of the power terminal 5 and its two solder layers are all equal.

[0057] In one optional embodiment, a first conductive pad is disposed between the connecting copper layer 11 of the first substrate and the upper bridge arm chip 3. The connecting copper layer 11 of the first substrate is connected to the bottom surface of the first conductive pad, and the top surface of the first conductive pad is connected to the solder joint surface of the upper bridge arm chip 3, so that the height of the upper surface of the upper bridge arm chip 3 is equal to the height of the upper surface of the signal terminal 6. A second conductive pad is disposed between the connecting copper layer 21 of the second substrate and the lower bridge arm chip 4, so that the connecting copper layer 21 of the second substrate is connected to the bottom surface of the second conductive pad, and the top surface of the second conductive pad is connected to the solder joint surface of the lower bridge arm chip 4, so that the height of the upper surface of the lower bridge arm chip 4 is equal to the height of the lower surface of the signal terminal 6.

[0058] Specifically, the thickness of commonly used signal terminal components is greater than the thickness of chip components. Therefore, to compensate for this height difference, a first conductive pad can be placed between the connecting copper layer 11 of the first substrate and the upper bridge arm chip 3, and a second conductive pad can be placed between the connecting copper layer 21 of the second substrate and the lower bridge arm chip 4. This makes the height of the upper surface of the upper bridge arm chip 3 equal to the height of the upper surface of the signal terminal 6, and the height of the upper surface of the lower bridge arm chip 4 equal to the height of the lower surface of the signal terminal 6. It can be understood that the upper surface of the signal terminal 6 refers to the surface of the signal terminal 6 closest to the second substrate 2, and the lower surface of the signal terminal 6 refers to the surface of the signal terminal 6 closest to the first substrate 1.

[0059] Therefore, after the above components complete their respective connections, the spacing between the first substrate 1 and the second substrate 2, the overall thickness of the upper bridge arm chip 3 and the first conductive pad, the overall thickness of the lower bridge arm chip 4 and the second conductive pad, the thickness of the signal terminal 6, and the thickness of the power terminal 5 will all be equal.

[0060] When the above components are connected by welding, a solder layer will be formed on the surface of any component that is connected to other components, so that the spacing between the first substrate 1 and the second substrate 2, the overall thickness of the upper bridge arm chip 3 and its two sides of solder layer and the first conductive pad and its two sides of solder layer, the overall thickness of the lower bridge arm chip 4 and its two sides of solder layer and the first conductive pad and its two sides of solder layer, the thickness of the signal terminal 6 and its two sides of solder layer, and the thickness of the power terminal 5 and its two sides of solder layer are all equal.

[0061] In one alternative implementation, such as Figure 4 As shown, the first substrate 1 and the second substrate 2 are mounted at a distance within the insulating housing 7 and overlap vertically, such that the connecting copper layer 11 of the first substrate and the connecting copper layer 21 of the second substrate are opposite to each other, and the outer copper layer 13 of the first substrate and the outer copper layer 23 of the second substrate are opposite to each other and are exposed outside the insulating housing 7. The signal terminal 6 and the power terminal 5 are exposed horizontally on both sides of the insulating housing 7.

[0062] Specifically, the insulating shell 7 can be made of epoxy resin material. The first substrate 1 and the second substrate 2 are spaced apart and installed in the insulating shell 7, forming a structure in which the insulating shell 7 wraps the first substrate 1 and the second substrate 2. The insulating shell 7 can provide an insulating environment for the elements included therein, further improving the stability of the power semiconductor module in use. The outer copper layer 13 of the first substrate and the outer copper layer 23 of the second substrate are exposed outside the insulating shell 7. It can be understood that the top surface and the bottom surface of the insulating shell 7 are provided with a similar hollow structure and do not cover the outer copper layer 13 of the first substrate and the outer copper layer 23 of the second substrate. This allows the power semiconductor module to achieve a double-sided heat dissipation effect through the outer copper layer 13 of the first substrate and the outer copper layer 23 of the second substrate. Further, a heat dissipation device can be externally connected to the top surface and the bottom surface of the insulating shell 7. Since the outer copper layer 13 of the first substrate and the outer copper layer 23 of the second substrate are exposed outside the insulating shell 7, they can both be in contact with the heat dissipation device, thereby improving the double-sided heat dissipation efficiency of the power semiconductor module.

[0063] In an alternative embodiment, a positioning groove 71 is provided on one side of the insulating shell 7 close to the signal terminal 6, offset from the center line of the insulating shell 7.

[0064] It can be understood that, through the foregoing arrangement of the power semiconductor module, the first substrate 1 and the second substrate 2 are similar in structure and are arranged opposite to each other in the insulating shell 7. When the power semiconductor module is flipped, it is difficult to quickly determine the direction of the power semiconductor, which may cause confusion about the specific functions of each signal terminal 6 and each power terminal 5, thereby negatively affecting the subsequent connection of a drive board or a capacitor or other devices. Therefore, in the present embodiment, a positioning groove 71 is provided on one side of the insulating shell 7 close to the signal terminal 6, offset from the center line of the insulating shell 7. Since the positioning groove 71 is offset from the center line of the insulating shell 7, the direction of the first substrate 1 and the second substrate 2 can be determined according to the direction in which the positioning groove 71 is currently offset. For example, in the case where the positioning groove 71 is offset to the horizontal left side of the insulating shell 7, it can be determined that the direction of the current power semiconductor module is such that the second substrate 2 is located above the first substrate 1, and the positions of each signal terminal 6 and each power terminal 5 are determined according to the direction, thereby avoiding incorrect installation during application of the power semiconductor module. Figure 4

[0065] In an alternative embodiment, as shown in Figures 5-6 ​As shown, the connecting copper layer 11 of the first substrate includes a first main copper foil 111, a second main copper foil 112, and a third main copper foil 113 that are insulated from each other. The connecting copper layer 21 of the second substrate includes a fourth main copper foil 211, a fifth main copper foil 212, and a sixth main copper foil 213 that are insulated from each other. The first main copper foil 111 is connected to the solder joint surface of the upper bridge arm chip 3, the second main copper foil 112 is connected to the upper surface of the lower bridge arm chip 4, and the sixth main copper foil 213 is connected to both the solder joint surface of the lower bridge arm chip 4 and the upper surface of the upper bridge arm chip 3.

[0066] The power terminal 5 includes a DC positive terminal DC+, a DC negative terminal DC-, and an AC terminal AC. The DC positive terminal DC+ is connected to the first main copper foil 111 and the fourth main copper foil 211, the DC negative terminal DC- is connected to the second main copper foil 112 and the fifth main copper foil 212, and the AC terminal AC is connected to the third main copper foil 113 and the sixth main copper foil 213.

[0067] After the above setup, the commutation circuit current enters the first main copper foil 111 from the DC positive terminal DC+, flows through the solder joint surface of the upper bridge arm chip 3, and enters the sixth main copper foil 213 through the upper surface of the upper bridge arm chip 3. It then flows through the AC terminal AC and the solder joint surface of the lower bridge arm chip 4, and then enters the second main copper foil 112 through the upper surface of the lower bridge arm chip 4, and exits the power semiconductor module from the DC negative terminal DC-.

[0068] Preferably, such as Figures 5-6 As shown, the connecting copper layer 11 of the first substrate also includes a first auxiliary copper foil 1110, a second auxiliary copper foil 1120, a third auxiliary copper foil 1130, a fourth auxiliary copper foil 1140 and a fifth auxiliary copper foil 1150 that are insulated from each other. The third auxiliary copper foil 1130 and the fourth auxiliary copper foil 1140 are respectively connected to the upper surface of the lower bridge arm chip 4.

[0069] The connecting copper layer 21 of the second substrate also includes a sixth auxiliary copper foil 2110, a seventh auxiliary copper foil 2120, an eighth auxiliary copper foil 2130, a ninth auxiliary copper foil 2140 and a tenth auxiliary copper foil 2150 that are insulated from each other. The seventh auxiliary copper foil 2120 and the eighth auxiliary copper foil 2130 are respectively connected to the upper surface of the upper bridge arm chip 3.

[0070] The signal terminals 6 include a first collector signal terminal C1, a second collector signal terminal C2, a first emitter signal terminal E1, a second emitter signal terminal E2, a first gate signal terminal G1, and a second gate signal terminal G2. The first collector signal terminal C1 connects the first main copper foil 111 and the sixth auxiliary copper foil 2110, the first emitter signal terminal E1 connects the first auxiliary copper foil 1110 and the seventh auxiliary copper foil 2120, the first gate signal terminal G1 connects the second auxiliary copper foil 1120 and the eighth auxiliary copper foil 2130, the second collector signal terminal C2 connects the fifth auxiliary copper foil 1150 and the sixth main copper foil 213, the second emitter signal terminal E2 connects the fourth auxiliary copper foil 1140 and the tenth auxiliary copper foil 2150, and the second gate signal terminal G2 connects the third auxiliary copper foil 1130 and the ninth auxiliary copper foil 2140.

[0071] After the above setting, the commutation loop current enters the first main copper foil 111 from the DC positive terminal DC+, flows through the first collector signal terminal C1 and the soldered surface of the upper bridge arm chip 3 in the first main copper foil 111, and enters the sixth main copper foil 213, the seventh auxiliary copper foil 2120 and the eighth auxiliary copper foil 2130 through the upper surface of the upper bridge arm chip 3, respectively flows through the first emitter signal terminal E1, the first gate signal terminal G1, the AC terminal AC, the second collector signal terminal C2 and the soldered surface of the lower bridge arm chip 4, and then enters the second main copper foil 112, the third auxiliary copper foil 1130 and the fourth auxiliary copper foil 1140 through the upper surface of the lower bridge arm chip 4, flows through the second emitter signal terminal E2 and the second gate signal terminal G2, and flows out of the power semiconductor module from the DC negative terminal DC-.

[0072] Preferably, the upper bridge arm chip 3 includes an upper bridge arm IGBT chip UG and an upper bridge arm diode chip UD, and the lower bridge arm chip 4 includes a lower bridge arm IGBT chip LG and a lower bridge arm diode chip LD. The circuit topology of the realized commutation loop is shown in Figure 7 .

[0073] Preferably, the connecting copper layer 11 of the first substrate and the soldered surface of the upper bridge arm chip 3 are connected by vacuum reflow soldering, and the connecting copper layer 21 of the second substrate and the upper surface of the upper bridge arm chip 3 are connected by vacuum reflow soldering. The connecting copper layer 21 of the second substrate and the soldered surface of the lower bridge arm chip 4 are connected by vacuum reflow soldering, and the connecting copper layer 11 of the first substrate and the upper surface of the lower bridge arm chip 4 are connected by vacuum reflow soldering.

[0074] It can be understood that in the embodiment using the first conductive pad and the second conductive pad, the connecting copper layer 11 of the first substrate is connected to the bottom surface of the first conductive pad by vacuum reflow soldering, the top surface of the first conductive pad is connected to the soldering point surface of the upper bridge arm chip 3 by vacuum reflow soldering, the connecting copper layer 21 of the second substrate is connected to the bottom surface of the second conductive pad by vacuum reflow soldering, and the top surface of the second conductive pad is connected to the soldering point surface of the lower bridge arm chip 4 by vacuum reflow soldering.

[0075] Preferably, the material of the first conductive pad and the second conductive pad comprises aluminum silicon carbide, molybdenum copper alloy or copper.

[0076] The application further discloses a power semiconductor packaging assembly, comprising at least three power semiconductor modules as described above, and each power semiconductor module is arranged in parallel and in the same direction.

[0077] Specifically, in the packaging assembly, each power semiconductor module is arranged in parallel and in the same direction, and it can be understood that the power terminals of each power semiconductor module are distributed on the same side, and the directions of the first substrate and the second substrate in each power semiconductor module are the same. Further, the packaging assembly can be connected with a heat dissipation device in contact with the outer copper layer of each power semiconductor module, and double-sided heat dissipation of each power semiconductor module in the packaging assembly can be realized. The packaging assembly obtained by the above can be compatible with silicon-based power chips and silicon carbide power chips, can constitute a single three-phase full-bridge inverter, a double three-phase full-bridge inverter, a Boost circuit and other power electronic circuits, and can be applied to motor control modules and vehicle assemblies.

[0078] After the above technical scheme is adopted, compared with the prior art, the following beneficial effects are obtained: the soldering point surface of the chip is directly connected to the connecting copper layer through flip chip technology, thereby reducing the vertical size of the power semiconductor module; the upper bridge arm chip and the lower bridge arm chip are installed on the first substrate and the second substrate in opposite directions, thereby reducing the pads connecting the first substrate and the second substrate and reducing the horizontal size of the power semiconductor module; and the exposed outer copper layer is arranged, so that the power semiconductor module can be double-sidedly heat-dissipated.

[0079] It should be noted that the embodiments of the application have better implementation, and do not limit the application in any form, and any skilled person in the art can change or modify the equivalent effective embodiments by using the technical content disclosed above, as long as the content of the technical scheme of the application is not deviated, and any modification or equivalent change and modification of the above embodiments according to the technical essence of the application are still within the scope of the technical scheme of the application.

Claims

1. A power semiconductor module with double-sided heat dissipation, characterized in that, a first substrate and a second substrate are provided, each of the first substrate and the second substrate comprises a connection copper layer, an insulating medium layer and an outer copper layer arranged in sequence, and the insulating medium layer is arranged between the connection copper layer and the outer copper layer; the first substrate and the second substrate are spaced apart and vertically coincident, so that the connection copper layer of the first substrate is opposite to the connection copper layer of the second substrate; an upper bridge arm chip is arranged on the connection copper layer of the first substrate, the connection copper layer of the first substrate is connected to the soldering surface of the upper bridge arm chip, and the connection copper layer of the second substrate is connected to the upper surface of the upper bridge arm chip; a lower bridge arm chip is arranged on the connection copper layer of the second substrate, the connection copper layer of the second substrate is connected to the soldering surface of the lower bridge arm chip, and the connection copper layer of the first substrate is connected to the upper surface of the lower bridge arm chip; signal terminals and power terminals are arranged on both sides between the connection copper layer of the first substrate and the connection copper layer of the second substrate, the signal terminals are arranged in the form of strips, and the power terminals are arranged in the form of sheets; the first substrate and the second substrate are spaced apart and vertically coincident in an insulating shell, so that the connection copper layer of the first substrate is opposite to the connection copper layer of the second substrate, and the outer copper layer of the first substrate and the outer copper layer of the second substrate are opposite and exposed outside the insulating shell; the signal terminals and the power terminals are exposed outside the insulating shell along the horizontal direction on both sides of the insulating shell; the connection copper layer of the first substrate comprises a first main copper foil, a second main copper foil and a third main copper foil which are insulated from each other, and the connection copper layer of the second substrate comprises a fourth main copper foil, a fifth main copper foil and a sixth main copper foil which are insulated from each other; the first main copper foil is connected to the soldering surface of the upper bridge arm chip, the second main copper foil is connected to the upper surface of the lower bridge arm chip, and the sixth main copper foil is connected to the soldering surface of the lower bridge arm chip and the upper surface of the upper bridge arm chip; the power terminals comprise a direct current positive terminal, a direct current negative terminal and an alternating current terminal, the direct current positive terminal is connected to the first main copper foil and the fourth main copper foil, the direct current negative terminal is connected to the second main copper foil and the fifth main copper foil, and the alternating current terminal is connected to the third main copper foil and the sixth main copper foil; a commutation loop current enters the first main copper foil from the direct current positive terminal, flows through the upper bridge arm chip and then enters the sixth main copper foil, flows through the alternating current terminal and the lower bridge arm chip, and then enters the second main copper foil, and flows out of the power semiconductor module from the direct current negative terminal. 2.The power semiconductor module according to claim 1, characterized in that, a first conductive pad is arranged between the connection copper layer of the first substrate and the upper bridge arm chip, the connection copper layer of the first substrate is connected to the bottom surface of the first conductive pad, and the top surface of the first conductive pad is connected to the soldering surface of the upper bridge arm chip, so that the height of the upper surface of the upper bridge arm chip is equal to the height of the upper surface of the signal terminal. The second substrate is provided with a second conductive pad between the connecting copper layer and the lower bridge arm chip, so that the connecting copper layer of the second substrate is connected with the bottom surface of the second conductive pad, and the top surface of the second conductive pad is connected with the solder surface of the lower bridge arm chip, so that the height of the upper surface of the lower bridge arm chip is equal to the height of the lower surface of the signal terminal.

3. The power semiconductor module according to claim 1, characterized in that, A positioning groove is arranged on the side of the insulating shell close to the signal terminal and offset from the center line of the insulating shell.

4. The power semiconductor module according to claim 1, characterized in that, The connecting copper layer of the first substrate further comprises a first auxiliary copper foil, a second auxiliary copper foil, a third auxiliary copper foil, a fourth auxiliary copper foil and a fifth auxiliary copper foil, which are insulated from each other, and the third auxiliary copper foil and the fourth auxiliary copper foil are respectively connected to the upper surface of the lower bridge arm chip. The connecting copper layer of the second substrate further comprises a sixth auxiliary copper foil, a seventh auxiliary copper foil, an eighth auxiliary copper foil, a ninth auxiliary copper foil and a tenth auxiliary copper foil, which are insulated from each other, and the seventh auxiliary copper foil and the eighth auxiliary copper foil are respectively connected to the upper surface of the upper bridge arm chip. The signal terminal comprises a first collector signal terminal, a second collector signal terminal, a first emitter signal terminal, a second emitter signal terminal, a first gate signal terminal and a second gate signal terminal. The first collector signal terminal connects the first main copper foil and the sixth auxiliary copper foil, the first emitter signal terminal connects the first auxiliary copper foil and the seventh auxiliary copper foil, the first gate signal terminal connects the second auxiliary copper foil and the eighth auxiliary copper foil, the second collector signal terminal connects the fifth auxiliary copper foil and the sixth main copper foil, the second emitter signal terminal connects the fourth auxiliary copper foil and the tenth auxiliary copper foil, and the second gate signal terminal connects the third auxiliary copper foil and the ninth auxiliary copper foil. The commutation loop current enters the first main copper foil from the direct current positive terminal, flows through the first collector signal terminal and the upper bridge arm chip, enters the sixth main copper foil, the seventh auxiliary copper foil and the eighth auxiliary copper foil, respectively flows through the first emitter signal terminal, the first gate signal terminal, the alternating current terminal, the second collector signal terminal and the lower bridge arm chip, and then enters the second main copper foil, the third auxiliary copper foil and the fourth auxiliary copper foil, flows through the second emitter signal terminal and the second gate signal terminal, and flows out of the power semiconductor module from the direct current negative terminal.

5. The power semiconductor module according to claim 1, characterized in that, The upper bridge arm chip comprises an upper bridge arm IGBT chip and an upper bridge arm diode chip, and the lower bridge arm chip comprises a lower bridge arm IGBT chip and a lower bridge arm diode chip.

6. The power semiconductor module according to claim 1, characterized in that, The connecting copper layer of the first substrate is connected with the soldering point surface of the upper bridge arm chip through vacuum reflow soldering, and the connecting copper layer of the second substrate is connected with the upper surface of the upper bridge arm chip through vacuum reflow soldering; The connecting copper layer of the second substrate is connected with the soldering point surface of the lower bridge arm chip through vacuum reflow soldering, and the connecting copper layer of the first substrate is connected with the upper surface of the lower bridge arm chip through vacuum reflow soldering.

7. The power semiconductor module according to claim 2, characterized in that The material of the first conductive pad and the second conductive pad comprises aluminum silicon carbide, molybdenum copper alloy or copper.

8. A power semiconductor package assembly, characterized in that The power semiconductor package assembly comprises at least three power semiconductor modules as claimed in any one of claims 1-7, and each of the power semiconductor modules is arranged in parallel in the same direction. A heat sink is connected to the outer copper layer of the first substrate and the outer copper layer of the second substrate of each of the power semiconductor modules.

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