A Hardware Layout Optimization Method, Device, Electronic Device and Storage Medium for FPGA

Abstract

The embodiments of the present invention disclose a method, apparatus, electronic device, and storage medium for optimizing the hardware layout of an FPGA. The method includes: obtaining the RTL code of the FPGA to be optimized; constructing an abstract hardware module diagram of the FPGA to be optimized based on the RTL code of the FPGA to be optimized; performing cross-region optimization on the current hardware layout structure of the FPGA to be optimized based on the abstract hardware module diagram and cross-region associated resource parameters to obtain a cross-region optimized hardware layout structure; and performing intra-region optimization on the cross-region optimized hardware layout structure based on the abstract hardware module diagram and intra-region associated resource parameters to obtain a target optimized hardware layout structure of the FPGA to be optimized. The technical solution of the embodiments of the present invention can optimize the overall hardware layout of the FPGA, thereby reducing the latency of the FPGA and improving the frequency performance of the FPGA.

Description

Technical Field

[0001] The embodiments of the present invention relate to the technical field of FPGA (Field Programmable Gate Array) hardware design, and in particular to a method, device, electronic device, and storage medium for optimizing FPGA hardware layout. Background Art

[0002] Deep learning is currently being widely applied in various artificial intelligence fields, with a wide variety of model algorithms emerging one after another and achieving remarkable results. However, this also incurs enormous computational and memory usage. For example, GoogLeNet (Google's deep neural network model) requires 6.99M parameters and 1580M computational resources for inference. Therefore, to accelerate the deployment and inference of related applications, the high-performance computing chip industry has also seen significant growth, driven by large-scale computing applications like deep learning. To achieve high performance, the chip area used has reached hundreds of mm². Multi-die packaging provides a promising approach for achieving the increasingly aggressive power, performance, and area trade-offs in actual production. The latest multi-die FPGAs utilize silicon interposers to integrate multiple reconfigurable regions, enabling more logic to be packed into a single device. Such multi-die FPGA systems consist of multiple FPGA reconfigurable logic regions connected via pre-configured external connections. Compared to the interconnect network within the reconfigurable regions, the number of these external connections, also known as super long lines (SLLs), is limited.

[0003] For mapping the overall hardware design to the FPGA board, there is currently a relatively similar process. Figure 1 This is a schematic diagram of the overall process of designing FPGA based on Vivado (an integrated design environment) design tools in the prior art. Figure 1 The figure below illustrates the entire process of Xilinx's Vivado design tool, from compiling the RTL (Register Transfer Level) design to generating the bitstream that is ultimately burned into the FPGA board. The RTL code can be generated into the board structure after completing the pre-implementation simulation and implementation deployment phases. Before generating the bitstream, the design results are further optimized and evaluated through timing closure and design analysis. Designs that fail to meet timing requirements are terminated. During the implementation deployment phase, the FPGA hardware logic layout and logic routing processes impact timing closure and design analysis. Logic layout primarily involves the layout of the FPGA hardware design.

[0004] Currently, work on optimizing the layout design of multi-die FPGA architectures primarily focuses on partitioning the hardware design across different dies. However, due to the nature of RTL, these partitioning methods must adhere to loop-accurate specifications. Building on this, researchers have proposed optimizing bus length and aspect ratio based on the facet stacking planar graph. Other researchers have attempted to modify the layout cost function to reduce die crossings, but this results in designs being confined to fewer dies, further increasing local congestion. Another optimization approach involves designing to minimize total wire length while simultaneously reducing the sum of die crossing delays for comprehensive optimization. Another optimization approach, AutoBridge (an existing hardware layout optimization method for FPGAs), further builds on this approach by modeling the total bandwidth of cross-die connections and favoring a more balanced layout across all slots, defined by reconfigurable region boundaries and I / O (Input / Output) groups.

[0005] During the process of implementing the present invention, the inventors discovered that in the production and manufacturing of modern multi-chip FPGAs, the resource conditions at different locations vary greatly, and some key resources are only available at specific locations, such as external interfaces and DDR (Double Data Rate SDRAM) connections. Therefore, these differences have a significant impact on the setting of hardware layout strategies. Figure 2 The figure shows the resource overhead ratios of different hardware functional units. The sample hardware design features multiple different types of components, including read / write units, pipelines, caches, control units, and compute units. After normalizing the resource usage of these units, it can be seen that different types of components tend to use different types of resources. Furthermore, these components not only vary in number but also have complex connections. If these resource preferences and varying quantities are not comprehensively considered during the layout phase, they will create numerous design bottlenecks. However, current FPGA hardware layout optimization methods fail to consider the impact of these factors, resulting in suboptimal optimization results. Summary of the Invention

[0006] Embodiments of the present invention provide a method, device, electronic device, and storage medium for optimizing the hardware layout of an FPGA, which can optimize the overall hardware layout of the FPGA, thereby reducing the latency of the FPGA and improving the frequency performance of the FPGA.

[0007] According to one aspect of the present invention, a method for optimizing FPGA hardware layout is provided, comprising:

[0008] Obtain the RTL code of the register conversion level circuit of the FPGA to be optimized;

[0009] Constructing an abstract hardware module diagram of the FPGA to be optimized according to the RTL code of the FPGA to be optimized;

[0010] Performing cross-region optimization on the current hardware layout structure of the FPGA to be optimized according to the abstract hardware module diagram and the cross-region associated resource parameters to obtain a cross-region optimized hardware layout structure;

[0011] The cross-region optimized hardware layout structure is optimized within the region according to the abstract hardware module diagram and the region-associated resource parameters to obtain the target optimized hardware layout structure of the FPGA to be optimized.

[0012] According to another aspect of the present invention, there is provided a device for optimizing hardware layout of an FPGA, comprising:

[0013] RTL code acquisition module, used to obtain the RTL code of the FPGA to be optimized;

[0014] An abstract hardware module diagram construction module, configured to construct an abstract hardware module diagram of the FPGA to be optimized based on the RTL code of the FPGA to be optimized;

[0015] a cross-region optimization module, configured to perform cross-region optimization on the current hardware layout structure of the FPGA to be optimized according to the abstract hardware module diagram and the cross-region associated resource parameters, to obtain a cross-region optimized hardware layout structure;

[0016] The intra-region optimization module is used to perform intra-region optimization on the cross-region optimized hardware layout structure according to the abstract hardware module diagram and the intra-region associated resource parameters to obtain the target optimized hardware layout structure of the FPGA to be optimized.

[0017] According to another aspect of the present invention, an electronic device is provided, comprising:

[0018] at least one processor; and

[0019] a memory communicatively connected to the at least one processor; wherein,

[0020] The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can execute the FPGA hardware layout optimization method described in any embodiment of the present invention.

[0021] According to another aspect of the present invention, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the FPGA hardware layout optimization method described in any embodiment of the present invention when executed.

[0022] The embodiment of the present invention constructs an abstract hardware module diagram of the FPGA to be optimized based on the acquired RTL code of the FPGA to be optimized, performs cross-zone optimization on the current hardware layout structure of the FPGA to be optimized based on the abstract hardware module diagram and cross-zone associated resource parameters to obtain a cross-zone optimized hardware layout structure, and performs intra-zone optimization on the cross-zone optimized hardware layout structure based on the abstract hardware module diagram and intra-zone associated resource parameters to obtain a target optimized hardware layout structure of the FPGA to be optimized. This solves the problem of poor optimization effect of existing FPGA hardware layout optimization methods and can achieve overall hardware layout optimization of the FPGA, thereby reducing the FPGA's latency and improving the FPGA's frequency performance.

[0023] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present invention, nor is it intended to limit the scope of the present invention. Other features of the present invention will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0025] Figure 1 This is a schematic diagram of the overall process of designing FPGA based on Vivado design tools in the prior art;

[0026] Figure 2 This is a schematic diagram of resource overhead ratios of different types of hardware functional units in an FPGA in the prior art;

[0027] Figure 3 This is a flowchart of a method for optimizing FPGA hardware layout provided by the first embodiment of the present invention;

[0028] Figure 4 This is a schematic diagram of a multi-chip FPGA layout structure and a layout example provided in the first embodiment of the present invention;

[0029] Figure 5 This is a schematic diagram of resource distribution within each SLR horizontal block BLOCK in an FPGA provided by the first embodiment of the present invention;

[0030] Figure 6 This is a schematic diagram showing the effect of congestion level of an FPGA sample hardware design provided in the first embodiment of the present invention;

[0031] Figure 7This is a flowchart of a method for optimizing FPGA hardware layout provided by the second embodiment of the present invention;

[0032] Figure 8 This is a schematic diagram showing the effects of cross-region optimization and intra-region optimization on an FPGA to be optimized, provided by the second embodiment of the present invention;

[0033] Figure 9 This is a schematic diagram of a workflow for optimizing the overall layout of an FPGA provided by the second embodiment of the present invention;

[0034] Figure 10 This is a schematic diagram showing the effect of visualizing cross-wafer connection edges after an Across-SLR strategy is implemented in the second embodiment of the present invention;

[0035] Figure 11 This is a schematic diagram showing the comparison of frequency results achieved by a sample program provided in the second embodiment of the present invention on the U250 and U280 platforms respectively;

[0036] Figure 12 This is a schematic diagram showing the effect of comparing resource overhead of a sample program after FrqBooster optimization provided by the second embodiment of the present invention;

[0037] Figure 13 This is a schematic diagram showing the effect of local congestion after deployment of an FrqBooster optimization provided by the second embodiment of the present invention;

[0038] Figure 14 This is a schematic diagram showing the effect of comparing the frequency results achieved by AutoBridge on the U250 and U280 platforms using a sample program provided in the second embodiment of the present invention;

[0039] Figure 15 1 is a schematic diagram showing a comparative effect of resource adaptability compared to the AutoBridge implementation result provided by the second embodiment of the present invention;

[0040] Figure 16 This is a schematic diagram of an FPGA hardware layout optimization device provided in a third embodiment of the present invention;

[0041] Figure 17 This is a structural diagram of an electronic device provided in Example 4 of the present invention. DETAILED DESCRIPTION

[0042] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0043] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0044] Example 1

[0045] Figure 3 This is a flowchart of an FPGA hardware layout optimization method provided by the first embodiment of the present invention. This embodiment is applicable to the situation where the FPGA hardware layout structure is optimized across regions and within regions using the FPGA abstract hardware module diagram. The method can be executed by an FPGA hardware layout optimization device, which can be implemented by software and / or hardware and can generally be integrated into an electronic device. The electronic device can be a terminal device or a server device. As long as it can execute the FPGA hardware layout optimization method, the embodiment of the present invention does not limit the specific device type of the electronic device. Accordingly, if Figure 3 As shown, the method includes the following operations:

[0046] S110 , obtaining the RTL code of the FPGA to be optimized.

[0047] The FPGA to be optimized can be one that has completed a preliminary hardware layout design and needs to optimize the hardware layout. The RTL code can be the kernel code written in a language such as C / C++ for the FPGA to be optimized, compiled using an HLS (High-Level Synthesis) tool.

[0048] In an embodiment of the present invention, before optimizing the hardware layout of the FPGA to be optimized, the RTL code of the FPGA to be optimized can be obtained first, so as to obtain the current hardware layout information of the FPGA through the RTL code of the FPGA to be optimized.

[0049] S120. Construct an abstract hardware module graph of the FPGA to be optimized according to the RTL code of the FPGA to be optimized.

[0050] Among them, the abstract hardware module graph can be a schematic structural diagram composed of hardware modules abstracted from the FPGA to be optimized based on each RTL code, and it is a graph structure.

[0051] It can be understood that the FPGA to be optimized includes various types of RTL codes, and each RTL code can implement the function of a specific hardware module in the FPGA to be optimized. Correspondingly, after obtaining the RTL code of the FPGA to be optimized, each RTL code can be parsed to determine the hardware module function corresponding to each RTL code, so as to abstractly represent the hardware design of the FPGA to be optimized as a graph structure.

[0052] Optionally, the module function structure of the RTL code can be obtained through PyVerilog (a compiler for compiling Verilog hardware description language into executable hardware). Further, based on each RTL code, each hardware module in the FPGA to be optimized can be abstracted, and then an abstract hardware module graph of the FPGA to be optimized can be constructed based on the abstracted hardware modules. The abstract hardware module graph can be represented as graph G<V, E>. In the abstract hardware module graph G<V, E>, each RTL code can be represented as a vertex V. For graph G<V, E>, the vertex set V∈{V i |0≤i<N} represents different hardware modules in the hardware design of the FPGA to be optimized, and the connection edge set E∈{E_j|0≤j<M} represents the connection relationship between each hardware module.

[0053] S130. Perform cross-region optimization on the current hardware layout structure of the FPGA to be optimized according to the abstract hardware module graph and cross-region associated resource parameters, and obtain a cross-region optimized hardware layout structure.

[0054] Among them, the cross-region associated resource parameters can be the parameters of relevant resources referred to when performing cross-region optimization on the current hardware layout structure of the FPGA to be optimized, and this parameter can reflect the resource limitation situation between different regions in the FPGA to be optimized. The current hardware layout structure can be the current hardware layout structure of the FPGA to be optimized. The cross-region optimized hardware layout structure can be the hardware layout structure obtained after performing cross-region optimization on the current hardware layout structure of the FPGA to be optimized.

[0055] In the embodiments of the present invention, "cross-region" refers to crossing different programmable logic regions (Super Logic Regions, SLRs) in the FPGA, while "intra-region" refers to the same SLR region in the FPGA. Multi-chip FPGAs often have multiple SLR regions (hereinafter referred to as SLRs), each of which can include a certain amount of logic, storage, and DSP (Digital Signal Processor) resources. Among them, logic resources may include, but are not limited to, LUTs (Lookup Tables) and FFs (flip-flops), and storage resources may include, but are not limited to BRAMs (Block RAMs, the inherent hardware storage resources of the FPGA). Figure 4 This is a schematic diagram of a multi-chip FPGA layout structure and a layout example provided by the first embodiment of the present invention. In a specific example, Figure 4 Figures A and B illustrate the layout of Xilinx's Alveo U250 and U280 data center-class acceleration FPGA boards, which utilize a multi-die architecture. Both boards internally connect multiple SLRs (SLRs) via SLLs, with each SLR containing corresponding IO banks (a resource within the FPGA that manages the input and output pins on the FPGA chip). The U250 includes four SLRs, while the U280 includes three. Both connect to the host computer via PCIe (Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard) 3.0x16, enabling data transfer speeds of up to 8GT / s. The U250 connects to a total of 64GB of DDR4 memory for external data exchange via four DDR4 2400MT / s 16GB interfaces distributed across each SLR. The U280 integrates only 8GB of High Bandwidth Memory (HBM) in SLR0 for external data interaction, with a total bandwidth of 460GB / s. It also has 32 independent HBM interfaces with a capacity of 256MB at the bottom of the chip, connecting to the reconfigurable area.

[0056] Figure 4Figure C in Figure 1 shows some examples of layouts in large-scale FPGA hardware designs that connect modules across SLRs via SLLs. Understandably, hardware interconnects that cross multi-die boundaries incur significant latency penalties. Furthermore, current programmable logic also embeds specialized IP (Interrupt Priority Register) blocks, such as PCIe and DDR controllers. These IP blocks typically have fixed locations near dedicated I / O banks and consume significant amounts of nearby programmable resources. Consequently, these specialized IP blocks often bypass nearby signals, leading to more expensive and / or longer routing paths. Furthermore, modules that interact with these fixed-location IP blocks face more restricted layouts, which in turn results in remote communication with other modules. These combined factors often further reduce the FPGA's ultimate achievable clock frequency. Therefore, the deployment and limitations of cross-region-related resources within an FPGA significantly impact its frequency performance.

[0057] Therefore, when optimizing the hardware layout of the FPGA to be optimized, one can first consider using the abstract hardware module diagram generated above to determine the deployment relationship between each SLR, and then combine the cross-region associated resource parameters between different SLRs to perform cross-region optimization on the current hardware layout structure of the FPGA to be optimized, such as optimizing the cross-wafer connection between SLRs and the position allocation of different hardware modules within each SLR. After completing the cross-region optimization of the current hardware layout structure of the FPGA to be optimized, a cross-region optimized hardware layout structure can be obtained. The cross-region optimized hardware layout structure can achieve the optimal resource allocation between different SLRs of the FPGA to be optimized.

[0058] S140 , performing intra-region optimization on the cross-region optimized hardware layout structure according to the abstract hardware module diagram and intra-region associated resource parameters to obtain a target optimized hardware layout structure of the FPGA to be optimized.

[0059] The intra-region-related resource parameters may be parameters of related resources referenced during intra-region optimization of the current hardware layout structure of the FPGA to be optimized. These parameters may reflect resource constraints within a region of the FPGA to be optimized. The target optimized hardware layout structure may be the hardware layout structure obtained by intra-region optimization of the cross-region optimized hardware layout structure.

[0060] Figure 5 Schematic diagram of resource distribution within each SLR horizontal block BLOCK in an FPGA provided by the first embodiment of the present invention. In a specific example, Figure 4 and Figure 5As shown in the figure, the FPGA is divided horizontally into blocks. The resource distribution within each block varies, indicating that the resource distribution ratios on the FPGA board vary. This resource distribution significantly impacts the resource layout within each SLR of the FPGA. Current FPGA hardware layout optimization solutions typically focus on optimizing cross-chip interconnects between hardware modules. To reduce this metric, the resource overhead of different components is often overlooked during the layout phase. As a result, once resource utilization reaches 70-80% in some locations, various types of congestion are likely to occur. FPGA congestion is generally categorized into three types: global congestion, long congestion, and short congestion. These three types represent different resource locations where excessive overhead prevents optimal routing, thus affecting the FPGA's final frequency performance.

[0061] Figure 6 This is a schematic diagram showing the effect of congestion level of an FPGA sample hardware design provided by the first embodiment of the present invention. In a specific example, Figure 6 The figure shows a partial congestion level graph and congestion report for a sample hardware design after compilation and deployment. Darker colors represent higher congestion levels in that area. The congestion type in the congestion report indicates that the multiple blocks of congestion in that area are caused by excessive resource overhead of different types. The congested areas all exceed 80% of resource usage, but the overall resource usage of the sample design actually does not exceed 50%. This result can significantly affect the wiring of certain components near the congested area, making it impossible to meet the design's timing constraints, preventing the critical path from being reduced, and thus limiting the final frequency performance of the FPGA.

[0062] It can be seen that the deployment and restrictions of related resources in the FPGA area also have a significant impact on the frequency performance of the FPGA.

[0063] Therefore, when optimizing the hardware layout of the FPGA to be optimized, the current hardware layout structure of the FPGA to be optimized is cross-region optimized. After obtaining the cross-region optimized hardware layout structure, the cross-region optimized hardware layout structure can be further optimized within the region based on the abstract hardware module diagram and the associated resource parameters within the region, such as optimizing the position allocation of different hardware modules within the SLR. Optionally, each SLR can be optimized within the region in parallel to improve the efficiency of the optimization within the region. After completing the optimization within the region of each SLR, the target optimized hardware layout structure of the FPGA to be optimized can be obtained to complete the resource optimization allocation of the entire FPGA to be optimized.

[0064] It can be seen that the above-mentioned FPGA hardware layout optimization method realizes the two-stage resource balancing optimization design to optimize the overall hardware layout of FPGA by adopting cross-region optimization and intra-region optimization methods. It can alleviate the local congestion phenomenon in FPGA chip design and effectively improve the final frequency performance of FPGA.

[0065] The embodiment of the present invention constructs an abstract hardware module diagram of the FPGA to be optimized based on the acquired RTL code of the FPGA to be optimized, performs cross-zone optimization on the current hardware layout structure of the FPGA to be optimized based on the abstract hardware module diagram and cross-zone associated resource parameters to obtain a cross-zone optimized hardware layout structure, and performs intra-zone optimization on the cross-zone optimized hardware layout structure based on the abstract hardware module diagram and intra-zone associated resource parameters to obtain a target optimized hardware layout structure of the FPGA to be optimized. This solves the problem of poor optimization effect of existing FPGA hardware layout optimization methods and can achieve overall hardware layout optimization of the FPGA, thereby reducing the FPGA's latency and improving the FPGA's frequency performance.

[0066] Example 2

[0067] Figure 7 This is a flowchart of a method for optimizing FPGA hardware layout according to the second embodiment of the present invention. This embodiment is based on the above embodiment and is specific. It provides multiple specific optional implementation methods for constructing an abstract hardware module diagram of the FPGA to be optimized, and performing cross-region optimization and intra-region optimization on the current hardware layout structure of the FPGA to be optimized. Figure 7 As shown, the method of this embodiment may include:

[0068] S210: Obtain the RTL code of the FPGA to be optimized.

[0069] S220 , constructing an abstract hardware module diagram of the FPGA to be optimized according to the RTL code of the FPGA to be optimized.

[0070] In an optional embodiment of the present invention, constructing the abstract hardware module graph of the FPGA to be optimized based on the RTL code of the FPGA to be optimized may include: determining multiple abstract RTL modules based on the RTL code of the FPGA to be optimized; determining the relative positions and connection relationships between each of the abstract RTL modules; abstracting each of the abstract RTL modules into each vertex of the abstract hardware module graph; determining the relative positions and connection edges between each vertex in the abstract hardware module graph based on the relative positions and connection relationships between each of the abstract RTL modules, to obtain the abstract hardware module graph of the FPGA to be optimized.

[0071] The abstract RTL module is a hardware function module abstracted from each RTL code.

[0072] In a specific example, Figure 4 As shown in Figure C, for each RTL code in the FPGA to be optimized, each RTL code can be abstracted into a corresponding hardware function module in the FPGA to be optimized. Therefore, the hardware function implemented by each RTL code can be abstracted into a corresponding abstract RTL module. This abstract RTL module can serve as a vertex structure in the abstract hardware module graph, such as vertices 1-9. Furthermore, the relative positions and connection relationships between the abstract RTL modules can be determined based on the RTL code in the FPGA to be optimized. For example, a directed connection relationship exists between abstract RTL module 1 and abstract RTL module 3. Accordingly, the relative positions of each vertex in the abstract hardware module graph can be determined based on the relative positions of the abstract RTL modules. For example, the relative positions between abstract RTL modules 1 and 2 can determine that vertex 1 and vertex 2 belong to SLR0, and vertex 1 is to the left of vertex 2. Furthermore, based on the connection relationships between the abstract RTL modules, connecting edges can be established between the vertices. For example, a directed connection edge between vertex 1 and vertex 3 can be established based on the directed connection relationship between abstract RTL module 1 and abstract RTL module 3. After determining the relative positions and connecting edges between the vertices in the abstract hardware module graph, the abstract hardware module graph of the FPGA to be optimized can be obtained.

[0073] S230: Optimize the cross-wafer connection relationship between the SLRs of the current hardware layout structure according to the abstract hardware module diagram.

[0074] Since the multi-chip FPGA architecture is divided into multiple non-intersecting SLR areas, the routing delays at the intersection of the areas are relatively long, which will cause additional signal delays. At the same time, the limited availability and high cost of cross-wafer connections SLL increase the complexity of the physical design of such a multi-chip system. Therefore, the FPGA layout and routing tools must consider the cost of using SLL connections in the cost function, and longer line lengths and higher delays will also directly affect the value of the entire worst negative timing margin (Worst Negative Slack, WNS), thereby further reducing the potential frequency performance of the FPGA. In addition, such limited available connections may also cause resource congestion at the boundaries of the reconfigurable area, thereby affecting the overall hardware design performance. As shown below, the solution F max As shown in the formula, longer wires and higher delays directly affect the WNS value of the clock signal in the clock path portion, thereby reducing the potential frequency performance of the FPGA.

[0075]

[0076] Among them, F maxIndicates the maximum frequency performance, T indicates the target clock period. The formula shows that when WNS<0, F max It increases monotonically with the value of WNS.

[0077] To this end, considering that frequent and excessively long inter-chip connections in FPGA layout planning will occupy additional resources, thereby affecting the hardware frequency performance after deployment, when performing cross-region optimization on the current hardware layout structure of the FPGA to be optimized, the cross-chip connection relationship between the SLRs of the current hardware layout structure can be first optimized according to the abstract hardware module diagram.

[0078] Alternatively, a strategy that optimizes cross-die connections between SLRs can be called an Across-SLR strategy. A strategy that optimizes the abstract RTL module placement relationships between SLRs in the current hardware layout structure can be called an Inter-Die resource balancing strategy. A strategy that optimizes the cross-die optimized hardware layout structure within a die can be called an Intra-Die resource balancing strategy.

[0079] When optimizing the hardware layout of an FPGA, it is necessary to perform hardware modeling on the FPGA to be optimized. Table 1 shows the symbols and definitions of the main variables used in the subsequent optimization process.

[0080] Table 1 Main parameters and description of hardware modeling

[0081]

[0082] In an optional embodiment of the present invention, optimizing the cross-chip connection relationship between the SLRs of the current hardware layout structure according to the abstract hardware module diagram may include: determining a source node vector and a target node vector according to the abstract hardware module diagram; calculating a cross-region distance according to the source node vector and the target node vector; determining a cross-chip connection relationship optimization target according to the cross-region distance and a bandwidth vector; and solving the cross-chip connection relationship optimization target to optimize the cross-chip connection relationship between the SLRs of the current hardware layout structure.

[0083] The source node vector is a vector consisting of source nodes, and the target node vector is a vector consisting of target nodes. The source node and the target node can be two nodes in different SLRs. The cross-region distance can be the distance calculated from the source node to the target node. The cross-wafer connection relationship optimization target can be an optimization target configured based on the cross-region distance.

[0084] Specifically, in the abstract hardware module diagram G<V,E> Based on this, the source node vector can be determined and the target node vector And use the decision variable location information LF To define the cross-area distance D. And on this basis, further combine the bandwidth vector Constructing the cross-chip connection relationship optimization target Obj of the Across-SLR strategy across Accordingly, after obtaining the cross-chip connection relationship optimization target, the cross-chip connection relationship optimization target can be solved to optimize the cross-chip connection relationship between the SLRs of the current hardware layout structure.

[0085] In an optional embodiment of the present invention, calculating the cross-region distance according to the source node vector and the target node vector may include:

[0086] The cross-zone distance is calculated based on the following formula:

[0087] D j =2*Manhattan(L F [src j ,L F [dst j ])-1

[0088] Determining the cross-wafer connection relationship optimization target according to the cross-zone distance and the bandwidth vector may include:

[0089] The cross-wafer connection relationship optimization target is calculated based on the following formula:

[0090]

[0091] Among them, D j Indicates the cross-region distance, src j Represents the source node vector of the jth connection edge in the abstract hardware module graph, dst j represents the target node vector of the jth connection edge in the abstract hardware module graph, L F Indicates the position value of the vertex during cross-region optimization, which is the position information of the decision variable. across represents the cross-wafer connection relationship optimization target, w j Represents the bandwidth vector of the j-th connection edge in the abstract hardware module graph.

[0092] As can be seen from the above formula, this embodiment of the present invention uses Manhattan distance in the cross-zone distance objective function to calculate cross-zone distance. A longer Manhattan distance results in a larger cross-zone distance value, which can reduce the impact of long-distance communication. Furthermore, by using negative objective function values, the interconnected modules of the source and destination nodes can be placed as close to the same region as possible. This design allows for the aggregation of more hardware modules in the resulting floor plan and reduces the cross-border overhead of multiple modules.

[0093] Optionally, a mixed integer quadratic programming approach may be used to solve the optimization problem of the cross-wafer connection relationship optimization objective.

[0094] S240: Optimize the abstract RTL module layout relationship between the SLRs of the current hardware layout structure according to the abstract hardware module diagram and the cross-region associated resource parameters of the SLR to obtain the cross-region optimized hardware layout structure.

[0095] The abstract RTL module layout relationship is also the layout relationship of the abstract RTL modules included in an SLR.

[0096] One of the important limitations in the layout planning of larger designs in multi-chip FPGAs is that different SLRs have different upper limits on the availability of different resources. Therefore, an embodiment of the present invention provides a cross-zone resource balancing strategy, namely an inter-Die resource balancing strategy, to complete the perception of congestion status between different SLRs for layout optimization. The inter-Die resource balancing strategy focuses on the location allocation of different abstract RTL modules caused by the different upper limits on resource usage of different SLRs. The inter-Die resource balancing strategy can optimize the abstract RTL module layout relationship between the SLRs of the current hardware layout structure based on the abstract hardware module diagram and the cross-zone associated resource parameters of the SLR.

[0097] In an optional embodiment of the present invention, the cross-region associated resource parameters of the SLR may include SLR resource overhead, cross-region resource availability, cross-region maximum resource usage limit and difference vectors between different SLRs; optimizing the abstract RTL module layout relationship between the SLRs of the current hardware layout structure based on the abstract hardware module diagram and the cross-region associated resource parameters of the SLR may include: calculating the resource utilization rate of each SLR based on the SLR resource overhead, the cross-region resource availability and the cross-region maximum resource usage limit; determining a cross-region resource balancing target based on the resource utilization rate of each SLR and the difference vectors between the different SLRs; and solving the cross-region resource balancing target to optimize the abstract RTL module layout relationship between the SLRs.

[0098] Among them, the cross-zone resource balancing goal is also the optimization goal of the inter-Die resource balancing strategy.

[0099] In the embodiment of the present invention, in the abstract hardware module diagram G<V,E> Based on the SLR cross-region associated resource parameters, the SLR resource cost R can be obtained. cost and decision variable location information L F To define the resource utilization R in each SLR interThen, by calculating the square of the resource ratio difference between the SLR resource utilization rate and the difference vector between different SLRs, the cross-region resource balancing target Obj of the inter-Die resource balancing strategy can be constructed. inter .

[0100] In an optional embodiment of the present invention, calculating the resource utilization rate of each SLR based on the SLR resource overhead, the available amount of cross-zone resources, and the maximum cross-zone resource usage limit may include: calculating the resource utilization rate of each SLR based on the following formula:

[0101]

[0102] Determining the inter-region resource balancing target according to the resource usage rate of each SLR and the difference vector between different SLRs may include: calculating the inter-region resource balancing target based on the following formula:

[0103]

[0104] Among them, R inter represents the resource utilization rate of each SLR, Represents the transpose of the position value of the vertex during cross-region optimization, R cost Represents the SLR resource overhead, R F Indicates the available amount of cross-region resources, Indicates the maximum resource usage limit across regions, Obj inter represents the cross-region resource balancing target, Δ inter Denotes the difference vector between the different SLRs. inter As a known quantity, the impact of imbalance in resource utilization among SLRs can be reduced. inter Solving the minimization, that is, solving the minimization of the square of the difference will also make the resource overhead ratio of each SLR as similar as possible.

[0105] Optionally, a mixed integer quadratic programming approach may be used to solve the optimization problem of cross-regional resource balancing objectives.

[0106] In an optional embodiment of the present invention, the above method may also include: determining a first optimization weight of the cross-chip connection relationship optimization target and a second optimization weight of the cross-region resource balancing target; weighting the cross-chip connection relationship optimization target and the cross-region resource balancing target according to the first optimization weight and the second optimization weight to obtain a comprehensive cross-region optimization target; solving the comprehensive cross-region optimization target to optimize the abstract RTL module layout relationship between the SLRs of the current hardware layout structure to obtain the cross-region optimized hardware layout structure.

[0107] The first optimization weight may be a weight adapted to the cross-wafer connection relationship optimization objective. The second optimization weight may be a weight adapted to the cross-region resource balancing objective. The comprehensive cross-region optimization objective may be a cross-region optimization objective determined based on the cross-wafer connection relationship optimization objective and the cross-region resource balancing objective.

[0108] Since both the Across-SLR strategy and the inter-Die resource balancing strategy are cross-zone optimization strategies, after determining the cross-chip connection relationship optimization target based on the Across-SLR strategy and determining the cross-zone resource balancing target based on the inter-Die resource balancing strategy, the first optimization weight of the cross-chip connection relationship optimization target and the second optimization weight of the cross-zone resource balancing target can be determined respectively. The weight values of the first optimization weight and the second optimization weight can be determined dynamically in real time. That is, in different optimization rounds, the weight values of the first optimization weight and the second optimization weight can be the same or different, and the embodiment of the present invention does not limit this. Accordingly, after determining the first optimization weight of the cross-chip connection relationship optimization target and the second optimization weight of the cross-zone resource balancing target, the cross-chip connection relationship optimization target and the cross-zone resource balancing target can be weighted according to the first optimization weight and the second optimization weight to obtain a comprehensive cross-zone optimization target.

[0109] For example, it can be based on the formula: z =A·Obj across +B·Obj inter The cross-chip connection relationship optimization goal and cross-region resource balancing goal are weighted. z Represents the comprehensive cross-region optimization goal, A represents the first optimization weight, and B represents the second optimization weight.

[0110] Figure 8 This is a schematic diagram of the effect of cross-region optimization and intra-region optimization of an FPGA to be optimized provided by the second embodiment of the present invention. In a specific example, Figure 8 As shown, although Figure 8 The unoptimized hardware layout example in Figure A can meet the resource overhead constraints, but the uneven use of different resources between each SLR brings the risk of local congestion. Figure 8 After cross-region optimization, the hardware layout example in Figure A can be obtained as follows: Figure 8 The optimization effect shown in Figure B is used to balance the differences in cross-wafer resource utilization between different SLRs.

[0111] S250 , performing intra-region optimization on the cross-region optimized hardware layout structure according to the abstract hardware module diagram and intra-region associated resource parameters to obtain a target optimized hardware layout structure of the FPGA to be optimized.

[0112] In an optional embodiment of the present invention, the intra-region optimization of the cross-region optimized hardware layout structure according to the abstract hardware module diagram and the intra-region associated resource parameters to obtain the target optimized hardware layout structure of the FPGA to be optimized may include: calculating the resource overhead ratio of the current SLR according to the abstract hardware module diagram and the intra-region associated resource parameters of the SLR; determining the intra-region resource balancing target according to the resource overhead ratio of the current SLR and the intra-region associated resource parameters of the SLR; solving the intra-region resource balancing target to perform intra-region optimization on the cross-region optimized hardware layout structure to obtain the target optimized hardware layout structure of the FPGA to be optimized.

[0113] The current SLR is the SLR currently being optimized within the area, and the resource overhead ratio is the ratio of currently occupied resources to the total available resources.

[0114] Another significant limitation in floorplanning larger designs in multi-die FPGAs is the inconsistent resource ratios across different regions within the same SLR. Therefore, embodiments of the present invention provide an intra-die resource balancing strategy to optimize the allocation of unevenly distributed resources within the same SLR.

[0115] In the embodiment of the present invention, in the abstract hardware module diagram G<V,E> Based on the SLR region-associated resource parameters, the resource cost R of each vertex in the SLR region can be obtained. cost and decision variable location information L S , we can define the resource overhead ratio R in each SLR region intra The intra-region resource balancing target of each SLR is further determined based on the resource overhead ratio in each SLR region, thereby solving the intra-region resource balancing target to optimize the cross-region optimized hardware layout structure within the region and obtain the target optimized hardware layout structure of the FPGA to be optimized.

[0116] In an optional embodiment of the present invention, the intra-area associated resource parameters of the SLR may include SLR resource overhead, intra-area resource availability, intra-area maximum resource usage limit, and difference vectors of different areas of the current SLR; and calculating the resource overhead ratio of the current SLR according to the abstract hardware module diagram and the intra-area associated resource parameters of the SLR may include: calculating the resource overhead ratio of the current SLR based on the following formula:

[0117]

[0118] Determining the intra-area resource balancing target according to the resource overhead ratio of the current SLR and the intra-area associated resource parameter of the SLR may include: calculating the intra-area resource balancing target based on the following formula:

[0119] Obj intra =∑(Δ intra ×R intra [slr]) 2

[0120] Among them, R intra [slr] represents the resource overhead ratio of the current SLR, Represents the transpose of the position value of the vertex when the current SLR is optimized within the region, R cost Represents the SLR resource overhead, R S Indicates the available amount of resources in the area, Indicates the maximum resource usage limit within the current SLR area, Obj intra represents the resource balancing target within the region, Δ intra Represents the difference vectors of different regions of the current SLR. intra is a known quantity, representing the difference vector in different areas of the same SLR, which can reduce the impact of uneven resource distribution. intra The solution is to minimize the square of the difference so that the resource cost of each area is similar.

[0121] According to the above formula, the intra-Die resource balancing strategy divides each SLR into two parts to optimize the resource balance within the SLR. Optionally, a mixed integer quadratic programming approach can be used to solve the optimization problem of the intra-zone resource balancing objective.

[0122] In a specific example, Figure 8 As shown in Figure C, shading is used to distinguish resource usage in two regions within the SLR. The intra-die resource balancing strategy adjusts the location of abstract RTL modules within the SLR to avoid overuse of certain resource types, thereby reducing the risk of local congestion within the SLR.

[0123] In summary, in the embodiment of the present invention, during the cross-region optimization of the FPGA to be optimized, the cross-chip connection relationship optimization target Obj in the Across-SLR strategy can be minimized. Across and the cross-district resource balancing objective Obj in the inter-Die resource balancing strategy interThe sum of , can be used to determine the SLR position of each abstract RTL module, as shown in the following cross-region optimization formula. In the process of optimizing the FPGA to be optimized, the intra-Die resource balancing strategy can be minimized in each SLR. intra , to determine the distribution of each abstract RTL module within each SLR, as shown in the following intra-region optimization formula.

[0124] Cross-region optimization: Minimize Sum(Obj across ,Obj inter )

[0125] Area optimization: Minimize Object intra

[0126] Make

[0127] In addition, the formula: The constraints for cross-region optimization F and intra-region optimization S are defined, including the decision variable L F / S and the maximum resource usage limit as a hyperparameter This constraint formula ensures that the optimization results do not exceed the resource usage limit of each region.

[0128] It should be noted that the aforementioned FPGA hardware layout optimization method can iteratively optimize the FPGA to be optimized until an optimization termination condition is met. Optionally, the optimization termination condition can be when the number of iterations reaches a set value, or when optimization cannot be completed based on the input parameters.

[0129] Figure 9 This is a schematic diagram of the overall layout optimization workflow of FPGA provided by the second embodiment of the present invention. In order to more clearly describe the technical solution provided by the embodiment of the present invention, refer to Figure 9 The figure specifically illustrates the overall process of hardware layout optimization of FPGA in the embodiment of the present invention. Figure 9 As shown in the figure, the entire optimization process first requires obtaining RTL code through PyVerilog to construct an abstract hardware block diagram of the FPGA to be optimized. Next, based on the hardware formula model, the abstract hardware block diagram undergoes two optimization steps in sequence, and the optimization problem is solved using mixed-integer quadratic programming. The resulting floorplan constraint results are then generated based on the output. Finally, a delay equalizer and RTL generator are used to update the pipeline of the dataflow core in the Verilog code. A TCL (Tool Command Language) script is generated to guide the Vivado tool in achieving the target floorplan.

[0130] like Figure 9 As shown, a constraint file can be used to guide and optimize the hardware layout process of the FPGA to be optimized. This mainly involves compiling the kernel code written in C / C++ into RTL code using the HLS tool, which is then implemented as a bitstream by Vivado for FPGA programming. The optimization method in this embodiment of the present invention mainly includes three strategies and two optimization processes: a cross-zone optimization process with an Across-SLR strategy and an inter-Die resource balancing strategy, and an intra-zone optimization process with an intra-Die resource balancing strategy. These processes are used to detect the congestion status of the FPGA to be optimized for layout optimization.

[0131] In an embodiment of the present invention, the overall hardware layout optimization method for the FPGA to be optimized can adopt an iterative optimization method. Specifically, in the initialization phase before optimization, the hardware design results of the FPGA core to be optimized can be directly provided by a traditional design tool. Then, based on the provided report, the worst negative timing margin data of the critical path is used to obtain the maximum clock frequency F of the FPGA to be optimized. max An estimate of the maximum clock frequency F max The estimated value can be used as a reference. Simultaneously, analyze the resource usage of each component of the FPGA to be optimized, as well as the placement and routing results, to determine the overall design congestion. Based on these conditions, analyze the current bottleneck location and update the relevant design parameters for the next iterative optimization phase.

[0132] During the iterative optimization process, we can first obtain the hardware design vertex set V and resource cost R cost , interconnected edge set E, target hardware resource availability R F , the available amount of hardware resources within SLR R S , maximum resource usage limit L, and optimization weights A and B, and calculates and outputs the optimal layout space Location based on the input parameters. After obtaining the input parameters, the following process can be executed cyclically:

[0133] First calculate the Across-SLR strategy target Obj across and inter-Die resource balancing strategy objective Obj inter , based on the formula: Obj Z =A·Obj across +B·Obj inter The two cross-region optimization objectives are weighted, and the weighted comprehensive cross-region optimization objective Obj ZSolve and obtain the cross-region optimization results. Based on the cross-region optimization results, perform intra-region optimization on each SLR, calculate the intra-Die equilibrium strategy target of each SLR, and solve the intra-Die equilibrium strategy target to obtain the final optimization result. After the current round of optimization process is completed, you can continue to return to calculate the Across-SLR strategy target Obj across and inter-Die resource balancing strategy objective Obj inter The optimization process continues until the termination condition is reached. As the final step in deploying the designed hardware core to the corresponding reconfigurable platform, the optimization method generates the layout of the FPGA hardware to be optimized in a gradually relaxed state and iterates the bottleneck optimization to generate the best possible result.

[0134] After the initialization phase, the iteration phase will repeatedly check the current generation information, reversely update the input parameters, and regenerate the hardware design according to the new constraints. In the current phase, the iteration constraints mainly take into account the resource constraints and parameter space. Since there may be situations where the design constraints cannot be achieved during the iteration process, in order to facilitate processing, after directly using parameter backtracking, the update step size of the design parameters can be reduced to perform the next step of verification. When the overall optimization search process reaches the termination condition or cannot continue, the optimal design parameters of the process will be output. In this way, the entire iteration phase is divided into three main steps:

[0135] (1) Multi-stage hardware design optimization: After generating input parameters, directly use RTL tools for simulation implementation. Figure 1 The workflow shown in the figure breaks down the design process into logic synthesis, logic optimization, logic placement, logic routing, and bitstream generation. The logic placement stage is where hardware design constraints have the greatest impact. The hardware placement optimization method for the FPGA to be optimized is also a key component of the logic placement phase. During the placement planning process, the optimization method first defines the Across-SLR strategy objectives and the Inter-Die Balance strategy objectives. After optimizing the overall objectives using the first and second optimization weights, the vertex positions are obtained during the cross-zone optimization phase and then divided by SLR. The second phase then performs intra-zone optimization, optimizing the intra-Die resources within each SLR to obtain the final placement result. This combination of three placement strategies can potentially achieve better timing performance for the FPGA to be optimized.

[0136] (2) Evaluation of RTL generated design results: After obtaining the final layout results of the FPGA to be optimized, the RTL design tool can be used to generate the hardware design bitstream of the optimized FPGA and evaluate the corresponding results. Under the guidance of the corresponding design constraints, the overall layout of the optimized FPGA hardware will be significantly different from the original design. Therefore, the congestion map and congestion report generated by the optimized FPGA hardware can be used to guide the update of the overall algorithm design parameters.

[0137] (3) Update design parameters: After evaluating the current design results, update the resource ratios and optimization target weights of different regions based on the corresponding congestion status of the optimized FPGA. For example, when congestion is unevenly distributed, the second optimization weight of the inter-die balancing strategy objective can be increased; if congestion is evenly distributed, but a certain SLR is severely congested, the resource allocation of that SLR region can be adjusted. This method can be used to distribute the entire FPGA IP design more evenly across the board, as appropriate, to reduce congestion risks from both global and local perspectives.

[0138] After the optimization method converges to the constraints, the final stage generates RTL design tools based on the converged design parameters to complete the entire iterative optimization method.

[0139] An embodiment of the present invention provides a hardware layout optimization method for FPGA deployment with maximum frequency boost, which can be called FrqBooster. It is aimed at large FPGA chips with multiple packages and reduces the worst-case latency performance by optimizing the overall layout to improve the final frequency result.

[0140] First, this embodiment of the present invention analyzes the connectivity between various component modules in FPGA hardware design and uses a planning algorithm to search for an appropriate component distribution, thereby reducing the impact of cross-chip connections on FPGA frequency. Next, this embodiment of the present invention analyzes the resource overhead of each component in the FPGA IP core design. Based on the target FPGA resource distribution, a two-stage resource balancing optimization design is implemented to alleviate local congestion in FPGA chip design. Finally, the overall layout is optimized to reduce the FPGA's worst-case latency performance, thereby improving the final FPGA frequency.

[0141] The present invention uses the FrqBooster hardware layout optimization method to optimize multiple FPGA experimental test cases, achieving frequency increases of up to 73% and 81% on the U250 and U280, respectively. Compared to related work on the same scale and sample, frequency increases of up to 21.2% and 36.1% were achieved on the U250 and U280 platforms, respectively.

[0142] In order to evaluate the FPGA hardware layout optimization method provided by the embodiment of the present invention, the embodiment of the present invention uses the tools provided by Xilinx to conduct two parts of experiments and comparative analysis. First, the effectiveness of FrqBooster is verified. Experiments are conducted on three cases of no optimization, coarse-grained layout optimization, and overall optimization in applications of different scales to compare the effectiveness of the FPGA hardware layout optimization method. Secondly, a comparative experiment is conducted on related work. Under the same conditions, the optimization results of the related work AutoBridge and FrqBooster are compared to illustrate the advantages of the FPGA hardware layout optimization method provided by the embodiment of the invention.

[0143] The Xilinx Alveo U250 and U280 were used as verification platforms in the experiments. These are custom FPGAs, Xilinx accelerator boards for data center use. Stacked Silicon Interconnect (SSI) technology is used throughout to achieve higher FPGA capacity, bandwidth, and energy efficiency. The Alveo U250 incorporates four Super Logic Regions (SLRs), each connected by very long wires (SLLs) near the side edges. The design tools used throughout the entire process were Vivado HLS, Vivado, and Vitis (Virtual Instrument Software Architecture) version 2019.02. Vivado provided resource consumption and interface information for the initial FPGA hardware design. Given the design parameters and constraints, Vitis generated a systematic evaluation of the entire FPGA hardware layout design. The optimization algorithm also used data collected during these processes to iteratively optimize the design layout parameters.

[0144] In order to make the algorithm more effective, some designs were made when assigning the values of the given initial input parameters. Like AutoBridge, the area division for Alveo U250 and Alveo U280 is based on the original design of the FPGA board and is divided into SLR units, while the SLR is divided into IO banks. In the end, FPGA U250 and U280 were divided into 8 and 6 sub-areas respectively. At the same time, for the resource usage constraints of each sample, the design tool is given 1.2 times the resource usage ratio in the initial stage, and the maximum does not exceed 90%. After completing the entire iterative search process, the Vitis tool will evaluate the overall design.

[0145] In order to illustrate the optimization effect brought by Frqbooster, the embodiment of the present invention provides two benchmarks for comparative analysis, namely Frq-Ori and Frq-Cross, as well as the implementation of the overall method FrqBooster. Among them, the implementation details of the Frq-Ori benchmark are mainly to use the original design code directly using the tool for design generation. The overall layout design is the result of automatic optimization. The implementation details of the Frq-Cross benchmark are mainly to use only cross-multi-chip interconnection optimization to reduce the frequency impact brought by various connections across multiple chips in the hardware layout. FrqBooster is the result of the overall implementation of the FrqBooster method. Compared with the implementation of Frq-Cross, inter-Die and intra-Die equalization are added to further reduce the frequency impact caused by local congestion.

[0146] and Figures 10 to 13 The following table shows the differences in frequency and resource consumption between the FrqBooster method and Frq-Ori and Frq-Cross. The vertical axis represents the differences in various performance indicators, while the horizontal axis represents different hardware design examples. The different values represent different sizes of computing cores, and the resource consumption of the overall examples is arranged in ascending order. In addition, subsequent performance comparisons will be tested on the Alveo U250 and U280.

[0147] First, the performance of Frq-Ori and Frq-Cross is compared. Figure 10 The figure shows the interconnection across multiple chips after Frq-Ori and Frq-Cross generate hardware design. Figure 10 This visualization shows the results after spatially normalizing the total cross-boundary amount. Each matrix represents the total cross-boundary amount for the corresponding example program, with darker colors indicating a greater number of cross-boundary interconnect edges. Internal connections within a region are not of primary interest and are therefore marked in white. Compared to Frq-Ori, the Frq-Cross interconnect matrix is closer to the diagonal edge. In particular, for the 1-3 interconnection regions of the first example, the Frq-Cross method displays a lighter color than the Frq-Ori method, demonstrating that the Frq-Cross method reduces the number of cross-boundary interconnect edges. This indicates that after optimizing cross-die interconnects, the FPGA hardware design is more inwardly converged, further reducing the impact of cross-die regions. Furthermore, compared to other examples, Frq-Cross achieves superior performance, reducing the number of cross-die boundary connections. This demonstrates that this method effectively optimizes the layout of cross-die connections, leading to better implementation.

[0148] from Figure 11The performance comparison results show that thanks to the excellent cross-chip interconnect performance, Frq-Cross has improved by 40% to 65% and 28% to 66% on the U250 and U280 platforms respectively. The highest cases occurred in Sample 1 of the U250, where the maximum estimated frequency increased from 228MHz to 375MHz, and Sample 4 of the U280, where the maximum estimated frequency increased from 209MHz to 347MHz. Figure 9 It can also be seen that due to the overly complex designs of samples 5, 6, and 7 on the U250 platform and sample 5 on the U280 platform, resource overhead is high, and direct automatic design results in more localized congestion, thus failing to generate direct results. This fully demonstrates the effectiveness of cross-chip interconnect optimization.

[0149] Further compare the performance of Frq-Cross and FrqBooster. Figure 11 As shown in the figure, FrqBooster improves Frq-Cross by 1% to 34% and 4% to 11% on the U250 and U280 platforms respectively. The highest cases occur in Sample 8 of the U250, where the maximum estimated frequency increases from 238MHz to 318MHz, and Sample 3 of the U280, where the maximum estimated frequency increases from 360MHz to 398MHz. Figure 12 It can be seen that the performance improvement achieved by FrqBooster has almost no additional resource overhead. This fully demonstrates that after the resource balancing optimization, the overall hardware layout of FPGA has been improved, thus achieving higher frequency performance. In addition, from the performance comparison Figure 11 As can be seen here, although samples 5, 6, and 7 on the U250 platform and sample 5 on the U280 platform failed to achieve direct results using design tools due to their design complexity and excessive resource overhead, samples 8 on the U250 platform and sample 6 on the U280 platform were still achievable using automated design tools. This is primarily due to the excessive resource overhead of these samples. For example, the DSP resource overhead in the IP design of sample 8 on the U250 platform is nearly 80%, forcing the tool to place the design globally. Consequently, while they were ultimately deployed successfully on the FPGA board, the frequency was still limited.

[0150] The FrqBooster provided by the embodiment of the present invention can avoid this problem. Through a two-stage resource balancing optimization method, the occurrence of such extreme resource usage is minimized to generate a design result with better frequency performance. Figure 13 This result can be seen everywhere. Figure 13The left side shows the results of a part of the on-chip design after only Frq-Cross optimization, while the right side shows the results after FrqBooster optimization. The darker the color, the more serious the congestion performance, which leads to a poor critical path and affects the final frequency performance in the hardware design. It can be seen that compared with Frq-Cross, FrqBooster successfully reduces the layout congestion performance under the same sample. And after performance comparison Figure 11 It can also be seen that the hardware design after resource balancing optimization achieved good performance in all examples, alleviating the original local congestion while maintaining the same level of resource overhead, ultimately achieving a higher maximum estimated frequency. This shows that FrqBooster's resource balancing strategy played a role in the hardware layout stage.

[0151] Next, we compare the performance of related work, AutoBridge and FrqBooster. Currently, AutoBridge only considers cross-die connectivity between hardware interconnect graphs during the layout phase, supplemented by a search algorithm to minimize cross-die connection bandwidth. However, AutoBridge ignores the resource overhead of each FPGA hardware module and the resource ratios in different regions. This can be negligible in small-scale examples, but in larger-scale examples, it can lead to localized congestion in various locations, resulting in suboptimal overall frequency performance.

[0152] like Figure 14 The figure shows the comparison of the frequency performance of FrqBooster and AutoBridge under the same sample. Overall, FrqBooster improves by 2.9% to 18.3% compared to AutoBridge on the U250 platform, and FrqBooster improves by 7.8% to 33.6% compared to AutoBridge on the U280 platform. The highest cases occur in Sample 2 of the U250, where the maximum estimated frequency increases from approximately 333MHz to 394MHz, and Sample 1 of the U280, where the maximum estimated frequency increases from 329MHz to 453MHz. At the same time, by comparing the performance trends between different samples, it can be seen that the frequency performance of AutoBridge in Samples 6 and 7 of the U250 platform is actually worse than that of Sample 8, although from the perspective of resource usage, the average resource utilization of Samples 6 and 7 is 5% to 10% lower than that of Sample 8.

[0153] Therefore, after analyzing the design result reports of AutoBridge samples 6, 7, and 8, it was found that it was precisely because of the impact of more local congestion that the overall FPGA optimization results did not produce a monotonic effect. For sample 8, when only counting the design core resource overhead, the various resources used were basically close to 60%-70%. It was no longer possible to concentrate the hardware design in certain areas while minimizing the cross-chip connection bandwidth. Therefore, the entire design would be flattened in the FPGA reconfigurable area to obtain better frequency performance. Therefore, after FrqBooster optimization, the impact of uneven resource usage in some locations was reduced, making the design performance of different samples show a monotonic trend.

[0154] In order to further measure whether the resource allocation after design optimization is appropriate, the embodiment of the present invention provides an indicator of resource adaptability Δ. The specific calculation formula of resource adaptability is: in, Represents the resource overhead ratio of a certain type of resource in partition i in the current hardware design layout, and avg(resource ratio ) represents the average share of hardware design resource overhead across the entire FPGA board. The resource fit metric combines fluctuations in resource overhead across various types of resources to reflect the resource fit of the overall layout design, enabling evaluation of hardware layout optimization on multi-chip FPGA platforms.

[0155] like Figure 15 The figure shows the difference in resource adaptability Δ between FrqBooster and AutoBridge. It can be seen that FrqBooster improves resource adaptability Δ by 9.9% to 62.7% compared to AutoBridge on the U250 platform. At the same time, as shown in Table 2, after comparing the relevant resource overhead, it can be found that FrqBooster (abbreviated as FrqB in Table 2) also maintains a similar resource ratio to AutoBridge (abbreviated as Auto in Table 2), with basically no additional overhead to compensate.

[0156] Table 2 Comparison of resource overhead between FrqBooster and AutoBridge

[0157]

[0158]

[0159] It should be noted that any arrangement and combination of the technical features in the above embodiments also falls within the protection scope of the present invention.

[0160] Example 3

[0161] Figure 16 Schematic diagram of a hardware layout optimization device for FPGA provided by the third embodiment of the present invention, such as Figure 16 As shown, the apparatus includes: an RTL code acquisition module 310, an abstract hardware module graph construction module 320, a cross-region optimization module 330, and an intra-region optimization module 340, wherein:

[0162] An RTL code acquisition module 310 is used to acquire the RTL code of the FPGA to be optimized;

[0163] An abstract hardware module diagram construction module 320 is configured to construct an abstract hardware module diagram of the FPGA to be optimized based on the RTL code of the FPGA to be optimized;

[0164] A cross-region optimization module 330 is configured to perform cross-region optimization on the current hardware layout structure of the FPGA to be optimized based on the abstract hardware module diagram and the cross-region associated resource parameters to obtain a cross-region optimized hardware layout structure;

[0165] The intra-region optimization module 340 is used to perform intra-region optimization on the cross-region optimized hardware layout structure according to the abstract hardware module diagram and intra-region associated resource parameters to obtain a target optimized hardware layout structure of the FPGA to be optimized.

[0166] The embodiment of the present invention constructs an abstract hardware module diagram of the FPGA to be optimized based on the acquired RTL code of the FPGA to be optimized, performs cross-zone optimization on the current hardware layout structure of the FPGA to be optimized based on the abstract hardware module diagram and cross-zone associated resource parameters to obtain a cross-zone optimized hardware layout structure, and performs intra-zone optimization on the cross-zone optimized hardware layout structure based on the abstract hardware module diagram and intra-zone associated resource parameters to obtain a target optimized hardware layout structure of the FPGA to be optimized. This solves the problem of poor optimization effect of existing FPGA hardware layout optimization methods and can achieve overall hardware layout optimization of the FPGA, thereby reducing the FPGA's latency and improving the FPGA's frequency performance.

[0167] Optionally, the abstract hardware module graph construction module 320 is specifically used to: determine multiple abstract RTL modules based on the RTL code of the FPGA to be optimized; determine the relative position and connection relationship between each of the abstract RTL modules; abstract each of the abstract RTL modules into each vertex of the abstract hardware module graph; determine the relative position and connection edges between each vertex in the abstract hardware module graph based on the relative position and connection relationship between each of the abstract RTL modules, and obtain the abstract hardware module graph of the FPGA to be optimized.

[0168] Optionally, the cross-region optimization module 330 is specifically used to: optimize the cross-chip connection relationship between the programmable logic areas SLR of the current hardware layout structure according to the abstract hardware module diagram; optimize the abstract RTL module layout relationship between the SLRs of the current hardware layout structure according to the abstract hardware module diagram and the cross-region associated resource parameters of the SLR to obtain the cross-region optimized hardware layout structure.

[0169] Optionally, the cross-zone optimization module 330 is specifically used to: determine the source node vector and the target node vector based on the abstract hardware module diagram; calculate the cross-zone distance based on the source node vector and the target node vector; determine the cross-chip connection relationship optimization target based on the cross-zone distance and the bandwidth vector; solve the cross-chip connection relationship optimization target to optimize the cross-chip connection relationship between the SLRs of the current hardware layout structure.

[0170] Optionally, the cross-region optimization module 330 is specifically configured to calculate the cross-region distance based on the following formula:

[0171] D j =2*Manhattan(L F [src j ],L F [dst j ])-1

[0172] The cross-wafer connection relationship optimization target is calculated based on the following formula:

[0173]

[0174] Among them, D j Indicates the cross-region distance, src j Represents the source node vector of the jth connection edge in the abstract hardware module graph, dst j represents the target node vector of the jth connection edge in the abstract hardware module graph, L F Indicates the position value of the vertex during cross-region optimization, Obj across represents the cross-wafer connection relationship optimization target, w j Represents the bandwidth vector of the j-th connection edge in the abstract hardware module graph.

[0175] Optionally, the cross-region associated resource parameters of the SLR include SLR resource overhead, cross-region resource availability, cross-region maximum resource usage limit and the difference vector between different SLRs; the cross-region optimization module 330 is specifically used to: calculate the resource utilization rate of each SLR based on the SLR resource overhead, the cross-region resource availability and the cross-region maximum resource usage limit; determine the cross-region resource balancing target based on the resource utilization rate of each SLR and the difference vector between the different SLRs; solve the cross-region resource balancing target to optimize the abstract RTL module layout relationship between the SLRs.

[0176] Optionally, the cross-zone optimization module 330 is specifically configured to calculate the resource usage of each SLR based on the following formula:

[0177]

[0178] The cross-region resource balancing target is calculated based on the following formula:

[0179] Obj inter =∑(Δ inter ×R inter ) 2

[0180] Among them, R inter represents the resource utilization rate of each SLR, Represents the transpose of the position value of the vertex during cross-region optimization, R cost Represents the SLR resource overhead, R F Indicates the available amount of cross-region resources, Indicates the maximum resource usage limit across regions, Obj inter represents the cross-region resource balancing target, Δ inter represents the difference vector between the different SLRs.

[0181] Optionally, the cross-region optimization module 330 is specifically used to: determine a first optimization weight of the cross-chip connection relationship optimization target and a second optimization weight of the cross-region resource balancing target; perform weighted processing on the cross-chip connection relationship optimization target and the cross-region resource balancing target according to the first optimization weight and the second optimization weight to obtain a comprehensive cross-region optimization target; solve the comprehensive cross-region optimization target to optimize the abstract RTL module layout relationship between the SLRs of the current hardware layout structure to obtain the cross-region optimized hardware layout structure.

[0182] Optionally, the intra-zone optimization module 340 is specifically used to: calculate the resource overhead ratio of the current SLR based on the abstract hardware module diagram and the intra-zone associated resource parameters of the SLR; determine the intra-zone resource balancing target based on the resource overhead ratio of the current SLR and the intra-zone associated resource parameters of the SLR; solve the intra-zone resource balancing target to perform intra-zone optimization on the cross-zone optimized hardware layout structure to obtain the target optimized hardware layout structure of the FPGA to be optimized.

[0183] Optionally, the intra-area associated resource parameters of the SLR include SLR resource overhead, intra-area resource availability, intra-area maximum resource usage limit, and difference vectors of different areas of the current SLR; the intra-area optimization module 340 is specifically configured to:

[0184] The resource overhead ratio of the current SLR is calculated based on the following formula:

[0185]

[0186] The resource balancing target within the zone is calculated based on the following formula:

[0187] Obj intra =∑(Δ intra ×R intra [slr]) 2

[0188] Among them, R intra [slr] represents the resource overhead ratio of the current SLR, Represents the transpose of the position value of the vertex when the current SLR is optimized within the region, R cost Represents the SLR resource overhead, R S Indicates the available amount of resources in the area, Indicates the maximum resource usage limit within the current SLR area, Obj intra represents the resource balancing target within the region, Δ intra The difference vectors representing different regions of the current SLR.

[0189] The aforementioned FPGA hardware layout optimization device can execute the FPGA hardware layout optimization method provided in any embodiment of the present invention, and includes the corresponding functional modules and beneficial effects of executing the method. For technical details not fully described in this embodiment, please refer to the FPGA hardware layout optimization method provided in any embodiment of the present invention.

[0190] Since the FPGA hardware layout optimization device described above is a device that can execute the FPGA hardware layout optimization method in the embodiments of the present invention, those skilled in the art will be able to understand the specific implementation and various variations of the FPGA hardware layout optimization device in this embodiment based on the FPGA hardware layout optimization method described in the embodiments of the present invention. Therefore, how the FPGA hardware layout optimization device implements the FPGA hardware layout optimization method in the embodiments of the present invention will not be described in detail here. As long as a person skilled in the art implements the device used by the FPGA hardware layout optimization method in the embodiments of the present invention, it falls within the scope of protection of this application.

[0191] Example 4

[0192] Figure 17 A schematic diagram of the structure of an electronic device 10 that can be used to implement an embodiment of the present invention is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices (such as helmets, glasses, watches, etc.) and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present invention described and / or claimed herein.

[0193] like Figure 17 As shown, the electronic device 10 includes at least one processor 11 and a memory, such as a read-only memory (ROM) 12, a random access memory (RAM) 13, etc., which is communicatively connected to the at least one processor 11. The memory stores a computer program that can be executed by the at least one processor. The processor 11 can perform various appropriate actions and processes according to the computer program stored in the read-only memory (ROM) 12 or the computer program loaded from the storage unit 18 into the random access memory (RAM) 13. Various programs and data required for the operation of the electronic device 10 can also be stored in the RAM 13. The processor 11, ROM 12, and RAM 13 are connected to each other via a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0194] Multiple components in the electronic device 10 are connected to the I / O interface 15, including an input unit 16, such as a keyboard, a mouse, etc.; an output unit 17, such as various types of displays, speakers, etc.; a storage unit 18, such as a magnetic disk, an optical disk, etc.; and a communication unit 19, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 19 allows the electronic device 10 to exchange information / data with other devices via a computer network such as the Internet and / or various telecommunication networks.

[0195] The processor 11 can be any general-purpose and / or specialized processing component with processing and computing capabilities. Some examples of the processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various specialized artificial intelligence (AI) computing chips, various processors that run machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc. The processor 11 executes the various methods and processes described above, such as the FPGA hardware layout optimization method.

[0196] Optionally, the FPGA hardware layout optimization method may include: obtaining the RTL code of the FPGA to be optimized; constructing an abstract hardware module diagram of the FPGA to be optimized based on the RTL code of the FPGA to be optimized; performing cross-region optimization on the current hardware layout structure of the FPGA to be optimized based on the abstract hardware module diagram and cross-region associated resource parameters to obtain a cross-region optimized hardware layout structure; performing intra-region optimization on the cross-region optimized hardware layout structure based on the abstract hardware module diagram and intra-region associated resource parameters to obtain a target optimized hardware layout structure of the FPGA to be optimized.

[0197] In some embodiments, the hardware layout optimization method for FPGA can be implemented as a computer program, which is tangibly contained in a computer-readable storage medium, such as storage unit 18. In some embodiments, part or all of the computer program can be loaded and / or installed on the electronic device 10 via ROM 12 and / or communication unit 19. When the computer program is loaded into RAM 13 and executed by processor 11, one or more steps of the hardware layout optimization method for FPGA described above can be performed. Alternatively, in other embodiments, processor 11 can be configured to execute the hardware layout optimization method for FPGA by any other appropriate means (for example, by means of firmware).

[0198] Various embodiments of the systems and techniques described herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), system-on-chip systems (SOCs), programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments can include being implemented in one or more computer programs that are executable and / or interpreted on a programmable system that includes at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0199] Computer programs for implementing the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when the computer program is executed by the processor, the functions / operations specified in the flowcharts and / or block diagrams are implemented. The computer program may be executed entirely on the machine, partially on the machine, as a stand-alone software package, partially on the machine and partially on a remote machine, or entirely on a remote machine or server.

[0200] In the context of the present invention, computer-readable storage media can be tangible media that can contain or store a computer program for use with an instruction execution system, device or equipment or used in combination with an instruction execution system, device or equipment. Computer-readable storage media can include but are not limited to electronic, magnetic, optical, electromagnetic, infrared or semiconductor systems, devices or equipment, or any suitable combination of the foregoing. Alternatively, computer-readable storage media can be machine-readable signal media. More specific examples of machine-readable storage media can include electrical connections based on one or more lines, portable computer disks, hard disks, random access memories (RAM), read-only memories (ROM), erasable programmable read-only memories (EPROM or flash memory), optical fibers, portable compact disk read-only memories (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0201] To provide interaction with a user, the systems and techniques described herein can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user can provide input to the electronic device. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and the input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0202] The systems and techniques described herein can be implemented in a computing system that includes back-end components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes front-end components (e.g., a user computer with a graphical user interface or web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such back-end components, middleware components, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), a blockchain network, and the Internet.

[0203] A computing system may include clients and servers. The clients and servers are typically remote from each other and typically interact via a communication network. This client-server relationship arises through computer programs running on the respective computers, creating a client-server relationship. The server may be a cloud server, also known as a cloud computing server or cloud host. This server is a hosting product within the cloud computing service ecosystem that addresses the management difficulties and limited scalability of traditional physical hosting and VPS services.

Claims

1. A method for optimizing the hardware layout of a field programmable gate array (FPGA), characterized in that: include: Obtain the RTL code of the register conversion level circuit of the FPGA to be optimized; Constructing an abstract hardware module diagram of the FPGA to be optimized according to the RTL code of the FPGA to be optimized; Performing cross-region optimization on the current hardware layout structure of the FPGA to be optimized according to the abstract hardware module diagram and the cross-region associated resource parameters to obtain a cross-region optimized hardware layout structure; Performing intra-region optimization on the cross-region optimized hardware layout structure according to the abstract hardware module diagram and intra-region associated resource parameters to obtain a target optimized hardware layout structure of the FPGA to be optimized; The cross-region optimization of the current hardware layout structure of the FPGA to be optimized according to the abstract hardware module diagram and the cross-region associated resources to obtain the cross-region optimized hardware layout structure includes: optimizing the abstract RTL module layout relationship between the SLRs of the current hardware layout structure according to the abstract hardware module diagram and the cross-region associated resource parameters of the SLR to obtain the cross-region optimized hardware layout structure; The cross-region associated resource parameters of the SLR include SLR resource overhead, cross-region resource availability, cross-region maximum resource usage limit, and difference vectors between different SLRs; optimizing the abstract RTL module layout relationship between the SLRs of the current hardware layout structure based on the abstract hardware module diagram and the cross-region associated resource parameters of the SLR includes: calculating the resource utilization rate of each SLR based on the SLR resource overhead, the cross-region resource availability, and the cross-region maximum resource usage limit; determining a cross-region resource balancing target based on the resource utilization rate of each SLR and the difference vectors between the different SLRs; and solving the cross-region resource balancing target to optimize the abstract RTL module layout relationship between the SLRs. Calculating the resource utilization rate of each SLR according to the SLR resource overhead, the available amount of cross-region resources, and the maximum cross-region resource usage limit includes calculating the resource utilization rate of each SLR based on the following formula: ； The determining of the cross-region resource balancing target according to the resource utilization rate of each SLR and the difference vector between the different SLRs includes: The cross-region resource balancing target is calculated based on the following formula: ； in, represents the resource utilization rate of each SLR, Represents the transpose of the position value of the vertex during cross-region optimization, represents the SLR resource overhead, Indicates the available amount of cross-region resources, Indicates the maximum resource usage limit across zones. represents the cross-region resource balancing target, represents the difference vector between the different SLRs.

2. The method according to claim 1, characterized in that The step of constructing an abstract hardware module diagram of the FPGA to be optimized based on the RTL code of the FPGA to be optimized includes: Determine a plurality of abstract RTL modules according to the RTL code of the FPGA to be optimized; Determining the relative positions and connection relationships between the abstract RTL modules; Abstracting each of the abstract RTL modules into vertices of the abstract hardware module graph; According to the relative positions and connection relationships between the abstract RTL modules, the relative positions and connection edges between the vertices in the abstract hardware module graph are determined to obtain the abstract hardware module graph of the FPGA to be optimized.

3. The method according to claim 1, characterized in that The cross-region optimization of the current hardware layout structure of the FPGA to be optimized according to the abstract hardware module diagram and the cross-region associated resources to obtain the cross-region optimized hardware layout structure further includes: The cross-wafer connection relationship between the programmable logic regions (SLRs) of the current hardware layout structure is optimized according to the abstract hardware module diagram.

4. The method according to claim 3, characterized in that Optimizing the cross-wafer connection relationship between SLRs of the current hardware layout structure according to the abstract hardware module diagram includes: Determine a source node vector and a target node vector according to the abstract hardware module diagram; Calculating a cross-region distance based on the source node vector and the target node vector; Determining an optimization target for cross-wafer connection relationships based on the cross-region distance and bandwidth vector; The cross-wafer connection relationship optimization target is solved to optimize the cross-wafer connection relationship between the SLRs of the current hardware layout structure.

5. The method according to claim 4, characterized in that The calculating the cross-region distance according to the source node vector and the target node vector includes: The cross-zone distance is calculated based on the following formula: ； Determining the cross-wafer connection relationship optimization target according to the cross-zone distance and the bandwidth vector includes: The cross-wafer connection relationship optimization target is calculated based on the following formula: ； in, represents the cross-region distance, represents the source node vector of the jth connection edge in the abstract hardware module graph, represents the target node vector of the jth connection edge in the abstract hardware module graph, Indicates the position value of the vertex during cross-region optimization, represents the cross-wafer connection relationship optimization target, Represents the bandwidth vector of the j-th connection edge in the abstract hardware module graph.

6. The method according to claim 1, characterized in that The method further comprises: Determining a first optimization weight for a cross-wafer connection relationship optimization objective and a second optimization weight for the cross-region resource balancing objective; weighting the cross-wafer connection relationship optimization target and the cross-region resource balancing target according to the first optimization weight and the second optimization weight to obtain a comprehensive cross-region optimization target; The comprehensive cross-region optimization target is solved to optimize the abstract RTL module layout relationship between the SLRs of the current hardware layout structure to obtain the cross-region optimized hardware layout structure.

7. The method according to claim 1, characterized in that The intra-region optimization of the cross-region optimized hardware layout structure according to the abstract hardware module diagram and the intra-region associated resource parameters to obtain the target optimized hardware layout structure of the FPGA to be optimized includes: Calculating a resource overhead ratio of a current SLR based on the abstract hardware module diagram and the intra-area associated resource parameters of the SLR; Determine an intra-area resource balancing target based on the resource overhead ratio of the current SLR and the intra-area associated resource parameters of the SLR; The intra-region resource balancing target is solved to perform intra-region optimization on the cross-region optimized hardware layout structure, thereby obtaining a target optimized hardware layout structure of the FPGA to be optimized.

8. The method according to claim 7, characterized in that The intra-area associated resource parameters of the SLR include SLR resource overhead, intra-area resource availability, intra-area maximum resource usage limit, and difference vectors of different areas of the current SLR; The calculating the resource overhead ratio of the current SLR according to the abstract hardware module diagram and the intra-area associated resource parameters of the SLR includes: The resource overhead ratio of the current SLR is calculated based on the following formula: ； The determining of the intra-area resource balancing target according to the resource overhead ratio of the current SLR and the intra-area associated resource parameters of the SLR includes: The resource balancing target within the zone is calculated based on the following formula: ； in, represents the resource overhead ratio of the current SLR, Indicates the transposition of the position value of the vertex when the current SLR is optimized within the area. represents the SLR resource overhead, Indicates the available amount of resources in the area, Indicates the maximum resource usage limit within the current SLR, represents the resource balancing target within the zone, The difference vectors representing different regions of the current SLR.

9. A device for optimizing FPGA hardware layout, characterized in that: include: RTL code acquisition module, used to obtain the RTL code of the FPGA to be optimized; An abstract hardware module diagram construction module, configured to construct an abstract hardware module diagram of the FPGA to be optimized based on the RTL code of the FPGA to be optimized; a cross-region optimization module, configured to perform cross-region optimization on the current hardware layout structure of the FPGA to be optimized according to the abstract hardware module diagram and the cross-region associated resource parameters, to obtain a cross-region optimized hardware layout structure; An intra-region optimization module, configured to perform intra-region optimization on the cross-region optimized hardware layout structure according to the abstract hardware module diagram and intra-region associated resource parameters, to obtain a target optimized hardware layout structure of the FPGA to be optimized; The cross-region optimization module is specifically configured to optimize the abstract RTL module layout relationship between the SLRs of the current hardware layout structure according to the abstract hardware module diagram and the cross-region associated resource parameters of the SLR to obtain the cross-region optimized hardware layout structure; The cross-region associated resource parameters of the SLR include SLR resource overhead, cross-region resource availability, cross-region maximum resource usage limit, and difference vectors between different SLRs; the cross-region optimization module is specifically used to: calculate the resource utilization rate of each SLR based on the SLR resource overhead, the cross-region resource availability, and the cross-region maximum resource usage limit; determine a cross-region resource balancing target based on the resource utilization rate of each SLR and the difference vectors between the different SLRs; and solve the cross-region resource balancing target to optimize the abstract RTL module layout relationship between the SLRs; The cross-region optimization module is specifically used to calculate the resource utilization rate of each SLR based on the following formula: ； The cross-region resource balancing target is calculated based on the following formula: ； in, represents the resource utilization rate of each SLR, Represents the transpose of the position value of the vertex during cross-region optimization, represents the SLR resource overhead, Indicates the available amount of cross-region resources, Indicates the maximum resource usage limit across zones. represents the cross-region resource balancing target, represents the difference vector between the different SLRs.

10. An electronic device, characterized in that: The electronic device comprises: at least one processor; and a memory communicatively connected to the at least one processor; wherein, The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can execute the FPGA hardware layout optimization method according to any one of claims 1 to 8.

11. A computer-readable storage medium, characterized in that The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the FPGA hardware layout optimization method according to any one of claims 1 to 8 when executed.

Images