An atomic deposition chamber, apparatus, apparatus manufacturing method, and capacitor preparation method

Abstract

The application discloses an atomic deposition chamber, and relates to the field of semiconductor manufacturing equipment.The atomic deposition chamber comprises a plasma reaction cavity, and a separation ring arranged in the interior of the plasma reaction cavity, wherein the outer wall of the separation ring covers the inner wall of the plasma reaction cavity.The atomic deposition equipment comprises an equipment body, a thermal reaction chamber arranged in parallel with the plasma reaction cavity, a vacuum unit for switching between vacuum and atmospheric environment in the equipment, a loading unit for placing a wafer, a transfer unit for transferring the wafer, and a first mechanical arm and a second mechanical arm.The application fully utilizes the function of the atomic deposition equipment by equipment modification, so that the single chamber has the functions of deposition and etching, the utilization rate of the equipment is improved, and the equipment can realize one machine with multiple functions, so as to cope with the machine table which must be used for general mass production products but is used in a small amount.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing equipment technology, and in particular to an atomic deposition chamber, equipment, equipment manufacturing method, and capacitor preparation method. Background Technology

[0002] Atomic layer deposition (ALD) is a method of thin film deposition that uses atomic layer-by-layer growth to achieve thin film deposition, and it is widely used in the chip wafer manufacturing industry. Due to its extremely high step coverage, ALD applications have expanded with each generation of chip manufacturing processes below 45 nanometers. ALD can be divided into plasma ALD (PEALD) and thermal ALD. The difference lies in that PEALD uses plasma precursors, the reaction does not require heating, and device damage is minimal; it is mainly used for depositing low-dielectric materials and other dielectrics. Thermal ALD requires heating to occur, and the reaction takes place at high temperatures. It has a faster deposition rate and better film density, but the high temperature can damage the film; it is mainly used for depositing metal gates / high-dielectric metal compound films.

[0003] High-stability-state RAM (HsRAM) is a novel type of memory chip that uses high-K ferroelectric material as the capacitor dielectric to form an embedded ferroelectric capacitor based on logic chips. It leverages the polarity of the ferroelectric material to achieve storage functionality. During the fabrication of the 3D-CELL segment, the top and bottom electrode layers and the high-K (high-dielectric material) layer need to be deposited into cylindrical holes on the dielectric layer of the array region. The fabrication of the top and bottom electrode layers and the high-K ferroelectric layer requires ALD (atomic layer deposition) equipment, specifically PEALD (plasma atomic layer deposition) and ThermalALD (thermal atomic layer deposition), respectively. The outer film layer needs to be removed by dry etching. Due to the special properties of high-K ferroelectric material (hafnium oxide / zirconia), to avoid cross-contamination between the process and equipment, wafer fabs generally require dedicated high-K process equipment, and the Foup (wafer cassette) must be changed when entering and leaving the high-K process area. According to standard wafer foundry practices, completing the ferroelectric capacitor fabrication process for HsRAM (Ultra-Stable Memory) chips requires at least three different ALD (Atomic Layer Deposition) machines and two or more DryEtch (plasma etching) machines. However, capacitor fabrication accounts for a relatively small proportion of the overall process, resulting in low utilization rates for ALD and corresponding dry etching equipment. Furthermore, if ALD machines and DryEtch machines are separated and controlled in conjunction, the production and operating costs become high. Summary of the Invention

[0004] In view of the problems existing in the prior art, the present invention is proposed.

[0005] Therefore, the first objective of this invention is to provide an atomic deposition chamber that can integrate atomic deposition and etching processes into a single chamber, reducing the number of devices required.

[0006] To solve the above-mentioned technical problems, the present invention provides the following technical solution: an atomic deposition chamber, comprising a plasma reaction chamber; an isolation ring disposed inside the plasma reaction chamber, wherein the outer wall of the isolation ring covers the inner wall of the plasma reaction chamber.

[0007] As a preferred embodiment of the atomic deposition chamber of the present invention, it further includes an etching conduit connected to the plasma reaction chamber for releasing etching gas.

[0008] In a preferred embodiment of the atomic deposition chamber of the present invention, the isolation ring and the plasma reaction chamber are detachably connected.

[0009] In a preferred embodiment of the atomic deposition chamber of the present invention, the isolation ring is made of silicon or silicon carbide.

[0010] In a preferred embodiment of the atomic deposition chamber of the present invention, the plasma reaction chamber is made of aluminum alloy.

[0011] The second objective of this invention is to provide an atomic deposition apparatus that can solve the problem of transferring wafers between multiple devices when fabricating capacitors.

[0012] To solve the above-mentioned technical problems, the present invention provides the following technical solution: an atomic deposition apparatus, comprising an atomic deposition chamber and an apparatus body; a thermal reaction chamber, which is arranged in parallel with the plasma reaction chamber; a vacuum unit for switching between vacuum and atmospheric environments in the apparatus, including a first vacuum lock and a second vacuum lock; a loading unit for placing wafers, including a first loading stage and a second loading stage; and a transfer unit for transferring wafers, including a first robotic arm and a second robotic arm.

[0013] A third objective of this invention is to provide a method for manufacturing an atomic deposition apparatus, by which the aforementioned atomic deposition apparatus can be manufactured.

[0014] To solve the above-mentioned technical problems, the present invention provides the following technical solution: a method for manufacturing an atomic deposition device, which is applicable to manufacturing the above-mentioned atomic deposition device, including setting a plasma reaction chamber on the device body; setting an isolation ring inside the plasma reaction chamber, such that the outer wall of the isolation ring covers the inner wall of the plasma reaction chamber.

[0015] In a preferred embodiment of the manufacturing method of the atomic deposition equipment of the present invention, an etching pipeline is further connected to the plasma reaction chamber, and an etching gas is passed through the etching pipeline.

[0016] The fourth objective of this invention is to provide a capacitor manufacturing method that simplifies the capacitor manufacturing process, reduces equipment transfer, and avoids wafer contamination.

[0017] To solve the above-mentioned technical problems, the present invention provides the following technical solution: a capacitor fabrication method, which is fabricated using the above-mentioned atomic deposition equipment, comprising: providing a dielectric layer; forming a capacitor hole in the dielectric layer; sequentially forming a barrier layer, a lower electrode layer, a dielectric layer, and an upper electrode layer on the inner wall of the capacitor hole; forming an aluminum wire plate on the upper electrode layer and filling the capacitor hole.

[0018] In a preferred embodiment of the capacitor fabrication method of the present invention, the lower electrode layer and the upper electrode layer are formed in the plasma reaction chamber by atomic deposition; the etching required for the lower electrode layer, the upper electrode layer, and the dielectric layer is completed in the plasma reaction chamber.

[0019] The beneficial effects of this invention are as follows: by modifying the equipment, the functions of the atomic deposition equipment are fully utilized, enabling its single chamber to have both deposition and etching functions, thereby improving equipment utilization and achieving multi-functionality, so as to meet the needs of general mass-produced products that require but are used in relatively small quantities. Attached Figure Description

[0020] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a front cross-sectional view of the atomic deposition chamber.

[0022] Figure 2 This is a schematic diagram of the piping of an atomic deposition equipment.

[0023] Figure 3 This is a schematic diagram of an atomic deposition apparatus.

[0024] Figure 4 This is a schematic cross-sectional view of the dielectric layer in the capacitor fabrication method.

[0025] Figure 5 This is a schematic diagram illustrating the fabrication of capacitor holes in a capacitor manufacturing process.

[0026] Figure 6 This is a schematic diagram of the deposition of the barrier layer in the capacitor fabrication method.

[0027] Figure 7 This is a schematic diagram of the deposition of the lower electrode layer in the capacitor fabrication method.

[0028] Figure 8 This is a schematic diagram of the etching of the lower electrode layer in the capacitor fabrication method.

[0029] Figure 9 This is a schematic diagram of the deposition of the dielectric layer in the capacitor fabrication method.

[0030] Figure 10 This is a schematic diagram of the deposition of the upper electrode layer in the capacitor fabrication method.

[0031] Figure 11 This is a schematic diagram of the etching of the upper electrode layer and the dielectric layer in the capacitor fabrication method.

[0032] Figure 12 This is a schematic diagram of aluminum plate wire deposition in a capacitor fabrication process. Detailed Implementation

[0033] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0034] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the invention. Therefore, the invention is not limited to the specific embodiments disclosed below.

[0035] Secondly, the term "an embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The phrase "in one embodiment" appearing in different places throughout this specification does not necessarily refer to the same embodiment, nor is it an embodiment that is mutually exclusive, either alone or selectively, with other embodiments.

[0036] Example 1

[0037] Reference Figure 1 and Figure 2 This is the first embodiment of the present invention, which provides an atomic deposition chamber, which includes a plasma reaction chamber 100 and an isolation ring 200.

[0038] Specifically, the plasma reaction chamber 100 is a chamber used in the prior art for plasma atomic layer deposition (PEALD) processes. Its function and shape are similar to those in the prior art, and it is generally made of aluminum alloy.

[0039] The isolation ring 200 is circular in shape and conforms to the shape of the inner wall of the plasma reaction chamber 100. The annular outer wall of the isolation ring 200 can completely cover the inner wall of the plasma reaction chamber 100, such as... Figure 1 .

[0040] Preferably, the plasma reaction chamber 100 is further connected to an etching conduit 300. The etching conduit 300 carries BF3 or Cl2 gas for semiconductor etching. Power is supplied by a power source, and a power amplifier amplifies the oscillation frequency, causing BF3 to dissociate into F-containing free radicals (or Cl2 to dissociate into Cl-containing free radicals). These F- or Cl-containing free radicals are transported and adsorbed onto the etching layer, reacting with the surface of the etching layer to form volatile byproducts, thereby achieving directional and isolated etching of the material. In this example, the etching conduit 300, from the gas cylinder to the equipment interface, consists of: a handle valve for manually controlling the gas cylinder's gas switch; a filter for removing particulate impurities from the gas; a one-way valve to prevent gas backflow; a regulator for adjusting the gas flow rate; a pressure gauge for testing gas pressure; a pneumatic valve for controlling the gas circuit switch; a flow meter for monitoring gas flow; and a needle valve for precise control of the switch and equipment interface, such as... Figure 2 .

[0041] Preferably, the isolation ring 200 is made of silicon or silicon carbide and is detachably connected to the plasma reaction chamber 100. Inside the plasma reaction chamber 100, from top to bottom, are a gas control device 101, a spray head 102, and the isolation ring 200. In this embodiment, the isolation ring 200 is a stepped ring, which is held in place inside the plasma reaction chamber 100 by the spray head 102.

[0042] It's worth noting that atomic deposition equipment is designed for thin film deposition (i.e., increasing film thickness), while etching is subtractive (reducing film thickness). The plasma reaction chamber 100 is typically made of aluminum alloy. For the fabrication of high-stability memory using High-K ferroelectric materials as capacitor dielectrics, one crucial function is etching metallic materials such as TiN and TaN. However, prolonged reaction time in a typical atomic deposition chamber inevitably leads to corrosion of the chamber's inner wall, which is why atomic deposition equipment cannot be directly used for etching production.

[0043] In this embodiment, during etching, due to the presence of the isolation ring 200, the direct target of the plasma attack changes from the sidewall of the reaction chamber to the isolation ring 200, thereby protecting the reaction chamber. F ions (or Cl ions) react with the isolation ring to generate volatile reactants, which are extracted together with the silicon wafer etching products.

[0044] In addition, because the isolation ring 200 will be continuously thinned during the etching process, it is a consumable and needs to be replaced regularly. If the etching process of the reaction chamber is performed frequently, the replacement frequency needs to be increased.

[0045] In summary, by adding etching channels 300 and isolation rings 200, the plasma reaction chamber 100 can simultaneously perform both atomic thin film deposition and thin film dry etching functions. In the embedded capacitor process, the lower electrode plate, high dielectric material, and upper electrode plate thin film on the wafer surface can all be removed using the plasma reaction chamber 100. The entire High-K production process no longer requires the use of dry etching equipment, and the utilization rate of the atomic deposition equipment can be greatly improved.

[0046] Example 2

[0047] Reference Figure 3 This is the second embodiment of the present invention, which is based on the previous embodiment. This embodiment provides an atomic deposition apparatus, which includes the atomic deposition chamber described in Embodiment 1.

[0048] Specifically, the equipment includes a main body 400, on which two production chambers, a thermal reaction chamber 500 and a plasma reaction chamber 100, are installed side-by-side. The thermal reaction chamber 500 is used for thermal atom deposition to prepare high-dielectric materials. The plasma reaction chamber 100 is used for both plasma deposition and dry etching processes to prepare the upper and lower electrodes.

[0049] The wafers in the thermal reaction chamber 500 and the plasma reaction chamber 100 are transported and transferred by the first robotic arm 801.

[0050] On the other side of the first robotic arm 801, a first vacuum lock 601 and a second vacuum lock 602 are also installed for switching between vacuum and atmospheric environments in the equipment.

[0051] At the other end of the equipment body 400, a loading unit 700 is also installed, which includes a first loading stage 701 and a second loading stage 702 for placing wafer cassettes, providing wafers to be processed into the equipment and recovering wafers that have completed the process. The wafers between them are transported and transferred by a second robotic arm 802.

[0052] Example 3

[0053] Reference Figure 3 This is the third embodiment of the present invention, based on the first two embodiments. This embodiment provides a method for manufacturing an atomic deposition apparatus, used to manufacture the atomic deposition apparatus described in Embodiment 2, comprising:

[0054] A plasma reaction chamber 100 is provided on the main body of the equipment 400.

[0055] Specifically, an ion reaction chamber 100 is added to the original device body 400, which has only one thermal reaction chamber 500, and the wafer is transferred between the thermal reaction chamber 500 and the plasma reaction chamber 100 by the first robotic arm 801.

[0056] The plasma reaction chamber 100 is connected to the etching pipeline 300.

[0057] Specifically, the etching pipeline 300 is filled with BF3 or Cl2 gas for semiconductor etching. One end of the etching pipeline 300 is connected to a gas cylinder, and the other end is connected to the plasma reaction chamber 100.

[0058] An isolation ring 200 is provided inside the plasma reaction chamber 100, such that the outer wall of the isolation ring 200 covers the inner wall of the plasma reaction chamber 100.

[0059] Specifically, the isolation ring 200 is detachably installed in the plasma reaction chamber 100. This means the isolation ring 200 can be designed to fit directly into the spray head 102, allowing it to be secured inside the plasma reaction chamber 100. The outer wall of the isolation ring 200 completely covers the inner wall of the plasma reaction chamber 100 to protect it from corrosion.

[0060] Example 4

[0061] Reference Figures 4-12 This is the fourth embodiment of the present invention, based on the previous three embodiments. This embodiment provides a capacitor fabrication method, using the atomic deposition equipment described in Embodiment 2, including:

[0062] S1: Provides a dielectric layer of 900.

[0063] Specifically, dielectric layer 900 is formed by alternating stacks of silicon oxide and silicon nitride, such as... Figure 4 .

[0064] S2: A capacitor hole 1000 is formed in the dielectric layer 900.

[0065] Specifically, using an array device, cylindrical holes, i.e., capacitor holes 1000, are formed on the dielectric layer 900 of the array region through dry etching. Figure 5 .

[0066] S3: A barrier layer 1100, a lower electrode layer 1200, a dielectric layer 1300, and an upper electrode layer 1400 are sequentially formed on the inner wall of the capacitor hole 1000.

[0067] S3-1: Barrier layer 1100 deposition: A tantalum or tantalum nitride thin film is formed on the inner side of the capacitor via 1000 using PVD (Physical Vapor Deposition) equipment, serving as the copper barrier layer 1100 to prevent copper diffusion. Figure 6 .

[0068] S3-2: Lower electrode layer 1200 deposition. In the plasma reaction chamber 100, a titanium nitride (TiN) layer is deposited on the barrier layer 1100 using plasma atomic deposition as the lower electrode plate of the capacitor. Figure 7 .

[0069] S3-3: Etching of the lower electrode layer 1200. In the plasma reaction chamber 100, etching gases such as BF3 or CL2 are introduced through the etching pipeline 300 to remove the titanium nitride (TiN) on the wafer surface and part of the barrier layer 1100, retaining the titanium nitride inside the capacitor hole 1000 (because the capacitor hole 1000 has a high aspect ratio, the thin film inside the hole can be retained). It is necessary to control the over-etching amount; the TiN on the inner sidewall of the hole is over-etched by 100~150 nanometers to avoid short circuit between the two electrode layers. Figure 8 .

[0070] S3-4: Dielectric layer 1300 deposition. In the thermal reaction chamber 500, a thin film of about 10 nm thick, consisting of ferroelectric materials (hafnium oxide and zirconium oxide) with high K (dielectric constant) values, is formed on the inner wall of the capacitor aperture 1000 using thermal atom deposition. This film serves as the dielectric of the capacitor. Figure 9 .

[0071] S3-5: Upper electrode layer 1400 deposition. In the plasma reaction chamber 100, a thin film is formed on the wafer surface using plasma atomic deposition to serve as the upper electrode plate of the capacitor. Figure 10 .

[0072] S3-6: Etching of the upper electrode layer 1400 and the dielectric layer 1300. In the plasma reaction chamber 100, a portion of the upper electrode layer 1400 and the dielectric layer 1300 on the wafer surface are removed by plasma and etching gases such as BF3 or CL2 introduced through the etching pipeline 300, while retaining a portion of the dielectric layer 1300 within the capacitor via 1000. Figure 11 .

[0073] S4: An aluminum wire plate 1500 is formed on the upper electrode layer 1400, and the capacitor hole 1000 is filled.

[0074] Specifically, a thin aluminum film is formed using physical vapor deposition (PVD), patterned using photolithography, and then etched using aluminum wire etching (dry etching) to remove excess aluminum film. The etching stops at the upper electrode layer 1400. Figure 12 .

[0075] In summary, the capacitor fabrication method in this embodiment enables the etching processes in the lower electrode layer 1200, upper electrode layer 1400, and dielectric layer 1300 to be completed in the plasma reaction chamber 100 without the need for additional etching equipment, thereby improving equipment utilization and reducing production costs.

[0076] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. An atomic deposition chamber, characterized by: include, Plasma reaction chamber (100); An isolation ring (200) is disposed inside the plasma reaction chamber (100), and the outer wall of the isolation ring (200) completely covers the inner wall of the plasma reaction chamber (100); The isolation ring (200) and the plasma reaction chamber (100) are detachably connected; The isolation ring (200) is a stepped ring, which is held inside the plasma reaction chamber (100) by a spray head (102); It also includes an etching conduit (300) connected to the plasma reaction chamber (100) for releasing etching gas; The etching pipeline (300) is filled with gas BF3 or Cl2 for semiconductor etching. Energy is provided by a power supply, and the power amplifier enhances the oscillation frequency, causing BF3 or Cl2 to dissociate into free radicals containing F or Cl. The free radicals containing F or Cl are transported and adsorbed onto the etching layer, reacting with the surface of the etching layer to form volatile byproducts, thereby achieving directional isolation etching of the material. By adding the etching channel (300) and the isolation ring (200), the plasma reaction chamber (100) can simultaneously perform both atomic thin film deposition and thin film dry etching functions.

2. The atomic deposition chamber of claim 1, wherein: The material of the isolation ring (200) is silicon or silicon carbide.

3. The atomic deposition chamber of claim 1 or 2, wherein: The plasma reaction chamber (100) is made of aluminum alloy.

4. An atomic deposition apparatus, characterized by: Including the atomic deposition chamber as described in any one of claims 1 to 3, further comprising: Equipment body (400); A thermal reaction chamber (500) is arranged side by side with the plasma reaction chamber (100); Vacuum unit (600) is used for switching between vacuum and atmospheric environments in the equipment, including a first vacuum lock (601) and a second vacuum lock (602). The loading unit (700) is used to place the wafer and includes a first loading stage (701) and a second loading stage (702). The transfer unit (800) is used to transfer wafers and includes a first robotic arm (801) and a second robotic arm (802).

5. A method of manufacturing an atomic deposition apparatus, characterized by: Suitable for manufacturing the atomic deposition apparatus as described in claim 4, comprising, A plasma reaction chamber (100) as described in claim 1 is provided on the device body (400). An isolation ring (200) is provided inside the plasma reaction chamber (100) such that the outer wall of the isolation ring (200) covers the inner wall of the plasma reaction chamber (100).

6. The method of manufacturing an atomic deposition apparatus according to claim 5, wherein: An etching pipeline (300) is also connected to the plasma reaction chamber (100), and an etching gas flows through the etching pipeline (300).

7. A method of making a capacitor, comprising: The preparation is carried out using the atomic deposition apparatus as described in claim 4, comprising: Provide a dielectric layer (900); A capacitor hole (1000) is formed in the dielectric layer (900). A barrier layer (1100), a lower electrode layer (1200), a dielectric layer (1300), and an upper electrode layer (1400) are sequentially formed on the inner wall of the capacitor hole (1000). An aluminum wire plate (1500) is formed on the upper electrode layer (1400) and the capacitor hole (1000) is filled.

8. The method of claim 7, wherein: The lower electrode layer (1200) and the upper electrode layer (1400) are formed in the plasma reaction cavity (100) by atomic deposition; The etching of the lower electrode layer (1200), the upper electrode layer (1400) and the dielectric layer (1300) is completed in the plasma reaction cavity (100).

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