A low-noise single-photon detector

Abstract

The present invention discloses a low-noise single-photon detector, which includes a controller, a bias voltage generation circuit, a refrigeration temperature control circuit, a gating voltage generation circuit, an avalanche signal extraction circuit, and an APD refrigeration box. One end of the bias voltage generation circuit, the gating voltage generation circuit, and the avalanche signal extraction circuit is connected to the controller. One end of the refrigeration temperature control circuit is connected to the TEC of the APD refrigeration box, and the other end is connected to the controller. The other end of the avalanche signal extraction circuit is connected to the anode of the APD in the APD refrigeration box through an AC coupling capacitor C2. The anode of the APD is grounded through a sampling resistor R2. The other end of the bias voltage generation circuit is connected to the cathode of the APD through a resistor R1. The other end of the gating voltage generation circuit is connected to the cathode of the APD through an AC coupling capacitor C1. Through the technical solution of the present invention, passive quenching in the free-running operating mode is achieved, the dead-time processing circuit is simplified, the detection efficiency is ensured, and the noise level of the detector is reduced.

Description

Technical Field

[0001] The present invention relates to the field of quantum communication, and more particularly, to a low-noise single-photon detector. Background Art

[0002] A single-photon detector is a super-sensitive detector that reaches the limit of weak-light detection, and can achieve the capture and conversion of light energy at the single-photon level. It is widely used in "high-precision and cutting-edge" scientific and technological fields. The single-photon detector is not only a key component of a quantum communication system, but also a key component of the systems in the fields of quantum measurement, lidar, fluorescence lifetime detection, space exploration, etc.

[0003] Currently, the main single-photon detectors are superconducting detectors, frequency up-conversion detectors, and semiconductor avalanche diode detectors. The first two types of detectors are large in volume and high in cost, and their practicability is not high; the semiconductor avalanche diode detector is small in volume and low in cost, but has high noise and cannot be used directly. Therefore, corresponding measures need to be taken to reduce the noise level.

[0004] The principle of a single-photon detection by an avalanche photodiode (APD) is as follows: The APD operates in Geiger mode to obtain a sufficiently high gain. When a photon is detected and incident, an avalanche current will be generated in the APD and continue spontaneously. Being in the avalanche state for a long time will affect the service life and stability of the APD. Therefore, after triggering an avalanche once, it is necessary to reduce the reverse bias voltage of the APD below the avalanche voltage through an active or passive method to exit the Geiger mode and quench the avalanche current. For a single-photon detector based on APD, several performance indicators such as detection efficiency, noise (dark count and afterpulse), and count rate are mutually restricted. Prolonging the APD avalanche duration or increasing the reverse bias voltage can improve the detection efficiency, but will increase the dark count and afterpulse; reducing the cooling temperature will reduce the dark count, but will increase the afterpulse; increasing the dead time length can suppress the probability of afterpulse generation, but will reduce the count rate. Therefore, according to different application requirements and scenario requirements, maintaining as high a detection efficiency as possible and suppressing the avalanche noise of the APD is an important research and development direction.

[0005] The patent document with publication number CN101650227A discloses a GHz sinusoidal wave gated low-pass filtered infrared single-photon detector, providing a general circuit composition. A sinusoidal wave with a frequency of GHz output from a sinusoidal wave gated power source is used as the gated signal for an indium gallium arsenide indium phosphide avalanche photodiode circuit. At the same time, a low-pass filter is used to perform low-pass filtering on the spike noise caused by the differential effect of the junction capacitance for GHz high-speed infrared single-photon detection. However, it does not adjust the amplitude of the sinusoidal gated signal and has no closed-loop stability maintenance function, unable to ensure the continuous stability of the detection efficiency. The gated signal cannot be revoked, and the bias voltage is generated by a high-precision programmable power supply with an output range of only 40 - 50V, not exceeding the reverse breakdown voltage of the APD. Therefore, the single-photon detector can only operate in the gated detection mode (also known as the gated mode).

[0006] The patent document with publication number CN113405677A discloses a high-speed sinusoidal gated single-photon detector, including a detection circuit and a reference circuit with a double sinusoidal gate and double APD tubes. The self-differential cancellation scheme is used to eliminate the noise signals and carriers generated by the detection circuit, enabling the high-speed sinusoidal gated single-photon detector to extract avalanche pulse electrical signals from the noise signals generated by the detection circuit. However, the cost of the double APD tube circuit is relatively high, making it less suitable for application scenarios with strict cost requirements.

[0007] The patent document with publication number CN115452145A discloses a test device for a single-photon detector. This test device for a single-photon detector realizes the test calibration switching process between the gated mode and the free-running mode. However, auxiliary means such as a switching switch, a bias device, and adjustable resistor adjustment are required to achieve the switching between the two modes. Since the switching circuit has circuit parasitic parameters (such as impedance mismatch problems), it has a greater impact on high-speed circuits and is not very suitable for high-speed detectors above GHz. In addition, using an adjustable resistor to adjust the APD bias voltage has the problem of low automation and is not suitable for product-level applications.

[0008] Currently, related technologies generally only optimize some performances of the detector, without considering the mutual restraint effect between different performances of the detector, nor providing a general circuit composition. At the same time, the lack of a scheme considering specific detailed parameter requirements makes it impossible for the single-photon detector to obtain better performance. Summary of the Invention

[0009] The technical problem to be solved by the present invention is how to consider the mutual restraint effect between different performances of the detector, so as to achieve deep suppression of noise signals while ensuring the detection efficiency.

[0010] The present invention realizes the solution to the above technical problems through the following technical means: A low-noise single-photon detector includes a controller, a bias voltage generation circuit, a refrigeration temperature control circuit, a gating voltage generation circuit, and an APD refrigeration box. One end of the refrigeration temperature control circuit is connected to the TEC of the APD refrigeration box, and the other end is connected to the controller. The low-noise single-photon detector further includes an avalanche signal extraction circuit. One ends of the bias voltage generation circuit, the gating voltage generation circuit, and the avalanche signal extraction circuit are connected to the controller. The other end of the avalanche signal extraction circuit is connected to the anode of the APD in the APD refrigeration box through an AC coupling capacitor C2. The anode of the APD is grounded through a sampling resistor R2. The other end of the bias voltage generation circuit is connected to the cathode of the APD through a resistor R1. The other end of the gating voltage generation circuit is connected to the cathode of the APD through an AC coupling capacitor C1.

[0011] As a further optimized technical solution, the resistance value of the series resistor R1 is 1 kΩ, the resistance value of the sampling resistor R2 is 50 Ω, and the capacitance values of the AC coupling capacitors C1 and C2 are both 100 nF.

[0012] As a further optimized technical solution, the bias voltage generation circuit includes a first digital-to-analog converter DAC1 and a boost converter. The input end of the first digital-to-analog converter DAC1 is connected to the controller, and the output end is connected to the boost converter. One output end of the boost converter serves as the output end of the bias voltage generation circuit.

[0013] As a further optimized technical solution, the bias voltage generation circuit further includes a first operational amplifier and a first analog-to-digital converter ADC1. The other output end of the boost converter is sequentially connected to the controller through the first operational amplifier and the first analog-to-digital converter ADC1. The current output by the boost converter to the APD is mirror-imaged at a ratio of 1:1, and after realizing I-V conversion through the first operational amplifier, it enters the first analog-to-digital converter ADC1 for digital sampling. The controller reads the sampled voltage value in real time, and judges the magnitude of the injected optical intensity of the APD by monitoring the change amplitude of the bias current, and further judges whether there is a strong light injection behavior.

[0014] As a further optimized technical solution, the refrigeration temperature control circuit includes a switching power supply, a second digital-to-analog converter DAC2, a second analog-to-digital converter ADC2, and a second operational amplifier. The controller is sequentially connected to the TEC of the APD refrigeration box through the second digital-to-analog converter DAC2 and the switching power supply. The NTC on the TEC is sequentially connected to the controller through the second operational amplifier and the second analog-to-digital converter ADC2.

[0015] As a further optimized technical solution, the gating voltage generation circuit includes a PLL and a phase shifter controller connected in sequence from the synchronous clock input end to the gating voltage output end.

[0016] As a further optimized technical solution, the PLL uses a phase-locked loop with an enabling function to phase-lock and frequency-multiply a 100 kHz low-frequency synchronous clock to 1.25 GHz. The phase-shift controller uses an adjustable phase shifter with a 360° phase-shift capability and a minimum adjustment range of 12.5 ps.

[0017] As a further optimized technical solution, the gating voltage generation circuit further includes a gating amplitude stability control circuit. The gating amplitude stability control circuit includes an attenuator, a power amplifier, a coupler connected in sequence behind the phase-shift controller, a first detector and a third analog-to-digital converter ADC3 connected between the output end of the coupler and the controller, and also includes a third digital-to-analog converter DAC3 and a third operational amplifier connected in sequence between the controller and the input end of the attenuator, where the controller is connected to the PLL_EN port of the PLL.

[0018] As a further optimized technical solution, the process of gating amplitude stability is as follows: The gating voltage after passing through the attenuator and the power amplifier outputs a part of the power through the coupler to the first detector for detection. The detected voltage enters the controller for algorithm adjustment after passing through the third analog-to-digital converter ADC3. The controller compares the real-time detected voltage with the target detected voltage. If the detected voltage is lower than the target detected voltage, the output of the third digital-to-analog converter DAC3 is changed, and through the third operational amplifier, it acts on the attenuator to reduce the attenuation value to increase the gating voltage value output at the output end of the gating voltage. If the detected voltage is higher than the target detected voltage, the output of the third digital-to-analog converter DAC3 is changed, and through the third operational amplifier, it acts on the attenuator to increase the attenuation value to reduce the gating voltage value output at the output end of the gating voltage, thereby maintaining the stability of the gating voltage.

[0019] As a further optimized technical solution, the controller can disable the PLL by setting the PLL_EN of the PLL low, turn off the gating voltage function, and increase the bias voltage so that the APD operates in the free-running mode (also known as the free-running mode).

[0020] As a further optimized technical solution, the avalanche signal extraction circuit includes a cascaded filter amplification circuit and a discrimination circuit connected in sequence, where the cascaded filter amplification circuit uses "3-stage filtering + 2-stage amplification", and its topological structure is "filter - amplification - filter - filter - amplification".

[0021] As a further optimized technical solution, the first-stage, second-stage, and third-stage filters use low-pass filters, the first-stage amplifier uses a low-noise amplifier, the second-stage amplifier uses a gain amplifier, and the discrimination circuit uses a high-speed comparator.

[0022] As a further optimized technical solution, the controller controls the gating voltage generation circuit to turn off, adjusts the bias voltage generated by the bias voltage generation circuit to be higher than the avalanche breakdown voltage, and passive quenching is completed by the resistor R1 in series with the APD. At this time, the detector operates in the free-running mode; the controller controls the gating voltage generation circuit to turn on, adjusts the bias voltage generated by the bias voltage generation circuit to be lower than the avalanche breakdown voltage, applies the gating voltage to make the voltage across the APD exceed the avalanche breakdown voltage, and active quenching is completed by the gating voltage. At this time, the detector operates in the gated mode.

[0023] The advantages of the present invention are as follows:

[0024] 1. A general low-noise single-photon detector scheme designed by the present invention comprehensively considers the combination of bias voltage, gating voltage, refrigeration control, and avalanche signal extraction. While ensuring the detection efficiency, passive quenching in the free-running mode is achieved through a series resistor. An avalanche signal extraction point is set at the anode of the APD, simplifying the dead-time processing circuit. The APD thermal noise is reduced by setting a refrigeration temperature control circuit. By setting an avalanche signal extraction circuit, the suppression of gated differential noise is realized, and the detector noise level can be greatly reduced.

[0025] 2. The avalanche signal extraction circuit designed by the present invention can extract the avalanche signal only by adopting a three-stage filtering and two-stage amplification structure, simplifying the circuit and reducing the circuit volume. The suppression of gated differential noise reaches 85 dB, and the amplification of the avalanche signal reaches 45 dB, enabling deep suppression of noise signals (such as gated differential signals) and amplification of avalanche signals.

[0026] 3. The designed bias voltage generation circuit has the capabilities of automatically adjustable bias signal amplitude and bias current detection. By detecting the magnitude of the bias voltage current of the APD during operation, it is used as a judgment condition for identifying whether there is a strong light attack. When the bias current is too large, the bias voltage applied to the APD can be reduced in a timely manner to avoid overcurrent damage caused by too long avalanche time of the APD.

[0027] 4. In the designed gating voltage generation circuit, it not only has the ability to amplify the gating voltage, but also has the ability to phase-lock and frequency-multiply the 100 kHz low-frequency synchronous clock to 1.25 GHz and perform 360° phase shift adjustment. It can realize the alignment operation of the gating voltage and the incident optical signal, and considers the gating amplitude stability ability at different phase points, which can maintain the stability of the detection efficiency of the single-photon detector.

[0028] 5. The circuit designed by the present invention has universality, and devices with corresponding frequency points and functions can be selected according to different application scenarios to change the gating frequency.

[0029] 6. The single-photon detector designed by the present invention has a simple structure, is easy to implement in engineering, and has a low cost. According to different application scenarios, the gating voltage can be turned off by disabling the phase-locked loop, and the single-photon detector can be flexibly switched between the gated detection working mode and the free-running working mode, with high working adaptability and reliability. Description of the Drawings

[0030] Figure 1 is the structural block diagram of the low-noise single-photon detector according to the embodiment of the present invention;

[0031] Figure 2 is the flowchart of the switching operation between the gated mode and the free-running mode according to the embodiment of the present invention;

[0032] Figure 3 is the overall circuit function relationship diagram of the low-noise single-photon detector circuit according to the embodiment of the present invention;

[0033] Figure 4 is the circuit diagram of the bias voltage generation according to the embodiment of the present invention;

[0034] Figure 5 is the circuit diagram of the refrigeration temperature control according to the embodiment of the present invention;

[0035] Figure 6 is the circuit diagram of the gating voltage generation according to the embodiment of the present invention;

[0036] Figure 7 is the circuit diagram of the avalanche signal extraction according to the embodiment of the present invention;

[0037] Figure 8 is the schematic diagram of the detection mode of the bias voltage superimposed on the gating voltage according to the embodiment of the present invention;

[0038] Figure 9 is the flowchart of the single-photon detector operation in the gated detection working mode according to the embodiment of the present invention;

[0039] Figure 10 is the flowchart of the single-photon detector operation in the free-running working mode according to the embodiment of the present invention. Detailed Embodiments

[0040] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the embodiments of the present invention. Apparently, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0041] In the present invention, the controller can be implemented as a general-purpose processor, a programmable logic controller (PLC), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or any suitable combination thereof for performing the functions described in the present disclosure. In the embodiments, the FPGA controller is taken as an example for illustration.

[0042] Figure 1 FIG. 4 is a block diagram of the overall structure of a low-noise single-photon detector according to an embodiment of the present invention, including an FPGA controller, a bias voltage generation circuit, a refrigeration temperature control circuit, a gating voltage generation circuit, an APD (Avalanche Photo Diode) refrigeration box, and an avalanche signal extraction circuit. One end of the bias voltage generation circuit and the gating voltage generation circuit are respectively connected to the cathode of the APD in the APD refrigeration box and the FPGA controller, one end of the avalanche signal extraction circuit is connected to the anode of the APD in the APD refrigeration box, and the other end is connected to the FPGA controller. One end of the refrigeration temperature control circuit is connected to the multi-stage TEC (Thermoelectric cooler) of the APD refrigeration box, and the other end is connected to the FPGA controller.

[0043] Bias voltage generation circuit: It is used to apply a reverse bias voltage to the APD. The applied reverse bias voltage has the characteristics of being adjustable and having high precision, and can apply a bias voltage lower or higher than the avalanche breakdown voltage.

[0044] Gating voltage generation circuit: It is used to generate a gating voltage. The amplitude of the gating voltage is adjustable and the output can be turned off. Different combinations of the amplitude of the gating voltage and the bias voltage can make the voltage finally applied across the APD higher or lower than the avalanche breakdown voltage, enabling the APD to alternate between the avalanche and quenching processes.

[0045] Refrigeration temperature control circuit: By detecting the temperature of the cold surface of the TEC and applying a control voltage to the multi-stage TEC to complete TEC refrigeration, it realizes the cooling of the working temperature of the APD to reduce the thermal noise level of the APD.

[0046] APD Cooling Box: The cooling box body is designed with airtight sealing, and it contains an APD, a multi-stage TEC, a negative temperature coefficient thermistor (NTC), and other resistors and capacitors. Among them, the APD and the NTC resistor are placed on the cold surface of the TEC. The cooling current of the TEC and the detection result of the NTC are connected to the cooling temperature control circuit. The bias voltage signal generated by the bias voltage generation circuit passes through the series resistor R1 (1kΩ), and the gating voltage generated by the gating voltage generation circuit passes through the AC coupling capacitor C1 (100nF), and then they are combined and loaded onto the cathode of the APD. The anode of the APD is connected to the avalanche signal extraction circuit through the AC coupling capacitor C2. One end of the sampling resistor R2 (50Ω) is connected to the anode of the APD and the AC coupling capacitor C2, and the other end is grounded. The avalanche signal is converted from current to voltage through the sampling resistor R2, and then output to the avalanche signal extraction circuit through the AC coupling capacitor C2 (100nF);

[0047] Avalanche Signal Extraction Circuit: It suppresses the gating noise, amplifies the avalanche signal, and performs coincidence filtering on the unexpected signals to achieve noise suppression and avalanche signal extraction;

[0048] FPGA Controller: As the control unit of the single-photon detector, it is mainly used to control the generation and stabilization of the bias voltage and the gating voltage, adjust the TEC temperature, receive the avalanche signal, and evaluate the working state of the detector in real time by sampling the mirrored bias operating current and take corresponding measures in case of anomalies to ensure the safety of the APD operation.

[0049] The above circuit architecture can adjust the gating voltage working mode and the bias voltage amplitude through the FPGA controller, and combine to achieve two working modes: gating detection and free running. The FPGA controller controls the gating voltage generation circuit to close, adjusts the bias voltage generated by the bias voltage generation circuit to be higher than the avalanche breakdown voltage, and the passive quenching is completed by the resistor R1 in series with the APD. At this time, the detector works in the free running mode; the FPGA controller controls the gating voltage generation circuit to open, adjusts the bias voltage generated by the bias voltage generation circuit to be lower than the avalanche breakdown voltage, loads the gating voltage to make the voltage across the APD exceed the avalanche breakdown voltage, and the active quenching is completed by the gating voltage. At this time, the detector works in the gating mode.

[0050] In the present invention, the automatic switching between the two working modes of the detector is realized through the control instructions of the FPGA controller, with a high degree of automation, and the single-photon detector with different performances can be reconstructed according to different application scenarios.

[0051] The switching working process of the gating mode and the free running mode of the low-noise single-photon detector of the present invention is as Figure 2 shown, and specifically includes the following steps:

[0052] Step 1: Power on the detector;

[0053] Step 2: Control the register PLL_EN in the gating voltage generation circuit through the FPGA to set it low (set to 0), turn off the gating voltage output, so as to only retain the bias voltage output of the bias voltage generation circuit;

[0054] Step 3: Set the bias voltage higher than the avalanche breakdown voltage;

[0055] Step 4: The detector enters the free-running working mode;

[0056] Step 5: Determine whether the detector receives a gating mode instruction. When receiving the gating mode instruction, go to Step 6; otherwise, return to Step 4;

[0057] Step 6: Reduce the target bias voltage below the avalanche breakdown voltage;

[0058] Step 7: Control the register PLL_EN in the gating voltage generation circuit through the FPGA controller to set it high (set to 1), turn on the gating voltage output;

[0059] Step 8: The detector enters the gated detection working mode;

[0060] Step 9: Determine whether the detector receives a free-running mode instruction. When receiving the free-running mode instruction, return to Step 2; otherwise, return to Step 8.

[0061] Please refer to Figure 3 , which is the overall circuit functional relationship diagram of the low-noise single-photon detector in the embodiment of the present invention. The circuit diagrams of the bias voltage generation circuit, the refrigeration temperature control circuit, the gating voltage generation circuit, and the avalanche signal extraction circuit in the present invention are as shown in Figures 4 to 7 shown.

[0062] Meanwhile, refer to Figure 4 , the bias voltage generation circuit in the embodiment of the present invention includes a first digital-to-analog converter DAC1, a boost converter, a first operational amplifier, and a first analog-to-digital converter ADC1. The input end of the first digital-to-analog converter DAC1 is connected to the FPGA controller, the output end is connected to the boost converter, one output end of the boost converter is used as the output end of the bias voltage generation circuit, and the bias voltage is output to the APD. One end is sequentially connected to the FPGA controller through the first operational amplifier and the first analog-to-digital converter ADC1.

[0063] The FPGA controller sets the bias voltage control value through the first digital-to-analog converter DAC1. A boost converter with current detection function (such as model: SGM41285A) can generate a bias voltage in the range of 10V - 70V under the action of the control voltage, and the step value is less than 10mV. When the boost converter is controlled by an external voltage, the maximum control voltage is 1.2V. When the external input exceeds 1.2V, the boost converter will force the use of the internal 1.2V reference voltage to protect the maximum output bias voltage of 70V. The current output from the boost converter to the APD can also be mirrored at a ratio of 1:1. The mirrored bias operating current (referred to as "bias current") undergoes I-V conversion through the first operational amplifier and then enters the first analog-to-digital converter ADC1 for digital sampling. The FPGA controller reads the sampled voltage value in real time, and identifies the magnitude of the optical intensity injected into the APD by monitoring the change amplitude of the bias current, and further determines whether there is a strong light injection behavior.

[0064] Also refer to Figure 5 As shown, in the embodiment of the present invention, the refrigeration temperature control circuit includes a switching power supply, a second digital-to-analog converter DAC2, a second analog-to-digital converter ADC2, and a second operational amplifier. Among them, the FPGA controller is sequentially connected to the TEC of the APD refrigeration box through the second digital-to-analog converter DAC2 and the switching power supply, and the NTC on the TEC is sequentially connected to the FPGA controller through the second operational amplifier and the second analog-to-digital converter ADC2.

[0065] The FPGA controller sets the voltage control value of the switching power supply (DC-DC) through the second digital-to-analog converter DAC2. The switching power supply provides a large refrigeration current (greater than 5A) for the TEC; the output of the NTC detection is amplified by the second operational amplifier and then enters the second analog-to-digital converter ADC2 (the reference voltage is 4.096V, 16bit) for digital sampling. The FPGA controller reads the sampled voltage value in real time. When the sampled NTC temperature is cooled to the target temperature range, the target bias voltage is loaded. At the same time, the FPGA controller uses a closed-loop feedback control algorithm to achieve temperature stability control ability, reduce the APD thermal noise level, and the temperature accuracy of stability can reach ±0.1°C.

[0066] Also refer to Figure 6As shown in the figure, in the embodiment of the present invention, the gating voltage generation circuit includes a PLL (phase locked loop), a phase shifter controller, an attenuator, a power amplifier, and a coupler that are connected in sequence from the synchronous clock input terminal to the gating voltage output terminal. It also includes a first detector and a third analog-to-digital converter ADC3 that are connected in sequence between the output terminal of the coupler and the FPGA controller, and a third digital-to-analog converter DAC3 and a third operational amplifier that are connected in sequence between the FPGA controller and the input terminal of the attenuator. The FPGA controller is connected to the PLL_EN port of the PLL.

[0067] Taking the injection of a low-frequency synchronous clock (100 kHz) to generate a single-frequency sinusoidal gating voltage as an example, the gating voltage generation circuit can generate a sinusoidal gating voltage with an amplitude range of 5 - 20 V, adjustable phase, and stable gating amplitude. Among them, as an optional device combination, the PLL uses a phase-locked loop with an enabling function (for example, model: AD9520) to phase-lock and frequency-multiply the 100 kHz low-frequency synchronous clock to 1.25 GHz. The phase shifter controller uses an adjustable phase shifter (for example, model: MAPS-011007) with a 360° phase-shifting ability and a minimum adjustment range of 12.5 ps. The attenuator uses a voltage-controlled attenuator (for example, model: RFSA2013) to meet the attenuation range control. Of course, those of ordinary skill in the art know that many other models of devices can still achieve the functions or capabilities described by the above devices. Therefore, the above devices can also use other existing devices that can achieve the same or similar functions.

[0068] Among them, the attenuator, power amplifier, coupler, first detector, third analog-to-digital converter ADC3, third digital-to-analog converter DAC3, third operational amplifier, and FPGA controller form a closed-loop gating amplitude stability control circuit, which can maintain the stability of the gating voltage at different phase points. The working process of gating amplitude stability is as follows: The gating voltage after the attenuator and power amplifier (point A) outputs a part of the power through the coupler (30 dB) to the first detector for detection. The detected voltage enters the FPGA controller for algorithm adjustment after passing through the third analog-to-digital converter ADC3. The FPGA controller compares the real-time detected voltage with the target detected voltage. If the detected voltage is lower than the target detected voltage, it changes the output of the third digital-to-analog converter DAC3, and through the third operational amplifier, it acts on the attenuator to reduce the attenuation value to increase the gating voltage value output at the gating voltage output terminal (point B). If the detected voltage is higher than the target detected voltage, it changes the output of the third digital-to-analog converter DAC3, and through the third operational amplifier, it acts on the attenuator to increase the attenuation value to reduce the gating voltage value output at the gating voltage output terminal (point B), thereby maintaining the stability of the gating voltage.

[0069] Furthermore, the FPGA controller can disable the PLL by setting PLL_EN of the PLL low, turn off the gating voltage function, increase the bias voltage, and make the APD operate in the free-running mode.

[0070] Please refer to Figure 7 , in the embodiment of the present invention, the avalanche signal extraction circuit includes a cascaded filter amplification circuit and a discrimination circuit connected in sequence, wherein the cascaded filter amplification circuit adopts "3-stage filtering + 2-stage amplification", and its topological structure is "filtering - amplification - filtering - filtering - amplification". The circuit topological structure of the present invention reduces the volume of the avalanche extraction circuit, reduces the number of filters and amplifiers used, thereby reducing the parasitic parameters of the avalanche extraction circuit, reducing the jitter of the avalanche signal front edge, and effectively reducing the detector noise level.

[0071] When the detector operates in the gated detection mode, since the main energy frequency of the avalanche signal is below 1 GHz, the first-stage filter adopts a low-pass filter to filter out the gated differential noise (1.25 GHz) and higher-frequency external crosstalk signals while retaining the useful avalanche signal; since the filter has a certain insertion loss that will reduce the already relatively small avalanche signal, therefore, a low-noise amplifier is used after the first-stage filter to amplify the avalanche signal. Since the gated voltage suppressed by the first-stage filter will be amplified again by the low-noise amplifier, the second-stage and third-stage filters are added after the low-noise amplifier to filter the gated noise to the white noise level, and then the avalanche signal can be extracted after one-stage gain amplification. Among them, the first-stage, second-stage, and third-stage filters adopt low-pass filters (for example, model: LFCN-800+), with a 3 dB cut-off frequency of 990 MHz; the first-stage amplifier adopts a low-noise amplifier (for example, model: WHM02AE), with a noise figure NF = 0.7 dB; the second-stage amplifier adopts a gain amplifier (for example, model: SGA4486A), and the amplified avalanche signal is discriminated by a high-speed comparator (8 GHz) to retain the front-edge information of the avalanche signal as much as possible, and the signal after discrimination is output as a detection pulse.

[0072] When the detector operates in the free-running mode, since the passive quenching method is adopted and there is no gated differential noise in the avalanche signal, the three-stage filter can still filter out the noise signals in the unexpected frequency band and suppress the entry of external high-frequency crosstalk into the avalanche amplification circuit. The two-stage amplifier can amplify the avalanche signal to an appropriate level, and the amplified avalanche signal is discriminated by a high-speed comparator (8 GHz) to retain the front-edge information of the avalanche signal as much as possible, and the signal after discrimination is output as a detection pulse.

[0073] The FPGA controller, as the control unit of the single-photon detector, is used to control the generation of bias voltage and the detection of bias current, the generation and stabilization of gating voltage, the temperature stabilization control of TEC, etc. It can control the single-photon detector to work in the gated detection mode or the free-running mode, and evaluate the working state of the detector in real time and take corresponding measures in case of abnormalities to ensure the safety of the APD operation; Figure 9 , Figure 10 respectively show the overall working processes of the low-noise single-photon detector in two working modes.

[0074] As Figure 9 shown, combined with Figure 3 , for the gated detection working mode, the working process of the low-noise single-photon detector includes:

[0075] Step S1: Power on the single-photon detector;

[0076] Step S2: Load the default bias voltage (40V);

[0077] Step S3: Start the refrigeration temperature control circuit to control the refrigeration of TEC. Specifically, the FPGA controller sets the voltage control value of the switching power supply (DC-DC) through the second digital-to-analog converter DAC2, and the switching power supply provides a large refrigeration current (greater than 5A) for TEC;

[0078] Step S4: Collect the NTC temperature. Specifically, the output end of the NTC detection is amplified by the second operational amplifier and then enters the second analog-to-digital converter ADC2 (reference voltage is 4.096V, 16bit) for digital sampling, and the FPGA controller reads the sampled voltage value in real time;

[0079] Step S5: The FPGA controller determines whether the refrigeration temperature is within the target temperature range. If it is within the target temperature range, go to step S6; otherwise, return to step S3;

[0080] Step S6: The FPGA controller issues the target bias voltage. Specifically, the FPGA controller sets the value of the first digital-to-analog converter DAC1, and generates the target bias voltage (such as 62V) after passing through the boost converter. The set bias voltage is slightly lower than the avalanche breakdown voltage (such as 64V). The bias voltage acts on the cathode of the APD at point C. At the same time, monitor the change of the APD bias current to identify whether there is strong light injection behavior;

[0081] Step S7: The FPGA controller detects the PLL lock indication (i.e., sets PLL_EN high);

[0082] Step S8: The FPGA controller determines whether the PLL receives the lock indication. When the PLL is locked, go to step S9; otherwise, return to step S7;

[0083] Step S9: After detecting the PLL lock indication, send the target gated voltage amplitude signal (such as 10V). Specifically, the FPGA controller sets PLL_EN high, accepts the synchronous clock input, and generates the initial gated voltage through the PLL and the phase shifter controller. At point B, it acts on the cathode of the APD through the AC coupling capacitor C1. After the bias voltage is superimposed on the gated voltage, the voltage amplitude applied to the APD is greater than the avalanche breakdown voltage. When the bias voltage superimposed on the gated voltage exceeds the avalanche breakdown voltage, avalanche can occur and single-photon detection can be performed. When the bias voltage superimposed on the gated voltage does not exceed the avalanche breakdown voltage, the avalanche process is quenched, as Figure 8 shown;

[0084] Step S10: Start the gate amplitude stability maintenance. Specifically, the process of gate amplitude stability maintenance is as follows: The gated voltage after the initial gated voltage passes through the attenuator and the power amplifier (at point A) outputs a part of the power through the coupler (30dB) to the first detector for detection. The detected voltage enters the FPGA controller for algorithm adjustment after passing through the third analog-to-digital converter ADC3. The FPGA controller compares the real-time detected voltage with the target detected voltage. If the detected voltage is lower than the target detected voltage, it changes the output of the third digital-to-analog converter DAC3, and through the third operational amplifier, it acts on the attenuator to reduce the attenuation value to increase the gated voltage value output at the gated voltage output end (point B). If the detected voltage is higher than the target detected voltage, it changes the output of the third digital-to-analog converter DAC3, and through the third operational amplifier, it acts on the attenuator to increase the attenuation value to reduce the gated voltage value output at the gated voltage output end (point B), thereby maintaining the stability of the gated voltage;

[0085] Step S11: When a single-photon signal is incident, start the delay scan to find the maximum detection efficiency point;

[0086] Step S12: Enter the normal single-photon detection state. The avalanche signal is output from point D. The avalanche signal extraction circuit filters out the gated noise and amplifies the avalanche signal, adopting a circuit topology of "filtering - low-noise amplification - filtering - filtering - amplification", reducing the number of filters and amplifiers used, and reducing the front-edge jitter of the avalanche signal.

[0087] As Figure 10 shown, combined with Figure 3 , for the free-running working mode, the working process of the low-noise single-photon detector includes:

[0088] Step S10: Power on the single-photon detector. The FPGA controller outputs the PLL_EN signal to control the phase-locked loop so that the PLL has no output, and then there is no gated voltage output at point B;

[0089] Step S20: Load the default bias voltage (40V);

[0090] Step S30: Start the refrigeration temperature control circuit to perform refrigeration control on the TEC. Specifically, the FPGA controller sets the voltage control value of the switched-mode power supply (DC-DC) through the second digital-to-analog converter DAC2. The switched-mode power supply provides a large refrigeration current (greater than 5A) for the TEC.

[0091] Step S40: Collect the NTC temperature. Specifically, the output of the NTC detection is amplified by the second operational amplifier and then enters the second analog-to-digital converter ADC2 (reference voltage is 4.096V, 16-bit) for digital sampling. The FPGA controller reads the sampled voltage value in real time.

[0092] Step S50: The FPGA controller determines whether the refrigeration temperature is within the target temperature range. If it is within the target temperature range, go to step S60; otherwise, return to step S30.

[0093] Step S60: The FPGA controller issues the target bias voltage. Specifically, the FPGA controller sets the value of the first digital-to-analog converter DAC1, and after passing through the boost converter, a target bias voltage (such as 68V) is generated. The set bias voltage is higher than the avalanche breakdown voltage (such as 64V). The bias voltage acts on the cathode of the APD at point C. At the same time, monitor the change of the APD bias current to identify whether there is a strong light injection behavior. When the APD generates continuous avalanche, as the avalanche current increases, the series resistor R1 (1kΩ) will generate a large voltage drop, making the reverse bias voltage across the APD lower than the breakdown voltage, thus realizing the avalanche quenching process.

[0094] Step S70: When a single-photon signal is incident, start the delay scan to find the maximum detection efficiency point.

[0095] Step S80: Enter the normal single-photon detection state. The avalanche signal is output from point D. The avalanche signal extraction circuit filters out the noise and amplifies the avalanche signal. It adopts a circuit topology of "filtering - low-noise amplification - filtering - filtering - amplification", reducing the number of filters and amplifiers used and reducing the front-edge jitter of the avalanche signal.

[0096] In the circuit designed by the present invention, the avalanche signal is extracted at the anode of the APD. When the single-photon detector is in the free-running working mode, only the resistor R1 generates a voltage drop, making the voltage across the APD lower than the avalanche breakdown voltage, realizing avalanche quenching and simplifying the dead-time processing circuit.

[0097] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A low-noise single-photon detector, comprising a controller, a bias voltage generation circuit, a refrigeration temperature control circuit, a gating voltage generation circuit, and an APD refrigeration box. One end of the refrigeration temperature control circuit is connected to the TEC of the APD refrigeration box, and the other end is connected to the controller. It further includes an avalanche signal extraction circuit. One ends of the bias voltage generation circuit, the gating voltage generation circuit, and the avalanche signal extraction circuit are connected to the controller. The other end of the avalanche signal extraction circuit is connected to the anode of the APD in the APD refrigeration box through an AC coupling capacitor C2. The anode of the APD is grounded through a sampling resistor R2. The other end of the gating voltage generation circuit is connected to the cathode of the APD through an AC coupling capacitor C1. The working temperature of the APD is cooled through the refrigeration temperature control circuit to reduce the APD thermal noise level. The gating noise is suppressed, the avalanche signal is amplified, and the non-expected signals are coincidence-filtered through the avalanche signal extraction circuit to achieve gating noise suppression and avalanche signal extraction. Characterized in that, The other end of the bias voltage generation circuit is connected to the cathode of the APD through a resistor R1. The controller closes the gating voltage function by disabling the PLL of the gating voltage generation circuit, increases the bias voltage so that the detector operates in the free-running mode; reduces the bias voltage below the avalanche breakdown voltage, and the controller enables the PLL of the gating voltage generation circuit to turn on the gating voltage generation circuit. At this time, the detector operates in the gating mode.

2. The low-noise single-photon detector according to claim 1, Characterized in that, The resistance value of the resistor R1 is 1 kΩ, the resistance value of the sampling resistor R2 is 50 Ω, and the capacitance values of the AC coupling capacitors C1 and C2 are both 100 nF.

3. The low-noise single-photon detector according to claim 1, Characterized in that, The bias voltage generation circuit includes a first digital-to-analog converter DAC1 and a boost converter. The input end of the first digital-to-analog converter DAC1 is connected to the controller, and the output end is connected to the boost converter. One output end of the boost converter serves as the output end of the bias voltage generation circuit.

4. The low-noise single-photon detector according to claim 3, Characterized in that, The bias voltage generation circuit further includes a first operational amplifier and a first analog-to-digital converter ADC1. The other output end of the boost converter is sequentially connected to the controller through the first operational amplifier and the first analog-to-digital converter ADC1. The current output by the boost converter to the APD is mirror-imaged at a ratio of 1:1, and after I-V conversion through the first operational amplifier, it enters the first analog-to-digital converter ADC1 for digital sampling. The controller reads the sampled voltage value in real time, and identifies the magnitude of the injected optical intensity of the APD by monitoring the change amplitude of the mirrored bias operating current, and further determines whether there is a strong light injection behavior.

5. The low-noise single-photon detector according to claim 1, Characterized in that, The refrigeration temperature control circuit includes a switching power supply, a second digital-to-analog converter (DAC2), a second analog-to-digital converter (ADC2), and a second operational amplifier. The controller is sequentially connected to the TEC of the APD refrigeration box through the second DAC2 and the switching power supply. The NTC on the TEC is sequentially connected to the controller through the second operational amplifier and the second ADC2.

6. The low-noise single-photon detector according to claim 1, characterized in that the gating voltage generation circuit includes a PLL and a phase shifter controller connected in sequence from the synchronous clock input terminal to the gating voltage output terminal.

7. The low-noise single-photon detector according to claim 6, characterized in that the PLL uses a phase-locked loop with an enabling function to phase-lock and frequency-multiply a 100 kHz low-frequency synchronous clock to 1.25 GHz. The phase shifter controller uses an adjustable phase shifter with a 360° phase-shifting ability and a minimum adjustment range of 12.5 ps.

8. The low-noise single-photon detector according to claim 6, characterized in that the gating voltage generation circuit further includes a gating amplitude stability control circuit. The gating amplitude stability control circuit includes an attenuator, a power amplifier, a coupler connected in sequence behind the phase shifter controller, a first detector and a third ADC3 connected between the output terminal of the coupler and the controller, and a third DAC3 and a third operational amplifier connected in sequence between the controller and the input terminal of the attenuator. The controller is connected to the PLL_EN port of the PLL.

9. The low-noise single-photon detector according to claim 8, characterized in that the working process of the gating amplitude stability is as follows: The gating voltage after passing through the attenuator and the power amplifier outputs a part of the power through the coupler to the first detector for detection. The detected voltage enters the controller for algorithm adjustment after passing through the third ADC3. The controller compares the real-time detected voltage with the target detected voltage. If the detected voltage is lower than the target detected voltage, the output of the third DAC3 is changed and acts on the attenuator through the third operational amplifier to reduce the attenuation value to increase the gating voltage value output at the gating voltage output terminal. If the detected voltage is higher than the target detected voltage, the output of the third DAC3 is changed and acts on the attenuator through the third operational amplifier to increase the attenuation value to reduce the gating voltage value output at the gating voltage output terminal, thereby maintaining the stability of the gating voltage.

10. The low-noise single-photon detector according to claim 8, characterized in that the controller can disable the PLL by setting the PLL_EN of the PLL low, turn off the gating voltage function, and increase the bias voltage so that the APD operates in the free-running mode.

11. The low-noise single-photon detector according to claim 1, characterized in that the avalanche signal extraction circuit includes a cascaded filter amplification circuit and a discrimination circuit connected in sequence. The cascaded filter amplification circuit uses "3-stage filtering + 2-stage amplification", and its topological structure is "filter - amplification - filter - filter - amplification".

12. The low-noise single-photon detector according to claim 11, characterized in that, the first-stage, second-stage, and third-stage filters adopt low-pass filters, the first-stage amplifier adopts a low-noise amplifier, the second-stage amplifier adopts a gain amplifier, and the discrimination circuit adopts a high-speed comparator.

13. The low-noise single-photon detector according to any one of claims 1 to 12, characterized in that, the controller controls the gating voltage generation circuit to turn off, adjusts the bias voltage generated by the bias voltage generation circuit to be higher than the avalanche breakdown voltage, and passive quenching is completed by the resistor R1 in series with the APD. At this time, the detector operates in the free-running mode; the controller controls the gating voltage generation circuit to turn on, adjusts the bias voltage generated by the bias voltage generation circuit to be lower than the avalanche breakdown voltage, applies the gating voltage to make the voltage across the APD exceed the avalanche breakdown voltage, and active quenching is completed by the gating voltage. At this time, the detector operates in the gated mode.

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