A shift register circuit, a display panel and a display device

Abstract

Embodiments of the present application provide a shift register circuit, a display panel and a display device. The shift register circuit comprises a plurality of cascaded shift registers, and the shift registers receive a first clock signal to realize a shift function. The shift register comprises a first output unit and a first voltage stabilizing unit. The first output unit is used to be turned on and continuously output a non-enable signal in a holding stage. The first voltage stabilizing unit is electrically connected with the first output unit. The first voltage stabilizing unit is used to maintain the open state of the first output unit in the holding stage. The first voltage stabilizing unit comprises a first capacitor, a first plate of the first capacitor is electrically connected with the first output unit, and a second plate of the first capacitor is used to receive a first signal in the holding stage, and the first signal jumps between a high level and a low level. The absolute value of the difference between the high level and the low level of the first clock signal is a first difference, the absolute value of the difference between the high level and the low level of the first signal is a second difference, and the first difference is greater than the second difference.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a shift register, a display panel, and a display device. Background Art

[0002] To save energy, existing display panels operate at ultra-low frequencies when displaying simple standby screens. For example, when displaying simple screens like a clock face, the display panel's operating frequency is as low as 1 Hz or even lower. When operating at ultra-low frequencies, the display panel's power consumption is relatively low. However, further product optimization requires further reductions in display panel power consumption. Summary of the Invention

[0003] In order to solve the above problems, the present application provides a shift register circuit, a display panel and a display device to solve the problem of high power consumption of display panels in the prior art.

[0004] In a first aspect, the present application provides a shift register circuit, comprising a plurality of cascaded shift registers, wherein the shift register receives a first clock signal to implement a shifting function, and the shift register comprises: a first output unit and a first voltage stabilizing unit. The first output unit is configured to be turned on during the holding phase of the shift register and to continuously output a non-enable signal during the holding phase. The first voltage stabilizing unit is electrically connected to the first output unit. The first voltage stabilizing unit is configured to maintain the first output unit in an on state during the holding phase. The first voltage stabilizing unit comprises a first capacitor, wherein the first plate of the first capacitor is electrically connected to the first output unit, and the second plate of the first capacitor is configured to receive a first signal during the holding phase of the shift register and the first signal jumps between a high level and a low level. The absolute value of the difference between the high level and the low level of the first clock signal is a first difference, the absolute value of the difference between the high level and the low level of the first signal is a second difference, and the first difference is greater than the second difference.

[0005] During the holding phase of the shift register, the potential of the second plate of the first capacitor frequently switches between the high level and the low level of the first signal. Therefore, during the holding phase of the shift register, the potential variation range of the second plate of the first capacitor is the difference between the high level and the low level of the first signal. The second difference being less than the first difference means that the potential variation range of the second plate of the first capacitor is less than the difference between the high level and the low level of the first clock signal, and the smaller potential variation range of the second plate of the first capacitor can effectively save the power consumption of the frequent charging and discharging of the first capacitor. Therefore, the present application reduces the power consumption of the entire shift register circuit by reducing the power consumption of the first capacitor.

[0006] In one implementation of the first aspect, the first voltage stabilizing unit further includes a first switch. A first end of the first switch is electrically connected to a first signal line, the first signal line being configured to transmit the first signal during the hold phase. A second end of the first switch is electrically connected to a second plate of the first capacitor.

[0007] In this implementation, the first signal is written to the second plate of the first capacitor when the first switch is turned on. For example, during the hold phase of the shift register, the first switch is turned on, thereby frequently writing the high or low level of the first signal to the second plate of the first capacitor.

[0008] In an implementation of the first aspect, the control end of the first switch is electrically connected to the first plate of the first capacitor.

[0009] The control terminal of the first switch is electrically connected to the first plate of the first capacitor, that is, the first capacitor is disposed between the control terminal of the first switch and the second terminal of the first switch. The first capacitor can stabilize the voltage between the control terminal of the first switch and the second terminal of the first switch, thereby improving the stability of the first switch.

[0010] In one implementation of the first aspect, the first signal transmitted by the first signal line during the hold phase is a clock signal. The first signal line includes a first sub-signal line and a second sub-signal line. The first sub-signal line is used to transmit a first sub-clock signal during the hold phase, and the second sub-signal line is used to transmit a second sub-clock signal during the hold phase. The first sub-clock signal and the second sub-clock signal are asynchronous signals. In two adjacent cascaded shift registers, the first end of a first switch of one shift register is electrically connected to the first sub-signal line, and the first end of a first switch of the other shift register is electrically connected to the second sub-signal line.

[0011] In this implementation, in two adjacent cascaded shift registers, the first end of the first switch of one shift register is electrically connected to the first sub-signal line, and the first end of the first switch of the other shift register is electrically connected to the second sub-signal line. This design facilitates implementation, reduces implementation difficulty, and saves costs. Therefore, connecting two adjacent cascaded shift registers to different sub-signal lines can reduce the implementation difficulty of the overall circuit while ensuring normal stage transmission of the shift register circuit.

[0012] In one implementation of the first aspect, the first voltage stabilizing unit further includes a second switch. A first end of the second switch is configured to receive the first voltage signal, and a second end of the second switch is electrically connected to the second plate of the first capacitor. The second switch is configured to write the first voltage signal to the second plate of the first capacitor when a signal is written to the control end of the first output unit.

[0013] In this implementation, the second switch is used to write the first voltage signal to the second plate of the first capacitor when a signal is written to the control terminal of the first output unit, thereby making the potential of the second plate of the first capacitor a positive potential of the first voltage. The potential of the second plate of the first capacitor is at a relatively high positive potential. On the one hand, it can ensure that the shift register has a stable voltage difference between the two plates of the first capacitor during the holding phase. This stable voltage difference can ensure that the potential of the control terminal of the first output unit is in a stable state during the holding phase after the enable signal is written to the control terminal of the first output unit, thereby ensuring that the first output unit remains in an on state. On the other hand, during the triggering and output phases of the shift register, there is a stable voltage difference between the two plates of the first capacitor. This stable voltage difference can ensure that the potential of the control terminal of the first output unit is in a stable state during the triggering and output phases of the shift register, thereby ensuring that the first output unit is in an off state.

[0014] In one implementation of the first aspect, the second switch is further configured to write the first voltage signal to the second plate of the first capacitor when the control terminal of the first output unit receives a disable signal. Therefore, by utilizing the stable voltage difference between the two plates of the first capacitor, it is possible to ensure that, during a holding phase after the disable signal is written to the control terminal of the first input unit, the potential at the control terminal of the first output unit is such that the first output unit is in an off state.

[0015] In an implementation of the first aspect, the second difference is greater than 2*|Vth|, where |Vth| is an absolute value of a threshold voltage of the first switch.

[0016] The second difference is greater than 2*|Vth|, which can ensure the normal operation of the first switch.

[0017] In an implementation manner of the first aspect, the first signal line is further used to transmit the first signal in the trigger phase and / or the output phase.

[0018] In the trigger stage and / or the output stage, the first signal line is used to transmit the first signal, which can minimize the power consumption of the first capacitor while achieving normal stage transmission of the shift register circuit, thereby reducing the overall power consumption of the shift register circuit.

[0019] In one implementation of the first aspect, the shift register further includes a second output unit. A first end of the first output unit is electrically connected to a second signal line, and a second end of the first output unit is configured to output a second voltage signal transmitted by the second signal line during an output phase. A first end of the second output unit is electrically connected to a third signal line, and a second end of the second output unit is configured to output a third voltage signal transmitted by the third signal line during an output phase. A high level of the first signal is less than the larger of the second and third voltage signals, and / or a low level of the first signal is greater than the smaller of the second and third voltage signals.

[0020] In this implementation, the high level of the first signal is less than the larger one of the second voltage signal and the third voltage signal, and / or the low level of the first signal is greater than the smaller one of the second voltage signal and the third voltage signal. On the one hand, this ensures that the first difference is less than the second difference, and on the other hand, it does not affect the normal level transmission function of the shift register circuit.

[0021] In an implementation of the first aspect, a high level of the first signal is lower than a high level of the first clock signal, and / or a low level of the first signal is higher than a low level of the first clock signal.

[0022] In this implementation, the high level of the first signal is less than the high level of the first clock signal; and / or the low level of the first signal is greater than the low level of the first clock signal. This ensures that the first difference is less than the second difference while also ensuring normal stage transfer in the shift register circuit. Therefore, this implementation reduces power consumption without affecting the operating performance of the shift register circuit.

[0023] In a second aspect, the present application further provides a display panel, which includes the shift register circuit of the first aspect or any one implementation manner of the first aspect.

[0024] The shift register circuit according to the first aspect or any one of the implementations of the first aspect can effectively reduce the power consumption of the display panel during display.

[0025] In a third aspect, the present application provides a display device, comprising the display panel of the second aspect.

[0026] The use of the display panel of the second aspect can enable the display device to have lower power consumption during display, thereby achieving the purpose of energy saving.

[0027] The shift register circuit provided by the application, in the holding stage of the shift register, the potential of the second plate of the first capacitor frequently switches between the high level and the low level of the first signal. Therefore, in the holding stage of the shift register, the potential variation range of the second plate of the first capacitor is the difference between the high level and the low level of the first signal. The second difference is smaller than the first difference, which means that the potential variation range of the second plate of the first capacitor is smaller than the difference between the high level and the low level of the first clock signal. Compared with the prior art in which the first difference is equal to the second difference, the shift register circuit provided by the embodiment reduces the potential variation difference of the second plate of the first capacitor, thereby effectively reducing the power consumption of the second plate of the second capacitor in the frequent charging and discharging process, i.e. reducing the overall power consumption of the shift register circuit. BRIEF DESCRIPTION OF DRAWINGS

[0028] In order to more clearly illustrate the technical solutions of the embodiments of the application, the drawings needed in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative labor.

[0029] Figure 1 is a schematic diagram of a pixel circuit;

[0030] Figure 2 is a schematic diagram of a shift register;

[0031] Figure 3 is a schematic diagram of a shift register circuit provided by an embodiment of the application;

[0032] Figure 4 is a schematic diagram of a shift register provided by an embodiment of the application;

[0033] Figure 5 is a schematic diagram of a shift register provided by an embodiment of the application;

[0034] Figure 6 is a schematic diagram of a first voltage stabilizing unit and a first output unit provided by an embodiment of the application;

[0035] Figure 7 is a schematic diagram of a shift register provided by an embodiment of the application;

[0036] Figure 8 is a schematic diagram of three cascaded shift registers provided by an embodiment of the application;

[0037] Figure 9 is a timing control diagram of the shift register provided by an embodiment of the application; Figure 8

[0038] ​Figure 10 A method for Figure 8 Timing control diagram;

[0039] Figure 11 Schematic diagram of a shift register in the prior art;

[0040] Figure 12 A display panel provided in an embodiment of the present application;

[0041] Figure 13 A display device is provided in an embodiment of the present application.

[0042] Label Description

[0043] 100. Shift register circuit; 101. First clock signal line; 102. Second clock signal line; 110. Shift register; 111. First output unit; 112. First voltage stabilizing unit; 113. Trigger unit; 114. First control unit; 115. Second control unit; 116. Second voltage stabilizing unit; 117. Second output unit; 120. First signal line; 121. First sub-signal line; 122. Second sub-signal line; 200. Display panel; 300. Display device. DETAILED DESCRIPTION

[0044] In order to better understand the technical solution of the present application, the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0045] It should be clear that the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0046] The terms used in the embodiments of the present application are for the purpose of describing specific embodiments only and are not intended to limit the present application. The singular forms "a", "an", "the" and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms unless the context clearly indicates otherwise.

[0047] It should be understood that the term "and / or" as used herein simply describes a relationship between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can represent: A alone, A and B together, or B alone. Furthermore, the character " / " in this document generally indicates an "or" relationship between the associated objects.

[0048] In order to better understand the technical solutions provided by the embodiments of the present application, the technical problems to be solved by the present application are first described in detail.

[0049] The shift register circuit functions as a stage-by-stage relay, providing scan signals to the pixel circuits row by row or according to a set sequence, thereby controlling the pixel circuits. The pixel circuits include several semiconductor switches, and the outputs of each stage of the shift register circuit are electrically connected to the control terminals of the corresponding semiconductor switches in the corresponding pixel circuits. For example, if the i-th stage shift register is used to control the semiconductor switches of the threshold compensation modules in the m-th row of pixel circuits, then the outputs of the i-th stage shift register are electrically connected to the control terminals of the semiconductor switches of the threshold compensation modules in the m-th row of pixel circuits. Here, i and m are both positive integers.

[0050] Figure 1 is a schematic diagram of a pixel circuit. Figure 1 As shown, at least one of the semiconductor switch S2N1 of the threshold compensation module in the pixel circuit and the semiconductor switch S1N1 in the first reset module can be controlled by a shift register. It should be noted that, Figure 1 The pixel circuit shown is only an example and is not a specific limitation. Similarly, the type of semiconductor switch controlled by the shift register, the connection position in the circuit, etc. are also an example and are not a specific limitation.

[0051] Figure 2 This is a schematic diagram of a shift register. Figure 2 As shown, the shift register receives the clock signal CK. The shift register includes a trigger unit, and the clock signal CK is used to trigger the unit. The shift register includes a voltage stabilizing unit, and the voltage stabilizing unit includes a voltage stabilizing capacitor. One plate of the voltage stabilizing capacitor is used to receive the input signal of the shift register, and the other plate of the voltage stabilizing capacitor is used to receive the clock signal XCK, so that the shift register can be in the holding phase. When the shift register is in the holding phase, a non-enable signal is output to the outside (the non-enable signal refers to the semiconductor switch that is electrically connected to be in the off state). For ease of control, in the existing technology, the high level of the clock signal CK is equal to the high level of the clock signal XCK, and the low level of the clock signal CK is equal to the low level of the clock signal XCK. Therefore, the plate of the voltage stabilizing capacitor receiving the clock signal XCK will be frequently written with high and low levels, and the difference between the high and low levels is equal to the difference between the clock signal CK. This frequent high and low level change of the plates of the voltage stabilizing capacitor is equivalent to frequent charging and discharging, thereby causing the voltage stabilizing capacitor to generate a large amount of power consumption, and ultimately leading to high power consumption of the shift register and even the shift register circuit.

[0052] In order to solve this problem, the present application provides a shift register circuit to improve the problem of high power consumption caused by the voltage-stabilizing capacitor in the prior art.

[0053] Figure 3 A schematic diagram of a shift register circuit provided in an embodiment of the present application.Figure 4 A schematic diagram of a shift register provided in an embodiment of the present application.

[0054] like Figure 3 As shown, a shift register circuit 100 includes a plurality of cascaded shift registers 110. The shift register 110 receives a first clock signal CK to implement a shift function. In a possible implementation, the shift register 110 is electrically connected to a first clock signal line 101, and the first clock signal line 101 is used to transmit the first clock signal CK. Figure 4 As shown, the shift register 110 includes a first output unit 111 and a first voltage stabilizing unit 112 .

[0055] The first output unit 111 is configured to be turned on during the holding phase of the shift register 110 . The first output unit 111 continuously outputs a non-enable signal during the holding phase of the shift register 110 .

[0056] The holding phase of the shift register 110 refers to the phase in which the first output unit 111 of the shift register 110 remains turned on. When the first output unit 111 is in the turned-on state, the shift register 110 outputs a non-enable signal to the outside. For example, the holding phase of the shift register 110 can be the phase from when the shift register 110 stops outputting the enable signal (i.e., when it starts outputting the non-enable signal) to before it is triggered again. The shift register 110 outputs an enable signal, which means that the signal output by the shift register 110 is an enable signal, which can cause the semiconductor switch electrically connected to the output end of the shift register 110 to be in the on state. The shift register 110 outputs a non-enable signal, which means that the signal output by the shift register 110 is a non-enable signal, which can cause the semiconductor switch electrically connected to the output end of the shift register 110 to be in the off state.

[0057] like Figure 4 As shown, the first voltage stabilizing unit 112 is electrically connected to the first output unit 111 , and the first voltage stabilizing unit 112 is used to maintain the first output unit 111 in an on state during the holding phase.

[0058] For example, the first voltage stabilizing unit 112 is electrically connected to the control terminal of the first output terminal. The first voltage stabilizing unit 112 has a voltage stabilizing function and can stabilize the potential of the control terminal of the first output unit 111 so that the first output unit 111 remains in an on state during the holding phase.

[0059] like Figure 4 As shown, the first voltage stabilizing unit 112 includes a first capacitor C1. A first plate of the first capacitor C1 is electrically connected to the first output unit 111. A second plate of the first capacitor C1 is used to receive a first signal during the hold phase of the shift register 110. The first signal transitions between a high level and a low level.

[0060] In one possible implementation, the first plate of the first capacitor C1 is electrically connected to the control terminal of the first output unit 111. The first capacitor C1 is used to stabilize the potential of the control terminal of the first output unit 111. The first signal transitioning between a high level and a low level can help maintain the potential of the control terminal of the first output unit 111, so that the first output unit 111 is in an on state during the hold phase of the shift register 110.

[0061] like Figure 4 As shown, the absolute value of the difference between the high level and the low level of the first clock signal CK is a first difference, the absolute value of the difference between the high level and the low level of the first signal is a second difference, and the first difference is greater than the second difference.

[0062] During the holding phase of the shift register 110, the high level and the low level of the first signal are frequently written to the second plate of the first capacitor C1, that is, the potential of the second plate of the first capacitor C1 frequently switches between the high level and the low level of the first signal. Therefore, the range of variation of the potential of the second plate of the first capacitor C1 in the present application is the second difference. While the range of variation of the potential of the second plate of the first capacitor C1 in the prior art is the first difference. The second difference is less than the first difference, which means that the range of variation of the potential of the second plate of the first capacitor C1 is reduced compared to the prior art. The reduction in the range of variation of the potential of the second plate of the first capacitor C1 means that the power consumption of the first capacitor C1 is reduced. Therefore, the shift register circuit 100 provided in the present application reduces the power consumption of the first capacitor C1 in the voltage stabilizing module of the shift register 110, and ultimately reduces the overall power consumption of the shift register circuit 100.

[0063] Figure 5 A schematic diagram of a shift register 110 provided in an embodiment of the present application.

[0064] like Figure 5As shown, in one embodiment of the present application, the shift register 110 further includes a trigger unit 113, a first control unit 114, a second control unit 115, a second voltage stabilizing unit 116, and a second output unit 117. The trigger unit 113 is used to receive an input signal (i.e., the output signal of the previous shift register 110), and the control end of the trigger unit 113 is electrically connected to the first clock signal CK. The first clock signal CK is used to control the trigger unit 113. The first control unit 114 and the second control unit 115 are respectively electrically connected to the trigger unit 113. The first control unit 114 is electrically connected to the control end of the first output unit 111. The input signal is transmitted to the first control unit 114 via the trigger unit 113, and the first control unit 114 transmits the received input signal to the control end of the first output unit 111, thereby controlling the first output unit 111. The second control unit 115 is also used to receive the second clock signal XCK1. The second control unit 115 is electrically connected to the second clock signal line 102, which is used to transmit the second clock signal XCK1. The second control unit 115 is capable of transmitting the second clock signal XCK1 to the control terminal of the second output unit 117, so that the second clock signal XCK1 controls the second output unit 117. The second output unit 117 is configured to remain on and continuously output an enable signal during the output phase of the shift register 110. The second voltage stabilizing unit 116 is configured to maintain the second output phase in an off state during the hold phase of the shift register 110. The output phase of the shift register 110 refers to the output of the shift register 110 as an enable signal, which turns on a switch electrically connected to the shift register 110.

[0065] The second output unit 117 is electrically connected to the first output unit 111, and the second output unit 117 and the first output unit 111 share a common output terminal. At any given moment, at most one of the first output unit 111 and the second output unit 117 is in an on state. That is, when the first output unit 111 is in an on state, the second output unit 117 is in an off state, and the shift register 110 outputs a disable signal. When the second output unit 117 is in an on state, the first output unit 111 is in an off state, and the shift register outputs an enable signal.

[0066] The first voltage stabilizing unit 112 is further configured to maintain the first output unit 111 in an off state during the triggering phase and the output phase of the shift register 110. The second voltage stabilizing unit 116 is further configured to maintain the second output unit 117 in an on state during the starting phase and the output phase of the shift register 110. The triggering phase of the shift register 110 refers to a phase in which the input signal of the shift register 110 is the enable signal output by the previous shift register 110, i.e., the signal received by the triggering unit 113 of the shift register 110 is the enable signal output by the previous shift register 110. In some cases, the triggering phase of the shift register 110 and the output phase of the shift register 110 overlap in time, i.e., at a certain moment, the shift register 110 is both in the triggering phase and in the output phase.

[0067] In this embodiment, the operating principle of the shift register 110 is as follows: when the previous stage shift register 110 outputs an enable signal, the trigger unit 113 of the current stage shift register 110 is triggered. At the same time, the first clock signal CK controls the trigger unit 113 to be in a conductive state. At the same time, the first control unit 114 is in a conductive state. At this time, the enable signal output by the previous stage shift register 110 is transmitted to the control terminal of the first output unit 111, turning off the first output unit 111. Then, the second clock signal XCK1 controls the second control unit 115 to turn on, and the second clock signal XCK1 is transmitted to the control terminal of the second output unit 117 via the second control unit 115. The second output unit 117 turns on, and the shift register 110 outputs the enable signal to the outside. After the trigger phase ends, when the first clock signal CK provides a valid signal for the first time, the second output unit 117 ends the on state (i.e., the second output unit 117 is in a closed state), and the first output unit 111 is in a conductive state. At this time, the shift register 110 stops outputting the enable signal and starts outputting the disable signal. Therefore, after the trigger phase ends, when the signal provided by the first clock signal CK becomes a valid signal for the first time, it means the end of the output phase of the shift register 110 and the beginning of the hold phase of the shift register 110. The trigger phase of the shift register 110 refers to the signal received by the trigger unit 113 being the enable signal output by the previous shift register 110. A valid signal is a signal that turns the controlled switch on. For example, the signal provided by the first clock signal CK is a valid signal, which means that, driven by the valid signal, the trigger unit 113 is in the on state. An invalid signal is a signal that cannot turn the controlled switch on, for example, an invalid signal is a signal that turns the controlled switch off.

[0068] Figure 6 A schematic diagram of a first voltage stabilizing unit 112 and a first output unit 111 provided in an embodiment of the present application.

[0069] As shown in FIG. 1, in an embodiment of the present application, the first voltage stabilizing unit 112 further comprises a first switch T1. A first end of the first switch T1 is electrically connected with a first signal line 120, and the first signal line 120 is used for transmitting a first signal in a holding stage. A second end of the first switch T1 is electrically connected with a second plate of the first capacitor C1. Figure 6

[0070] The first switch T1 is used for transmitting the first signal to the second plate of the first capacitor C1 when the first switch T1 is turned on. In a possible implementation, the first switch T1 can be a semiconductor switch. Taking a PMOS tube as an example, the first end of the first switch T1 is the source, and the second end of the first switch T1 is the drain. The source of the first switch T1 is electrically connected with the first signal line 120, and the first signal is transmitted to the source of the first switch T1 through the first signal line 120 in the holding stage of the shift register 110. When the first switch T1 is turned on, the first signal received by the source of the first switch T1 is transmitted to the drain of the first switch T1. The drain of the first switch T1 is electrically connected with the second plate of the first capacitor C1, so that the second plate of the first capacitor C1 receives the first signal.

[0071] As shown in FIG. 1, in an embodiment of the present application, the control end of the first switch T1 is electrically connected with the first plate of the first capacitor C1. Figure 6

[0072] The control end of the first switch T1 is electrically connected with the first plate of the first capacitor C1, that is, the first capacitor C1 is arranged between the control end of the first switch T1 and the second end of the first switch T1. The first capacitor C1 can stabilize the voltage between the control end of the first switch T1 and the second end of the first switch T1, thereby improving the stability of the first switch T1.

[0073] In a possible implementation, the first plate of the first capacitor C1 is electrically connected with the control end of the first output unit 111, and thus the control end of the first switch T1 is electrically connected with the control end of the first output unit 111. In the holding stage of the shift register 110, the first switch T1 is always in a conductive state, so that the second plate of the first capacitor C1 is written with the first signal in this stage, and the jump between the high level and the low level of the first signal makes the potential of the second plate of the first capacitor C1 frequently jump between the high level of the first signal and the low level of the first signal. The jump of the potential of the second plate of the first capacitor C1 between the high level of the first signal and the low level of the first signal can help maintain the potential of the control end of the first output unit 111.

[0074] As shown in FIG. 1, in an embodiment of the present application, the control end of the first switch T1 is electrically connected with the first plate of the first capacitor C1. Figure 6 ​​As shown, in one embodiment of the present application, the first voltage stabilizing unit 112 further includes a second switch T2. The first end of the second switch T2 is configured to receive the first voltage signal, and the second end of the second switch T2 is electrically connected to the second plate of the first capacitor C1. The second switch T2 is configured to write the first voltage signal to the second plate of the first capacitor C1 when a signal is written to the control end of the first output unit 111.

[0075] The control terminal of the second switch T2 is electrically connected to the trigger unit 113, which is further configured to receive the second voltage signal. When the first clock signal CK controls the trigger unit 113 to be in an on state, the trigger unit 113 transmits the second voltage signal to the control terminal of the second switch T2, turning the second switch T2 in an on state. This causes the second voltage signal to be transmitted to the second plate of the first capacitor C1 via the second switch T2.

[0076] The fact that a signal is written to the control terminal of the first output unit 111 means that the trigger unit 113 is in the on state, and the input signal received by the trigger unit 113 is transmitted to the control terminal of the first output unit 111. It should be noted that due to the presence of the first voltage stabilizing unit 112, after the input signal is written to the control terminal of the first output unit 111, the control terminal of the first output unit 111 remains in a state of receiving the input signal until the next input signal is written.

[0077] In this embodiment, the second switch T2 is used to write the first voltage signal to the second plate of the first capacitor C1 when a signal is written to the control terminal of the first output unit 111. Therefore, the potential of the second plate of the first capacitor C1 is a positive potential of the first voltage. The potential of the second plate of the first capacitor C1 is at a relatively high positive potential. On the one hand, it can ensure that there is a stable voltage difference between the two plates of the first capacitor C1 during the hold phase of the shift register 110. This stable voltage difference can ensure that the potential of the control terminal of the first output unit 111 is in a stable state during the hold phase after the enable signal is written to the control terminal of the first output unit 111, thereby ensuring that the first output unit 111 remains in an on state. On the other hand, during the trigger phase and output phase of the shift register 110, there is a stable voltage difference between the two plates of the first capacitor C1. This stable voltage difference can ensure that the potential of the control terminal of the first output unit 111 is in a stable state during the trigger phase and output phase of the shift register 110, thereby ensuring that the first output unit 111 is in an off state.

[0078] During the hold phase of the shift register 110, the first switch T1 is constantly on, so the second plate of the first capacitor C1 is frequently written with the high or low level of the first signal. The second switch T2 is controlled by the first clock signal CK. When the second switch T2 is on, the second plate of the first capacitor C1 simultaneously receives the high level of the first signal and the first voltage signal. Therefore, to ensure normal operation of the circuit, the high level of the first signal is equal to the positive potential of the first voltage signal.

[0079] In one possible implementation of this embodiment, the second switch T2 is further configured to write the first voltage signal to the second plate of the first capacitor C1 when the control terminal of the first output unit 111 receives a disable signal. Therefore, by utilizing the stable voltage difference between the two plates of the first capacitor C1, it is possible to ensure that, during the holding phase after the disable signal is written to the control terminal of the first input unit, the potential at the control terminal of the first output unit 111 is such that the first output unit 111 is in the off state.

[0080] Figure 7 A schematic diagram of a storage register provided in an embodiment of the present application.

[0081] like Figure 7As shown, in one embodiment of the present application, the first output unit 111 includes a first output switch T3, the first end of the first output switch T3 being the first end of the first output unit 111, the second end of the first output switch T3 being the second end of the first output unit 111, and the control end of the first output switch T3 being the control end of the first output unit 111. The second output unit 117 includes a second output switch T4, the first end of the second output switch T4 being the first end of the second output unit 117, the second end of the second output switch T4 being the second end of the second output unit 117, and the control end of the second output switch T4 being the control end of the second output unit 117. The first control module includes a switch T11, the first end of the switch T11 being electrically connected to the second end of the switch T0 of the trigger unit 113, the second end of the switch T11 being electrically connected to the control end of the first output switch T3, and the control end of the switch T11 receiving the second voltage signal. The first end of the switch T0 is electrically connected to the output end of the previous shift register 110. The trigger unit 113 further includes a switch T5, wherein the control end of switch T5 is electrically connected to the control end of switch T0, and the control end of switch T5 and the control end of switch T0 respectively receive the first clock signal CK, and the first end of switch T5 is configured to receive the second voltage signal. The second control unit 115 includes switches T6, T7, T8, and T9, wherein the control end of switch T6 is electrically connected to the second end of switch T0, the first end of switch T6 is electrically connected to the control end of switch T0, the first end of switch T6 is configured to receive the first clock signal CK, the second end of switch T6 is electrically connected to the first end of switch T7, the second end of switch T7 is electrically connected to one plate of capacitor C3 and the control end of switch T8, and the control end of switch T7 is electrically connected to the second end of switch T5. The first end of switch T8 is configured to receive the second clock signal XCK1, and the second end of switch T8 is electrically connected to the other plate of capacitor C3 and the first end of switch T9. The control end of switch T9 is electrically connected to the first end of switch T8. The control end of switch T9 is used to receive the second clock signal XCK1. The second end of switch T9 is electrically connected to the control end of the second output switch T4. The second voltage stabilizing unit 116 includes a switch T10 and a capacitor C2. The first end of switch T10 is electrically connected to one plate of capacitor C2. The first end of switch T10 is used to receive a third voltage signal. The second end of switch T10 is electrically connected to the second end of switch T9, the other plate of capacitor C2, and the control end of the second output switch T4, respectively. The control end of switch T10 is electrically connected to the second end of switch T0 and the first end of switch T11, respectively. In one possible implementation, the positive potential of the third voltage signal is equal to the potential of the high level of the first clock signal CK and the potential of the high level of the second clock signal XCK1.

[0082] Next, taking the example where all switches in the shift register 110 are PMOS, the enable signal output by the shift register 110 is high, the first voltage signal is VGH2, the second voltage signal is VGL, and the third voltage signal is VGH1, the specific working processes of the trigger stage, output stage, and holding stage of the shift register 110 are explained.

[0083] Figure 8 A schematic diagram of three cascaded shift registers 110 provided in an embodiment of the present application. Figure 9 A method for Figure 8 Timing control diagram. Figure 10 A method for Figure 8 Timing control diagram. Among them, Figure 9 and Figure 10 The trigger stage, output stage and holding stage are for the i-th stage shift register.

[0084] like Figure 8 to Figure 10 As shown, the triggering phase of the shift register 110 is as follows: the first terminal of switch T0 receives a high level signal, and the first clock signal CKCK provides a low level signal (i.e., a valid signal) at the beginning of the third period. At this time, switches T0 and T5 are turned on, and the high level signal is written to the control terminal of the first output switch T3, the control terminal of switch T6, and the control terminal of the first switch T1, causing the first output switch T3, switch T6, and the first switch T1 to be turned off. Switch T5 is turned on, causing VGL to be written to the control terminal of the second switch T2, and causing the second switch T2 to be turned on. At this time, VGH2 is written to the second plate of the first capacitor C1. Switch T7 is in a normally on state, and VGL is written to the control terminal of switch T8 via switch T7, turning on switch T8. During the third period, XCK1 provides a high level signal, and the high level of XCK1 is written to the corresponding plate of capacitor C3 and the control terminal of switch T9. At this time, switch T9 is in an off state. Due to the presence of the first capacitor C1 and the capacitor C3, during the third time period, when the CK signal begins to provide an invalid signal (i.e., a high-level signal), the first output unit 111 is still in the off state, and the switch T8 is still in the on state. Due to the presence of the capacitor C2 in the second voltage stabilizing unit 116, the potential of the control terminal of the second output switch T4 still causes the second output switch T4 to be in the off state. Therefore, during the third time period, the shift register 110 does not output a signal to the outside. From the fourth time period to the fifth time period, the shift register 110 of the previous stage still outputs a high level to the outside. Therefore, the fourth time period and the fifth time period still belong to the triggering stage of the shift register 110. The specific working process thereof refers to the third time period and is not described in detail here.

[0085] like Figure 9 to Figure 10As shown, during the output phase of the shift register unit, at the beginning of the fourth period, XCK1 begins providing a low-level signal (i.e., a valid signal). At this time, T9 turns on, and the VGL signal is written to the control terminal of the second output switch T4. The second output switch T4 then turns on, and the second output switch T4 outputs VGH1. Since the fourth and fifth periods are the trigger phase of the shift register 110, the fifth and sixth periods still belong to the output phase of the shift register 110. The specific operation process is similar to that of the fourth period and is not described here.

[0086] like Figure 9 to Figure 10 As shown, during the hold phase of shift register 110, at the start of the seventh period, the input signal to shift register 110 becomes low, and CK begins providing a low-level signal. At this point, switches T0, T5, and T10 are turned on. Since switch T0 is turned on, the input signal is written to the control terminal of switch T6, the control terminal of first switch T1, and the control terminal of first output switch T3. The input signal turns on switches T6, T1, and T3, and switches T10 on. VGH1 is written to the control terminal of second output switch T4, turning off second output switch T4. At this point, first output switch T3 outputs VGL. During the seventh period, when CK begins to provide an inactive signal (i.e., a high-level signal), switches T0 and T5 are turned off. The first capacitor C1 maintains the potential of the first output switch T3 at a relatively low level, thereby maintaining the first output switch T3 in the on state. At this time, switch T6 remains in the on state due to its internal parasitic capacitance. The high-level signal of CK is written to the control terminals of switch T8 and second switch T2. Consequently, switches T8 and T2 are turned off, and the XCK1 signal cannot be transmitted to the control terminal of second output switch T4. The hold phase of shift register 110 continues until trigger unit 113 receives a high level again.

[0087] During the hold phase of the shift register 110, the first switch T1 is always in the on state. Therefore, the high level and the low level of the first signal are frequently written to the second plate of the first capacitor C1. The significance of this is that the high level of the first signal can create a stable voltage difference between the two plates of the first capacitor C1. This stable voltage difference can cause the potential of the first plate of the first capacitor C1 to tilt downward when the first signal provides a low level to the second plate of the first capacitor C1, thereby maintaining the on state of the first output switch T3.

[0088] Figure 11 A schematic diagram of a shift register 110 in the prior art is shown. Figure 8 、 Figure 9 、 Figure 10 and Figure 11It can be known that the VGH2 voltage of the XCK2 is lower than the high level of the CK, so that the potential is lower when the second plate of the first capacitor C1 is reset to VGH2, and then the potential is higher than VGL1 when the XCK2 jumps to VGL2, and the voltage difference of VGH2-VGL2 is obviously smaller than VGH1-VGL1, and the charge and discharge of the first capacitor C1 is obviously reduced. Therefore, the shift register circuit provided in the embodiment of the present application reduces the power consumption of the first capacitor C1 in the holding stage by reducing the potential variation range of the second plate of the first capacitor C1, and finally reduces the power consumption of the entire shift register circuit 100.

[0089] In an embodiment of the present application, the first signal transmitted by the first signal line 120 in the holding stage is a clock signal. The first signal line 120 includes a first sub-signal line 121 and a second sub-signal line 122, the first sub-signal line 121 is used to transmit a first sub-clock signal XCK2 in the holding stage, and the second sub-signal line 122 is used to transmit a second sub-clock signal XCK2' in the holding stage, the first sub-clock signal XCK2 and the second sub-clock signal XCK2' are asynchronous signals. In the two shift registers 110 cascaded adjacently, the first end of the first switch T1 of one shift register 110 is electrically connected to the first sub-signal line 121, and the first end of the first switch T1 of the other shift register 110 is electrically connected to the second sub-signal line 122.

[0090] In the two shift registers 110 cascaded adjacently, the first end of the first switch T1 of one shift register 110 is electrically connected to the first sub-signal line 121, and the first end of the first switch T1 of the other shift register 110 is electrically connected to the second sub-signal line 122, which is convenient to implement and helps to reduce the implementation difficulty and save costs. Therefore, the connection of the two shift registers 110 cascaded adjacently to different sub-signal lines can reduce the implementation difficulty of the overall circuit while ensuring the normal stage transmission of the shift register circuit 100.

[0091] In one possible implementation, the first clock signal CK is asynchronous with the second clock signal XCK1. When the first clock signal CK provides a valid signal, the second clock signal XCK1 provides an inactive signal, and when the second clock signal XCK1 provides a valid signal, the first clock signal CK provides an inactive signal. When the first clock signal CK provides a valid signal, the second sub-clock signal XCK2' provides a valid signal; when the first clock signal CK provides an inactive signal, the second sub-clock signal XCK2' provides an inactive signal. When the second clock signal XCK1 provides a valid signal, the first sub-clock signal XCK2 provides a valid signal; when the second clock signal XCK1 provides an inactive signal, the first sub-clock signal XCK2 provides an inactive signal. The high level of the first sub-clock signal XCK2 is equal to the high level of the second sub-clock signal XCK2', and the low level of the first sub-clock signal XCK2 is equal to the low level of the second sub-clock signal XCK2'.

[0092] In one possible implementation, the high level of the first clock signal CK is equal to the high level of the second clock signal XCK1, and the low level of the first clock signal CK is equal to the low level of the second clock signal XCK1. The high level of the first clock signal CK is equal to the larger of the second voltage signal and the third voltage signal, and the low level of the first clock signal CK is equal to the smaller of the second voltage signal and the third voltage signal. For example, if the voltage value of the second voltage signal is less than the voltage value of the third voltage signal, the high level of the first clock signal CK is the voltage value of the third voltage signal, and the low level of the first clock signal CK is the voltage value of the second voltage signal.

[0093] In one embodiment of the present application, the second difference is greater than 2*|Vth|, where |Vth| is the absolute value of the threshold voltage of the first switch T1 .

[0094] |Vth| is the absolute value of the threshold voltage of the first switch T1, that is, the absolute value of the threshold drive voltage of the first switch T1. To ensure that the first output switch T3 can still output the VGL voltage, it is necessary to ensure that VGH2 - VGL2 > 2|Vth|. Specifically, the initial potential of the N1 node is higher than VGL by |Vth|. To ensure that the node N1 is at least |Vth| lower than VGL after coupling through C2, the coupling voltage difference must be at least 2|Vth|. Typically, Vth = -1.5V to -3V, so VGH2 - VGL2 > (3 to 6)V.

[0095] See also Figure 8In one embodiment of the present application, the first signal line 120 is also used to transmit a second signal in the trigger phase of the shift register 110 and / or the output phase of the shift register 110, the second signal jumps between a high level and a low level, and the absolute value of the difference between the high level and the low level of the second signal is a third difference, and the third difference is greater than the second difference.

[0096] In this embodiment, the third difference being greater than the second difference means that a larger voltage difference occurs across the second plate of the first capacitor C1 during the triggering phase of the shift register 110 and / or the output phase of the shift register 110. Although the voltage difference is larger, the voltage difference is stable. This larger voltage difference can better keep the first output unit 111 in the off state during the triggering phase of the shift register 110 and / or the output phase of the shift register 110.

[0097] In one possible implementation, the third difference is equal to the first difference. For example, the high level of the second signal is equal to the high level of the first clock signal CK, and the low level of the second signal is equal to the low level of the first clock signal CK. The third difference being equal to the first difference can effectively ensure that the first output unit 111 is in the off state during the trigger phase of the shift register 110 and / or the output phase of the shift register 110.

[0098] In one possible implementation, the third difference is smaller than the first difference and greater than the second difference. This ensures that the first output unit 111 is in an off state during the triggering phase of the shift register 110 and / or the output phase of the shift register 110, while also reducing the power consumption of the first capacitor C1.

[0099] See also Figure 9 In one embodiment of the present application, the first signal line 120 is also used to transmit the first signal in the trigger phase of the shift register 110 and / or the output phase of the shift register 110 .

[0100] During the triggering phase of the shift register 110 and / or the output phase of the shift register 110, the first signal line 120 is used to transmit the first signal, which can minimize the power consumption of the first capacitor C1 while ensuring normal transmission of the shift register circuit 100, thereby reducing the overall power consumption of the shift register circuit 100.

[0101] See also Figure 7 to Figure 9In one embodiment of the present application, the shift register 110 further includes a second output unit 117. The first end of the first output unit 111 is electrically connected to the second signal line, and the second end of the first output unit 111 is used to output the second voltage signal transmitted by the second signal line during the output phase. The first end of the second output unit 117 is electrically connected to the third signal line, and the second end of the second output unit 117 is used to output the third voltage signal transmitted by the third signal line during the output phase. The high level of the first signal is less than the larger one of the second voltage signal and the third voltage signal, and / or the low level of the first signal is greater than the smaller one of the second voltage signal and the third voltage signal. The second end of the first output unit 111 is electrically connected to the second end of the second output unit 117.

[0102] In this embodiment, the high level of the first signal is less than the larger one of the second voltage signal and the third voltage signal, and / or the low level of the first signal is greater than the smaller one of the second voltage signal and the third voltage signal. On the one hand, this ensures that the first difference is less than the second difference, and on the other hand, it does not affect the normal level transmission function of the shift register circuit 100.

[0103] In one embodiment of the present application, the high level of the first signal is lower than the high level of the first clock signal CK, and / or the low level of the first signal is higher than the low level of the first clock signal CK.

[0104] In this implementation, the high level of the first signal is less than the high level of the first clock signal CK; and / or the low level of the first signal is greater than the low level of the first clock signal CK. This ensures that the first difference is less than the second difference while also ensuring normal stage transfer of the shift register circuit 100. Therefore, this implementation reduces the power consumption of the circuit without affecting the operating performance of the shift register circuit 100.

[0105] Figure 12 A display panel 200 is provided in an embodiment of the present application.

[0106] like Figure 12 As shown, the present application further provides a display panel 200, which includes the shift register circuit 100 provided by any of the aforementioned embodiments. The shift register circuit 100 provided by any of the embodiments can effectively reduce the power consumption of the display panel 200 during display.

[0107] Figure 13 A display device 300 is provided in an embodiment of the present application.

[0108] like Figure 13As shown, the present application further provides a display device 300, which includes the display panel 200 provided in the aforementioned embodiment. The display device 300 can be a computer, a mobile phone, a smart electronic product, a terminal device, etc. The use of the display panel 200 provided in the aforementioned embodiment can enable the display device 300 to have lower power consumption during display, thereby achieving energy conservation.

[0109] In this specification, reference can be made to the same or similar parts between the various embodiments. In particular, for the device embodiment and the terminal embodiment, since they are basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the description in the method embodiment.

Claims

1. A shift register circuit, characterized in that: The invention comprises a plurality of cascaded shift registers, wherein the shift registers receive a first clock signal to implement a shift function, and the shift registers include: a first output unit, configured to be turned on during a holding phase of the shift register and to continuously output a non-enable signal during the holding phase; a first voltage stabilizing unit, electrically connected to the first output unit and configured to maintain the first output unit in an on state during the hold phase; the first voltage stabilizing unit comprising a first capacitor, a first plate of the first capacitor electrically connected to the first output unit, and a second plate of the first capacitor configured to receive a first signal during the hold phase of the shift register, the first signal transitioning between a high level and a low level; The absolute value of the difference between the high level and the low level of the first clock signal is a first difference, the absolute value of the difference between the high level and the low level of the first signal is a second difference, and the first difference is greater than the second difference.

2. The shift register circuit according to claim 1, wherein: The first voltage stabilizing unit further includes: a first switch; a first end of the first switch is electrically connected to a first signal line, the first signal line is used to transmit the first signal in the holding phase; a second end of the first switch is electrically connected to the second plate of the first capacitor.

3. The shift register circuit according to claim 2, wherein: The control end of the first switch is electrically connected to the first plate of the first capacitor.

4. The shift register circuit according to claim 2, wherein: The first signal transmitted by the first signal line during the holding phase is a clock signal; The first signal line includes a first sub-signal line and a second sub-signal line, the first sub-signal line is used to transmit a first sub-clock signal during the holding phase, and the second sub-signal line is used to transmit a second sub-clock signal during the holding phase, and the first sub-clock signal and the second sub-clock signal are asynchronous signals; In two adjacent cascaded shift registers, the first end of the first switch of one shift register is electrically connected to the first sub-signal line, and the first end of the first switch of the other shift register is electrically connected to the second sub-signal line.

5. The shift register circuit according to claim 2, wherein: The first voltage stabilizing unit also includes: a second switch; the first end of the second switch is used to receive a first voltage signal, and the second end of the second switch is electrically connected to the second plate of the first capacitor; the second switch is used to write the first voltage signal into the second plate of the first capacitor when a signal is written to the control end of the first output unit.

6. The shift register circuit according to claim 2, wherein: The second difference is greater than 2*|Vth|, where |Vth| is an absolute value of a threshold voltage of the first switch.

7. The shift register circuit according to claim 2, wherein: The first signal line is further used to transmit the first signal in a triggering phase and / or an output phase.

8. The shift register circuit according to claim 1, wherein: The shift register further includes a second output unit; a first end of the first output unit is electrically connected to the second signal line, and a second end of the first output unit is used to output the second voltage signal transmitted by the second signal line during the output phase; a first end of the second output unit is electrically connected to the third signal line, and a second end of the second output unit is used to output the third voltage signal transmitted by the third signal line during the output phase; The high level of the first signal is smaller than the larger one of the second voltage signal and the third voltage signal, and / or the low level of the first signal is larger than the smaller one of the second voltage signal and the third voltage signal.

9. The shift register circuit according to any one of claims 1 to 8, wherein: The high level of the first signal is lower than the high level of the first clock signal; and / or the low level of the first signal is higher than the low level of the first clock signal.

10. A display panel, characterized in that: The display panel includes the shift register circuit according to any one of claims 1 to 9.

11. A display device, characterized in that: The display device includes the display panel according to claim 10.

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