Scan signal line driving circuit and display device having the same

Abstract

The present application realizes reduction of power consumption and stabilization of operation of a gate driver. A thin film transistor (T5) is provided in a unit circuit of each stage constituting a shift register, and has a control terminal to which one of a plurality of gate clock signals is applied, a first conduction terminal connected to a third node (N3), and a second conduction terminal to which a direct current power supply voltage of low level is applied. The third node (N3) is connected to a control terminal of a thin film transistor (T4) for making a potential of a second node (N2) (a node connected to a control terminal of a thin film transistor (T10) for making a potential of an output terminal low) high. A gate clock signal applied to a control terminal of a thin film transistor (T3) for making a potential of the third node (N3) high is changed from high to low, and a gate clock signal applied to the control terminal of the thin film transistor (T5) is changed from low to high.

Description

TECHNICAL FIELD

[0001] The following disclosure relates to a display device, and more particularly to a scan signal line drive circuit provided with a shift register that drives a scan signal line provided to a display section of a display device. BACKGROUND

[0002] Conventionally, a liquid crystal display device provided with a display section including a plurality of source buses (image signal lines) and a plurality of gate buses (scan signal lines) is known. In such a liquid crystal display device, a pixel formation section that forms a pixel is provided at an intersection of a source bus and a gate bus. Each pixel formation section includes a thin film transistor (TFT) that is a switching element, a pixel capacitor that holds a pixel voltage value, and the like, in which a gate terminal thereof is connected to a gate bus through a corresponding intersection and a source terminal thereof is connected to a source bus through the intersection. In the liquid crystal display device, a gate driver (scan signal line drive circuit) that drives the gate buses and a source driver (image signal line drive circuit) that drives the source buses are also provided.

[0003] An image signal that indicates a pixel voltage value is transmitted through a source bus. However, each source bus cannot transmit image signals that indicate a plurality of lines of pixel voltage values at once (simultaneously). Therefore, writing (charging) of the image signals to pixel capacitors provided in a plurality of pixel formation sections in the display section is performed in order by line. In order to achieve this, the gate driver includes a shift register composed of a plurality of stages, so that a plurality of gate buses are sequentially selected every predetermined period. Further, by sequentially outputting an active scan signal from the plurality of stages, writing of the image signals to the pixel capacitors is sequentially performed by line as described above.

[0004] However, in the past, the gate driver was mounted in the form of an integrated circuit (IC) chip on a peripheral portion of a substrate that constitutes a liquid crystal panel. However, in recent years, cases in which the gate driver is directly formed on the substrate have increased. Such a gate driver is referred to as a "monolithic gate driver".

[0005] Further, hereinafter, a circuit that constitutes each stage of the shift register in the gate driver is referred to as a "unit circuit". In addition, with respect to a thin film transistor of an n-channel type, the side in which the potential is higher between the drain and the source is referred to as the drain, but in the thin film transistor in the unit circuit described below, there are cases in which the drain and the source are switched during operation. Therefore, hereinafter, one of the two terminals that functions as the drain or the source is referred to as a "first conduction terminal", and the other terminal is referred to as a "second conduction terminal". In addition, a terminal that functions as the gate of the thin film transistor is referred to as a "control terminal".

[0006] Figure 22is a circuit diagram showing one configuration example of a conventional unit circuit 9. Further, it is assumed that Figure 22 The unit circuit 9 shown in FIG. 9 is a unit circuit 9(n) of the nth stage. The unit circuit 9 has nine thin film transistors Tl to T4, T6 to TlO and one capacitor (capacitive element) C. In addition, the unit circuit 9 has five input terminals 21 to 24, 26 and one output terminal 29. The input terminal 21 is applied with a set signal S which is an output signal Q(n-4) from a unit circuit of a stage preceding the fourth stage. The input terminal 22 is applied with a reset signal R which is an output signal Q(n+6) from a unit circuit of a stage succeeding the sixth stage. The input terminal 23 is applied with a first clock signal CKl which is one of a plurality of gate clock signals applied to a gate driver. Here, it is assumed that the plurality of gate clock signals are eight-phase clock signals. The input terminal 24 is applied with a second clock signal CK2 which is one of the plurality of gate clock signals. The phase of the second clock signal CK2 is advanced by 45 degrees from the phase of the first clock signal CKl. The input terminal 26 is applied with a direct current power supply voltage VSS of a low level. The output terminal 29 outputs an output signal Q(n). The output signal Q(n) is applied as a scan signal to a corresponding gate bus line.

[0007] The second conduction terminal of the thin film transistor Tl, the first conduction terminal of the thin film transistor T2, the control terminal of the thin film transistor T6, the control terminal of the thin film transistor T7, the control terminal of the thin film transistor T8, the first conduction terminal of the thin film transistor T9 and one end of the capacitor C are connected to each other via the first node Nl. The second conduction terminal of the thin film transistor T4, the first conduction terminal of the thin film transistor T7, the control terminal of the thin film transistor T9 and the control terminal of the thin film transistor TlO are connected to each other via the second node N2. The second conduction terminal of the thin film transistor T3, the control terminal of the thin film transistor T4 and the first conduction terminal of the thin film transistor T6 are connected to each other via the third node N3.

[0008] Next, the operation of the unit circuit 9 will be described with reference to a signal waveform diagram shown in FIG. 10. Figure 23 During a period in which the liquid crystal display device having the unit circuit 9 operates, the first clock signal CKl and the second clock signal CK2 having a duty ratio of substantially 50% are supplied to the unit circuit 9.

[0009] During a period until time t91, the set signal S, the output signal Q(n) and the reset signal R are maintained at a low level. In addition, the potential of the first node Nl is maintained at a low level, the potential of the second node N2 alternately appears at a high level and a low level every prescribed period, and the potential of the third node N3 is maintained at a high level. However, as to the potential of the third node N3, a relatively high high level and a relatively low low level alternately appear every prescribed period.

[0010] When time t91 is reached, the set signal S changes from low to high. For example... Figure 22 As shown, thin-film transistor T1 becomes diode-connected. Therefore, with the pulse of the setting signal S, thin-film transistor T1 becomes conductive, and the potential of the first node N1 rises. Consequently, thin-film transistors T6, T7, and T8 become conductive. When thin-film transistor T6 becomes conductive, the potential of the third node N3 becomes low. Furthermore, during the period from time t91 to time t92, since the first clock signal CK1 is low, even if thin-film transistor T8 becomes conductive, the output signal Q(n) remains low.

[0011] When time t92 is reached, the first clock signal CK1 changes from low to high. At this time, since the thin-film transistor T8 is in the on state, the potential of the output terminal 29 rises as the potential of the input terminal 23 rises. Here, as... Figure 22 As shown, since capacitor C is positioned between the first node N1 and the output terminal 29, the potential of the first node N1 also rises (the first node N1 becomes a boost state) as the potential of the output terminal 29 rises. As a result, a large voltage is applied to the control terminal of the thin-film transistor T8, and the potential of the output signal Q(n) rises to a level sufficient to select the gate bus connected to the output terminal 29. Furthermore, during the period from time t92 to time t93, the reset signal R remains low, and the potential of the second node N2 also remains low. Therefore, during this period, thin-film transistors T2 and T10 remain in the off state, and the potential of the first node N1 and the potential of the output signal Q(n) (the potential of the output terminal 29) do not decrease.

[0012] When time t93 is reached, the first clock signal CK1 changes from high to low. Consequently, the potential at input terminal 23 decreases, and the potential at output terminal 29 also decreases. That is, the potential of the output signal Q(n) becomes low. Additionally, the potential of the first node N1 decreases through capacitor C.

[0013] When time t94 is reached, the reset signal R changes from low to high. This turns thin-film transistor T2 on, and the potential of the first node N1 becomes low. During the period after time t94, the same operation occurs as before time t91.

[0014] By performing the operations described above through each unit circuit 9, the multiple gate buses provided in the liquid crystal display device are sequentially selected, and image signals are written to the pixel capacitors line by line. Furthermore, regarding each unit circuit, during the period when the potential of the first node N1 is maintained at a high level (in... Figure 23The period from time t91 to time t94 in the illustrated example) is called a "selection period", and a period other than the selection period is called a "non-selection period".

[0015] However, in Figure 22 The unit circuit 9 of the illustrated configuration is provided with a stabilizing circuit 91 for reliably maintaining the potential of the output terminal 29 at a low level in the non-selection period. The stabilizing circuit 91 includes a third node N3 connected to the control terminal of a thin film transistor T4 for controlling the potential of a second node (a node connected to the control terminal of a thin film transistor T10 for controlling the potential of the output terminal 29) N2. By appropriately controlling the potentials of the second node N2 and the third node N3, the states of the thin film transistor T10 and the thin film transistor T4 are appropriately controlled, and the operation of the unit circuit 9 is stabilized. In Figure 23 In the illustrated example, the thin film transistor T10 becomes in the on state every prescribed period by repeating the change from the low level to the high level and the change from the high level to the low level of the potential of the second node N2 in the non-selection period. Thereby, in the non-selection period, for example, even if the potential of the output terminal 29 fluctuates due to noise, the potential of the output terminal 29 is pulled down to the low level every prescribed period.

[0016] The configuration of the unit circuit within the shift register provided in the display device is disclosed, for example, in Japanese Patent Application Publication No. 2019-045673, Japanese Patent Application Publication No. 2014-063164, Japanese Patent Application Publication No. 2010-262296, Japanese Patent Application Publication No. 2013-142899, and Japanese Patent Application Publication No. 2010-218673. SUMMARY

[0017] Technical problem to be solved by the invention

[0018] Regarding the operation of the unit circuit 9, in Figure 23 In the illustrated example, in the non-selection period, during the period in which the second clock signal CK2 is at the high level, the thin film transistor T3 becomes in the on state, the third node N3 is maintained at the high level, and thus the thin film transistor T4 is maintained in the on state, and therefore the potential of the second node N2 becomes the high level. In the non-selection period, if the second clock signal CK2 changes from the high level to the low level, the thin film transistor T3 becomes in the off state, and the third node N3 becomes in the floating state, but the potential of the second node N2 becomes the low level along with the decrease in the potential of the input terminal 24.

[0019] As described above, according to the configuration of the existing unit circuit 9, the charging and discharging of the second node N2 is repeated during the non-selection period. This becomes a main cause of an increase in power consumption of the gate driver. In addition, regarding the thin film transistor T10 for controlling the potential of the output terminal 29, since the change from the on state to the off state and the change from the off state to the on state are frequently repeated, a case where the pull-down function of introducing the potential of the output terminal 29 to the low level cannot function normally occurs. Similarly, regarding the thin film transistor T9 for controlling the potential of the first node N1, since the change from the on state to the off state and the change from the off state to the on state are frequently repeated, a case where the pull-down function of introducing the potential of the first node N1 to the low level cannot function normally also occurs.

[0020] Therefore, the following disclosure aims at achieving a reduction in power consumption and stabilization of operation of a gate driver (particularly, a monolithic gate driver).

[0021] Solution to the problem

[0022] (1) A scan signal line driving circuit according to some embodiments of the present application is for driving a plurality of scan signal lines, the scan signal line driving circuit including a shift register that operates based on a plurality of clock signals and is constituted by a plurality of stages corresponding one-to-one to the plurality of scan signal lines,

[0023] A unit circuit that constitutes each stage included in the shift register includes:

[0024] a first node;

[0025] a second node;

[0026] a third node;

[0027] a first output node that outputs an output signal to a corresponding scan signal line;

[0028] a first output control transistor having a control terminal connected to the first node, a first conduction terminal to which one of the plurality of clock signals is applied, and a second conduction terminal connected to the first output node;

[0029] a first node pull-up section for causing the potential of the first node to become an on level based on a set signal;

[0030] a first node pull-down section for causing the potential of the first node to become an off level based on a reset signal;

[0031] a stabilization transistor having a control terminal connected to the second node, a first conduction terminal connected to the first node or the first output node, and a second conduction terminal to which an off level potential is applied; and

[0032] a stabilization circuit connected to the second node, the stabilization circuit including:

[0033] a second node pull-up transistor having a control terminal connected to the third node, a first conduction terminal to which one of the plurality of clock signals is applied, and a second conduction terminal connected to the second node;

[0034] a first second node pull-down transistor having a control terminal connected to the first node, a first conduction terminal connected to the second node, and a second conduction terminal to which a potential of an off level is applied;

[0035] a first third node pull-down transistor having a control terminal connected to the first node, a first conduction terminal connected to the third node, and a second conduction terminal to which a potential of an off level is applied;

[0036] a third node pull-up transistor having a control terminal to which one of the plurality of clock signals is applied, and a first conduction terminal, and a second conduction terminal connected to the third node; and

[0037] a second third node pull-down transistor having a control terminal to which one of the plurality of clock signals is applied, a first conduction terminal connected to the third node, and a second conduction terminal to which a potential of an off level is applied,

[0038] at a time when the clock signal applied to the control terminal of the third node pull-up transistor changes from an on level to an off level, the clock signal applied to the control terminal of the second third node pull-down transistor changes from an off level to an on level.

[0039] (2) In addition, the scan signal line drive circuit based on some embodiments of the present application includes the configuration of (1) described above, and the set signal is an output signal output from a first output node of a unit circuit that constitutes a stage earlier than the present stage,

[0040] the reset signal is an output signal output from a first output node of a unit circuit that constitutes a stage later than the present stage.

[0041] (3) In addition, the scan signal line drive circuit based on some embodiments of the present application includes the configuration of (1) described above, and the unit circuit includes:

[0042] a second output node that outputs another stage control signal, the another stage control signal being used to control the operation of the unit circuit that constitutes a stage earlier than the present stage and the unit circuit that constitutes a stage later than the present stage; and

[0043] a second output control transistor having a control terminal connected to the first node, a first conduction terminal to which one of the plurality of clock signals is applied, and a second conduction terminal connected to the second output node, the clock signal applied to the first conduction terminal of the first output control transistor and the clock signal applied to the first conduction terminal of the second output control transistor being the same clock signal,

[0044] the set signal is an other-stage control signal output from a second output node of a unit circuit constituting a stage preceding the present stage,

[0045] the reset signal is an other-stage control signal output from a second output node of a unit circuit constituting a stage succeeding the present stage.

[0046] (4) In addition, the scan signal line drive circuit according to some embodiments of the present application includes the configuration of (1) described above, and the first node pull-up section includes a first node pull-up transistor having a control terminal to which the set signal is applied and a first conduction terminal, and a second conduction terminal connected to the first node.

[0047] (5) In addition, the scan signal line drive circuit according to some embodiments of the present application includes the configuration of (1) described above, and the first node pull-down section includes a first node pull-down transistor of the first kind having a control terminal to which the reset signal is applied, a first conduction terminal connected to the first node, and a second conduction terminal to which a potential of an off level is applied.

[0048] (6) In addition, the scan signal line drive circuit according to some embodiments of the present application includes the configuration of (1) described above, and the unit circuit includes a first node pull-down transistor of the second kind as the stabilization transistor, the first node pull-down transistor of the second kind having a first conduction terminal connected to the first node.

[0049] (7) In addition, the scan signal line drive circuit according to some embodiments of the present application includes the configuration of (1) described above, and the unit circuit includes a first output node pull-down transistor as the stabilization transistor, the first output node pull-down transistor having a first conduction terminal connected to the first output node.

[0050] (8) In addition, the scan signal line drive circuit according to some embodiments of the present application includes the configuration of (1) described above, and the unit circuit includes a first node pull-down transistor of the second and a first output node pull-down transistor as the stabilizing transistor, the first node pull-down transistor of the second having a first conduction terminal connected to the first node, and the first output node pull-down transistor having a first conduction terminal connected to the first output node.

[0051] (9) In addition, the scan signal line drive circuit according to some embodiments of the present application includes the configuration of (1) described above, and the unit circuit includes a second node pull-down transistor of the second, the second node pull-down transistor of the second having a control terminal to which the set signal is applied, a first conduction terminal connected to the second node, and a second conduction terminal to which a potential of an off level is applied.

[0052] (10) In addition, the scan signal line drive circuit according to some embodiments of the present application includes the configuration of (1) described above, and P is set to a natural number, the plurality of clock signals are P-phase clock signals,

[0053] The phase of the clock signal applied to the control terminal of the third node pull-up transistor is advanced by (360 / P) degrees from the phase of the clock signal applied to the first conduction terminal of the first output control transistor.

[0054] (11) In addition, the scan signal line drive circuit according to some embodiments of the present application includes the configuration of (1) described above, and the clock signal applied to the control terminal of the third node pull-up transistor and the clock signal applied to the first conduction terminal of the first output control transistor are the same clock signal.

[0055] (12) In addition, the scan signal line drive circuit according to some embodiments of the present application includes the configuration of (1) described above, and the channel length of the third node pull-up transistor is longer than the channel length of any one of the first output control transistor, the stabilizing transistor, the second node pull-up transistor, the second node pull-down transistor of the first, the third node pull-down transistor of the first, and the third node pull-down transistor of the second.

[0056] (13) In addition, the scan signal line drive circuit according to some embodiments of the present application is for driving a plurality of scan signal lines, and includes a shift register that operates based on a plurality of clock signals and is configured by a plurality of stages corresponding one-to-one to the plurality of scan signal lines,

[0057] The unit circuit that configures each stage included in the shift register includes:

[0058] a first node;

[0059] a second node;

[0060] a third node;

[0061] a first output node that outputs an output signal to a corresponding scan signal line;

[0062] a first output control transistor having a control terminal connected to the first node, a first conduction terminal to which one of the plurality of clock signals is applied, and a second conduction terminal connected to the first output node;

[0063] a first node pull-up section for causing a potential of the first node to become an on level based on a set signal;

[0064] a first node pull-down section for causing the potential of the first node to become an off level based on a reset signal;

[0065] a stabilization transistor having a control terminal connected to the second node, a first conduction terminal connected to the first node or the first output node, and a second conduction terminal to which a potential of the off level is applied; and

[0066] a stabilization circuit connected to the second node, the stabilization circuit including:

[0067] a second node pull-up transistor having a control terminal connected to the third node, a first conduction terminal to which one of the plurality of clock signals is applied, and a second conduction terminal connected to the second node;

[0068] a second node pull-down transistor having a control terminal connected to the first node, a first conduction terminal connected to the second node, and a second conduction terminal to which a potential of the off level is applied;

[0069] a first third node pull-down transistor having a control terminal connected to the first node, a first conduction terminal connected to the third node, and a second conduction terminal to which a potential of the off level is applied;

[0070] a third node pull-up transistor having a control terminal to which one of the plurality of clock signals is applied and a first conduction terminal, and a second conduction terminal connected to the third node; and

[0071] a second third node pull-down transistor having a control terminal connected to the third node and a first conduction terminal, and a second conduction terminal to which one of the plurality of clock signals is applied,

[0072] The clock signal applied to the control terminal of the third node pull-up transistor and the clock signal applied to the second conduction terminal of the second 2 third node pull-down transistor are the same clock signal.

[0073] (14) In addition, the scan signal line driving circuit based on some embodiments of the present application includes the configuration of (13) described above, and the set signal is an output signal output from a first output node of a unit circuit constituting a stage prior to the present stage,

[0074] The reset signal is an output signal output from a first output node of a unit circuit constituting a stage subsequent to the present stage.

[0075] (15) In addition, the scan signal line driving circuit based on some embodiments of the present application includes the configuration of (13) described above, and the unit circuit includes:

[0076] a second output node that outputs another stage control signal for controlling the operation of the unit circuit constituting the stage prior to the present stage and the unit circuit constituting the stage subsequent to the present stage; and

[0077] a second output control transistor having a control terminal connected to the first node, a first conduction terminal to which one of the plurality of clock signals is applied, and a second conduction terminal connected to the second output node,

[0078] the clock signal applied to the first conduction terminal of the first output control transistor and the clock signal applied to the first conduction terminal of the second output control transistor are the same clock signal,

[0079] The set signal is another stage control signal output from a second output node of a unit circuit constituting a stage prior to the present stage, and the reset signal is another stage control signal output from a second output node of a unit circuit constituting a stage subsequent to the present stage.

[0080] (16) In addition, the display device based on some embodiments of the present application includes:

[0081] a substrate;

[0082] a plurality of image signal lines formed on the substrate;

[0083] a plurality of scan signal lines formed on the substrate so as to cross the plurality of image signal lines;

[0084] a plurality of pixel formation portions formed on the substrate so as to correspond to the intersection points of the plurality of image signal lines and the plurality of scan signal lines, respectively;

[0085] an image signal line drive circuit for driving the plurality of image signal lines; and a scan signal line drive circuit according to any one of (1) to (15) above for driving the plurality of scan signal lines and formed on the substrate.

[0086] (17) Further, a display device based on some embodiments of the present application includes the configuration of (16) above, and the regions on the substrate include:

[0087] a display region in which the plurality of pixel formation portions are formed;

[0088] a shift register region in which the shift register is formed; and

[0089] a stem wiring region in which a plurality of clock signal stem wirings that transmit the plurality of clock signals are formed,

[0090] the shift register region is provided between the display region and the stem wiring region, and for each unit circuit, a clock signal branch wiring is provided, one end of the clock signal branch wiring is connected to one of the plurality of clock signal stem wirings, and the other end is connected to the control terminal of the second third node pull-down transistor.

[0091] (18) Further, a display device based on some embodiments of the present application includes the configuration of (17) above, and the plurality of image signal lines are formed by a first metal film, the plurality of scan signal lines are formed by a second metal film,

[0092] the plurality of clock signal stem wirings are formed by the first metal film, and the clock signal branch wirings are formed by the second metal film,

[0093] one of the clock signal branch wirings and the plurality of clock signal stem wirings is connected via a contact hole in the stem wiring region.

[0094] (19) Further, a display device based on some embodiments of the present application includes the configuration of (16) above, and the regions on the substrate include:

[0095] a display region in which the plurality of pixel formation portions are formed;

[0096] a shift register region in which the shift register is formed; and

[0097] a stem wiring region in which a plurality of clock signal stem wirings that transmit the plurality of clock signals are formed,

[0098] The shift register region is provided between the display region and the stem wiring region, n is set to a natural number, and a first conduction terminal of the first output control transistor included in a unit circuit of an (n-1)th stage and a control terminal and a first conduction terminal of the third node pull-up transistor included in a unit circuit of an nth stage are connected to the same clock signal branch wiring, one end of the clock signal branch wiring being connected to one of the plurality of clock signal stem wirings.

[0099] Effects of Invention

[0100] According to the scan signal line drive circuit based on some embodiments of the present application, a second third node pull-down transistor is provided in each unit circuit of each stage constituting the shift register, the second third node pull-down transistor having a control terminal to which one of the plurality of clock signals is applied, a first conduction terminal connected to the third node, and a second conduction terminal to which a potential of an off level is applied. Different clock signals (for example, clock signals having a phase shift of 180 degrees) are applied to the control terminal of the third node pull-up transistor for changing the potential of the third node to an on level and the control terminal of the second third node pull-down transistor. Thus, in each unit circuit, during a non-selection period, the potential of the third node repeatedly changes from the off level to the on level and from the on level to the off level. In addition, at the time when the clock signal applied to the control terminal of the third node pull-up transistor changes from the on level to the off level, the clock signal applied to the control terminal of the second node pull-down transistor changes from the off level to the on level. Thus, during the period when the clock signal applied to the control terminal of the third node pull-up transistor is the off level, the potential of the third node is the off level, and the second node pull-up transistor is maintained in an off state. As described above, the potential of the second node is maintained at the on level through the non-selection period. That is, the charging and discharging of the second node are inhibited from being excessively performed. As a result, power consumption is reduced. In addition, since the change of the stable transistor having the control terminal connected to the second node from the on state to the off state and from the off state to the on state during the non-selection period is inhibited, deterioration of the stable transistor is inhibited. Thus, the operation of bringing the potential of the first node or the first output node to the off level is stably performed. As described above, reduction of power consumption and stabilization of operation of the scan signal line drive circuit are achieved.

[0101] According to the scan signal line drive circuit based on the other embodiments of the present application, a second third-node pull-down transistor is provided in the unit circuit of each stage constituting the shift register, and the second third-node pull-down transistor has a control terminal connected to the third node, a first conduction terminal connected to the third node, and a second conduction terminal to which one of the plurality of clock signals is applied. The same clock signal is applied to the control terminal of the third-node pull-up transistor for making the potential of the third node a conduction level and the control terminal of the second third-node pull-down transistor. With the above-described configuration, in each unit circuit, during the non-selection period, the potential of the third node repeats the change from the off level to the conduction level and the change from the conduction level to the conduction level. In this regard, when the clock signal applied to the control terminal of the third-node pull-up transistor changes from the conduction level to the off level, the potential of the third node changes from the conduction level to the off level via the second third-node pull-down transistor. Therefore, during the period in which the clock signal applied to the control terminal of the third-node pull-up transistor is the off level, the potential of the third node is the off level, and the second-node pull-up transistor is maintained in the off state. As described above, the potential of the second node is maintained at the conduction level through the non-selection period. That is, the charging and discharging of the second node are inhibited from being excessively performed. As a result, the power consumption is reduced. In addition, since the change from the on state to the off state and the change from the off state to the on state of the stabilization transistor having the control terminal connected to the second node are inhibited from repeating during the non-selection period, the deterioration of the stabilization transistor is inhibited. Therefore, the operation of bringing the potential of the first node or the first output node to the off level is stably performed. As described above, the reduction of the power consumption and the stabilization of the operation of the scan signal line drive circuit are achieved. BRIEF DESCRIPTION OF DRAWINGS

[0102] Figure 1 FIG. 1 is a circuit diagram showing the configuration of a unit circuit in an embodiment.

[0103] Figure 2 FIG. 2 is a block diagram showing the overall configuration of an active matrix liquid crystal display device according to the embodiment.

[0104] Figure 3 FIG. 3 is a block diagram for explaining the schematic configuration of a gate driver in the embodiment.

[0105] Figure 4 FIG. 4 is a block diagram showing the configuration of a shift register in the gate driver in the embodiment.

[0106] Figure 5 FIG. 5 is a waveform chart of a gate clock signal in the embodiment.

[0107] Figure 6is a signal waveform diagram for explaining the phase relationship between the plurality of gate clock signals in the above-described embodiment.

[0108] Figure 7 is a diagram for explaining the input and output signals of the unit circuit in the above-described embodiment.

[0109] Figure 8 is a signal waveform diagram for explaining the operation of the gate driver in the above-described embodiment.

[0110] Figure 9 is a waveform diagram for explaining the operation of the unit circuit in the above-described embodiment.

[0111] Figure 10 is a diagram for explaining the layout in the above-described embodiment.

[0112] Figure 11 is a diagram for explaining the layout in the above-described embodiment.

[0113] Figure 12 is a circuit diagram showing the configuration of the unit circuit in the first modified example of the above-described embodiment (the configuration of one stage of the shift register).

[0114] Figure 13 is a circuit diagram showing the configuration of the unit circuit in the second modified example of the above-described embodiment (the configuration of one stage of the shift register).

[0115] Figure 14 is a circuit diagram showing the configuration of the unit circuit in the third modified example of the above-described embodiment (the configuration of one stage of the shift register).

[0116] Figure 15 is a circuit diagram showing the configuration of the unit circuit in the fourth modified example of the above-described embodiment (the configuration of one stage of the shift register).

[0117] Figure 16 is a waveform diagram for explaining the operation of the unit circuit in the fourth modified example of the above-described embodiment.

[0118] Figure 17 is a circuit diagram showing the configuration of the unit circuit in the fifth modified example of the above-described embodiment (the configuration of one stage of the shift register).

[0119] Figure 18 is a waveform diagram for explaining the operation of the unit circuit in the fifth modified example of the above-described embodiment.

[0120] Figure 19 is a circuit diagram showing the configuration of the unit circuit in the sixth modified example of the above-described embodiment (the configuration of one stage of the shift register).

[0121] Figure 20 is a view for explaining input and output signals of the unit circuit in the sixth modification of the above-described embodiment.

[0122] Figure 21 is a waveform chart for explaining an operation of the unit circuit in the sixth modification of the above-described embodiment.

[0123] Figure 22 is a circuit diagram showing a configuration of the unit circuit in the related art example (a configuration of one stage of the shift register).

[0124] Figure 23 is a waveform chart for explaining an operation of the unit circuit in the related art example. DETAILED DESCRIPTION

[0125] Hereinafter, an embodiment will be described with reference to the drawings. Note that it is assumed that all the transistors in this embodiment are n-channel thin film transistors, but the embodiment is not limited to this.

[0126] <1. Overall configuration and operation summary>

[0127] Figure 2 is a block diagram showing an overall configuration of an active matrix liquid crystal display device according to an embodiment. The liquid crystal display device includes a display control circuit 100, a gate driver (scanning signal line driver circuit) 200, a source driver (image signal line driver circuit) 300, and a display portion (display region) 400. In this embodiment, a pixel circuit and the gate driver 200 that configure the display portion 400 are integrally formed on one of two substrates (an active matrix substrate) that configure a liquid crystal panel 5. That is, the gate driver 200 in this embodiment is a monolithic gate driver.

[0128] The display unit 400 is provided with multiple (j) source buses (image signal lines) SL(1) to SL(j) and multiple (i) gate buses (scan signal lines) GL(1) to GL(i). Pixel forming units 4, which form pixels, are provided at each intersection of these multiple (j) source buses SL(1) to SL(j) and multiple (i) gate buses GL(1) to GL(i). That is, the display unit 400 includes multiple (i×j) pixel forming units 4. Each pixel forming unit 4 includes: a thin-film transistor (pixel TFT) 40 serving as a switching element, whose gate terminal is connected to a gate bus GL passing through a corresponding intersection and whose source terminal is connected to a source bus SL passing through the intersection; a pixel electrode 41 connected to a second conduction terminal of the thin-film transistor 40; a common electrode 44 and an auxiliary capacitor electrode 45 shared with the aforementioned plurality of pixel forming units 4; a liquid crystal capacitor 42 formed by the pixel electrode 41 and the common electrode 44; and an auxiliary capacitor 43 formed by the pixel electrode 41 and the auxiliary capacitor electrode 45. The liquid crystal capacitor 42 and the auxiliary capacitor 43 constitute a pixel capacitor 46. Furthermore, in Figure 2 Only one pixel forming part 4 is shown in the image.

[0129] The display control circuit 100 receives an image signal DAT transmitted from an external source, as well as a timing signal group TG including a horizontal synchronization signal and a vertical synchronization signal, and outputs a digital image signal DV, a gate control signal GCTL for controlling the operation of the gate driver 200, and a source control signal SCTL for controlling the operation of the source driver 300. That is, the display control circuit 100 controls the operation of the gate driver 200 and the source driver 300. Furthermore, the gate control signal GCTL includes a gate start pulse signal, a clear signal, and a gate clock signal, and the source control signal SCTL includes a source start pulse signal, a source clock signal, and a latch strobe signal.

[0130] The gate driver 200 applies an active scan signal to each gate bus GL repeatedly for a period of one vertical scan, based on the gate control signal GCTL sent from the display control circuit 100. Alternatively, a configuration may be adopted in which the gate driver 200 is present at both one end and the other end of the gate bus GL (i.e., in...). Figure 2 The display unit 400 has a configuration where both the left and right sides are equipped with gate drivers 200. A detailed description of the gate drivers 200 will be given later.

[0131] The source driver 300 applies a driving image signal to each source bus SL(1) to SL(j) based on the digital image signal DV sent from the display control unit 100 and the source control signal SCTL. At this time, in the source driver 300, at the moment the source clock signal pulse is generated, the digital image signal DV, representing the voltage to be applied to each source bus SL, is held sequentially. Then, at the moment the latch strobe signal pulse is generated, the held digital image signal DV is converted into an analog voltage. This converted analog voltage is simultaneously applied as a driving image signal to all source buses SL(1) to SL(j).

[0132] As described above, by applying a driving image signal to the source bus SL(1) to SL(j) and a scan signal to the gate bus GL(1) to GL(i), an image based on image data DAT transmitted from the outside is displayed in the display unit 400.

[0133] <2. Gate Driver>

[0134] Figure 3 This is a block diagram illustrating the schematic configuration of the gate driver 200 in this embodiment. (As shown...) Figure 3 As shown, the gate driver 200 is composed of a shift register 210, which is composed of multiple stages. An i-row × j-column pixel matrix is ​​formed in the display unit 400, but each stage of the shift register 210 is arranged in a manner that corresponds one-to-one with each row of these pixel matrices. That is, the shift register 210 contains i unit circuits 2(1) to 2(i). Furthermore, more specifically, before the first stage and after the i-th stage, for example, every four stages, a unit circuit (i) is provided as a dummy stage. Figure 3 (Not shown in the figure). However, since the dummy level is not directly related to the present invention, its description is omitted. Hereinafter, the configuration and operation of the gate driver 200 will be described in detail.

[0135] <2.1 Overall Structure and Operation of a Shift Register>

[0136] Figure 4 This is a block diagram showing the configuration of the shift register 210 within the gate driver 200. As described above, this shift register 210 includes i unit circuits 2(1) to 2(i). Furthermore, in Figure 4 The diagram shows unit circuits 2(n-3) to 2(n+4) from level (n-3) to level (n+4). Hereinafter, without needing to distinguish between the i unit circuits 2(1) to 2(i), the unit circuits will be labeled with reference numeral 2.

[0137] The shift register 210 is given a gate start pulse signal (in Figure 4 (not shown in the image), clear signal (in)Figure 4 The gate clock signals GCK (GCK1 to GCK8) are supplied to the shift register 210 as the gate control signals GCTL. In addition, a low-level direct-current power supply voltage VSS is supplied to the shift register 210. Figure 5 FIG. 8 is a waveform chart of the gate clock signals GCK1 to GCK8. The gate clock signals GCK1 to GCK8 are generated by the shift register 210. Figure 5 As is apparent from FIG. 8, the gate clock signals GCK1 to GCK8 are 8-phase clock signals, and the duty ratios of all the gate clock signals GCK1 to GCK8 are approximately 50%. In addition, as shown in FIG. 9, the phases of the gate clock signals GCKz (z is 2 to 8) lag behind the phase of the gate clock signal GCK1 (45 x (z - 1)) degrees. Figure 5

[0138] Each unit circuit 2 includes an input terminal that receives any one of the gate clock signals GCK1 to GCK8 as the first clock signal CK1, an input terminal that receives any one of the gate clock signals GCK1 to GCK8 as the second clock signal CK2, an input terminal that receives any one of the gate clock signals GCK1 to GCK8 as the third clock signal CK3, an input terminal that receives the set signal S, an input terminal that receives the reset signal R, an input terminal that receives the low-level direct-current power supply voltage VSS, and an output terminal that outputs the output signal Q.

[0139] In addition, when the gate clock signal input to the unit circuit 2 (n) of the nth stage as the first clock signal CK1 is denoted as GCK (n), the gate clock signal that leads the phase of the gate clock signal GCK (n) by K degrees is denoted as GCK (n - K / 45), and the gate clock signal that lags behind the phase of the gate clock signal GCK (n) by K degrees is denoted as GCK (n + K / 45), the waveforms of the 8-phase gate clock signals are as shown in FIG. 8. In the present embodiment, in the unit circuit 2 (n) of the nth stage, the gate clock signal GCK (n - 1) is input as the second clock signal CK2, and the gate clock signal GCK (n + 3) is input as the third clock signal CK3. In this way, in each unit circuit 2, the phase of the second clock signal CK2 leads the phase of the first clock signal CK1 by 45 degrees, and the phase of the third clock signal CK3 lags behind the phase of the first clock signal CK1 by 135 degrees. Figure 6

[0140] ​​The signals applied to the input terminals of the stages (unit circuits 2) of the shift register 210 are as follows. To the unit circuit 2(n-3) of the (n-3)th stage, the gate clock signal GCK1 is supplied as the first clock signal CK1, the gate clock signal GCK8 is supplied as the second clock signal CK2, and the gate clock signal GCK4 is supplied as the third clock signal CK3. To the unit circuit 2(n-2) of the (n-2)th stage, the gate clock signal GCK2 is supplied as the first clock signal CK1, the gate clock signal GCK1 is supplied as the second clock signal CK2, and the gate clock signal GCK5 is supplied as the third clock signal CK3. To the unit circuit 2(n-1) of the (n-1)th stage, the gate clock signal GCK3 is supplied as the first clock signal CK1, the gate clock signal GCK2 is supplied as the second clock signal CK2, and the gate clock signal GCK6 is supplied as the third clock signal CK3. To the unit circuit 2(n) of the nth stage, the gate clock signal GCK4 is supplied as the first clock signal CK1, the gate clock signal GCK3 is supplied as the second clock signal CK2, and the gate clock signal GCK7 is supplied as the third clock signal CK3. To the unit circuit 2(n+1) of the (n+1)th stage, the gate clock signal GCK5 is supplied as the first clock signal CK1, the gate clock signal GCK4 is supplied as the second clock signal CK2, and the gate clock signal GCK8 is supplied as the third clock signal CK3. To the unit circuit 2(n+2) of the (n+2)th stage, the gate clock signal GCK6 is supplied as the first clock signal CK1, the gate clock signal GCK5 is supplied as the second clock signal CK2, and the gate clock signal GCK1 is supplied as the third clock signal CK3. To the unit circuit 2(n+3) of the (n+3)th stage, the gate clock signal GCK7 is supplied as the first clock signal CK1, the gate clock signal GCK6 is supplied as the second clock signal CK2, and the gate clock signal GCK2 is supplied as the third clock signal CK3. To the unit circuit 2(n+4) of the (n+4)th stage, the gate clock signal GCK8 is supplied as the first clock signal CK1, the gate clock signal GCK7 is supplied as the second clock signal CK2, and the gate clock signal GCK3 is supplied as the third clock signal CK3. Such a configuration is repeated every 8 stages through all the stages of the shift register 210. In addition, as shown in FIG. 6, the gate clock signals GCK1 to GCK8 are supplied to the input terminals of the shift register 210 in the order of GCK1, GCK2, GCK3, GCK4, GCK5, GCK6, GCK7, and GCK8 in the first cycle, in the order of GCK2, GCK3, GCK4, GCK5, GCK6, GCK7, GCK8, and GCK1 in the second cycle, in the order of GCK3, GCK4, GCK5, GCK6, GCK7, GCK8, GCK1, and GCK2 in the third cycle, and in the order of GCK4, GCK5, GCK6, GCK7, GCK8, GCK1, GCK2, and GCK3 in the fourth cycle. Figure 7As shown, in the unit circuit 2(k) of an arbitrary stage (here, the kth stage: k is an integer of 1 or more and i or less), the output signal Q(k-4) output from the unit circuit 2(k-4) before the 4th stage is supplied as the set signal S, and the output signal Q(k+6) output from the unit circuit 2(k+6) after the 6th stage is supplied as the reset signal R. However, the gate start pulse signal is supplied as the set signal S to the prescribed number of unit circuits 2 on the primary side, and the clear signal is supplied as the reset signal R to the prescribed number of unit circuits 2 on the final stage side. As for the gate start pulse signal, either one or a plurality of them can be used. The same applies to the clear signal. The direct current power supply voltage VSS at the low level is commonly applied to all of the unit circuits 2(1) to 2(i).

[0141] The output signal Q is output from the output terminal of each stage (each unit circuit 2) of the shift register 210 (refer to FIG. 2). The output signal Q output from an arbitrary stage (here, the kth stage: k is an integer of 1 or more and i or less) is applied to the gate bus line GL(k) of the kth row as the scan signal GOUT(k), and is applied to the unit circuit 2(k-6) before the 6th stage as the reset signal R, and is applied to the unit circuit 2(k+4) after the 4th stage as the set signal S. Figure 7 ). The output signal Q output from an arbitrary stage (here, the kth stage: k is an integer of 1 or more and i or less) is applied to the gate bus line GL(k) of the kth row as the scan signal GOUT(k), and is applied to the unit circuit 2(k-6) before the 6th stage as the reset signal R, and is applied to the unit circuit 2(k+4) after the 4th stage as the set signal S.

[0142] In the above-described configuration, if the pulse of the gate start pulse signal as the set signal S is supplied to the unit circuit 2 serving as a dummy stage provided before the first stage of the shift register 210, the shift pulse included in the output signal Q output from each unit circuit 2 is sequentially transferred from the unit circuit 2(1) of the first stage to the unit circuit 2(i) of the i-th stage based on the clock operation of the gate clock signals GCK1 to GCK8. Then, in accordance with the transfer of the shift pulse, the output signal Q (scan signal GOUT) output from each unit circuit 2 becomes high level in sequence. As a result, as shown in FIG. 4, the scan signals GOUT(1) to GOUT(i) that become high level (activated) are sequentially supplied to the gate bus lines GL(1) to GL(i) in the display portion 400 at regular intervals. That is, the i gate bus lines GL(1) to GL(i) become the selection state in sequence. Figure 8

[0143] Further, in the present embodiment, as the gate clock signal GCK, the 8-phase clock signal having a duty ratio of substantially 50% is used, but the duty ratio and the number of phases of the gate clock signal GCK are not particularly limited.

[0144] <2.2 Configuration of Unit Circuit>

[0145] Figure 1 is a circuit diagram showing the configuration of the unit circuit 2 in the present embodiment. Further, it is assumed that​Figure 1 The unit circuit 2 shown is a unit circuit 2(n) of the n-th stage. As shown in Figure 1 The unit circuit 2 has 10 thin film transistors T1 to T10 and one capacitor (capacitive element) C. In addition, the unit circuit 2 has 6 input terminals 21 to 26 and 1 output terminal 29. The input terminal 21 is supplied with a set signal S that is an output signal Q(n-4) from a unit circuit of the stage before the 4-th stage. The input terminal 22 is supplied with a reset signal R that is an output signal Q(n+6) from a unit circuit of the stage after the 6-th stage. One of the gate clock signals GCK1 to GCK8 is supplied to the input terminal 23 as a first clock signal CK1. In the present embodiment, as shown in Figure 4 The unit circuit 2 has 10 thin film transistors T1 to T10 and one capacitor (capacitive element) C. In addition, the unit circuit 2 has 6 input terminals 21 to 26 and 1 output terminal 29. The input terminal 21 is supplied with a set signal S that is an output signal Q(n-4) from a unit circuit of the stage before the 4-th stage. The input terminal 22 is supplied with a reset signal R that is an output signal Q(n+6) from a unit circuit of the stage after the 6-th stage. One of the gate clock signals GCK1 to GCK8 is supplied to the input terminal 23 as a first clock signal CK1. In the present embodiment, as shown in Figure 4 The unit circuit 2 has 10 thin film transistors T1 to T10 and one capacitor (capacitive element) C. In addition, the unit circuit 2 has 6 input terminals 21 to 26 and 1 output terminal 29. The input terminal 21 is supplied with a set signal S that is an output signal Q(n-4) from a unit circuit of the stage before the 4-th stage. The input terminal 22 is supplied with a reset signal R that is an output signal Q(n+6) from a unit circuit of the stage after the 6-th stage. One of the gate clock signals GCK1 to GCK8 is supplied to the input terminal 23 as a first clock signal CK1. In the present embodiment, as shown in Figure 4 The unit circuit 2 has 10 thin film transistors T1 to T10 and one capacitor (capacitive element) C. In addition, the unit circuit 2 has 6 input terminals 21 to 26 and 1 output terminal 29. The input terminal 21 is supplied with a set signal S that is an output signal Q(n-4) from a unit circuit of the stage before the 4-th stage. The input terminal 22 is supplied with a reset signal R that is an output signal Q(n+6) from a unit circuit of the stage after the 6-th stage. One of the gate clock signals GCK1 to GCK8 is supplied to the input terminal 23 as a first clock signal CK1. In the present embodiment, as shown in

[0146] Next, the connection relationship among the constituent elements within the unit circuit 2 will be described. The second conduction terminal of the thin film transistor T1, the first conduction terminal of the thin film transistor T2, the control terminal of the thin film transistor T6, the control terminal of the thin film transistor T7, the control terminal of the thin film transistor T8, the first conduction terminal of the thin film transistor T9, and one end of the capacitor C are connected to each other via the first node N1. The second conduction terminal of the thin film transistor T4, the first conduction terminal of the thin film transistor T7, the control terminal of the thin film transistor T9, and the control terminal of the thin film transistor T10 are connected to each other via the second node N2. The second conduction terminal of the thin film transistor T3, the control terminal of the thin film transistor T4, the first conduction terminal of the thin film transistor T5, and the first conduction terminal of the thin film transistor T6 are connected to each other via the third node N3.

[0147] For the thin film transistor T1, the control terminal and the first conductive terminal are connected to the input terminal 21, and the second conductive terminal is connected to the first node N1. For the thin film transistor T2, the control terminal is connected to the input terminal 22, and the first conductive terminal is connected to the first node N1, and the second conductive terminal is connected to the input terminal 26. For the thin film transistor T3, the control terminal and the first conductive terminal are connected to the input terminal 24, and the second conductive terminal is connected to the third node N3. Regarding the thin film transistor T4, the control terminal is connected with the third node N3, the first conductive terminal is connected with the input terminal 24, and the second conductive terminal is connected with the second node N2. For the thin film transistor T5, the control terminal is connected to the input terminal 25, and the first conductive terminal is connected to the third node N3, and the second conductive terminal is connected to the input terminal 26. For the thin film transistor T6, the control terminal is connected to the first node N1, and the first conductive terminal is connected to the third node N3, and the second conductive terminal is connected to the input terminal 26. For the thin film transistor T7, the control terminal is connected to the first node N1, and the first conductive terminal is connected to the second node N2, and the second conductive terminal is connected to the input terminal 26. For the thin film transistor T8, the control terminal is connected to the first node N1, and the first conductive terminal is connected to the input terminal 23, and the second conductive terminal is connected to the output terminal 29. Further, the thin film transistor T8 is referred to as a "buffer transistor". For the thin film transistor T9, the control terminal is connected to the second node N2, and the first conductive terminal is connected to the first node N1, and the second conductive terminal is connected to the input terminal 26. For the thin film transistor T10, the control terminal is connected to the second node N2, and the first conductive terminal is connected to the output terminal 29, and the second conductive terminal is connected to the input terminal 26. Regarding the capacitor C, one end is connected with the first node N1, and the other end is connected with the output terminal 29.

[0148] The unit circuit 2 functionally includes: a first node pull-up section 201 for making the potential of the first node Nl high (on level) based on an output signal Q output from the output terminal 29 of the unit circuit 2 constituting a stage before the present stage; a first node pull-down section 202 for making the potential of the first node Nl low (off level) based on an output signal Q output from the output terminal 29 of the unit circuit 2 constituting a stage after the present stage; a stabilization circuit 203 for reliably maintaining the potential of the output terminal 29 at the low level during a non-selection period; an output control section 204 for applying the potential of the first clock signal CKl to the output terminal 29 based on the potential of the first node Nl; a second node pull-down section 205 for making the potential of the first node Nl low (off level) based on the potential of the second node N2; and an output pull-down section 206 for making the potential of the output terminal 29 low based on the potential of the second node N2. The first node pull-up section 201 includes a thin film transistor Tl. The first node pull-down section 202 includes a thin film transistor T2. The stabilization circuit 203 includes thin film transistors T3 to T7. The output control section 204 includes a thin film transistor T8. The second node pull-down section 205 includes a thin film transistor T9. The output pull-down section 206 includes a thin film transistor TlO.

[0149] Next, the functions of each of the constituent elements (the thin film transistors Tl to TlO and the capacitor C) will be described. When the set signal S becomes high, the thin film transistor Tl makes the potential of the first node Nl high. When the reset signal R becomes high, the thin film transistor T2 makes the potential of the first node Nl low. When the second clock signal CK2 becomes high, the thin film transistor T3 makes the potential of the third node N3 high. When the potential of the third node N3 becomes high, the thin film transistor T4 controls the potential of the second node N2 according to the level of the second clock signal CK2. When the third clock signal CK3 becomes high, the thin film transistor T5 makes the potential of the third node N3 low. When the potential of the first node Nl becomes high, the thin film transistor T6 makes the potential of the third node N3 low. When the potential of the first node Nl becomes high, the thin film transistor T7 makes the potential of the second node N2 low. When the potential of the first node Nl becomes high, the thin film transistor T8 supplies the potential of the first clock signal CKl to the output terminal 29. When the potential of the second node N2 becomes high, the thin film transistor T9 makes the potential of the first node Nl low. When the potential of the second node N2 becomes high, the thin film transistor TlO makes the potential of the output terminal 29 low. The capacitor C functions as a boost capacitor for raising the potential of the first node Nl.

[0150] Furthermore, in this embodiment, a first node pull-up transistor is implemented by thin-film transistor T1, a first node pull-down transistor is implemented by thin-film transistor T2, a third node pull-up transistor is implemented by thin-film transistor T3, a second node pull-up transistor is implemented by thin-film transistor T4, a second third node pull-down transistor is implemented by thin-film transistor T5, a first third node pull-down transistor is implemented by thin-film transistor T6, a first second node pull-down transistor is implemented by thin-film transistor T7, a first output control transistor is implemented by thin-film transistor T8, a second first node pull-down transistor serving as a stabilizing transistor is implemented by thin-film transistor T9, a first output node pull-down transistor serving as a stabilizing transistor is implemented by thin-film transistor T10, and a first output node is implemented through output terminal 29.

[0151] <2.3 Operation of a Unit Circuit>

[0152] Next, refer to Figure 9 The signal waveform diagram shown illustrates the operation of unit circuit 2. During the operation of the liquid crystal display device, first to third clock signals CK1 to CK3 with a duty cycle of approximately 50% are provided to unit circuit 2. As described above, the phase of the second clock signal CK2 is 45 degrees ahead of the phase of the first clock signal CK1, and the phase of the third clock signal CK3 is 135 degrees behind the phase of the first clock signal CK1. Furthermore, here, we focus on unit circuit 2(n) of the nth stage.

[0153] Before time t11, the set signal S is low, the output signal Q(n) is low, the reset signal R is low, the potential of the first node N1 is low, the potential of the second node N2 is high, and the potential of the third node N3 is low.

[0154] When time t11 is reached, the set signal S changes from low to high. For example... Figure 1As shown, thin-film transistor T1 becomes diode-connected. Therefore, with the pulse of the setting signal S, thin-film transistor T1 becomes conductive, and the potential of the first node N1 rises. Consequently, thin-film transistors T6, T7, and T8 become conductive. When thin-film transistor T7 becomes conductive, the potential of the second node N2 becomes low. Furthermore, during the period from time t11 to time t12, since the first clock signal CK1 is low, even if thin-film transistor T8 becomes conductive, the output signal Q(n) remains low. Additionally, as described later, the potential of the first node N1 is maintained at a high level until time t14. That is, during the period from time t11 to time t14, the potential of the first node N1 remains high. Therefore, during this period, thin-film transistors T7 and T6 remain conductive, while the potentials of the third node N3 and the second node N2 remain low.

[0155] When time t12 is reached, the first clock signal CK1 changes from low to high. At this time, since the thin-film transistor T8 is in the on state, the potential of the output terminal 29 rises as the potential of the input terminal 23 rises. Here, as... Figure 1 As shown, since capacitor C is positioned between the first node N1 and the output terminal 29, the potential of the first node N1 rises simultaneously with the potential of the output terminal 29 (the first node N1 enters a boost state). As a result, a large voltage is applied to the control terminal of the thin-film transistor T8, and the potential of the output signal Q(n) rises to a level sufficient for the gate bus GL(n) connected to the output terminal 29 to become selected. Furthermore, during the period from time t12 to time t13, the reset signal R remains low, and the potential of the second node N2 also remains low. Therefore, during this period, thin-film transistors T2 and T10 remain in the off state, and the potential of the first node N1 and the potential of the output signal Q(n) (the potential of the output terminal 29) do not decrease.

[0156] When time t13 is reached, the first clock signal CK1 changes from high to low. Consequently, the potential at input terminal 23 decreases, and the potential at output terminal 29 also decreases. That is, the potential of the output signal Q(n) becomes low. Additionally, the potential of the first node N1 decreases through capacitor C.

[0157] When time t14 is reached, the reset signal R changes from low to high. This turns thin-film transistor T2 on, and the potential of the first node N1 becomes low. By turning the potential of the first node N1 low, thin-film transistors T6, T7, and T8 become off.

[0158] When the time t15 is reached, the second clock signal CK2 changes from the low level to the high level. Thus, the thin film transistor T3 becomes in the on state. In addition, at the time t15, the third clock signal CK3 changes from the high level to the low level. Thus, the thin film transistor T5 becomes in the off state. At this time, the thin film transistor T6 is in the off state. As described above, at the time t15, the potential of the third node N3 changes from the low level to the high level. Thus, the thin film transistor T4 becomes in the on state. At this time, the thin film transistor T7 is in the off state. Thus, at the time t15, the potential of the second node N2 changes from the low level to the high level.

[0159] When the time t16 is reached, the second clock signal CK2 changes from the high level to the low level, and the third clock signal CK3 changes from the low level to the high level. Thus, at the time when the second clock signal CK2 applied to the control terminal of the thin film transistor T3 changes from the high level (on level) to the low level (off level), the third clock signal CK3 applied to the control terminal of the thin film transistor T5 changes from the low level (off level) to the high level (on level). Thus, the thin film transistor T3 becomes in the off state, and the thin film transistor T5 becomes in the on state. As described above, at the time t16, the potential of the third node N3 changes from the high level to the low level. At this time, since the thin film transistor T4 becomes in the off state, the potential of the second node N2 is maintained at the high level.

[0160] When the time t17 is reached, the second clock signal CK2 changes from the low level to the high level. Thus, the thin film transistor T3 becomes in the on state. In addition, at the time t17, the third clock signal CK3 changes from the high level to the low level. Thus, the thin film transistor T5 becomes in the off state. At this time, the thin film transistor T6 is in the off state. As described above, at the time t17, the potential of the third node N3 changes from the low level to the high level. Thus, the thin film transistor T4 becomes in the on state, and charges are supplied from the input terminal 24 to the second node N2. Therefore, even if the leakage of charges occurs in the thin film transistor T7 and the thin film transistor T9, the potential of the second node N2 is maintained at the high level.

[0161] During the non-selection period, as described above, the change from the low level to the high level and the change from the high level to the low level are repeated with respect to the potential of the third node N3, and the potential of the second node N2 is maintained at the high level. Thus, during the non-selection period, the potential of the first node N1 and the potential of the output signal Q(n) (the potential of the output terminal 29) are maintained at the low level.

[0162] By performing the above-described operation in each unit circuit 2, the plurality of (i) gate bus lines GL(1) to GL(i) provided in the liquid crystal display device become the selection state in turn, and the writing of the image signal to the pixel capacitance 46 is performed in turn. Thus, the image based on the image signal DAT transmitted from the outside is displayed on the display portion 400 (see Figure 2 ).

[0163] Further, in the present embodiment, an 8-phase clock signal is used as the gate clock signal GCK, but as described above, the number of phases of the gate clock signal GCK is not particularly limited. In this regard, for example, in the case where a P-phase clock signal is used as the natural number, a clock signal that is advanced by (360 / P) degrees from the clock signal applied to the first conduction terminal of the thin film transistor T8 is supplied to the control terminal of the thin film transistor T3.

[0164] <2.4 Transistor size and wiring>

[0165] Here, the size of the thin film transistors within the unit circuit 2 shown in Figure 1 and the wiring to the gate driver 200 will be described.

[0166] The thin film transistor T3 is an element for charging the third node N3. When the potential of the first node N1 is maintained at the high level in the selection period, the potential of the third node N3 is desired to be the low level. The channel length of the thin film transistor T3 is longer than the channel length of the other thin film transistors TFT, so that when the thin film transistor T3 as the pull-up transistor of the third node N3 and the thin film transistor T6 as the pull-down transistor of the third node N3 become the conduction state at the same time, the pull-down effect of the thin film transistor T6 can be obtained more greatly than the pull-up effect of the thin film transistor T3. The channel width of the thin film transistor T3 is the same as the channel width of the thin film transistors T4 and T5.

[0167] As described above, since the potential of the second node N2 is maintained at the high level in the non-selection period (see Figure 9 , the charging ability of the thin film transistor T4 is not particularly limited. In addition, the thin film transistor T5 is an element for discharging the third node N3, but a high discharging ability is not required. As described above, among the thin film transistors T1 to T10 provided in the unit circuit 2, the thin film transistors T4 and T5 are the smallest in size, so that the circuit area is made small.

[0168] As Figure 10As shown, the region on the active matrix substrate constituting the liquid crystal panel 5 schematically includes a display region in which a plurality of (i x j) pixel formation portions 4 are formed, a shift register region in which the shift register 210 is formed, and a trunk wiring region in which the clock signal trunk wiring 51 through which the gate clock signal GCK1 to GCK8 is transmitted and the power supply voltage trunk wiring 52 through which the direct current power supply voltage VSS at the low level is transmitted are formed. The clock signal trunk wiring 51 and the power supply voltage trunk wiring 52 are formed of a source metal (a metal film forming a source bus SL). Here, as a wiring for supplying the gate clock signal GCK to the control terminal of the thin film transistor T5, a clock signal branch wiring 53 connected at one end to one of the plurality of clock signal trunk wirings 51 and at the other end to the control terminal of the thin film transistor T5 is provided as shown. Figure 10 As shown, the region on the active matrix substrate constituting the liquid crystal panel 5 schematically includes a display region in which a plurality of (i x j) pixel formation portions 4 are formed, a shift register region in which the shift register 210 is formed, and a trunk wiring region in which the clock signal trunk wiring 51 through which the gate clock signal GCK1 to GCK8 is transmitted and the power supply voltage trunk wiring 52 through which the direct current power supply voltage VSS at the low level is transmitted are formed. The clock signal trunk wiring 51 and the power supply voltage trunk wiring 52 are formed of a source metal (a metal film forming a source bus SL). Here, as a wiring for supplying the gate clock signal GCK to the control terminal of the thin film transistor T5, a clock signal branch wiring 53 connected at one end to one of the plurality of clock signal trunk wirings 51 and at the other end to the control terminal of the thin film transistor T5 is provided as shown. Figure 10 As shown, the region on the active matrix substrate constituting the liquid crystal panel 5 schematically includes a display region in which a plurality of (i x j) pixel formation portions 4 are formed, a shift register region in which the shift register 210 is formed, and a trunk wiring region in which the clock signal trunk wiring 51 through which the gate clock signal GCK1 to GCK8 is transmitted and the power supply voltage trunk wiring 52 through which the direct current power supply voltage VSS at the low level is transmitted are formed. The clock signal trunk wiring 51 and the power supply voltage trunk wiring 52 are formed of a source metal (a metal film forming a source bus SL). Here, as a wiring for supplying the gate clock signal GCK to the control terminal of the thin film transistor T5, a clock signal branch wiring 53 connected at one end to one of the plurality of clock signal trunk wirings 51 and at the other end to the control terminal of the thin film transistor T5 is provided as shown.

[0169] As described above, the phase of the second clock signal CK2 is advanced by 45 degrees from the phase of the first clock signal CK1. Therefore, for example, the gate clock signal GCK applied to the control terminal and the first conduction terminal of the thin film transistor T3 included in the unit circuit 2(n) of the n-th stage as the second clock signal CK2 and the gate clock signal GCK applied to the first conduction terminal of the thin film transistor T8 included in the unit circuit 2(n-1) of the (n-1)-th stage as the first clock signal CK1 are the same signal. In view of this, in the present embodiment, one wiring (branch wiring) is realized for supplying the gate clock signal GCK to the control terminal and the first conduction terminal of the thin film transistor T3 included in the unit circuit 2(n) of the n-th stage and for supplying the gate clock signal GCK to the first conduction terminal of the thin film transistor T8 included in the unit circuit 2(n-1) of the (n-1)-th stage. Specifically, schematically as shown in Figure 11As shown, the first conduction terminal of the thin film transistor T8 included in the unit circuit 2(n-1) of the (n-1)th stage and the control terminal and the first conduction terminal of the thin film transistor T3 included in the unit circuit 2(n) of the nth stage are connected to the same clock signal branch wiring 56 that is connected at one end to one of the plurality of clock signal main wiring 51. Further, the clock signal branch wiring 56 is formed of gate metal, and is connected at the main wiring region to one of the plurality of clock signal main wiring 51 via a contact hole 57.

[0170] In the present embodiment, by adopting Figure 10 and Figure 11 the layout shown, an increase in circuit area is suppressed. Further, the first metal film is realized by source metal, and the second metal film is realized by gate metal.

[0171] <3. Effects>

[0172] According to the present embodiment, in the unit circuit 2 of each stage that configures the shift register 210 within the gate driver 200, a thin film transistor T5 is provided that has a control terminal to which one of a plurality of gate clock signals GCK is applied, a first conduction terminal connected to the third node N3, and a second conduction terminal to which a direct current power supply voltage VSS of low level is applied. The gate clock signal GCK (second clock signal CK2) applied to the control terminal and the first conduction terminal of the thin film transistor T3 and the gate clock signal GCK (third clock signal CK3) applied to the control terminal of the thin film transistor T5 are phase-shifted by 180 degrees. Therefore, during the non-selection period, the potential of the third node N3 repeatedly changes from low level to high level and from high level to low level. Further, at the time when the second clock signal CK2 changes from high level to low level, the third clock signal CK3 changes from low level to high level, and therefore, during the period when the second clock signal CK2 is low, the potential of the third node N3 is low, and the thin film transistor T4 is maintained in the off state. As described above, the potential of the second node N2 is maintained at high level over the non-selection period. That is, the charging and discharging of the second node N2 is suppressed from being excessively performed. As a result, power consumption is reduced. Further, since the situation in which the thin film transistors T9, T10 repeatedly change from the on state to the off state and from the off state to the on state during the non-selection period is suppressed, the deterioration of the thin film transistors T9, T10 is suppressed. Thereby, the effect of the pull-down function that introduces the potential of the first node N1 to low level and the effect of the pull-down function that introduces the potential of the output terminal 29 to low level are stabilized. As described above, according to the present embodiment, reduction in power consumption and stabilization of operation of the gate driver 200 (monolithic gate driver) can be realized.

[0173] <4. Modified example>

[0174] Next, a modification of the configuration of the unit circuit 2 will be described.

[0175] <4.1 First Modification>

[0176] Figure 12 is a circuit diagram showing the configuration of the unit circuit 2 in the first modification of the above-described embodiment. In the unit circuit 2 in this modification, unlike the unit circuit 2 (refer to Figure 1 ) of the above-described embodiment, the thin film transistor T9 is not provided. Thus, since the thin film transistor T9 is not provided, even if noise is generated in the first node N1 due to the clock operation of the first clock signal CK1 or the like during the non-selection period, the potential of the first node N1 is not introduced to the low level. Therefore, there is a possibility that the potential of the first node N1 during the non-selection period becomes unstable. However, since the thin film transistor T9 is not provided, compared with the above-described embodiment, an effect of being able to reduce the circuit area can be obtained.

[0177] <4.2 Second Modification>

[0178] Figure 13 is a circuit diagram showing the configuration of the unit circuit 2 in the second modification of the above-described embodiment. In the unit circuit 2 in this modification, unlike the unit circuit 2 (refer to Figure 1 ) of the above-described embodiment, the thin film transistor T10 is not provided. Thus, since the thin film transistor T10 is not provided, even if the potential of the output terminal 29 is varied due to noise or the like during the non-selection period, the potential of the output terminal 29 is not introduced to the low level. Therefore, there is a possibility that the potential of the output terminal 29 (the potential of the output signal Q) during the non-selection period becomes unstable. However, since the thin film transistor T10 is not provided, compared with the above-described embodiment, an effect of being able to reduce the circuit area can be obtained.

[0179] <4.3 Third Modification>

[0180] Figure 14 is a circuit diagram showing the configuration of the unit circuit 2 in the third modification of the above-described embodiment. In the unit circuit 2 in this modification, in addition to the configuration elements of the unit circuit 2 (refer to Figure 1 ) in the above-described embodiment, the thin film transistor T11 is provided. Regarding the thin film transistor T11, the control terminal is connected to the input terminal 21, the first conduction terminal is connected to the second node N2, and the second conduction terminal is connected to the input terminal 26. When the set signal S becomes the high level, the thin film transistor T11 makes the potential of the second node N2 the low level. Further, the second node pull-down transistor of the second is realized by the thin film transistor T11.

[0181] According to this modification, the charge of the second node N2 is discharged via the thin film transistor T7 and the thin film transistor T11. Therefore, at the time t11, the potential of the second node N2 is reliably introduced from the high level to the low level. Thus, the operation of the gate driver 200 is more stabilized. Figure 9 the potential of the second node N2 is reliably introduced from the high level to the low level. Thus, the operation of the gate driver 200 is more stabilized.

[0182] <4.4 Fourth Modification>

[0183] Figure 15 is a circuit diagram showing the configuration of the unit circuit 2 in the fourth modification of the above-described embodiment. In this modification, the control terminal and the first conduction terminal of the thin film transistor T3 are connected to the input terminal 23. Therefore, the input terminal 24 is not provided in this unit circuit 2. The same gate clock signal as the first clock signal CK1 is supplied to the control terminal and the first conduction terminal of the thin film transistor T3 and the first conduction terminal of the thin film transistor T8. In addition, as described later, at the time when the first clock signal CK1 applied to the control terminal of the thin film transistor T3 changes from the high level to the low level, the third clock signal CK3 applied to the control terminal of the thin film transistor T5 changes from the low level to the high level. In this regard, for example, the duty ratio of each clock signal is 50%, and the phase of the third clock signal CK3 lags behind the phase of the first clock signal CK1 by 180 degrees (see Figure 16 ).

[0184] Referring to Figure 16 , the operation of the unit circuit 2 in this modification will be described. Here, the unit circuit 2(n) of the nth stage is also focused on. At the time before the time t21, the set signal S is the low level, the output signal Q(n) is the low level, the reset signal R is the low level, the potential of the first node N1 is the low level, the potential of the second node N2 is the high level, and the potential of the third node N3 is the high level.

[0185] When the time t21 is reached, the set signal S changes from the low level to the high level. Thus, similarly to the time t11 in the above-described embodiment (see Figure 9 ), the potential of the first node N1 rises, and the potential of the second node N2 becomes the low level. In addition, at the time t21, the first clock signal CK1 changes from the high level to the low level, and the third clock signal CK3 changes from the low level to the high level. Thus, the thin film transistor T3 becomes the off state, and the thin film transistor T5 becomes the on state. As a result, the potential of the third node N3 becomes the low level. With regard to the time t22, the time t23, and the time t24, the operation is performed similarly to the time t12, the time t13, and the time t14 in the above-described embodiment.

[0186] When time t25 is reached, the first clock signal CK1 changes from low to high. Thus, the thin film transistor T3 becomes in an on state. In addition, at time t25, the third clock signal CK3 changes from high to low. Thus, the thin film transistor T5 becomes in an off state. As described above, similarly to time t15 in the above embodiment, the potential of the third node N3 and the potential of the second node N2 change from low to high.

[0187] When time t26 is reached, the first clock signal CK1 changes from high to low, and the third clock signal CK3 changes from low to high. Thus, at the time when the first clock signal CK1 applied to the control terminal of the thin film transistor T3 changes from high (on level) to low (off level), the third clock signal CK3 applied to the control terminal of the thin film transistor T5 changes from low (off level) to high (on level). Thus, the thin film transistor T3 becomes in an off state, and the thin film transistor T5 becomes in an on state. As described above, at time t26, the potential of the third node N3 changes from high to low. At this time, since the thin film transistor T4 becomes in an off state, the potential of the second node N2 is maintained at high.

[0188] When time t27 is reached, the first clock signal CK1 changes from low to high. Thus, the thin film transistor T3 becomes in an on state. In addition, at time t27, the third clock signal CK3 changes from high to low. Thus, the thin film transistor T5 becomes in an off state. Through the above, similarly to time t17 in the above embodiment, the potential of the third node N3 changes from low to high, and a charge is supplied from the input terminal 24 to the second node N2 via the thin film transistor T4.

[0189] As described above, in this modification example, the potential of the second node N2 is also maintained at high during the non-selection period. Thus, the potential of the first node N1 and the potential of the output signal Q(n) (the potential of the output terminal 29) are maintained at low during the non-selection period.

[0190] According to the above modification example, the wiring (branch wiring) for supplying the gate clock signal GCK to the control terminal of the thin film transistor T3 and the first on terminal and the wiring (branch wiring) for supplying the gate clock signal GCK to the first on terminal of the thin film transistor T8 can be realized by one wiring (branch wiring). Thus, an effect of reducing the circuit area, an effect of reducing the wiring cross portion can be obtained. Also, the same effects as the above embodiment are obtained.

[0191] <4.5 Fifth Modification Example>

[0192] Figure 17is a circuit diagram showing the configuration of the unit circuit 2 in the fifth modification of the above-described embodiment. In this modification, the configuration of the thin film transistor T5 is different from that of the above-described embodiment. In the thin film transistor T5 in this modification, the control terminal and the first conduction terminal are connected to the third node N3, and the second conduction terminal is connected to the input terminal 24. Therefore, the input terminal 25 is not provided in this unit circuit 2. The same gate clock signal GCK as the second clock signal CK2 is supplied to the control terminal and the first conduction terminal of the thin film transistor T3 and the second conduction terminal of the thin film transistor T5.

[0193] Referring to Figure 18 , the operation of the unit circuit 2 in this modification will be described. Here, the unit circuit 2 (n) of the nth stage is also focused on. The operation in the period before time t34 is performed similarly to the period before time t14 in the above-described embodiment (refer to Figure 9 ).

[0194] When time t35 is reached, the second clock signal CK2 changes from the low level to the high level. Thereby, the thin film transistor T3 changes to the on state. In addition, since the potential of the second conduction terminal of the thin film transistor T5 rises, the thin film transistor T5 is maintained in the off state. At this time, the potential of the first node N1 is the low level, and therefore the thin film transistor T6 is in the off state. As described above, at time t35, the potential of the third node N3 changes from the low level to the high level. Thereby, the thin film transistor T4 changes to the on state. At this time, the thin film transistor T7 is in the off state. Thereby, at time t35, the potential of the second node N2 changes from the low level to the high level.

[0195] When time t36 is reached, the second clock signal CK2 changes from the high level to the low level. Thereby, the thin film transistor T3 changes to the off state. In addition, since the potential of the second conduction terminal of the thin film transistor T5 falls, the thin film transistor T5 changes to the on state and the potential of the third node N3 falls. Thereby, the thin film transistor T4 changes to the off state. Therefore, the potential of the second node N2 is maintained at the high level.

[0196] When time t37 is reached, the second clock signal CK2 changes from the low level to the high level. Thereby, similarly to time t35, the potential of the third node N3 changes from the low level to the high level. Thereby, the thin film transistor T4 changes to the on state. At this time, the thin film transistor T7 is in the off state. As described above, the charge is supplied from the input terminal 24 to the second node N2 via the thin film transistor T4.

[0197] As described above, in this modification, the potential of the second node N2 is also maintained at the high level during the non-selection period. Therefore, the potential of the first node N1 and the potential of the output signal Q(n) (the potential of the output terminal 29) are maintained at the low level during the non-selection period.

[0198] According to the present modification as described above, the wiring (branch wiring) for supplying the gate clock signal GCK to the control terminal and the first conduction terminal of the thin film transistor T3 and the wiring (branch wiring) for supplying the gate clock signal GCK to the second conduction terminal of the thin film transistor T5 can be realized by one wiring (branch wiring). Thus, the effects of reducing the circuit area and reducing the wiring intersection part can be obtained. Also, the same effects as the above-described embodiment are obtained.

[0199] <4.6 Sixth Modification>

[0200] In the above-described embodiment and the above-described first to fifth modifications, the output signal from one output terminal 29 is supplied as the scan signal GOUT to the corresponding gate bus line GL, as the reset signal R to the unit circuit 2 which is six stages ahead of the present stage, and as the set signal S to the unit circuit 2 which is four stages behind the present stage. That is, the signal for controlling the scan signal GOUT and the operation of the other stages (hereinafter, referred to as "other stage control signal" for convenience) is output from the same output terminal 29. However, it is not limited thereto, and as to the unit circuit 2, a configuration in which the scan signal GOUT and the other stage control signal are output from different output terminals can also be adopted (configuration of the present modification).

[0201] Figure 19 is a circuit diagram showing the configuration of the unit circuit 2 in the present modification. Further, in this example, a configuration in which the output terminal 29 in the configuration of the above-described third modification (refer to Figure 14 ) is separated into two output terminals 29a, 29b is illustrated, but it is not limited thereto.

[0202] As shown in Figure 19 , the unit circuit 2 in the present modification includes two output terminals 29a, 29b. In correspondence thereto, the output control section 204 includes two thin film transistors T8a, T8b, and the output pull-down section 206 includes two thin film transistors T10a, T10b. Aspects other than this are the same as the above-described third modification.

[0203] The output signal Q(n) is output from the output terminal 29a, and the output signal G(n) is output from the output terminal 29b. The output signal Q(n) is supplied as an other-stage control signal to the unit circuit 2 constituting the other stage. In detail, the output signal Q(n) output from the output terminal 29a of the unit circuit 2(n) of the nth stage is supplied as a reset signal R to the unit circuit 2(n-6) of the (n-6)th stage and as a set signal S to the unit circuit 2(n+4) of the (n+4)th stage. The output signal G(n) is supplied as a scan signal GOUT(n) to the corresponding gate bus line GL(n). As described above, in the present modification, the input and output signals of each unit circuit 2 are as shown in FIG. 27. However, in the present modification, the input and output signals of each unit circuit 2 are as shown in FIG. 27. Figure 20 Figure 20 Figure 7 In the present modification, as in the first embodiment, k is set to an integer of 1 or more and i or less, and the unit circuit 2(k) of the kth stage is focused on.

[0204] As to the thin film transistor T8a, the control terminal is connected to the first node Nl, and the first conductive terminal is connected to the input terminal 23, and the second conductive terminal is connected to the output terminal 29a. As to the thin film transistor T8b, the control terminal is connected to the first node Nl, and the first conductive terminal is connected to the input terminal 23, and the second conductive terminal is connected to the output terminal 29b. As described above, the first conductive terminal of the thin film transistor T8a and the first conductive terminal of the thin film transistor T8b are supplied with the first clock signal CKl as the same clock signal. As to the thin film transistor TlOa, the control terminal is connected to the second node N2, and the first conductive terminal is connected to the output terminal 29a, and the second conductive terminal is connected to the input terminal 26. As to the thin film transistor TlOb, the control terminal is connected to the second node N2, and the first conductive terminal is connected to the output terminal 29b, and the second conductive terminal is connected to the input terminal 26.

[0205] Further, in the present modification, the first output node is realized by the output terminal 29b, the second output node is realized by the output terminal 29a, the first output control transistor is realized by the thin film transistor T8b, and the second output control transistor is realized by the thin film transistor T8a.

[0206] Referring to FIG. 27, the operation of the unit circuit 2 in the present modification will be described. Further, here, the unit circuit 2(n) of the nth stage is focused on. Figure 21 At a time before time t41, the set signal S is at the low level, the output signals Q(n), G(n) are at the low level, the reset signal R is at the low level, the potential of the first node Nl is at the low level, the potential of the second node N2 is at the high level, and the potential of the third node N3 is at the low level.

[0207]

[0208] ​​​When time t41 is reached, the set signal S changes from low to high. Consequently, similar to time t11 in the above embodiment, the potential of the first node N1 rises. As a result, thin-film transistors T6, T7, T8a, T8b, and T11 become active. Since thin-film transistors T7 and T11 are active, the potential of the second node N2 becomes low. Furthermore, during the period from time t42 to time t44, since the first clock signal CK1 is low, even though thin-film transistors T8a and T8b are active, the output signals Q(n) and G(n) remain low. Additionally, similar to the period from time t11 to time t14 in the above embodiment, during the period from time t41 to time t44, the potentials of the third node N3 and the second node N2 remain low.

[0209] When time t42 is reached, the first clock signal CK1 changes from low to high. At this time, since thin-film transistors T8a and T8b are in the conducting state, the potentials of output terminals 29a and 29b rise simultaneously with the potential rise at input terminal 23. Here, as... Figure 1 As shown, since a capacitor C is provided between the first node N1 and the output terminal 29b, the potential of the first node N1 also rises (the first node N1 is in a boost state) as the potential of the output terminal 29b rises. As a result, a large voltage is applied to the control terminal of the thin-film transistor T8b, and the potential of the output signal G(n) rises to a level sufficient for the gate bus GL(n) connected to the output terminal 29b to become selected. Similarly, the potential of the output signal Q(n) also rises. Furthermore, during the period from time t42 to time t43, the reset signal R remains at a low level, and the potential of the second node N2 also remains at a low level. Therefore, during this period, the thin-film transistors T2 and T10a and T10b remain in the off state, and the potentials of the first node N1 and the output signals Q(n) and G(n) (the potentials of the output terminals 29a and 29b) do not decrease.

[0210] When time t43 is reached, the first clock signal CK1 changes from high to low. Consequently, as the potential at input terminal 23 decreases, the potentials at output terminals 29a and 29b also decrease. That is, the potentials of output signals Q(n) and G(n) become low. Additionally, the potential of the first node N1 decreases through capacitor C.

[0211] When time t44 is reached, the reset signal R changes from low to high. This turns thin-film transistor T2 on, and the potential of the first node N1 becomes low. By turning the potential of the first node N1 low, thin-film transistors T6, T7, T8a, T8b, and T11 become off.

[0212] When the time t45 is reached, the potential of the third node N3 and the potential of the second node N2 change from the low level to the high level, as in the case of the time t15 in the above embodiment. During the period after the time t46, the operation is performed as in the period after the time t16 in the above embodiment.

[0213] In this modification, during the non-selection period, the potential of the third node N3 is repeatedly changed from the low level to the high level and from the high level to the low level, and the potential of the second node N2 is also maintained at the high level. Thus, the potential of the first node N1 and the potentials of the output signals Q(n), G(n) (the potentials of the output terminals 29a, 29b) are maintained at the low level through the non-selection period.

[0214] According to this modification, the output control section 204 in the unit circuit 2 includes two thin film transistors T8a, T8b (see Figure 19 ) that output the other-stage control signal from the output terminal 29a connected to the second conduction terminal of the thin film transistor T8a and the scan signal GOUT from the output terminal 29b connected to the second conduction terminal of the thin film transistor T8b. Since such a configuration is employed, even in the case where the load capacitance of the gate bus line GL is large, the waveform blunting of the other-stage control signal (the set signal S, the reset signal R) can be reduced. Thus, as for the shift register 210, the speedup of the operation of the circuit and the improvement of the reliability of the operation of the circuit can be achieved.

[0215] <5. OTHERS>

[0216] The present application has been described in detail above, but the above description is exemplary in all respects and is not restrictive. It should be understood that various other changes, modifications, and alterations can be conceived without departing from the scope of the present application.

[0217] Explanation of Reference Numerals

[0218] 2, 2(1) to 2(i)... unit circuit

[0219] 4... pixel formation section

[0220] 5... liquid crystal panel

[0221] 40... thin film transistor (pixel TFT)

[0222] 200... gate driver

[0223] 203... stabilizing circuit

[0224] 210... shift register

[0225] 400... display section

[0226] T1 - T11, T8a, T8b, T10a, T10b... Thin film transistors within a unit circuit CK1 - CK3... First to third clock signals

[0227] GCK1 - GCK8... Gate clock signals

[0228] GL, GL(l) - GL(i)... Gate bus lines

[0229] GOUT, GOUT(l) - GOUT(i)... Scan signals N1 - N3... First to third nodes

[0230] R... Reset signal

[0231] S... Set signal

[0232] VSS... Low-level DC power supply voltage

Claims

1. A scan signal line drive circuit for driving a plurality of scan signal lines, the scan signal line drive circuit characterized by, comprising a shift register which operates based on a plurality of clock signals and is constituted by a plurality of stages corresponding one-to-one to the plurality of scan signal lines, a unit circuit constituting each stage included in the shift register comprises: a first node; a second node; a third node; a first output node which outputs an output signal to a corresponding scan signal line; a first output control transistor having a control terminal connected to the first node, a first conduction terminal to which one of the plurality of clock signals is applied, and a second conduction terminal connected to the first output node; a first node pull-up section for causing the potential of the first node to become an on level based on a set signal; a first node pull-down section for causing the potential of the first node to become an off level based on a reset signal; a stabilization transistor having a control terminal connected to the second node, a first conduction terminal connected to the first node or the first output node, and a second conduction terminal to which a potential of an off level is applied; and a stabilization circuit connected to the second node, the stabilization circuit comprises: a second node pull-up transistor having a control terminal connected to the third node, a first conduction terminal to which one of the plurality of clock signals is applied, and a second conduction terminal connected to the second node; a first second node pull-down transistor having a control terminal connected to the first node, a first conduction terminal connected to the second node, and a second conduction terminal to which a potential of an off level is applied; a first third node pull-down transistor having a control terminal connected to the first node, a first conduction terminal connected to the third node, and a second conduction terminal to which a potential of an off level is applied; a third node pull-up transistor having a control terminal to which one of the plurality of clock signals is applied and a first conduction terminal, and a second conduction terminal connected to the third node; and a second third node pull-down transistor having a control terminal to which one of the plurality of clock signals is applied, a first conduction terminal connected to the third node, and a second conduction terminal to which a potential of an off level is applied, at the time when the clock signal applied to the control terminal of the third node pull-up transistor changes from an on level to an off level, the clock signal applied to the control terminal of the second third node pull-down transistor changes from an off level to an on level.

2. The scan signal line drive circuit according to claim 1, characterized in that, the set signal is an output signal output from the first output node of a unit circuit constituting a stage earlier than the present stage, the reset signal is an output signal output from the first output node of a unit circuit constituting a stage later than the present stage.

3. The scan signal line drive circuit according to claim 1, characterized in that, the unit circuit comprises: a second output node which outputs other-stage control signals for controlling the operation of the unit circuit which constitutes a stage preceding the present stage and the unit circuit which constitutes a stage succeeding the present stage; and a second output control transistor having a control terminal connected to the first node, a first conduction terminal to which one of the plurality of clock signals is applied, and a second conduction terminal connected to the second output node, the clock signal applied to the first conduction terminal of the first output control transistor and the clock signal applied to the first conduction terminal of the second output control transistor are the same clock signal, the set signal is an other-stage control signal output from the second output node of the unit circuit which constitutes a stage preceding the present stage, the reset signal is an other-stage control signal output from the second output node of the unit circuit which constitutes a stage succeeding the present stage.

4. The scan signal line drive circuit according to claim 1, wherein the first node pull-up section includes a first node pull-up transistor having a control terminal to which the set signal is applied and a first conduction terminal, and a second conduction terminal connected to the first node.

5. The scan signal line drive circuit according to claim 1, wherein the first node pull-down section includes a first node pull-down transistor of the first stage having a control terminal to which the reset signal is applied, a first conduction terminal connected to the first node, and a second conduction terminal to which a potential of an off level is applied.

6. The scan signal line drive circuit according to claim 1, wherein the unit circuit includes a first node pull-down transistor of the second stage as the stabilizing transistor, the first node pull-down transistor of the second stage having a first conduction terminal connected to the first node.

7. The scan signal line drive circuit according to claim 1, wherein the unit circuit includes a first output node pull-down transistor as the stabilizing transistor, the first output node pull-down transistor having a first conduction terminal connected to the first output node.

8. The scan signal line drive circuit according to claim 1, wherein the unit circuit includes a first node pull-down transistor of the second stage and a first output node pull-down transistor as the stabilizing transistor, the first node pull-down transistor of the second stage having a first conduction terminal connected to the first node, and the first output node pull-down transistor having a first conduction terminal connected to the first output node.

9. The scan signal line drive circuit according to claim 1, wherein the unit circuit includes a second node pull-down transistor of the second stage having a control terminal to which the set signal is applied, a first conduction terminal connected to the second node, and a second conduction terminal to which a potential of an off level is applied.

10. The scan signal line drive circuit according to claim 1, wherein P is a natural number, and the plurality of clock signals are P-phase clock signals, The phase of a clock signal applied to the control terminal of the third node pull-up transistor is advanced (360 / P) degrees from the phase of a clock signal applied to the first conduction terminal of the first output control transistor.

11. The scan signal line drive circuit according to claim 1, wherein The clock signal applied to the control terminal of the third node pull-up transistor and the clock signal applied to the first conduction terminal of the first output control transistor are the same clock signal.

12. The scan signal line drive circuit according to claim 1, wherein The channel length of the third node pull-up transistor is longer than the channel length of any one of the first output control transistor, the stabilization transistor, the second node pull-up transistor, the first second node pull-down transistor, the first third node pull-down transistor, and the second third node pull-down transistor.

13. A scan signal line drive circuit for driving a plurality of scan signal lines, the scan signal line drive circuit characterized by comprising: a shift register which operates based on a plurality of clock signals and which is constituted by a plurality of stages corresponding one-to-one to the plurality of scan signal lines, a unit circuit which constitutes each stage included in the shift register includes: a first node; a second node; a third node; a first output node which outputs an output signal to a corresponding scan signal line; a first output control transistor having a control terminal connected to the first node, a first conduction terminal to which one of the plurality of clock signals is applied, and a second conduction terminal connected to the first output node; a first node pull-up section for making the potential of the first node a conduction level based on a set signal; a first node pull-down section for making the potential of the first node an off level based on a reset signal; a stabilization transistor having a control terminal connected to the second node, a first conduction terminal connected to the first node or the first output node, and a second conduction terminal to which an off level potential is applied; and a stabilization circuit connected to the second node, the stabilization circuit includes: a second node pull-up transistor having a control terminal connected to the third node, a first conduction terminal to which one of the plurality of clock signals is applied, and a second conduction terminal connected to the second node; a second node pull-down transistor having a control terminal connected to the first node, a first conduction terminal connected to the second node, and a second conduction terminal to which an off level potential is applied; a first third node pull-down transistor having a control terminal connected to the first node, a first conduction terminal connected to the third node, and a second conduction terminal to which an off level potential is applied; a third node pull-up transistor having a control terminal to which one of the plurality of clock signals is applied and a first conduction terminal, and a second conduction terminal connected to the third node; and and a second output control transistor having a control terminal connected to the first node, a first conduction terminal to which one of the plurality of clock signals is applied, and a second conduction terminal connected to the second output node, the clock signal applied to the control terminal of the first output control transistor and the clock signal applied to the second conduction terminal of the second output control transistor are the same clock signal.

14. The scan signal line drive circuit according to claim 13, wherein the set signal is an output signal output from a first output node of a unit circuit constituting a stage preceding the present stage, the reset signal is an output signal output from a first output node of a unit circuit constituting a stage succeeding the present stage.

15. The scan signal line drive circuit according to claim 13, wherein the unit circuit includes: a second output node outputting a stage other control signal for controlling the operation of a unit circuit constituting a stage preceding the present stage and a unit circuit constituting a stage succeeding the present stage, and a second output control transistor having a control terminal connected to the first node, a first conduction terminal to which one of the plurality of clock signals is applied, and a second conduction terminal connected to the second output node, the clock signal applied to the first conduction terminal of the first output control transistor and the clock signal applied to the first conduction terminal of the second output control transistor are the same clock signal, the set signal is a stage other control signal output from a second output node of a unit circuit constituting a stage preceding the present stage, the reset signal is a stage other control signal output from a second output node of a unit circuit constituting a stage succeeding the present stage.

16. A display device comprising: provided with: a substrate; a plurality of image signal lines formed on the substrate; a plurality of scan signal lines formed on the substrate so as to cross the plurality of image signal lines; a plurality of pixel formation portions formed on the substrate so as to correspond to the respective intersections of the plurality of image signal lines and the plurality of scan signal lines; an image signal line drive circuit for driving the plurality of image signal lines; and the scan signal line drive circuit according to any one of claims 1 to 15 for driving the plurality of scan signal lines, formed on the substrate.

17. The display device according to claim 16, wherein the region on the substrate includes: a display region in which the plurality of pixel formation portions are formed; a shift register region in which the shift register is formed; and a trunk wiring region in which a plurality of clock signal trunk wirings that transmit the plurality of clock signals are formed, the shift register region is provided between the display region and the trunk wiring region, for each unit circuit, a clock signal branch wiring is provided, one end of the clock signal branch wiring being connected to one of the plurality of clock signal trunk wirings, and the other end being connected to the control terminal of the second third node pull-down transistor.

18. The display device according to claim 17, wherein the plurality of image signal lines are formed by a first metal film, The multiple scanning signal lines are formed through a second metal film. The multiple clock signals are formed by backbone wiring through the first metal film. The clock signal is formed by branch wiring through the second metal film. The clock signal branch wiring and one of the multiple clock signal trunk wirings are connected via contact holes in the trunk wiring area.

19. The display device according to claim 16, characterized in that, The region on the substrate includes: The display area has the plurality of pixel forming portions formed therein; A shift register region, wherein the shift register is formed; and The backbone cabling area contains multiple backbone cabling lines for transmitting the aforementioned multiple clock signals. The shift register area is located between the display area and the main wiring area. Let n be a natural number, and the first on terminal of the first output control transistor included in the unit circuit of the (n-1)th stage and the control terminal and the first on terminal of the third node pull-up transistor included in the unit circuit of the nth stage are connected to the same clock signal by a branch wiring, one end of the clock signal by the branch wiring is connected to one of the multiple clock signals by the trunk wiring.

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