Semiconductor device and method of manufacturing the same

Abstract

The application provides a semiconductor device and a preparation method thereof, which comprises a substrate, a source structure, a gate metal layer, a via, a channel layer and a drain structure, wherein the source structure is located on the substrate, the gate metal layer is located on the source structure, the via is arranged through the gate metal layer, the channel layer covers the bottom and the sidewall of the via, and the bottom of the channel layer is in contact with the source structure; a gate dielectric layer is arranged between the channel layer and the gate metal layer, the thickness of the middle position of the gate dielectric layer is greater than the thickness of the end position of the gate dielectric layer, the drain structure is located on the channel layer, and the top of the channel layer is in contact with the drain structure. The application is beneficial to improving the reliability of the device.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, and in particular, to a semiconductor device and a preparation method thereof. BACKGROUND

[0002] Semiconductor transistors, such as metal-oxide-semiconductor transistors (MOS transistors), have been used in various applications, such as power supply, power converter, switch, etc. Conventional MOS transistors adopt a planar structure, and with the development of semiconductor integrated circuit technology over time, MOS transistors adopt a stacked structure to realize transistor miniaturization. In the design of the stacked structure, the gate dielectric layer plays a role in isolation and current control, and the thickness or quality of the gate dielectric layer is directly related to the reliability of the device. If the thickness or quality of the gate dielectric layer does not meet the requirements, the reliability of the device will be affected. SUMMARY

[0003] The present application aims to provide a semiconductor device and a preparation method thereof, which is beneficial to improve the reliability of the device.

[0004] To achieve the above-mentioned purpose, the present application provides a semiconductor device, comprising:

[0005] a substrate;

[0006] a source structure located on the substrate;

[0007] a gate metal layer located on the source structure;

[0008] a via hole disposed through the gate metal layer;

[0009] a channel layer covering the bottom and sidewall of the via hole, the bottom of the channel layer being in contact with the source structure;

[0010] a gate dielectric layer interposed between the channel layer and the gate metal layer, the thickness of the middle position of the gate dielectric layer being greater than the thickness of the end position thereof;

[0011] a drain structure located on the channel layer, the top of the channel layer being in contact with the drain structure.

[0012] Optionally, the gate dielectric layer comprises a first portion, a second portion and a third portion from bottom to top in the vertical direction, and the maximum thickness of the second portion is greater than the thickness of the first portion and the third portion.

[0013] Optionally, the maximum thickness of the first portion is less than or equal to the thickness of the third portion.

[0014] Optionally, a first isolation material layer is further included between the gate metal layer and the source structure, and the channel layer is in contact with the source structure through the first isolation material layer.

[0015] Optionally, the channel layer has a protruding portion connecting the first isolation material layer, the first portion and the second portion.

[0016] Optionally, a sacrificial layer is further included on the gate dielectric layer and between part of the gate dielectric layer and part of the channel layer.

[0017] Optionally, the first portion is between the gate metal layer, the first isolation material layer and the channel layer, and a bottom of the first portion is in contact with the first isolation material layer; the second portion is between the gate metal layer, the sacrificial layer and the channel layer, and the second portion connects the first portion and the third portion; and the third portion is between the sacrificial layer, the drain structure and the second portion, and a top of the third portion is in contact with the drain structure.

[0018] Optionally, a second isolation material layer is further included, part of the second isolation material layer is between the gate metal layer and the drain structure, and part of the second isolation material layer is in contact with the third portion.

[0019] Optionally, a sidewall of the first portion in contact with the channel layer is curved.

[0020] Optionally, a cross section of the second portion is an irregular polygon.

[0021] Optionally, the gate dielectric layer is a silicon nitride layer or a silicon oxide layer; or the gate dielectric layer is a stack of at least two of a silicon nitride layer, a silicon oxide layer and a silicon oxynitride layer.

[0022] The present application further provides a method for manufacturing a semiconductor device, comprising:

[0023] providing a substrate;

[0024] forming a source structure on the substrate;

[0025] forming a gate metal layer on the source structure;

[0026] forming a via through the gate metal layer;

[0027] forming a channel layer covering a bottom and a sidewall of the via, a bottom of the channel layer being in contact with the source structure; and forming a gate dielectric layer sandwiched between the channel layer and the gate metal layer, a thickness of a middle position of the gate dielectric layer being greater than a thickness of an end position of the gate dielectric layer.

[0028] A drain structure is formed on the channel layer, and a top of the channel layer is in contact with the drain structure.

[0029] Optionally, a first isolation material layer is formed between the gate metal layer and the source structure, and the step of forming the via and the gate dielectric layer comprises:

[0030] The gate metal layer is etched to form a via penetrating through the gate metal layer;

[0031] A first deposition process is performed to form the gate dielectric layer covering a bottom and sidewalls of the via, and a thickness of the gate dielectric layer at the bottom and a bottom corner of the via is greater than a thickness of the gate dielectric layer at the sidewalls of the via;

[0032] A second deposition process is performed to increase the thickness of the gate dielectric layer at the bottom and the sidewalls of the via;

[0033] A portion of the gate dielectric layer at the bottom of the via and a portion of the first isolation material layer are etched to expose the source structure, and the bottom of the via extends into the source structure, and the bottom sidewall of the via has a side etching area.

[0034] Optionally, after the second deposition process is performed, a sacrificial layer is further formed to cover the gate dielectric layer, and when a portion of the gate dielectric layer at the bottom of the via is etched, a portion of the sacrificial layer at the bottom of the via is also etched, and after the channel layer is formed, the sacrificial layer is located between a portion of the gate dielectric layer and a portion of the channel layer.

[0035] Optionally, after the channel layer is formed, the channel layer covers the side etching area, so that the channel layer has a protruding portion, and the protruding portion connects the first isolation material layer and the gate dielectric layer.

[0036] Optionally, the gate dielectric layer is a silicon nitride layer or a silicon oxide layer, or the gate dielectric layer is a stack of at least two layers of a silicon nitride layer, a silicon oxide layer and a silicon oxynitride layer.

[0037] The semiconductor device and its fabrication method provided by this invention include: a substrate, a source structure, a gate metal layer, a via, a channel layer, and a drain structure. The source structure is located on the substrate, the gate metal layer is located on the source structure, the via is disposed through the gate metal layer, the channel layer covers the bottom and sidewalls of the via, and the bottom of the channel layer contacts the source structure. A gate dielectric layer is sandwiched between the channel layer and the gate metal layer, with a thickness greater in the middle than at its ends. The drain structure is located on the channel layer, and the top of the channel layer contacts the drain structure. This invention, by setting the thickness of the gate dielectric layer to be greater in the middle than at its ends, allows for different thicknesses at different locations of the gate dielectric layer, which is beneficial for improving the reliability of the device. Attached Figure Description

[0038] Figure 1 This is a cross-sectional schematic diagram of a semiconductor device provided in an embodiment of the present invention.

[0039] Figure 2 This is a partially enlarged schematic diagram of a semiconductor device provided in an embodiment of the present invention.

[0040] Figure 3 This is another cross-sectional schematic diagram of a semiconductor device provided in an embodiment of the present invention.

[0041] Figures 4 to 13 This is a cross-sectional schematic diagram of the corresponding steps in a method for fabricating a semiconductor device according to an embodiment of the present invention.

[0042] The attached figures are labeled as follows:

[0043] 10-Substrate; 20-Dielectric layer; 22-Electrical connector; 30-Source structure; 31-First source barrier layer; 32-Source metal layer; 33-Second source barrier layer; 34-Source semiconductor layer; 41-First isolation material layer; 42-Second isolation material layer; 43-Third isolation material layer; 44-Fourth isolation material layer; 50-Gate metal layer; 51-First gate metal layer; 52-Second gate metal layer; 54-Through hole; 60-Gate dielectric layer; 60a-First portion; 60b-Second portion; 60c-Third portion; 62-Sacrificial layer; 70-Channel layer; 70a-Protrusion; 80-Capping layer; 90-Drain structure; 91-Drain barrier layer; 92-Drain metal layer. Detailed Implementation

[0044] In order to make the purposes, advantages and features of the present application clearer, the following further describes the present application in detail with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all very simplified and not drawn to scale, and are only used to facilitate and clarify the purpose of assisting in the description of the embodiments of the present application. In addition, the structures shown in the drawings are often part of the actual structure. In particular, the emphasis shown in each drawing is different, and sometimes different scales are used.

[0045] Figure 1 A cross-sectional schematic diagram of a semiconductor device provided for the present embodiment is shown in Figure 2 A partial enlarged schematic diagram of a semiconductor device provided for the present embodiment is shown in Figure 2 A cross-sectional schematic diagram of a semiconductor device provided for the present embodiment is shown in Figure 1 A cross-sectional schematic diagram of a semiconductor device provided for the present embodiment is shown in Figure 1 A cross-sectional schematic diagram of a semiconductor device provided for the present embodiment is shown in Figure 2 The present embodiment provides a semiconductor device, which comprises a substrate 10, a source structure 30, a gate metal layer 50, a via 54, a channel layer 70 and a drain structure 90. The substrate 10 can be a silicon substrate, a gallium arsenide substrate, a germanium substrate, a germanium silicon substrate, a fully depleted silicon-on-insulator substrate, and the like. In the present embodiment, a dielectric layer 20 is further formed on the substrate 10. The dielectric layer 20 can be a stack structure of different material layers, such as a stack structure of an oxide layer and a nitride layer, or a single material layer, such as an oxide layer or a nitride layer, and the like. The dielectric layer 20 is formed with an electrical connecting member 22, which penetrates the dielectric layer 20 and is electrically connected to the substrate 10 and the source structure 30. The electrical connecting member 22 is formed by forming a connecting hole in the dielectric layer 20, forming a barrier layer covering the inner wall of the connecting hole, and forming a metal material to fill the connecting hole to form the electrical connecting member 22.

[0046] The source structure 30 is located on the substrate 10. Since the dielectric layer 20 is further formed on the substrate 10, the source structure 30 is located on the dielectric layer 20, and the source structure 30 extends in a straight line along a first direction (X direction). In the present embodiment, the source structure 30 comprises a first source barrier layer 31, a source metal layer 32, a second source barrier layer 33 and a source semiconductor layer 34 stacked in order from bottom to top. The materials of the first source barrier layer 31 and the second source barrier layer 33 can comprise TiN, respectively. The material of the source metal layer 32 can comprise W. The material of the source semiconductor layer 34 can comprise polysilicon, and the like. However, the above-mentioned materials are not limited.

[0047] The gate metal layer 50 is located on the source structure 30. The gate metal layer 50 comprises a first gate metal layer 51 and a second gate metal layer 52 stacked in order from bottom to top. The materials of the first gate metal layer 51 and the second gate metal layer 52 are different. The materials of the first gate metal layer 51 and the second gate metal layer 52 can comprise TiN and W, and the like. However, the above-mentioned materials are not limited.

[0048] Further, a first isolation material layer 41 is arranged between the gate metal layer 50 and the source structure 30, and the material of the first isolation material layer 41 can include one of a low-k dielectric material, an oxide, a nitride, a silicon oxynitride, and a silicon carbon oxynitride, and is not limited to the above materials.

[0049] The via 54 is arranged through the gate metal layer 50 and the first isolation material layer 41, and the bottom of the via 54 extends into the source structure 30. The sidewall of the bottom of the via 54 has a side etching area recessed to the first isolation material layer 41 and the gate dielectric layer 60.

[0050] The channel layer 70 covers the bottom and sidewall of the via 54, and the bottom of the channel layer 70 is in contact with the source structure 30. Specifically, the channel layer 70 is in contact with the source structure 30 through the first isolation material layer 41. The channel layer 70 has a protruding portion 70a connected to the first isolation material layer 41 and the gate dielectric layer 60. The material of the channel layer 70 can include doped or undoped polysilicon, and can also include one or more combinations of a metal silicide material, a ferroelectric material, a high-k dielectric material, and IGZO, and is not limited to the above materials. In the embodiment, the protruding portion 70a of the channel layer 70 has a recess on the side away from the first isolation material layer 41 and the gate dielectric layer 60 (as shown in FIG. 6B). Figure 2

[0051] Figure 3 Another cross-sectional schematic view of the semiconductor device provided in the embodiment. Please refer to FIG. 6B. Figure 3 The protruding portion 70a of the channel layer 70 can also be flush (without a recess) on the side away from the first isolation material layer 41 and the gate dielectric layer 60 in the vertical direction (Y direction).

[0052] The gate dielectric layer 60 is arranged between the channel layer 70 and the gate metal layer 50 and on the first isolation material layer 41, and the thickness of the middle position of the gate dielectric layer 60 is greater than the thickness of the end position of the gate dielectric layer 60. In the embodiment, the gate dielectric layer 60 can be a silicon nitride layer or a silicon oxide layer; or the gate dielectric layer 60 can be a stack of at least two layers of a silicon nitride layer, a silicon oxide layer, and a silicon oxynitride layer, and is not limited to this. In the embodiment, the gate dielectric layer 60 includes a first portion 60a, a second portion 60b, and a third portion 60c from bottom to top in the vertical direction (Y direction) (as shown in FIG. 6B). Figure 2 Figure 2 ​​In order to clearly show the three parts, the second part 60b is filled, the maximum thickness of the second part 60b is greater than the thickness of the first part 60a and the third part 60c, the maximum thickness of the first part 60a is less than or equal to the thickness of the third part 60c, the maximum thickness of the first part 60a is D1, the maximum thickness of the second part 60b is D2, and the thickness of the third part 60c is D3. The protrusion 70a of the channel layer 70 is connected to the first isolation material layer 41, the first part 60a and the second part 60b, and the sidewall of the first part 60a in contact with the channel layer 70 (the protrusion 70a) is curved; the cross section of the second part 60b is an irregular polygon (for example, it can be an irregular hexagon as shown), and the sidewall of the second part 60b in contact with the protrusion 70a is curved. In this embodiment, by setting the thickness of the middle position (the second part 60b) of the gate dielectric layer 60 to be greater than the thickness of the end position (the first part 60a and the third part 60c), the gate dielectric layer 60 has different thicknesses at different positions, avoiding the formed side etching area from completely penetrating through the gate dielectric layer 60, and thereby improving the reliability of the device. Figure 2

[0053] Further, a sacrifice layer 62 is further included, the sacrifice layer 62 is located on the gate dielectric layer 60 and between the gate dielectric layer 60 and the channel layer 70, the bottom of the sacrifice layer 62 is inclined and in contact with the second part 60b, and the top of the sacrifice layer 62 is in contact with the drain structure 90. The material of the sacrifice layer 62 can include doped or undoped polysilicon, and can also include one or more combinations of metal silicide material, ferroelectric material, high-k dielectric material and IGZO, and is not limited to the above-mentioned materials; the material of the sacrifice layer 62 can be the same as the material of the channel layer 70.

[0054] In this embodiment, the first part 60a is located between the gate metal layer 50, the first isolation material layer 41 and the channel layer 70, the top of the first part 60a is lower than the top of the first gate metal layer 51 or the top of the first part 60a is flush with the top of the first gate metal layer 51, and the bottom of the first part 60a is in contact with the first isolation material layer 41. The second part 60b is located between the gate metal layer 50, the sacrifice layer 62 and the channel layer 70, and the second part 60b connects the first part 60a and the third part 60c, and the top of the second part 60b is lower than the top of the gate metal layer 50. The third part 60c is located between the sacrifice layer 62, the drain structure 90 and the second part 60b, and the top of the third part 60c is in contact with the drain structure 90.

[0055] ​Further, a second isolation material layer 42 is filled between the adjacent gate metal layers 50, and a part of the second isolation material layer 42 is located between the gate metal layer 50 and the drain structure 90, and the part of the second isolation material layer 42 is in contact with the sidewall of the part of the third portion 60c; the gate dielectric layer 60, the sacrificial layer 62 and the channel layer 70 are in contact with the drain structure 90 through the part of the second isolation material layer 42. The material of the second isolation material layer 42 can include one of a low-k dielectric material, an oxide, a nitride, a nitride oxide and a carbon silicon nitride oxide, and is not limited to the above materials.

[0056] Further, a third isolation material layer 43 and a cap layer 80 are filled in the via 54, the cap layer 80 covers the top of the third isolation material layer 43, and the bottom of the cap layer 80 can be higher or lower than the top of the gate structure 50, or can be flush with the top of the gate structure 50, and the top of the cap layer 80 is in contact with the drain structure 90. In the embodiment, the material of the third isolation material layer 43 can include one of a low-k dielectric material, an oxide, a nitride, a nitride oxide and a carbon silicon nitride oxide; the material of the cap layer 80 can include at least one of an insulating material, a semiconductor material, a metal material and a metal silicide material, and is not limited to the above materials.

[0057] The drain structure 90 is located on the channel layer 70, and the top of the channel layer 70 is in contact with the drain structure 30. In the embodiment, the drain structure 90 includes a drain barrier layer 91 and a drain metal layer 92 stacked in turn from bottom to top, wherein the material of the drain barrier layer 91 can include TiN, and the material of the drain metal layer 92 can include W, and is not limited to the above materials.

[0058] Further, a fourth isolation material layer 44 is located between the adjacent drain structures 90, and the material of the fourth isolation material layer 44 can include one of a low-k dielectric material, an oxide, a nitride, a nitride oxide and a carbon silicon nitride oxide, and is not limited to the above materials.

[0059] The application further provides a preparation method of a semiconductor device, which is used for preparing the semiconductor device and includes the following steps:

[0060] Step S1: providing a substrate;

[0061] Step S2: forming a source structure on the substrate;

[0062] Step S3: forming a gate metal layer on the source structure;

[0063] Step S4: forming a via arranged through the gate metal layer;

[0064] Step S5: Form a channel layer covering the bottom and sidewalls of the via, with the bottom of the channel layer in contact with the source structure; and form a gate dielectric layer sandwiched between the channel layer and the gate metal layer, with the thickness of the gate dielectric layer at the middle position being greater than the thickness at its end position.

[0065] Step S6: Form the drain structure on the channel layer, with the top of the channel layer in contact with the drain structure.

[0066] Figures 4 to 13 This is a cross-sectional schematic diagram of the corresponding steps in the fabrication method of the semiconductor device provided in this embodiment, wherein... Figures 4 to 13 For preparation Figure 1 A cross-sectional schematic diagram of the corresponding steps in the provided semiconductor device. The following is in conjunction with... Figures 4 to 13 The method for fabricating the semiconductor device provided in this embodiment will be described in detail.

[0067] Execution step S1: Please refer to Figure 4 A substrate 10 is provided, which can be a silicon substrate, a gallium arsenide substrate, a germanium substrate, a germanium-silicon substrate, or a fully depleted silicon-on-insulator substrate, and is not limited thereto. In this embodiment, a dielectric layer 20 is also formed on the substrate 10. The dielectric layer 20 can be a stacked structure composed of different material layers, such as a stacked structure composed of an oxide layer and a nitride layer, or it can be a single material layer, such as an oxide layer or a nitride layer, and is not limited thereto. An electrical connector 22 is formed in the dielectric layer 20. The electrical connector 22 penetrates the dielectric layer 20 and is electrically connected to the substrate 10 and the source structure 30. The electrical connector 22 is formed by forming a connection hole in the dielectric layer 20, forming a barrier layer to cover the inner wall of the connection hole, and forming a metal material to fill the connection hole to form the electrical connector 22.

[0068] Execution step S2: Please refer to Figure 4 The source structure 30 is formed on the substrate 10, specifically on the dielectric layer 20. In this embodiment, the source structure 30 includes a first source barrier layer 31, a source metal layer 32, a second source barrier layer 33, and a source semiconductor layer 34 stacked sequentially from bottom to top. The materials of the first source barrier layer 31, the source metal layer 32, the second source barrier layer 33, and the source semiconductor layer 34 are as described above.

[0069] Execution step S3: Please refer to Figure 4 A first isolation material layer 41, a first gate metal layer 51, and a second gate metal layer 52 are sequentially located on the source structure 30; please refer to Figure 5, etching the second gate metal layer 52, the first gate metal layer 51 and the first isolation material layer 41 to expose the source structure 30, the first gate metal layer 51 and the second gate metal layer 52 form a gate metal layer 50, the first isolation material layer 41 is located between the gate metal layer 50 and the source structure 30, and the first isolation material layer 41, the first gate metal layer 51 and the second gate metal layer 52 are made of the same material as described above.

[0070] Further, please refer to Figure 6 , the second isolation material layer 42 is formed to fill between adjacent gate metal layers 50 and cover the gate metal layer 50, and the second isolation material layer 42 is made of the same material as described above.

[0071] Step S4 is performed: please refer to Figure 7 , the via 54 is formed to pass through the gate metal layer 50, specifically, the gate metal layer 50 is etched to form the via 54 passing through the gate metal layer 50, and the second isolation material layer 42 on the top of the gate metal layer 50 is etched when the via 54 is etched, so that the via 54 also passes through part of the second isolation material layer 42.

[0072] Step S5 is performed: please refer to Figure 8 , the step of forming the gate dielectric layer 60 includes: performing a first deposition process to form the gate dielectric layer 60 covering the bottom and sidewall of the via 54, the thickness of the gate dielectric layer 60 at the bottom and the corner of the bottom of the via 54 is greater than the thickness of the gate dielectric layer 60 at the sidewall of the via 54, and the first deposition process can be a plasma nitriding process. Because the first isolation material layer 41 and the gate metal layer 50 are made of different materials (the material of the deposition surface is different), the thickness of the gate dielectric layer 60 formed is different, so that the thickness of the gate dielectric layer 60 at the bottom and the corner of the bottom of the via 54 is greater than the thickness of the gate dielectric layer 60 at the sidewall of the via 54. A second deposition process is performed to increase the thickness of the gate dielectric layer 60 at the bottom and the sidewall of the via 54. After the first deposition process and the second deposition process are performed, the gate dielectric layer 60 is deposited on the surface of the second isolation material layer 42, and the thickness of the gate dielectric layer 60 at the bottom and the corner of the bottom of the via 54 is greater than the thickness of the gate dielectric layer 60 at the sidewall of the via 54. In this embodiment, the gate dielectric layer 60 can be a silicon nitride layer or a silicon oxide layer; or the gate dielectric layer 60 can be a stack of at least two of a silicon nitride layer, a silicon oxide layer and a silicon oxynitride layer, without being limited thereto.

[0073] Further, please refer to Figure 9 , after the second deposition process is performed, the sacrificial layer 62 is also formed to cover the gate dielectric layer 60, and the sacrificial layer 62 is made of the same material as described above.

[0074] Please refer to Figure 10, etching part of the sacrificial layer 62, part of the gate dielectric layer 60 and part of the first isolation material layer 41 at the bottom of the via hole 54 to expose the source structure 30 and make the bottom of the via hole 54 extend into the source structure 30, the bottom sidewall of the via hole 54 has a side etching area which is recessed to the first isolation material layer 41 and the gate dielectric layer 60; synchronously etching to remove the sacrificial layer 62 and the gate dielectric layer 60 at the top of the second isolation material layer 42.

[0075] Please refer to Figure 11 , forming a channel layer 70 covering the bottom and sidewall of the via hole 54, the bottom of the channel layer 70 is in contact with the source structure 30; after forming the channel layer 70, the channel layer 70 covers the side etching area, so that the channel layer 70 has a protruding part 70a connecting the first isolation material layer 41 and the gate dielectric layer 60, the side of the protruding part 70a away from the first isolation material layer 41 and the gate dielectric layer 60 has a recess (the recess direction is the same as the protruding direction of the protruding part 70a), or the side of the protruding part away from the first isolation material layer and the gate dielectric layer is flush in the vertical direction (without recess, not shown in the figure). The gate dielectric layer 60 is arranged between the channel layer 70 and the gate metal layer 50, the thickness of the middle position of the gate dielectric layer 60 is greater than the thickness of the end position of the gate dielectric layer 60, and the sacrificial layer 62 is arranged between part of the gate dielectric layer 60 and part of the channel layer 70, and the material of the channel layer 70 is as described above.

[0076] Further, please refer to Figure 12 , after forming the channel layer 70, further comprising: forming a third isolation material layer 43 to fill part of the depth of the via hole 54, and the material of the third isolation material layer 43 is as described above. Please refer to Figure 13 , after forming the third isolation material layer 43, further comprising: forming a capping layer 80 to fill the remaining depth of the via hole 54, the capping layer 80 covers the top of the third isolation material layer 43, the bottom of the capping layer 80 can be higher or lower than the top of the gate structure 50, or can be flush with the top of the gate structure 50, and the material of the capping layer 80 is as described above.

[0077] Performing step S6: please refer to Figure 1 , forming a drain structure 90 on the channel layer 70, the top of the channel layer 70 is in contact with the drain structure 90; the drain structure 90 includes a drain barrier layer 91 and a drain metal layer 92 stacked from bottom to top, and the materials of the drain barrier layer 91 and the drain metal layer 92 are as described above.

[0078] Further, please refer to Figure 1 , after forming the drain structure 90, further comprising: forming a fourth isolation material layer 44 between adjacent drain structures 90, and the material of the fourth isolation material layer 44 is as described above.

[0079] To sum up, in the semiconductor device and the preparation method thereof provided by the application, the semiconductor device comprises a substrate, a source structure, a gate metal layer, a via, a channel layer and a drain structure, wherein the source structure is located on the substrate, the gate metal layer is located on the source structure, the via is arranged through the gate metal layer, the channel layer covers the bottom and the sidewall of the via, the bottom of the channel layer is in contact with the source structure, a gate dielectric layer is arranged between the channel layer and the gate metal layer, the thickness of the middle position of the gate dielectric layer is greater than the thickness of the end position of the gate dielectric layer, the drain structure is located on the channel layer, and the top of the channel layer is in contact with the drain structure. The thickness of the middle position of the gate dielectric layer is greater than the thickness of the end position of the gate dielectric layer, so that the gate dielectric layer has different thicknesses at different positions, thereby improving the reliability of the device.

[0080] The above is only the preferred embodiment of the application, and does not limit the application. Any person skilled in the art can make any equivalent replacement, modification or change to the technical scheme and technical content disclosed by the application without departing from the scope of the technical scheme of the application, and the application still falls within the protection scope of the application.

Claims

1. A semiconductor device, characterized by, include: Substrate; The source structure is located on the substrate; A gate metal layer is located on the source structure; A through-hole is disposed throughout the gate metal layer; A channel layer covers the bottom and sidewalls of the via, and the bottom of the channel layer is in contact with the source structure; A gate dielectric layer is sandwiched between the channel layer and the gate metal layer. The thickness of the gate dielectric layer at its middle position is greater than the thickness at its two ends. The two sides at the middle position of the gate dielectric layer directly contact the channel layer and the gate metal layer, respectively. A drain structure is located on the channel layer, and the top of the channel layer is in contact with the drain structure.

2. The semiconductor device of claim 1, wherein, The gate dielectric layer comprises, from bottom to top, a first portion, a second portion, and a third portion in the vertical direction, wherein the maximum thickness of the second portion is greater than the thickness of the first portion and the third portion.

3. The semiconductor device of claim 2, wherein, The maximum thickness of the first part is less than or equal to the thickness of the third part.

4. The semiconductor device of claim 2, wherein, It also includes a first isolation material layer, which is located between the gate metal layer and the source structure, and the channel layer passes through the first isolation material layer and contacts the source structure.

5. The semiconductor device of claim 4, wherein, The channel layer has a protrusion that connects the first insulating material layer, the first portion, and the second portion.

6. The semiconductor device of claim 4, wherein, It also includes a sacrificial layer located on the gate dielectric layer and between a portion of the gate dielectric layer and a portion of the channel layer.

7. The semiconductor device of claim 6, wherein the first and second semiconductor layers are formed of a same material. The first portion is located between the gate metal layer, the first isolation material layer and the channel layer, and the bottom of the first portion is in contact with the first isolation material layer; The second portion is located between the gate metal layer, the sacrificial layer and the channel layer, and the second portion connects the first portion and the third portion; the third portion is located between the sacrificial layer, the drain structure and the second portion, and the top of the third portion contacts the drain structure.

8. The semiconductor device of claim 2, wherein, It also includes a second isolation material layer, a portion of which is located between the gate metal layer and the drain structure, and a portion of which is in contact with the third portion.

9. The semiconductor device of claim 2, wherein, The sidewall of the first portion in contact with the channel layer is curved.

10. The semiconductor device of claim 2, wherein, The cross-section of the second part is an irregular polygon.

11. The semiconductor device of claim 1, wherein, The gate dielectric layer is a silicon nitride layer or a silicon oxide layer; or, the gate dielectric layer is a stack of at least two of a silicon nitride layer, a silicon oxide layer, and a silicon oxynitride layer.

12. A method of manufacturing a semiconductor device, characterized by, include: Provide substrate; The source structure is formed on the substrate; A gate metal layer is formed on the source structure; A through-hole is formed in the gate metal layer; A channel layer is formed to cover the bottom and sidewalls of the via, and the bottom of the channel layer is in contact with the source structure; and a gate dielectric layer is formed between the channel layer and the gate metal layer, wherein the thickness of the middle position of the gate dielectric layer is greater than the thickness of its two ends, and the two sides of the middle position of the gate dielectric layer are in direct contact with the channel layer and the gate metal layer, respectively. A drain structure is formed on the channel layer, and the top of the channel layer is in contact with the drain structure.

13. The method of producing a semiconductor device according to Claim 12, wherein A first isolation material layer is formed between the gate metal layer and the source structure, and the steps of forming the via and the gate dielectric layer include: Etching the gate metal layer forms a via through the gate metal layer; A first deposition process is performed to form a gate dielectric layer covering the bottom and sidewalls of the via, wherein the thickness of the gate dielectric layer at the bottom and bottom angle of the via is greater than the thickness of the gate dielectric layer on the sidewalls of the via. A second deposition process is performed to increase the thickness of the gate dielectric layer at the bottom and sidewalls of the via; A portion of the gate dielectric layer and a portion of the first isolation material layer at the bottom of the via are etched to expose the source structure, such that the bottom of the via extends into the source structure, and the bottom sidewall of the via has a side-etched region.

14. The method of producing a semiconductor device according to Claim 13, wherein After performing the second deposition process, the process further includes forming a sacrificial layer covering the gate dielectric layer; and etching a portion of the gate dielectric layer at the bottom of the via and etching a portion of the sacrificial layer at the bottom of the via. After the channel layer is formed, the sacrificial layer is located between a portion of the gate dielectric layer and a portion of the channel layer.

15. The method of producing a semiconductor device according to Claim 13, wherein After the channel layer is formed, the channel layer covers the side etch region, such that the channel layer has a protrusion that connects the first isolation material layer and the gate dielectric layer.

16. The method for fabricating a semiconductor device as described in claim 12, characterized in that, The gate dielectric layer is a silicon nitride layer or a silicon oxide layer; or, the gate dielectric layer is a stack of at least two of a silicon nitride layer, a silicon oxide layer, and a silicon oxynitride layer.

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