Data transmission method, device, system and computer readable storage medium

Abstract

The present application discloses a data transmission method, device, system and computer-readable storage medium, and relates to the field of communication technology. The method includes: a first module performs convolution interleaving on symbols included in a plurality of first codewords obtained to obtain an interleaving result, wherein the first codeword is a codeword that encodes the first data using a first FEC code; second data including identification information is obtained according to the interleaving result, and the second data is transmitted to a second module. By performing convolution interleaving on symbols included in a plurality of first codewords, when a burst error occurs in the subsequent second data, the burst error will be dispersed into a plurality of symbols, thereby reducing the BER of the second data after error correction. In the case where the second data includes a second codeword, the identification information includes codeword boundary information of the second codeword, and there is no need to insert additional data as identification information, so that the data transmission cost is low.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to a data transmission method, device, system and computer-readable storage medium. Background Art

[0002] With the development of communication technology, encoding data according to forward error correction (FEC) code at the data transmitting end and decoding the received data with the same FEC code at the data receiving end has become a more widespread data transmission method. During the decoding process, the data receiving end performs error correction on the received data to correct the bit errors in the data. Due to the different distribution of bit errors in the data, the bit error rate (BER) before error correction may be different under the same BER.

[0003] For example, according to the distribution, the bit errors include random errors and non-random errors. Non-random errors are manifested as multiple errors concentrated in a shorter data sequence. Generally, based on the same BER before error correction, non-random errors will lead to a higher BER after error correction than random errors. Therefore, a data transmission method is needed, which, based on FEC, swaps the data position in an interleaving manner at the data transmitting end, and restores the data position in a deinterleaving manner at the data receiving end, so that the distribution of non-random errors after deinterleaving approaches that of random errors, thereby reducing the BER after error correction. Summary of the invention

[0004] The present application proposes a data transmission method, device, system and computer-readable storage medium for realizing data transmission in combination with convolution interleaving based on FEC.

[0005] In a first aspect, a data transmission method is provided, the method comprising: a first module performs convolution interleaving on symbols included in a plurality of acquired first codewords to obtain an interleaving result, wherein the first codeword is a codeword obtained by encoding first data using a first FEC code; then, the first module obtains second data including identification information based on the interleaving result, and transmits the second data to a second module, wherein when the second data includes a second codeword, the identification information includes codeword boundary information of the second codeword.

[0006] In the method, by performing convolution interleaving on the symbols included in the multiple first codewords, when a burst error occurs in the subsequent second data, the burst error will be dispersed into multiple symbols, thereby reducing the BER of the second data after error correction. Furthermore, in the case where the second data includes the second codeword, the identification information is the codeword boundary information of the second codeword, and there is no need to additionally insert identification information for indicating the starting interleaving position for performing convolution interleaving on the symbols included in the multiple first codewords, so that the data transmission cost is low, the applicability to data transmission scenarios with limited bandwidth or phase-locked loop frequency is high, and the implementation complexity of the data transmission system for executing the method is low.

[0007] In a possible implementation, the symbols included in the obtained multiple first code words are convolutionally interleaved to obtain an interleaving result, including: inputting the symbols included in the multiple first code words into multiple first delay units of a convolution interleaver, convolutionally interleaving the symbols included in the polled multiple first code words through the multiple first delay units, obtaining multiple first bit groups output by polling of the multiple first delay units, and using the multiple first bit groups output by polling of the multiple first delay units as the interleaving result, wherein a first bit group includes symbols output by polling of multiple first delay units once. In the process of obtaining the interleaving result by convolution interleaving, the method performs convolution interleaving on the symbols included in the multiple first code words without introducing additional data. Therefore, the amount of data for performing convolution interleaving is small, and the efficiency of convolution interleaving is high.

[0008] In one possible implementation, the interleaving result includes n first bit groups output by polling multiple first delay units n times, and second data including identification information is obtained according to the interleaving result, including: encoding the n first bit groups output by polling multiple first delay units n times according to the second FEC code to obtain m second code words, and obtaining second data according to the m second code words; wherein the number of bits corresponding to the n first bit groups is equal to the number of bits included in the information bits of the code words of the m second FEC codes, m and n are both positive integers, and m is less than or equal to n.

[0009] In this implementation, m second code words are obtained by encoding n first bit groups according to the second FEC code. The receiving end can obtain the starting interleaving position for convolution interleaving of symbols included in multiple first code words by obtaining the code word boundary information of the second code word, and then perform convolution deinterleaving according to the starting interleaving position. Since there is no need to insert additional identification information, the data transmission cost of this implementation is low, and it is highly applicable to data transmission scenarios with limited bandwidth or phase-locked loop frequency.

[0010] In a possible implementation, the second data does not include the second codeword, the interleaving result includes n first bit groups output by polling multiple first delay units n times, and the second data including identification information is obtained according to the interleaving result, including: according to the format of the reference data frame, k target data frames are obtained based on the n first bit groups output by polling multiple first delay units n times, and the second data is obtained according to the k target data frames; wherein the target data frame includes frame synchronization information, the frame synchronization information is used as identification information, the number of bits corresponding to the n first bit groups is less than or equal to the number of bits included in the k target data frames, k and n are both positive integers, and k is less than or equal to n. In the case where the second data does not include the second codeword, it means that the method can be applied to the scenario of non-concatenated coding, and the applicable scenario of the method is relatively flexible.

[0011] In a possible implementation, the second data does not include the second codeword, and the symbols included in the obtained multiple first codewords are convolutionally interleaved to obtain an interleaving result, including: inputting at least one identification information and the symbols included in the multiple first codewords into multiple first delay units of the convolution interleaver, and convolutionally interleaving the at least one identification information polled and the symbols included in the multiple first codewords through the multiple first delay units to obtain multiple second bit groups polled and output by the multiple first delay units, and using the multiple second bit groups polled and output by the multiple first delay units as the interleaving result; wherein at least one second bit group includes the symbols polled and output by the multiple first delay units once, or at least one second bit group includes the identification information and the symbols polled and output by the multiple first delay units once, and the identification information is used to indicate the starting interleaving position of convolutionally interleaving the symbols included in the multiple first codewords. In the case of obtaining the interleaving result through this implementation, the specific form of the identification information can be set according to experience or actual needs, and the identification information can indicate the starting interleaving position of convolutionally interleaving the symbols included in the multiple first codewords, and the type of the identification information is relatively flexible.

[0012] In a possible implementation, a starting interleaving position for convolution interleaving of symbols included in the plurality of first codewords is located in any first delay unit among the plurality of first delay units, and the location of the starting interleaving position is relatively flexible.

[0013] In one possible implementation, symbols included in multiple first codewords are input into multiple first delay units of a convolution interleaver in the form of a first data stream, a transmission rate of the first data stream is greater than or equal to 100 gigabits per second (Gbps), and a rate at which symbols included in multiple first codewords are input into multiple first delay units of the convolution interleaver is relatively high.

[0014] In a possible implementation, the first data stream is transmitted to a plurality of first delay units of the convolution interleaver through at least one channel of an attachment unit interface (AUI), and the manner of transmitting the first data stream is relatively flexible.

[0015] In a second aspect, a data transmission method is provided, the method comprising: a second module receives second data including identification information transmitted by a first module, the second data is obtained based on an interleaving result obtained by convolution interleaving symbols included in multiple first codewords, the first codeword is a codeword for encoding the first data using a first FEC code, and when the second data includes the second codeword, the identification information includes codeword boundary information of the second codeword; according to the identification information, a starting interleaving position for convolution interleaving the symbols included in the multiple first codewords and data to be deinterleaved in the second data are obtained; and convolution deinterleaving the data to be deinterleaved is performed based on the starting interleaving position to obtain multiple first codewords.

[0016] In this method, since the second data is obtained based on the interleaving result obtained by convolution interleaving the symbols included in the multiple first codewords, when a burst error occurs in the second data, the burst error will be dispersed into multiple symbols, thereby reducing the BER of the second data after error correction. Furthermore, in the case where the second data includes the second codeword, the identification information is the codeword boundary information of the second codeword, and there is no need to insert additional identification information in the second data for indicating the starting interleaving position of convolution interleaving the symbols included in the multiple first codewords, so that the data transmission cost is low, the applicability to data transmission scenarios with limited bandwidth or phase-locked loop frequency is high, and the implementation complexity of the data transmission system used to execute the method is low.

[0017] In a possible implementation, obtaining the starting interleaving position for convolution interleaving the symbols included in the plurality of first codewords and the data to be deinterleaved in the second data according to the identification information includes: obtaining at least one second codeword included in the second data according to the codeword boundary information of the second codeword; obtaining the starting position of at least one second codeword, and using the starting position as the starting interleaving position for convolution interleaving the symbols included in the plurality of first codewords; decoding the at least one second codeword to obtain the data to be deinterleaved. This implementation is applicable to the scenario of cascade coding.

[0018] In a possible implementation, when the second data does not include the second codeword, the identification information is frame synchronization information, and the starting interleaving position for convolution interleaving the symbols included in the multiple first codewords and the data to be deinterleaved in the second data are obtained according to the identification information, including: obtaining at least one target data frame included in the second data according to the frame synchronization information; obtaining the starting position of the frame data of at least one target data frame, and using the starting position as the starting interleaving position for convolution interleaving the symbols included in the multiple first codewords; using the frame data included in at least one target data frame as the data to be deinterleaved. This implementation is applicable to the scenario of non-concatenated coding, and the second data includes the target data frame.

[0019] In a possible implementation, the data to be deinterleaved includes multiple third bit groups, and one third bit group includes the symbol of the first codeword output by polling multiple first delay units of the convolution interleaver once; the data to be deinterleaved is convolutionally deinterleaved based on the starting interleaving position to obtain multiple first codewords, including: obtaining the starting deinterleaving position corresponding to the starting interleaving position in multiple second delay units of the convolution deinterleaver; inputting the multiple third bit groups from the starting deinterleaving position into multiple second delay units, and convolutionally deinterleaving the symbols included in the polled multiple third bit groups through the multiple second delay units; obtaining the symbols included in the multiple first codewords polled and output by the multiple second delay units, and obtaining the multiple first codewords according to the symbols included in the multiple first codewords. In this implementation, the third bit group does not include identification information, and the efficiency of performing convolutional deinterleaving is relatively high.

[0020] In a possible implementation, when the second data does not include the second codeword, the identification information is used to indicate the starting interleaving position for convolution interleaving the symbols included in the multiple first codewords; obtaining the starting interleaving position for convolution interleaving the symbols included in the multiple first codewords and the data to be deinterleaved in the second data according to the identification information includes: obtaining the starting interleaving position for convolution interleaving the symbols included in the multiple first codewords indicated by the identification information; using the data at the starting interleaving position and the data after the starting interleaving position in the second data as the data to be deinterleaved. This implementation is applicable to the scenario of non-concatenated coding, and the second data does not include the target data frame.

[0021] In a possible implementation, the data to be deinterleaved includes multiple fourth bit groups, at least one fourth bit group includes the symbol of the first codeword output by polling multiple first delay units of the convolution interleaver once, or at least one fourth bit group includes identification information and symbols output by polling multiple first delay units once; performing convolution deinterleaving on the data to be deinterleaved based on the starting interleaving position to obtain multiple first codewords includes: obtaining the starting deinterleaving position corresponding to the starting interleaving position in multiple second delay units of the convolution deinterleaver; inputting the multiple fourth bit groups from the starting deinterleaving position into multiple second delay units, performing convolution deinterleaving on the symbols included in the polled multiple fourth bit groups, or the identification information and symbols included in the multiple fourth bit groups through the multiple second delay units; obtaining the symbols and identification information included in the multiple first codewords polled and output by the multiple second delay units, and obtaining the multiple first codewords according to the symbols included in the multiple first codewords. This implementation can be applied to performing convolution deinterleaving on the fourth bit group including the identification information.

[0022] In a possible implementation manner, the starting deinterleaving position is located at any second delay unit among the plurality of second delay units, and the position of the starting deinterleaving position is relatively flexible.

[0023] In a possible implementation, the plurality of second delay units of the convolutional deinterleaver output the symbols included in the plurality of first codewords in the form of a second data stream, and the transmission rate of the second data stream is greater than or equal to 100 Gbps. The plurality of second delay units output the symbols included in the plurality of first codewords at a higher rate.

[0024] In a possible implementation, the plurality of second delay units of the convolutional deinterleaver output the second data stream through at least one channel of the AUI, and the manner of transmitting the second data stream is relatively flexible.

[0025] In a third aspect, a data transmission device is provided, which is applied to a first module and includes:

[0026] an interleaving unit, configured to perform convolution interleaving on symbols included in the acquired plurality of first codewords to obtain an interleaving result, wherein the first codeword is a codeword for encoding the first data using the first FEC code;

[0027] an acquiring unit, configured to acquire second data including identification information according to the interleaving result, wherein when the second data includes a second codeword, the identification information includes codeword boundary information of the second codeword;

[0028] The transmission unit is used to transmit the second data to the second module.

[0029] In one possible implementation, an interleaving unit is used to input symbols included in multiple first code words into multiple first delay units of a convolution interleaver, and convolutionally interleave the symbols included in the polled multiple first code words through the multiple first delay units to obtain multiple first bit groups polled and output by the multiple first delay units, wherein a first bit group includes symbols output by polling multiple first delay units once; and the multiple first bit groups polled and output by the multiple first delay units are used as interleaving results.

[0030] In one possible implementation, the interleaving result includes n first bit groups output by polling multiple first delay units n times, and an acquisition unit is used to encode the n first bit groups output by polling multiple first delay units n times according to a second FEC code to obtain m second code words, where the number of bits corresponding to the n first bit groups is equal to the number of bits included in the information bits of the code words of the m second FEC codes, and m and n are both positive integers, and m is less than or equal to n; and the second data is obtained according to the m second code words.

[0031] In one possible implementation, the second data does not include a second codeword, the interleaving result includes n first bit groups output by polling multiple first delay units n times, and an acquisition unit is used to acquire k target data frames in accordance with the format of a reference data frame and based on the n first bit groups output by polling multiple first delay units n times, the target data frames include frame synchronization information, the frame synchronization information is used as identification information, the number of bits corresponding to the n first bit groups is less than or equal to the number of bits included in the k target data frames, k and n are both positive integers, and k is less than or equal to n; the second data is obtained according to the k target data frames.

[0032] In one possible implementation, the second data does not include the second codeword, and the interleaving unit is used to input at least one identification information and symbols included in multiple first codewords into multiple first delay units of a convolution interleaver, and convolutionally interleave the at least one identification information polled and the symbols included in multiple first codewords through the multiple first delay units to obtain multiple second bit groups polled and output by the multiple first delay units, at least one second bit group includes symbols output by polling multiple first delay units once, or at least one second bit group includes identification information and symbols output by polling multiple first delay units once, and the identification information is used to indicate the starting interleaving position for convolutionally interleaving the symbols included in the multiple first codewords; the multiple second bit groups polled and output by the multiple first delay units are used as interleaving results.

[0033] In a possible implementation manner, a starting interleaving position for performing convolution interleaving on symbols included in the plurality of first codewords is located at any first delay unit among the plurality of first delay units.

[0034] In a possible implementation, symbols included in the multiple first codewords are input into multiple first delay units of the convolution interleaver in the form of a first data stream, and a transmission rate of the first data stream is greater than or equal to 100 Gbps.

[0035] In a possible implementation, the first data stream is transmitted to a plurality of first delay units of a convolutional interleaver through at least one channel of the AUI.

[0036] In a fourth aspect, a data transmission device is provided, which is applied to the second module and includes:

[0037] an acquisition unit, configured to receive second data including identification information transmitted by the first module, the second data being acquired according to an interleaving result obtained by performing convolution interleaving on symbols included in a plurality of first codewords, the first codeword being a codeword for encoding the first data using a first FEC code, and in a case where the second data includes the second codeword, the identification information includes codeword boundary information of the second codeword;

[0038] The acquiring unit is further used to acquire, according to the identification information, a starting interleaving position for performing convolution interleaving on symbols included in the plurality of first code words and data to be deinterleaved in the second data;

[0039] The deinterleaving unit is used to perform convolution deinterleaving on the data to be deinterleaved based on the starting interleaving position to obtain multiple first code words.

[0040] In one possible implementation, an acquisition unit is used to acquire at least one second codeword included in the second data based on codeword boundary information of the second codeword; acquire a starting position of at least one second codeword, and use the starting position as a starting interleaving position for convolution interleaving symbols included in multiple first codewords; and decode at least one second codeword to obtain data to be deinterleaved.

[0041] In one possible implementation, when the second data does not include the second codeword, the identification information is frame synchronization information, and an acquisition unit is used to obtain at least one target data frame included in the second data according to the frame synchronization information; obtain the starting position of the frame data of the at least one target data frame, and use the starting position as the starting interleaving position; and use the frame data included in the at least one target data frame as data to be deinterleaved.

[0042] In one possible implementation, the data to be deinterleaved includes multiple third bit groups, and one third bit group includes symbols of a first codeword output by polling multiple first delay units of a convolutional interleaver once; a deinterleaving unit is used to obtain a starting deinterleaving position corresponding to a starting interleaving position in multiple second delay units of the convolutional deinterleaver; the multiple third bit groups are input from the starting deinterleaving position into multiple second delay units, and convolution deinterleaving is performed on the symbols included in the polled multiple third bit groups through the multiple second delay units; symbols included in multiple first codewords polled and output by multiple second delay units are obtained, and multiple first codewords are obtained according to the symbols included in the multiple first codewords.

[0043] In one possible implementation, when the second data does not include the second codeword, the identification information is used to indicate the starting interleaving position for convolution interleaving the symbols included in the multiple first codewords; an acquisition unit is used to obtain the starting interleaving position for convolution interleaving the symbols included in the multiple first codewords indicated by the identification information; and the data located at the starting interleaving position and the data after the starting interleaving position in the second data are used as data to be deinterleaved.

[0044] In one possible implementation, the data to be deinterleaved includes multiple fourth bit groups, at least one fourth bit group includes the symbol of the first codeword output by polling multiple first delay units of the convolution interleaver once, or at least one fourth bit group includes identification information and symbols output by polling multiple first delay units once; a deinterleaving unit is used to obtain a starting deinterleaving position corresponding to a starting interleaving position in multiple second delay units of the convolution deinterleaver; the multiple fourth bit groups are input from the starting deinterleaving position into multiple second delay units, and convolution deinterleaving is performed on the symbols included in the polled multiple fourth bit groups, or the identification information and symbols included in the multiple fourth bit groups through the multiple second delay units; the symbols and identification information included in the multiple first codewords output by polling multiple second delay units are obtained, and the multiple first codewords are obtained according to the symbols included in the multiple first codewords.

[0045] In a possible implementation manner, the starting deinterleaving position is located at any second delay unit among the multiple second delay units.

[0046] In a possible implementation, the plurality of second delay units of the convolutional deinterleaver output the symbols included in the plurality of first codewords in the form of a second data stream, and a transmission rate of the second data stream is greater than or equal to 100 Gbps.

[0047] In a possible implementation, the plurality of second delay units of the convolutional deinterleaver output the second data stream through at least one channel of the AUI.

[0048] In a fifth aspect, a data transmission system is provided, the system comprising a first module and a second module, the first module being used to execute any data transmission method in the above-mentioned first aspect, and the second module being used to execute any data transmission method in the above-mentioned second aspect.

[0049] In a sixth aspect, a computer system is provided, the computer system includes a processor, the processor includes a first module or a second module, when the processor includes the first module, when the processor executes a program instruction or code, the computer system implements any data transmission method in the first aspect, and when the processor includes the second module, when the processor executes a program instruction or code, the computer system implements any data transmission method in the second aspect. Exemplarily, the computer system also includes a memory, the memory is used to store the above-mentioned program instructions or codes.

[0050] In the seventh aspect, a computer-readable storage medium is provided, in which at least one program instruction or code is stored, and the program instruction or code is executed by a computer, and the computer includes a first module or a second module; when the computer includes the first module, the program instruction or code is executed by the computer so as to enable the computer to implement any data transmission method in the first aspect; when the computer includes the second module, the program instruction or code is executed by the computer so as to enable the computer to implement any data transmission method in the second aspect.

[0051] In an eighth aspect, a communication device is provided, the device comprising: a transceiver, a memory and a processor. The transceiver, the memory and the processor communicate with each other through an internal connection path, the memory is used to store instructions, the processor is used to execute instructions stored in the memory to control the transceiver to send and receive signals, and the processor comprises a first module or a second module. In the case where the processor comprises the first module, when the processor executes the instructions stored in the memory, the processor executes any of the data transmission methods in the first aspect, and in the case where the processor comprises the second module, when the processor executes the instructions stored in the memory, the processor executes any of the data transmission methods in the second aspect.

[0052] Illustratively, there are one or more processors and one or more memories.

[0053] For example, the memory may be integrated with the processor, or the memory may be provided separately from the processor.

[0054] In the specific implementation process, the memory can be a non-transitory memory, such as a read-only memory (ROM), which can be integrated with the processor on the same chip or can be set on different chips. This application does not limit the type of memory and the setting method of the memory and the processor.

[0055] In the ninth aspect, a computer program product is provided, comprising: computer program instructions or codes, the computer program instructions or codes are executed by a computer, and the computer comprises a first module or a second module; in the case where the computer comprises the first module, when the computer program instructions or codes are executed by the computer, the computer executes any of the data transmission methods in the first aspect; in the case where the computer comprises the second module, when the computer program instructions or codes are executed by the computer, the computer executes any of the data transmission methods in the second aspect.

[0056] In the tenth aspect, a chip is provided, which includes a processor, the processor includes a first module or a second module, the processor is used to run program instructions or codes, when the processor includes the first module, the device including the chip executes any data transmission method in the first aspect, when the processor includes the second module, the device including the chip executes any data transmission method in the second aspect.

[0057] Exemplarily, the chip further includes: an input interface, an output interface and the above-mentioned memory, the input interface, the output interface, the processor and the memory are connected via an internal connection path, and the memory is used to store the above-mentioned program instructions or codes.

[0058] It should be understood that the beneficial effects achieved by the technical solutions of the third to tenth aspects of the present application and their corresponding possible implementation methods can be referred to the technical effects of the above-mentioned first and second aspects and their corresponding possible implementation methods, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] Figure 1 is a schematic diagram of random bit errors and burst bit errors provided in an embodiment of the present application;

[0060] Figure 2 It is a schematic diagram of the use process of an interleaver and a deinterleaver provided in an embodiment of the present application;

[0061] Figure 3 is a schematic diagram of an interleaving process provided by an embodiment of the present application;

[0062] Figure 4 is a schematic diagram of a starting interlacing position provided in an embodiment of the present application;

[0063] Figure 5 It is a schematic diagram of an implementation scenario provided by an embodiment of the present application;

[0064] Figure 6 is a schematic diagram of another implementation scenario provided by an embodiment of the present application;

[0065] Figure 7 It is a schematic diagram of another implementation scenario provided by an embodiment of the present application;

[0066] Figure 8 is a flow chart of a data transmission method provided in an embodiment of the present application;

[0067] Fig. 9 is a schematic diagram of a process for obtaining second data provided by an embodiment of the present application;

[0068] Fig.10 is another schematic diagram of a process for obtaining second data provided in an embodiment of the present application;

[0069] Fig.11 is another schematic diagram of a process for obtaining second data provided in an embodiment of the present application;

[0070] Fig.12 is a schematic diagram of another process of obtaining second data provided in an embodiment of the present application;

[0071] Fig.13 It is a structural schematic diagram of a data transmission device provided in an embodiment of the present application;

[0072] Fig.14 is a structural schematic diagram of another data transmission device provided in an embodiment of the present application;

[0073] Fig.15 is a schematic diagram of the structure of a computer system provided in an embodiment of the present application;

[0074] Fig.16 It is a structural diagram of another computer system provided in an embodiment of the present application. DETAILED DESCRIPTION

[0075] The terms used in the implementation method of this application are only used to explain the embodiments of this application, and are not intended to limit this application. The embodiments of this application are described below in conjunction with the accompanying drawings.

[0076] In the process of data transmission, bit errors are an inevitable problem due to environmental interference and system errors. Bit errors are bits that are inconsistent between the data received by the data receiving end and the data sent by the data sending end. Bit errors in data may cause the data transmission system to crash and data loss. In addition, the occurrence of bit errors may also affect communication delays and user experience such as video, games, and calls. Therefore, the number of bit errors in the received data, that is, the bit error rate (BER) of the data, has always been a measure of the performance of the communication system.

[0077] The smaller the BER of data, the higher the reliability of data transmission. Therefore, by limiting the BER of received data, the reliability of the data transmission system can be guaranteed. For example, the Institute of Electrical and Electronics Engineers (IEEE) 802.3 400 Gigabit Ethernet (GE) standard requires that the BER of the receiving end data entering the media access control (MAC) layer be lower than 1e-13, which is 1x10. -13 The meaning is the same. Since the BER of data when it is transmitted through the link to the receiving end is about 2e-4, 2e-4 is the same as 2x10 -4 The meaning is the same, therefore, the FEC code is used to encode the data at the data transmitting end, and the same FEC code is used to decode the received data at the data receiving end, thereby correcting the bit errors in the received data, which becomes a way to eliminate the bit errors that occur during data transmission. After the bit errors in the data are corrected based on the FEC code, the BER of the received data is lower.

[0078] According to the distribution, the bit errors include random bit errors and non-random bit errors. The non-random bit errors may also be called burst errors. Figure 1 is a schematic diagram of a random bit error and a burst bit error scenario provided by an embodiment of the present application. Figure 1 In the figure, b represents correct data and y represents bit error. Figure 1 (1) in the equation represents the distribution of random bit errors. Figure 1 (2) in the figure represents the distribution of burst errors. Figure 1 The BER of the data shown in (1) and (2) is the same.

[0079] Due to the different distribution of bit errors in data, the BER after error correction may be different when the BER before error correction is the same. Under most data transmission conditions, based on the same BER before error correction, burst errors will lead to a higher BER after error correction than random errors. Therefore, interleaving data through an interleaver can further reduce the BER after error correction for burst errors.

[0080] Figure 2 This is a schematic diagram of the use process of an interleaver and a deinterleaver provided in an embodiment of the present application. The data position is swapped by interleaving at the data transmitting end, and the data position is restored by deinterleaving at the data receiving end, so that the burst errors that occur when the data is transmitted through the transmission channel are dispersed, so that the distribution of the burst errors after deinterleaving approaches random errors, thereby reducing the BER after error correction. Figure 2 As shown, the data transmitter can perform FEC encoding on the data through an FEC encoder before interleaving, and interleave the FEC-encoded data through an interleaver. The interleaved data is transmitted to the receiving end through a channel, and the receiving end can deinterleave the received data through a deinterleaver, and after deinterleaving, the data is FEC decoded by an FEC decoder. The FEC encoder at the transmitting end and the FEC decoder at the receiving end use the same FEC code, such as a Reed-Solomon (RS) code, a Bose-Chaudhuri-Hocquenghem (BCH) code, an extended BCH code, a Hamming code, an extended Hamming code, a staircase code, a low-density parity-check (LDPC) code, a turbo code, or a turbo product code (TPC). The FEC code mentioned in other parts of this application can also be a Reed-Solomon (RS) code, a Bose-Chaudhuri-Hocquenghem (BCH) code, an extended BCH code, a Hamming code, an extended Hamming code, a staircase code, a low-density parity-check (LDPC) code, a turbo code or a turbo product code (TPC).

[0081] In some embodiments, the interleaver may include a block interleaver and a convolution interleaver. Figure 3 is a schematic diagram of an interleaving process provided by an embodiment of the present application, wherein: Figure 3(1) is a schematic diagram of the packet interleaver interleaving data. Figure 3 (2) in FIG. 1 is a schematic diagram of a convolution interleaver interleaving data. Figure 3 Taking (1) in the example, at the data transmitting side (transmitter, Tx), codewords (codeword, cw) A to D encoded according to the first FEC code are arranged into four rows, and then output in columns with the symbol of the FEC codeword as the granularity to form interleaved data. Figure 3 In (1), a represents the symbols included in cwA, b represents the symbols included in cwB, c represents the symbols included in cwC, and d represents the symbols included in cwD.

[0082] by Figure 3 Taking (2) in the example, the convolution interleaver includes multiple delay units, and the delay units can correspond to Figure 3 The delay line shown in (2) in FIG. 1 is used to determine the delay length corresponding to each delay line according to the delay block length and delay block number of each delay line. Figure 3 As shown in (2), the number of delay rows is 4. In order from top to bottom, the four delay rows can be delay row 0, delay row 1, delay row 2 and delay row 3. The delay block can be implemented by a linear feedback shift register (LFSR), and the delay block can store data. Exemplarily, when the size of the delay blocks in each delay row is the same, the number of delay blocks in each delay row is different; when the size of the delay blocks in each delay row is different, the number of delay blocks in each delay row is the same. The input side and the output side of the convolution interleaver each have a switchable connection switch, and the two connection switches are used to connect a delay row at the same time. As shown Figure 3 As shown in (2), the symbols of the FEC codeword can enter the convolution interleaver by column. Every time a symbol enters from the input side, a symbol will be output from the output side, and then the connection switches on both sides will switch to the next delay row. Multiple delay rows can be polled in the order of 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, ... Figure 3 In (2), the delay block is represented by D, and the data from cwA to cwD stored in the delay block is represented by x.

[0083] Since the convolution interleaver includes multiple delay units, each of which has a different delay length, the receiving end of the data needs to determine the starting interleaving position for interleaving the symbols to obtain the correct data when deinterleaving. In the embodiment of the present application, the starting interleaving position may also be referred to as the synchronization position. Since the multiple delay units input and output symbols in a polling manner, the starting interleaving position appears periodically in the data stream after convolution interleaving. Figure 4 is a schematic diagram of a starting interleaving position provided in an embodiment of the present application, Figure 4 The data flow shown can be Figure 3 The data stream after convolution interleaving shown in (2) in the data stream, in which the starting interleaving position is Figure 4 The circle position in . Figure 4 The process of convolutionally deinterleaving the interleaved data stream is also shown, see Figure 4 , multiple symbols received through the channel are polled and input into multiple delay units of the convolutional deinterleaver, multiple symbols are convolutionally deinterleaved through the multiple delay units of the convolutional deinterleaver, and cwA to cwD are obtained according to the symbols polled and output by the multiple delay units of the convolutional deinterleaver.

[0084] The embodiment of the present application provides a data transmission method for realizing data transmission by combining convolution interleaving based on FEC. The method can be applied to Figure 5 For the implementation scenario shown, see Figure 5 The implementation scenario includes a first module 101 and a second module 102, and the first module 101 and the second module 102 are communicatively connected. Exemplarily, the first module 101 is included in a first device, and the second module 102 is included in a second device. The first module 101 and the second module 102 may also be included in the same device. The device where the first module 101 and the second module 102 are located may be a network device or other device based on an Ethernet interface.

[0085] Figure 5 The implementation scenario shown can be combined with the scenario of cascade coding, that is, the implementation environment of the method can be as follows Figure 6 See Figure 6, the first module 101 can perform encoding according to the first FEC code, convolution interleaving and encoding according to the second FEC code, and transmit the data obtained by encoding according to the second FEC code to the second module 102 through the channel, and the second module 102 can perform decoding according to the second FEC code, convolution deinterleaving and decoding according to the first FEC code. In a possible implementation, after the first module 101 performs encoding according to the second FEC code to obtain data, it can also interleave the data and transmit the interleaved data encoded by the second FEC code to the second module 102 through the channel. Correspondingly, the second module 102 can also deinterleave the interleaved data encoded by the second FEC code to obtain the data encoded by the second FEC code, and then perform subsequent operations such as decoding according to the second FEC code. Among them, the method of interleaving the data obtained by encoding according to the second FEC code includes but is not limited to group interleaving and convolution interleaving. In the case where the interleaving method is group interleaving, the method of deinterleaving the interleaved data encoded according to the second FEC code by the second module 102 is group deinterleaving. When the interleaving method is convolution interleaving, the second module 102 deinterleaves the interleaved data encoded according to the second FEC code in a convolution deinterleaving manner.

[0086] In addition, the above Figure 6 The first module 101 in the example uses two interleavings, and the first interleaving is convolution interleaving, and the second interleaving is convolution interleaving or group interleaving. In a possible implementation, the method provided in the embodiment of the present application can also support the first module 101 to use group interleaving for the first interleaving and convolution interleaving for the second interleaving. Correspondingly, the second module 102 performs two deinterleavings, the first deinterleaving is group deinterleaving, and the second deinterleaving is convolution deinterleaving. No matter which order the convolution interleaving or convolution deinterleaving is performed in, the convolution interleaving and convolution deinterleaving methods provided in the embodiment of the present application can be referred to.

[0087] Figure 5 The implementation scenario shown can also be combined with the non-concatenated coding scenario, that is, the implementation environment of the method can be as follows: Figure 7 See Figure 7 The first module 101 can perform encoding, convolution interleaving and acquisition of data frames according to the first FEC code, and transmit the acquired data frames to the second module 102 through the channel. The second module 102 can perform receiving data frames, convolution deinterleaving and decoding according to the first FEC code. Figures 5 to 7 The illustrated implementation scenario may also include other modules, which are not limited in the embodiments of the present application.

[0088] The data transmission method provided in the embodiment of the present application can be as follows Figure 8 As shown, next, combined Figure 5The implementation scenario shown is used to illustrate the data transmission method provided by the embodiment of the present application. Figure 8 As shown, the method includes S801 to S803.

[0089] S801, the first module performs convolution interleaving on symbols included in the acquired multiple first codewords to obtain an interleaving result, where the first codeword is a codeword for encoding first data using a first FEC code.

[0090] The embodiment of the present application does not limit the manner in which the first module obtains the first codeword. For example, the first module may receive multiple first codewords transmitted by other modules, or the first module may encode the first data according to the first FEC code to obtain multiple first codewords. The first data may be data transmitted by other modules and received by the first module, or data generated by the first module.

[0091] Exemplarily, the symbols of the multiple first codewords used to perform convolution interleaving can be distributed. For example, the first module distributes the symbols included in each first codeword to obtain multiple data paths, and any one data path includes symbols from multiple first codewords, and then the symbols included in each data path are used as symbols for performing convolution interleaving. Of course, the first module may not distribute the symbols included in the multiple first codewords, and directly use the symbols included in the multiple first codewords as symbols for performing convolution interleaving.

[0092] In the embodiment of the present application, the number of bits included in the symbol for performing convolution interleaving may be related to or unrelated to the first FEC code. For example, the number of bits included in the symbol for performing convolution interleaving is equal to the number of bits included in the symbol of the codeword of the first FEC code, or the number of bits included in the symbol for performing convolution interleaving can be determined based on experience or actual needs, and the embodiment of the present application does not limit the number of bits included in the symbol for performing convolution interleaving.

[0093] In a possible implementation, convolution interleaving is performed on symbols included in the acquired multiple first codewords to obtain interleaving results including the following method 1 and method 2.

[0094] Method 1: Input the symbols included in the multiple first code words into the multiple first delay units of the convolution interleaver, and perform convolution interleaving on the symbols included in the polled multiple first code words through the multiple first delay units to obtain multiple first bit groups output by polling of the multiple first delay units, wherein one first bit group includes the symbols output by polling of multiple first delay units once; and use the multiple first bit groups output by polling of the multiple first delay units as the interleaving results.

[0095] In the case where convolution interleaving is performed through multiple first delay units of a convolution interleaver, the starting interleaving position for convolution interleaving of symbols included in multiple first codewords may refer to the polling starting position when the symbols of the first codeword are polled and input. For example, the convolution interleaver includes four first delay units, and the four first delay units are numbered as first delay unit 0 to first delay unit 3. In the case where the symbols of the first codeword are polled and input from the first delay unit 0, the starting interleaving position is located at the first delay unit 0. In the case where the symbols of the first codeword are polled and input from the first delay unit 1, the starting interleaving position is located at the first delay unit 1. In the case where the symbols of the first codeword are polled and input from the first delay unit 2 or the first delay unit 3, the position of the starting interleaving position is the same in principle and will not be repeated here. In combination with the above content, it can be seen that in an embodiment of the present application, the starting interleaving position for convolution interleaving of symbols included in multiple first codewords can be located at any first delay unit among the multiple first delay units.

[0096] Exemplarily, the symbols output by polling multiple first delay units once are taken as a first bit group, and the symbols output by polling multiple first delay units n times are taken as n first bit groups, and n first bit groups are used as interleaving results, where n is a positive integer. In the case where the delay unit is a delay row, the multiple delay rows can output symbols by column. Thus, if the starting interleaving position is located at the first delay row among the multiple delay rows, the symbols output by polling multiple delay rows once are located in the same column; if the starting interleaving position is located at other delay rows among the multiple delay rows except the first delay row, the symbols output by polling multiple delay rows once are located in different columns.

[0097] In the process of convolution interleaving to obtain the interleaving result in the above-mentioned method 1, only the symbols included in the multiple first code words are convolution interleaved, and no additional data is introduced. Therefore, the amount of data for performing convolution interleaving is small, and the efficiency of convolution interleaving is high. In an embodiment of the present application, for a non-concatenated coding scenario, the first module can also obtain identification information, and the identification information is used to indicate the starting interleaving position for convolution interleaving the symbols included in the multiple first code words, and the identification information is convolution interleaved together with the symbols included in the multiple first code words. In this case, the interleaving result obtained includes the identification information indicating the starting interleaving position. The process of convolution interleaving the identification information and the symbols included in the multiple first code words can be referred to the method 2 below.

[0098] Method 2: input at least one identification information and symbols included in multiple first code words into multiple first delay units of a convolution interleaver, and perform convolution interleaving on the polled at least one identification information and symbols included in multiple first code words through multiple first delay units to obtain multiple second bit groups polled and output by multiple first delay units, at least one second bit group includes symbols polled once by multiple first delay units, or at least one second bit group includes identification information and symbols polled once by multiple first delay units; and use the multiple second bit groups polled and output by multiple first delay units as interleaving results.

[0099] The number of bits included in the identification information may be equal to the number of bits included in the symbol. When the interleaving result is obtained by the second method, the specific form of the identification information may be set according to experience or actual needs, and the identification information may indicate the starting interleaving position, which is not limited in the present embodiment.

[0100] In the second method, the starting interleaving position may also be located at any first delay unit among the multiple first delay units, which is not limited in the embodiments of the present application. Since the identification information is convolutionally interleaved with the symbol of the first codeword in the second method, a second bit group output by polling the multiple first delay units once may include only symbols, or may include both symbols and identification information. Exemplarily, the multiple first delay units output a second bit group once polling, and when the multiple first delay units poll and output t times, the multiple first delay units output t second bit groups, and the t second bit groups are used as the interleaving results, and t is a positive integer.

[0101] Exemplarily, the symbols included in the multiple first codewords are input into the multiple first delay units of the convolution interleaver in the form of a first data stream, and the transmission rate of the first data stream is greater than or equal to 100 Gbps. Of course, the transmission rate of the first data stream may also be a higher rate, for example, the transmission rate of the first data stream is greater than or equal to 200 Gbps. In one possible implementation, the first data stream may be transmitted to the multiple first delay units of the convolution interleaver through at least one channel of the AUI. Since at least one identification information and the symbols included in the multiple first codewords can be convolutionally interleaved together in the embodiment of the present application, in this case, at least one identification information and the symbols included in the multiple first codewords can also be input into the multiple first delay units of the convolution interleaver in the form of a data stream, that is, the first data stream may include at least one identification information and the symbols included in the multiple first codewords. In the embodiment of the present application, the symbols or identification information in the first data stream are input into the multiple first delay units in a polling manner.

[0102] S802: The first module obtains second data including identification information according to the interleaving result.

[0103] Combined with the content of S801 above, the identification information can be used to indicate the starting interleaving position of convolution interleaving of symbols included in multiple first codewords. Since the interleaving result obtained by the above method 1 does not include the identification information, the first module can introduce the identification information when obtaining the second data according to the interleaving result. For example, when the second data includes the second codeword, the identification information includes the codeword boundary information of the second codeword, that is, the codeword boundary information of the second codeword can be used to indicate the starting interleaving position of convolution interleaving of symbols included in multiple first codewords. Since the interleaving result obtained by the above method 2 includes the identification information, the first module can directly use the obtained interleaving result as the second data, thereby improving the efficiency of obtaining the second data. In the case of directly using the interleaving result as the second data, the second data does not include the second codeword. In an embodiment of the present application, the second codeword can be a codeword obtained by FEC encoding the interleaving result according to the second FEC code. For the content of obtaining the second codeword, please refer to the content of the following method A1, which will not be expanded here. In the case where the second data does not include the second codeword, it means that the method can be applied to the scenario of non-concatenated coding.

[0104] Exemplarily, when the interleaving result is obtained by the above-mentioned method 1, the interleaving result includes n first bit groups output by multiple first delay units polling n times. When the method is applied to the scenario of concatenated coding, the second data can be obtained by the following method A1.

[0105] Method A1, according to the second FEC code, encodes the n first bit groups output by polling multiple first delay units n times to obtain m second code words, the number of bits corresponding to the n first bit groups is equal to the number of bits included in the information bits of the m second FEC code code words, m and n are both positive integers, m is less than or equal to n; obtain the second data according to the m second code words.

[0106] In the case where the second data includes a second codeword, the identification information includes codeword boundary information of the second codeword. The second codeword includes an information bit and a check bit, and the codeword boundary information of the second codeword may include the boundary position of the check bit of the first second codeword and the information bit of the second second codeword in two adjacent second codewords.

[0107] The embodiment of the present application does not limit the second FEC code, and the second FEC code can be determined based on experience or actual needs. For example, when a certain FEC code is used as the second FEC code, the number of bits corresponding to a first bit group is equal to the number of bits included in the information bits of a codeword of the second FEC code, that is, n first bit groups are encoded to obtain n second codewords, and m is equal to n. For another example, when a certain FEC code is used as the second FEC codeword, the number of bits corresponding to multiple first bit groups is equal to the number of bits included in the information bits of a codeword of the second FEC code, that is, n first bit groups are encoded to obtain m second codewords, and m is less than n.

[0108] The number of bits included in the n first bit groups depends on the number of delay units included in the convolution interleaver and the number of bits included in the symbol. The number of bits included in the symbol can be determined according to the delay length corresponding to the delay block of the delay unit, that is, the number of bits included in the n first bit groups can be determined according to the structure of the convolution interleaver. In the case where the number of bits corresponding to the n first bit groups is equal to the number of bits included in the information bits of the codewords of the m second FEC codes, since the size relationship between m and n is relatively flexible, it means that the adaptation relationship between the convolution interleaver and the second FEC code is relatively flexible. In the case where m and n are both greater than 2, and m and n are not equal, at least two of the codeword boundary information of the multiple second codewords are different. When the method provided in the embodiment of the present application obtains the second data including the identification information according to the interleaving result, additional data can be inserted on the basis of the interleaving result as the identification information, and the starting interleaving position is indicated by the identification information.

[0109] Still Figure 4 Taking the schematic diagram as an example, if n=3, m=2, that is, 3 first bit groups are encoded to obtain 2 second code words, in this case, there are two types of code word boundary information of the second code word, and additional data can be inserted on the basis of the obtained interleaving result as identification information to indicate the starting interleaving position, so that the starting interleaving position can be determined based on the inserted identification information during deinterleaving, avoiding the problem of incorrect deinterleaving due to different code word boundary information, thereby ensuring the accuracy of deinterleaving.

[0110] Fig. 9 is a schematic diagram of a process for obtaining second data provided by an embodiment of the present application. Fig. 9 In the process of obtaining the second data shown, m is equal to n, that is, n bit groups are encoded according to the second FEC code to obtain n second code words, and the number of bits corresponding to a first bit group is equal to the number of bits included in the information bits of a code word of the second FEC code. Fig. 9 The process of convolution interleaving cwA to cwD is shown in FIG. Figure 3The convolution interleaving process shown in (2) is the same as the principle and will not be repeated here.

[0111] Fig.10 FIG. 1 is another schematic diagram of a process for obtaining second data provided by an embodiment of the present application. Fig.10 In the process of obtaining the second data shown, m is less than n, and the number of bits corresponding to the two first bit groups is equal to the number of bits included in the information bits of a codeword of the second FEC code. Fig.10 The process of convolution interleaving cwA to cwD is shown in FIG. Figure 3 The convolution interleaving process shown in (2) is the same as the principle and will not be repeated here.

[0112] Fig. 9 and Fig.10 The description is made by taking the case where symbols included in cwA to cwD appear continuously in one delay unit as an example. The method can also be applied to the case where multiple symbols from one codeword appear continuously in one delay unit. Fig.11 FIG. 1 is another schematic diagram of a process for obtaining second data provided by an embodiment of the present application. Fig.11 , the first codeword includes 320 bits, that is, cwA to cwD each include 320 bits, and the information bits of the codeword of the second FEC code include 160 bits. Fig.11 In the convolution interleave of the symbols included in cwA to cwD, the number of delay rows of the convolution interleaver is equal to the number of the first codewords, that is, the convolution interleaver includes four delay rows. Fig.11 In , a represents the symbols included in cwA, b represents the symbols included in cwB, c represents the symbols included in cwC, and d represents the symbols included in cwD. In the case where the symbols output by each column of the convolution interleaver are used to obtain a second codeword encoded according to the second FEC code, each symbol included in cwA to cwD includes 40 bits, and the number of bits corresponding to the delay blocks included in each delay row is also 40 bits. Since a first codeword includes 320 bits, the difference in the number of delay blocks included in each delay row is equal to (320 / 40) / 4=2. Thus, Fig.11 As shown, D represents a delay block, delay row 0 may include 6 delay blocks, delay row 1 may include 4 delay blocks, delay row 2 may include 2 delay blocks, and delay row 3 may include 0 delay blocks.

[0113] Please continue to see Fig.11 After the symbols included in the multiple first code words are convoluted and interleaved through the delay line, the four adjacent symbols outputted are all from different first code words. Therefore, if a burst error with a length of 160 bits occurs in the second data, the bits included in the burst error will be dispersed into four symbols, and the four symbols are from different first code words, thereby achieving the dispersion of the burst error. In addition, if Fig.11As shown, the four symbols output in a column are used to obtain a codeword encoded by a second FEC codeword, that is, in Fig.11 In the embodiment, four symbols outputted by polling four delayed rows once are encoded according to the second FEC code to obtain a second code word.

[0114] By encoding n first bit groups according to the second FEC code, m second codewords are obtained. The receiving end can obtain the starting interleaving position by obtaining the codeword boundary information of the second codeword, and then perform convolution deinterleaving according to the starting interleaving position, without inserting identification information for indicating the starting interleaving position. The method of inserting additional identification information will increase the link transmission rate, increase the transmission bandwidth required for data transmission, and bring higher data transmission costs. In addition, since the method of inserting additional identification information will cause the link transmission rate to increase, the applicability of the method of inserting additional identification information is poor for data transmission scenarios with limited bandwidth or phase-locked loop frequency. In method A1, since there is no need to insert additional identification information, the codeword boundary information of the second codeword can be directly used as identification information. The data transmission cost of this method is low, and it is more applicable to data transmission scenarios with limited bandwidth or phase-locked loop frequency.

[0115] When the method provided in the embodiment of the present application is applied to a non-concatenated coding scenario, the second data can be obtained by the following method A2.

[0116] Method A2, according to the format of the reference data frame, obtain k target data frames based on n first bit groups output by polling n times of multiple first delay units, the target data frames include frame synchronization information, the frame synchronization information is used as identification information, the number of bits corresponding to the n first bit groups is less than or equal to the number of bits included in the k target data frames, k and n are both positive integers, k is less than or equal to n; obtain the second data based on the k target data frames.

[0117] That is to say, in the scenario of non-concatenated coding, the second data can be obtained by obtaining k target data frames according to n first bit groups. In this case, the second data does not include the second codeword. Exemplarily, the frame synchronization information includes but is not limited to a frame alignment word in coherent transmission or other data used for frame synchronization. The format of the reference data frame can be determined according to the frame format required for data transmission, which is not limited in the embodiments of the present application. Exemplarily, k target data frames are used as the second data.

[0118] Fig.12 is a schematic diagram of another process of obtaining second data provided by an embodiment of the present application. Fig.12 In the process of obtaining the second data shown, k is smaller than n, and four first bit groups are used to obtain a target data frame. Fig.12The process of convolution interleaving cwA to cwD is shown in FIG. Figure 3 The convolution interleaving process shown in (2) is the same as the principle and will not be repeated here.

[0119] S803: The first module transmits second data to the second module.

[0120] The embodiment of the present application does not limit the manner in which the first module transmits the second data to the second data. For example, the first module transmits the second data to the second module through a channel.

[0121] In the method provided in the embodiment of the present application, by performing convolution interleaving on the symbols included in the multiple first codewords, when a burst error occurs in the subsequent second data, the burst error will be dispersed into multiple symbols, thereby reducing the BER of the second data after error correction. Furthermore, in the case where the second data includes the second codeword, the identification information is the codeword boundary information of the second codeword, and there is no need to insert additional identification information for indicating the starting interleaving position, so that the data transmission cost is low, the applicability to data transmission scenarios with limited bandwidth or phase-locked loop frequency is high, and the implementation complexity of the data transmission system used to execute the method is low.

[0122] The data transmission method provided by the embodiment of the present application is described above by taking the first module side as an example. Next, the data transmission method is described by taking the second module side as an example. Figure 8 As shown, the data transmission method includes S804 to S806.

[0123] S804: The second module receives second data including identification information transmitted by the first module.

[0124] The embodiment of the present application does not limit the manner in which the second module receives the second data, and can be adapted to the manner in which the first module transmits the second data to the second module. In combination with the content in S802 above, it can be seen that the second data is obtained based on the interleaving result obtained by convolutionally interleaving the symbols included in the plurality of first codewords, and the first codeword is a codeword that encodes the first data using the first FEC code. In the case where the second data includes the second codeword, the identification information includes the codeword boundary information of the second codeword.

[0125] S805: The second module obtains, according to the identification information, a starting interleaving position for performing convolution interleaving on symbols included in the plurality of first codewords and data to be deinterleaved in the second data.

[0126] According to different situations of the second data, the second module can perform operations of obtaining the starting interleaving position for convolution interleaving of symbols included in multiple first codewords and the data to be deinterleaved in the second data according to the identification information in different ways.

[0127] Case B1: the second data includes a second code word.

[0128] In the case where the second data includes a second codeword, the second module obtains at least one second codeword included in the second data according to codeword boundary information of the second codeword; obtains a starting position of at least one second codeword, and uses the starting position as a starting interleaving position for convolution interleaving symbols included in multiple first codewords; and decodes at least one second codeword to obtain data to be deinterleaved.

[0129] Exemplarily, the codeword boundary information of the second codeword can be obtained by codeword self-synchronization, so that the second module can obtain at least one second codeword included in the second data according to the boundary information of the second codeword. For example, the process of the second module obtaining the codeword boundary information of the second codeword by codeword self-synchronization includes: obtaining the codeword of the local second FEC code, and identifying the codeword boundary information of the second codeword according to the codeword of the local second FEC code. In the case where the second data includes an alignment marker (AM), the position of the AM is associated with the position of the second codeword, so that the second module can obtain the codeword boundary information of the second codeword by determining the position of the AM in the second data.

[0130] Since the second codeword is obtained by encoding the n first bit groups according to the second FEC code, and the n first bit groups are obtained from the starting interleaving position of convolution interleaving the symbols included in the multiple first codewords, the starting position of the second codeword can be used as the starting interleaving position of convolution interleaving the symbols included in the multiple first codewords. The second module decodes the second codeword in a manner corresponding to the manner in which the second codeword is obtained by encoding, that is, the second module can decode at least one second codeword according to the second FEC code to obtain the data to be deinterleaved.

[0131] Case B2: the second data does not include the second code word.

[0132] In the case where the second data does not include the second codeword, if the second data includes at least one target data frame and the identification information is frame synchronization information, the second module can perform the operation of obtaining the starting interleaving position for convolution interleaving of symbols included in multiple first codewords and the data to be deinterleaved in the second data according to the identification information in the following manner C1.

[0133] Method C1, obtaining at least one target data frame included in the second data according to frame synchronization information; obtaining the starting position of the frame data of at least one target data frame, and using the starting position as the starting interleaving position for convolution interleaving of symbols included in multiple first code words; using the frame data included in at least one target data frame as data to be deinterleaved.

[0134] For example, the second module divides the second data according to the frame synchronization information to obtain at least one target data frame included in the second data, and the number of target data frames can be k. Furthermore, after obtaining at least one target data frame, the starting position of the frame data of each target data frame can be obtained. Since the k target data frames are obtained based on the n first bit groups, and the n first bit groups are obtained from the starting interleaving position of convolution interleaving the symbols included in the multiple first codewords, the starting position of the frame data of the target data frame can be used as the starting interleaving position of convolution interleaving the symbols included in the multiple first codewords.

[0135] If the second data does not include either the second codeword or the target data frame, the identification information is used to indicate the starting interleaving position for convolution interleaving the symbols included in the multiple first codewords; the second module can perform the operation of obtaining the starting interleaving position for convolution interleaving the symbols included in the multiple first codewords and the data to be deinterleaved in the second data according to the identification information in the following manner C2.

[0136] Mode C2, obtaining the starting interleaving position for performing convolution interleaving on the symbols included in the plurality of first codewords indicated by the identification information; and taking the data located at the starting interleaving position and the data after the starting interleaving position in the second data as the data to be deinterleaved.

[0137] That is, the identification information can directly indicate the starting interleaving position for convolution interleaving the symbols included in the multiple first codewords, and then the second module uses the data located at the starting interleaving position and the data after the starting interleaving position in the second data as the data to be deinterleaved.

[0138] S806: The second module performs convolution deinterleaving on the data to be deinterleaved based on the starting interleaving position to obtain a plurality of first codewords.

[0139] Exemplarily, when the method in the above case B1 or the method C1 in the case B2 is used to obtain the data to be deinterleaved, the data to be deinterleaved includes multiple third bit groups, and one third bit group includes the symbol of the first codeword output by polling once by multiple first delay units of the convolution interleaver. Since bit errors may occur during data transmission, there may be bit errors in the third bit group.

[0140] In the case where the data to be deinterleaved includes multiple third bit groups, performing convolution deinterleaving on the data to be deinterleaved from a starting interleaving position to obtain multiple first code words may include: obtaining a starting deinterleaving position corresponding to the starting interleaving position in multiple second delay units of a convolutional deinterleaver; inputting the multiple third bit groups from the starting deinterleaving position into multiple second delay units, and performing convolution deinterleaving on symbols included in the multiple third bit groups polled through the multiple second delay units; obtaining symbols included in multiple first code words polled and output by the multiple second delay units, and obtaining multiple first code words based on the symbols included in the multiple first code words.

[0141] The starting interleaving position may be the same as the starting deinterleaving position, and after the second module obtains the starting interleaving position, the starting interleaving position may be used as the starting deinterleaving position. Similar to the starting deinterleaving position being located at any one of the plurality of first delay units, the starting deinterleaving position may be located at any one of the plurality of second delay units. After obtaining the symbols included in the plurality of first codewords, each first codeword may be obtained based on the symbols included in each first codeword.

[0142] Exemplarily, in the case of obtaining the data to be deinterleaved by the method C2 in the above-mentioned case B2, the data to be deinterleaved includes multiple fourth bit groups, at least one fourth bit group includes the symbol of the first codeword output by polling once by multiple first delay units of the convolution interleaver, or at least one fourth bit group includes identification information and symbols output by polling once by multiple first delay units. Since bit errors may occur during data transmission, there may be bit errors in the fourth bit group.

[0143] In the case where the data to be deinterleaved includes multiple fourth bit groups, performing convolution deinterleaving on the data to be deinterleaved from a starting interleaving position to obtain multiple first code words may include: obtaining a starting deinterleaving position corresponding to the starting interleaving position in multiple second delay units of a convolutional deinterleaver, inputting the multiple fourth bit groups from the starting deinterleaving position into multiple second delay units, and performing convolution deinterleaving on symbols included in multiple fourth bit groups polled, or identification information and symbols included in multiple fourth bit groups through multiple second delay units; obtaining symbols and identification information included in multiple first code words polled and output by multiple second delay units, and obtaining multiple first code words according to the symbols included in the multiple first code words.

[0144] In this case, the manner in which the second module obtains the content of the starting deinterleaving position, performs convolutional deinterleaving, and obtains multiple first codewords is the same as the relevant content principle in the above-mentioned case where the data to be deinterleaved includes multiple third bit groups, and will not be repeated here.

[0145] Exemplarily, the multiple second delay units of the convolutional deinterleaver output the symbols included in the multiple first codewords in the form of a second data stream, and the transmission rate of the second data stream is greater than or equal to 100 Gbps. Of course, the transmission rate of the second data stream can also be a higher rate, for example, the transmission rate of the second data stream is greater than or equal to 200 Gbps. In the case where the second data is convolutionally interleaved based on the identification information and the symbols of the multiple first codewords, the second data stream may also include the identification information. In this case, the multiple second delay units of the convolutional deinterleaver output the identification information and the symbols included in the multiple first codewords in the form of a second data stream. Exemplarily, the multiple second delay units of the convolutional deinterleaver output the second data stream through at least one channel of the AUI. The multiple second delay units can input the second data stream into at least one channel of the AUI in a polling manner, thereby outputting the second data stream through at least one channel of the AUI.

[0146] In the method provided in the embodiment of the present application, since the second data is obtained by convolution interleaving the symbols included in the multiple first codewords, when a burst error occurs in the second data, the burst error will be dispersed into multiple symbols, thereby reducing the BER of the second data after error correction. Furthermore, in the case where the second data includes the second codeword, the identification information is the codeword boundary information of the second codeword, and there is no need to insert additional identification information for indicating the starting interleaving position in the second data, so that the data transmission cost is low, the applicability to data transmission scenarios with limited bandwidth or phase-locked loop frequency is high, and the implementation complexity of the data transmission system used to execute the method is low.

[0147] The embodiment of the present application also provides a data transmission device. Fig.13 Schematic diagram of a data transmission device provided in an embodiment of the present application. Fig.13 The multiple units shown, Fig.13 The data transmission device shown can perform all or part of the operations performed by the first module. It should be understood that the device may include more additional units than the units shown or omit some of the units shown, and the embodiments of the present application are not limited to this. Fig.13 As shown, the device comprises:

[0148] An interleaving unit 1301 is configured to perform convolution interleaving on symbols included in the acquired multiple first codewords to obtain an interleaving result, where the first codeword is a codeword for encoding the first data using the first FEC code;

[0149] An acquiring unit 1302 is configured to acquire second data including identification information according to the interleaving result, where the identification information includes codeword boundary information of the second codeword when the second data includes the second codeword;

[0150] The transmission unit 1303 is configured to transmit the second data to the second module.

[0151] In one possible implementation, the interleaving unit 1301 is used to input the symbols included in the multiple first code words into the multiple first delay units of the convolution interleaver, and perform convolution interleaving on the symbols included in the polled multiple first code words through the multiple first delay units to obtain multiple first bit groups polled and output by the multiple first delay units, wherein a first bit group includes the symbols output by polling multiple first delay units once; and the multiple first bit groups polled and output by the multiple first delay units are used as the interleaving results.

[0152] In one possible implementation, the interleaving result includes n first bit groups output by polling multiple first delay units n times, and the acquisition unit 1302 is used to encode the n first bit groups output by polling multiple first delay units n times according to the second FEC code to obtain m second code words, the number of bits corresponding to the n first bit groups is equal to the number of bits included in the information bits of the code words of the m second FEC codes, m and n are both positive integers, and m is less than or equal to n; the second data is obtained according to the m second code words.

[0153] In one possible implementation, the second data does not include the second codeword, and the interleaving result includes n first bit groups output by polling multiple first delay units n times. The acquisition unit 1302 is used to acquire k target data frames based on the n first bit groups output by polling multiple first delay units n times in accordance with the format of the reference data frame, the target data frames include frame synchronization information, the frame synchronization information is used as identification information, the number of bits corresponding to the n first bit groups is less than or equal to the number of bits included in the k target data frames, k and n are both positive integers, and k is less than or equal to n; the second data is obtained according to the k target data frames.

[0154] In one possible implementation, the second data does not include the second codeword, and the interleaving unit 1301 is used to input at least one identification information and symbols included in multiple first codewords into multiple first delay units of a convolution interleaver, and convolutionally interleave the at least one identification information polled and the symbols included in multiple first codewords through the multiple first delay units to obtain multiple second bit groups polled and output by the multiple first delay units, at least one second bit group includes symbols output by polling multiple first delay units once, or at least one second bit group includes identification information and symbols output by polling multiple first delay units once, and the identification information is used to indicate the starting interleaving position for convolutionally interleaving the symbols included in the multiple first codewords; the multiple second bit groups polled and output by the multiple first delay units are used as interleaving results.

[0155] In a possible implementation manner, a starting interleaving position for performing convolution interleaving on symbols included in the plurality of first codewords is located at any first delay unit among the plurality of first delay units.

[0156] In a possible implementation, symbols included in the multiple first codewords are input into multiple first delay units of the convolution interleaver in the form of a first data stream, and a transmission rate of the first data stream is greater than or equal to 100 Gbps.

[0157] In a possible implementation, the first data stream is transmitted to a plurality of first delay units of a convolutional interleaver through at least one channel of the AUI.

[0158] In the device provided by the embodiment of the present application, by performing convolution interleaving on the symbols included in the multiple first codewords, when a burst error occurs in the subsequent second data, the burst error will be dispersed into multiple symbols, thereby reducing the BER of the second data after error correction. Furthermore, in the case where the second data includes the second codeword, the identification information is the codeword boundary information of the second codeword, and there is no need to insert additional identification information for indicating the starting interleaving position, so that the data transmission cost is low, the applicability to data transmission scenarios with limited bandwidth or phase-locked loop frequency is high, and the implementation complexity of the data transmission system including the device is low.

[0159] Fig.14 Schematic diagram of another data transmission device provided in an embodiment of the present application. Fig.14 The multiple units shown in Fig.14 The data transmission device shown can perform all or part of the operations performed by the second module. It should be understood that the device may include more additional units than the units shown or omit some of the units shown, and the embodiments of the present application are not limited to this. Fig.14 As shown, the device comprises:

[0160] An acquiring unit 1401 is configured to receive second data including identification information transmitted by the first module, where the second data is acquired according to an interleaving result obtained by performing convolution interleaving on symbols included in a plurality of first codewords, where the first codeword is a codeword obtained by encoding the first data using a first FEC code; wherein, when the second data includes the second codeword, the identification information includes codeword boundary information of the second codeword;

[0161] The acquisition unit 1401 is further configured to acquire, according to the identification information, a starting interleaving position for performing convolution interleaving on symbols included in the plurality of first codewords and data to be deinterleaved in the second data;

[0162] The deinterleaving unit 1402 is configured to perform convolution deinterleaving on the data to be deinterleaved based on the starting interleaving position to obtain a plurality of first codewords.

[0163] In one possible implementation, the acquisition unit 1401 is used to obtain at least one second codeword included in the second data according to the codeword boundary information of the second codeword; obtain the starting position of at least one second codeword, and use the starting position as the starting interleaving position for convolution interleaving of symbols included in multiple first codewords; and decode at least one second codeword to obtain data to be deinterleaved.

[0164] In one possible implementation, when the second data does not include the second codeword, the identification information is frame synchronization information, and the acquisition unit 1401 is used to obtain at least one target data frame included in the second data according to the frame synchronization information; obtain the starting position of the frame data of the at least one target data frame, and use the starting position as the starting interleaving position for convolution interleaving of symbols included in multiple first codewords; and use the frame data included in the at least one target data frame as data to be deinterleaved.

[0165] In one possible implementation, the data to be deinterleaved includes multiple third bit groups, and one third bit group includes symbols of a first codeword output by polling multiple first delay units of a convolutional interleaver once; a deinterleaving unit 1402 is used to obtain a starting deinterleaving position corresponding to a starting interleaving position in multiple second delay units of the convolutional deinterleaver; multiple third bit groups are input from the starting deinterleaving position into multiple second delay units, and symbols included in the polled multiple third bit groups are convolutionally deinterleaved through multiple second delay units; symbols included in multiple first codewords polled and output by multiple second delay units are obtained, and multiple first codewords are obtained based on the symbols included in the multiple first codewords.

[0166] In one possible implementation, when the second data does not include the second codeword, the identification information is used to indicate the starting interleaving position for performing convolution interleaving on the symbols included in the multiple first codewords; the acquisition unit 1401 is used to obtain the starting interleaving position for performing convolution interleaving on the symbols included in the multiple first codewords indicated by the identification information; and the data located at the starting interleaving position and the data after the starting interleaving position in the second data are used as the data to be deinterleaved.

[0167] In one possible implementation, the data to be deinterleaved includes multiple fourth bit groups, at least one fourth bit group includes the symbol of the first codeword output by polling multiple first delay units of the convolution interleaver once, or at least one fourth bit group includes identification information and symbols output by polling multiple first delay units once; the deinterleaving unit 1402 is used to obtain a starting deinterleaving position corresponding to a starting interleaving position in multiple second delay units of the convolution deinterleaver; the multiple fourth bit groups are input from the starting deinterleaving position into multiple second delay units, and convolution deinterleaving is performed on the symbols included in the polled multiple fourth bit groups, or the identification information and symbols included in the multiple fourth bit groups through the multiple second delay units; the symbols and identification information included in the multiple first codewords output by polling multiple second delay units are obtained, and multiple first codewords are obtained according to the symbols included in the multiple first codewords.

[0168] In a possible implementation manner, the starting deinterleaving position is located at any second delay unit among the multiple second delay units.

[0169] In a possible implementation, the plurality of second delay units of the convolutional deinterleaver output the symbols included in the plurality of first codewords in the form of a second data stream, and a transmission rate of the second data stream is greater than or equal to 100 Gbps.

[0170] In a possible implementation, the plurality of second delay units of the convolutional deinterleaver output the second data stream through at least one channel of the AUI.

[0171] In the device provided by the embodiment of the present application, since the second data is obtained by convolution interleaving the symbols included in the multiple first codewords, when a burst error occurs in the second data, the burst error will be dispersed into multiple symbols, thereby reducing the BER of the second data after error correction. Furthermore, in the case where the second data includes the second codeword, the identification information is the codeword boundary information of the second codeword, and there is no need to insert additional identification information for indicating the starting interleaving position in the second data, so that the data transmission cost is low, the applicability to data transmission scenarios with limited bandwidth or phase-locked loop frequency is high, and the implementation complexity of the data transmission system including the device is low.

[0172] It should be understood that the above Figure 13-14 When the device provided realizes its functions, only the division of the above-mentioned functional units is used as an example for illustration. In practical applications, the above-mentioned functions can be assigned to different functional units as needed, that is, the internal structure of the device is divided into different functional units to complete all or part of the functions described above. In addition, the device and method embodiments provided in the above embodiments belong to the same concept, and their specific implementation process is detailed in the method embodiment, which will not be repeated here.

[0173] See also Fig.15, Fig.15 The following is a schematic diagram of the structure of a computer system provided in an embodiment of the present application. Fig.15 As shown, the computer system is a computer system 2000. The computer system 2000 may be a network device, a routing device or a switching device. Fig.15 The computer system 2000 shown is used to execute the above Figure 8 The operations involved in the first module or the operations involved in the second module in the data transmission method shown. The computer system 2000 is, for example, a server, etc. The computer system 2000 can be implemented by a general bus architecture.

[0174] like Fig.15 As shown, the computer system 2000 includes at least one processor 2001 , a memory 2003 , and at least one communication interface 2004 .

[0175] Processor 2001 is, for example, a central processing unit (CPU), a digital signal processor (DSP), a network processor (NP), a graphics processing unit (GPU), a neural-network processing units (NPU), a data processing unit (DPU), a microprocessor, or one or more integrated circuits for implementing the solution of the present application. For example, processor 2001 includes an application-specific integrated circuit (ASIC), a programmable logic device (PLD) or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. PLD is, for example, a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof. It can implement or execute various logic blocks, modules, and circuits described in conjunction with the disclosure of the embodiments of the present application. The processor can also be a combination that implements a computing function, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, and the like.

[0176] Optionally, the computer system 2000 further includes a bus. The bus is used to transmit information between the components of the computer system 2000. The bus may be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus. The bus may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Fig.15 Only one thick line is used in the diagram, but this does not mean that there is only one bus or only one type of bus.

[0177] The memory 2003 is, for example, a read-only memory (ROM) or other types of static storage devices that can store static information and instructions, or a random access memory (RAM) or other types of dynamic storage devices that can store information and instructions, or an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compressed optical disc, laser disc, optical disc, digital versatile disc, Blu-ray disc, etc.), a magnetic disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store the desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited thereto. The memory 2003 is, for example, independent and connected to the processor 2001 via a bus. The memory 2003 can also be integrated with the processor 2001.

[0178] The communication interface 2004 uses any transceiver-like device to communicate with other devices or communication networks, and the communication network can be Ethernet, radio access network (RAN) or wireless local area network (WLAN), etc. The communication interface 2004 can include a wired communication interface and can also include a wireless communication interface. Specifically, the communication interface 2004 can be an Ethernet interface, a fast Ethernet (FE) interface, a gigabit Ethernet (GE) interface, an asynchronous transfer mode (ATM) interface, a WLAN interface, a cellular network communication interface or a combination thereof. The Ethernet interface can be an optical interface, an electrical interface or a combination thereof. In an embodiment of the present application, the communication interface 2004 can be used for the computer system 2000 to communicate with other devices.

[0179] In a specific implementation, as an embodiment, the processor 2001 may include one or more CPUs, such as Fig.15 0 and CPU1 shown in FIG. Each of these processors may be a single-CPU processor or a multi-CPU processor. A processor herein may refer to one or more devices, circuits, and / or processing cores for processing data (e.g., computer program instructions).

[0180] In a specific implementation, as an embodiment, the computer system 2000 may include multiple processors, such as Fig.15 2001 and processor 2005 are shown in FIG. Each of these processors may be a single-core processor (single-CPU) or a multi-core processor (multi-CPU). A processor herein may refer to one or more devices, circuits, and / or processing cores for processing data (such as computer program instructions).

[0181] In a specific implementation, as an embodiment, the computer system 2000 may further include an output device and an input device. The output device communicates with the processor 2001 and may display information in a variety of ways. For example, the output device may be a liquid crystal display (LCD), a light emitting diode (LED) display device, a cathode ray tube (CRT) display device, or a projector. The input device communicates with the processor 2001 and may receive user input in a variety of ways. For example, the input device may be a mouse, a keyboard, a touch screen device, or a sensor device.

[0182] In some embodiments, the memory 2003 is used to store the program code 2010 for executing the solution of the present application, and the processor 2001 can execute the program code 2010 stored in the memory 2003. The program code 2010 may include one or more software modules. Optionally, the processor 2001 itself may also store the program code or instructions for executing the solution of the present application.

[0183] In a specific embodiment, the computer system 2000 of the embodiment of the present application may include the first module in each of the above method embodiments, and the processor 2001 in the computer system 2000 reads the program code 2010 in the memory 2003 or the program code or instruction stored in the processor 2001 itself, so that Fig.15 The computer system 2000 shown is capable of executing all or part of the operations performed by the first module.

[0184] In a specific embodiment, the computer system 2000 of the embodiment of the present application may include the second module in each of the above-mentioned method embodiments, and the processor 2001 in the computer system 2000 reads the program code 2010 in the memory 2003 or the program code or instruction stored in the processor 2001 itself, so that Fig.15 The computer system 2000 shown is capable of executing all or part of the operations performed by the second module.

[0185] The computer system 2000 may also correspond to the above Fig.13 , 14 The device shown, Fig.13 , 14 Each functional unit in the device shown is implemented using software of the computer system 2000. In other words, Fig.13 , 14 The functional units included in the device shown are generated after the processor 2001 of the computer system 2000 reads the program code 2010 stored in the memory 2003.

[0186] in, Figure 8 Each step of the data transmission method shown is completed by an integrated logic circuit of hardware or software instructions in the processor of the computer system 2000. The steps of the method disclosed in conjunction with the embodiment of the present application can be directly embodied as a hardware processor, or a combination of hardware and software modules in the processor. The software module can be located in a mature storage medium in the field such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register, etc. The storage medium is located in the memory, and the processor reads the information in the memory, and completes the steps of the above method in conjunction with its hardware. To avoid repetition, it is not described in detail here.

[0187] Fig.16 is a schematic diagram of another computer system provided in an embodiment of the present application, the computer system is used to execute the above Figure 8 The operations involved in the first module or the operations involved in the second module in the data transmission method shown. Exemplarily, the computer system is a server, and the server may have relatively large differences due to different configurations or performances. The computer system may include one or more processors 1601 and one or more memories 1602, wherein the one or more memories 1602 store at least one computer program, and the at least one computer program is loaded and executed by the one or more processors 1601. Exemplarily, the processor 1601 is a CPU. Of course, the computer system may also have components such as a wired or wireless network interface, a keyboard, and an input and output interface for input and output. The computer system may also include other components for implementing device functions, which are not described here.

[0188] An embodiment of the present application also provides a computer system, which includes a processor, the processor includes a first module or a second module, and the processor is used to call and execute instructions stored in the memory from the memory; when the processor includes the first module, the computer system implements the data transmission method executed by the above-mentioned first module, and when the processor includes the second module, the computer system implements the data transmission method executed by the above-mentioned second module.

[0189] In a possible implementation, the computer system further includes: an input interface, an output interface and the above-mentioned memory, and the input interface, the output interface, the processor and the memory are connected through an internal connection path.

[0190] The embodiment of the present application also provides a data transmission system, which includes a first module and a second module. The first module is used to execute Figure 8 The method executed by the first module shown, the second module is used to execute Figure 8The functions of the first module and the second module of the data transmission system can be referred to above. Figure 8 The relevant descriptions shown will not be repeated here one by one.

[0191] The embodiment of the present application also provides a communication device, which includes: a transceiver, a memory and a processor. The transceiver, the memory and the processor communicate with each other through an internal connection path, the memory is used to store instructions, the processor is used to execute the instructions stored in the memory to control the transceiver to send and receive signals, and the processor includes a first module or a second module. In the case where the processor includes the first module, when the processor executes the instructions stored in the memory, the processor executes the data transmission method executed by the first module. In the case where the processor includes the second module, when the processor executes the instructions stored in the memory, the processor executes the data transmission method executed by the second module.

[0192] It should be understood that the processor may be a CPU, or other general-purpose processors, DSPs, ASICs, FPGAs or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor, etc. It is worth noting that the processor may be a processor supporting an advanced RISC machines (ARM) architecture.

[0193] Further, in an optional embodiment, the memory may include a read-only memory and a random access memory, and provide instructions and data to the processor. The memory may also include a non-volatile random access memory. For example, the memory may also store information about the device type.

[0194] The memory may be a volatile memory or a nonvolatile memory, or may include both volatile and nonvolatile memory. Among them, the nonvolatile memory may be a ROM, a programmable read-only memory (programmable ROM, PROM), an erasable programmable read-only memory (erasable PROM, EPROM), an electrically erasable programmable read-only memory (electrically EPROM, EEPROM) or a flash memory. The volatile memory may be a RAM, which is used as an external cache. By way of example but not limitation, many forms of RAM are available. For example, static random access memory (static RAM, SRAM), dynamic random access memory (dynamic random access memory, DRAM), synchronous dynamic random access memory (synchronous DRAM, SDRAM), double data rate synchronous dynamic random access memory (doubledata rate SDRAM, DDR SDRAM), enhanced synchronous dynamic random access memory (enhanced SDRAM, ESDRAM), synchronous connection dynamic random access memory (synchlink DRAM, SLDRAM) and direct memory bus random access memory (direct rambus RAM, DR RAM).

[0195] The embodiment of the present application also provides a computer-readable storage medium, in which at least one program instruction or code is stored, and the program instruction or code is executed by a computer, and the computer includes a first module or a second module. In the case where the computer includes the first module, when the program instruction or code is executed by the computer, the computer implements the data transmission method executed by the first module. In the case where the computer includes the second module, when the program instruction or code is executed by the computer, the computer implements the data transmission method executed by the second module.

[0196] The embodiment of the present application also provides a computer program product, which includes: computer program instructions or codes, the computer program instructions or codes are executed by a computer, and the computer includes a first module or a second module. In the case where the computer includes the first module, when the computer program instructions or codes are executed by the computer, the computer executes the data transmission method executed by the first module. In the case where the computer includes the second module, when the computer program instructions or codes are executed by the computer, the computer executes the data transmission method executed by the second module.

[0197] The embodiment of the present application also provides a chip, including a processor, the processor including a first module or a second module, and the processor is used to run program instructions or codes. In the case where the processor includes the first module, the device including the chip executes the data transmission method executed by the first module. In the case where the processor includes the second module, the device including the chip executes the data transmission method executed by the second module.

[0198] Exemplarily, the chip further includes: an input interface, an output interface and a memory, wherein the input interface, the output interface, the processor and the memory are connected via an internal connection path, and the memory contains the above-mentioned program instructions or codes.

[0199] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loading and executing computer program instructions on a computer, the process or function according to the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions can be transmitted from a website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server or data center. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server, data center, etc. that contains one or more available media integrations. The available medium may be a magnetic medium (eg, a floppy disk, a hard disk, a magnetic tape), an optical medium (eg, a digital video disc (DVD)), or a semiconductor medium (eg, a solid state disk (SSD)).

[0200] In the above embodiments, the unit of transmission rate Gb / s can also be abbreviated as G, such as the rate of 400 Gb / s can also be abbreviated as 400G.

[0201] In order to clearly illustrate the interchangeability of hardware and software, the steps and components of each embodiment have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. A person of ordinary skill in the art may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0202] The computer program code for realizing the method for the embodiment of the present application can be written in one or more programming languages. These computer program codes can be provided to the processor of a general-purpose computer, a special-purpose computer or other programmable data transmission device, so that the program code, when executed by a computer or other programmable data transmission device, causes the function / operation specified in the flow chart and / or block diagram to be implemented. The program code can be executed completely on a computer, partially on a computer, as an independent software package, partially on a computer and partially on a remote computer or completely on a remote computer or server.

[0203] In the context of the embodiments of the present application, computer program codes or related data may be carried by any appropriate carrier to enable a device, apparatus or processor to perform the various processes and operations described above. Examples of carriers include signals, computer readable media, etc. Examples of signals may include electrical, optical, radio, acoustic or other forms of propagation signals, such as carrier waves, infrared signals, etc.

[0204] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and modules described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0205] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the module is only a logical function division. There may be other division methods in actual implementation, such as multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or modules, or it can be an electrical, mechanical or other form of connection.

[0206] The modules described as separate components may or may not be physically separated, and the components displayed as modules may or may not be physical modules, that is, they may be located in one place or distributed on multiple network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the embodiments of the present application.

[0207] In addition, each functional module in each embodiment of the present application can be integrated into one processing module, or each module can exist physically separately, or two or more modules can be integrated into one module. The above integrated modules can be implemented in the form of hardware or software functional modules.

[0208] In this application, the words such as "first", "second", etc. are used to distinguish the same or similar items with basically the same effects and functions. It should be understood that there is no logical or temporal dependency between "first", "second", and "nth", nor is the quantity and execution order limited. It should also be understood that although the following description uses the terms first, second, etc. to describe various elements, these elements should not be limited by the terms. These terms are only used to distinguish one element from another element. For example, without departing from the scope of various examples, the first module can be referred to as the second module, and similarly, the second module can be referred to as the first module.

[0209] It should also be understood that in the various embodiments of the present application, the size of the serial number of each process does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0210] The term "at least one" in this application means one or more, and the term "multiple" in this application means two or more, for example, multiple code blocks means two or more code blocks. The terms "system" and "network" are often used interchangeably herein.

[0211] It should be understood that the terms used in the description of various examples herein are only for describing specific examples and are not intended to be limiting. As used in the description of various examples and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0212] It should also be understood that the term “comprise” (also known as “includes,” “including,” “comprises” and / or “comprising”) when used in this specification specifies the presence of stated features, integers, steps, operations, elements, and / or components, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0213] It should also be understood that, depending on the context, the phrase “if it is determined that…” or “if [stated condition or event] is detected” may be interpreted to mean “upon determining that…” or “in response to determining that…” or “upon detecting [stated condition or event]” or “in response to detecting [stated condition or event]”.

[0214] It should be understood that determining B based on A does not mean determining B only based on A. B can also be determined based on A and / or other information.

[0215] It should also be understood that the references to "one embodiment", "an embodiment", or "a possible implementation" throughout the specification mean that specific features, structures, or characteristics related to the embodiment or implementation are included in at least one embodiment of the present application. Therefore, the references to "in one embodiment" or "in an embodiment", or "a possible implementation" throughout the specification do not necessarily refer to the same embodiment. In addition, these specific features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

Claims

1. A data transmission method, characterized in that: The method comprises: Convolutionally interleaving the symbols included in the plurality of first codewords to obtain an interleaved result, wherein the interleaved result includes n first bit groups, and the first codeword is encoded using a first forward error correction FEC code; According to the second FEC code, the bits corresponding to the n first bit groups are encoded to obtain n second code words, the number of bits corresponding to the n first bit groups is equal to the number of bits included in the information bits of the n second code words, and n is a positive integer.

2. The method according to claim 1, characterized in that The four adjacent symbols in the interleaving result are from different first code words.

3. The method according to claim 1, characterized in that The second codeword includes codeword boundary information, and the codeword boundary information indicates a starting position of performing the convolution interleaving on the symbols included in the plurality of first codewords.

4. The method according to claim 1, characterized in that: The second FEC code is a Hamming code.

5. The method according to claim 1, characterized in that The step of performing convolution interleaving on the symbols included in the plurality of first codewords to obtain an interleaving result comprises: The symbols included in the multiple first code words input in a polling manner are convolutionally interleaved through multiple delay units of the convolution interleaver to obtain the interleaving result.

6. The method according to claim 2, characterized in that The step of performing convolution interleaving on the symbols included in the plurality of first codewords to obtain an interleaving result comprises: The symbols included in the multiple first code words input in a polling manner are convolutionally interleaved through multiple delay units of the convolution interleaver to obtain the interleaving result.

7. The method according to claim 5, characterized in that One of the first bit groups includes symbols output by the plurality of delay units polling once.

8. The method according to claim 6, characterized in that One of the first bit groups includes symbols output by the plurality of delay units polling once.

9. The method according to any one of claims 1 to 8, characterized in that: The starting interleaving position for performing convolution interleaving on the symbols included in the multiple first code words is the polling starting position when the symbols of the first code words are polled and input to the multiple delay units of the convolution interleaver.

10. The method according to any one of claims 1 to 8, characterized in that: The symbols included in the multiple first codewords are input into the multiple delay units of the convolution interleaver in the form of a first data stream, and the transmission rate of the first data stream is greater than or equal to 100 gigabits per second.

11. The method according to claim 9, characterized in that The symbols included in the multiple first codewords are input into the multiple delay units of the convolution interleaver in the form of a first data stream, and the transmission rate of the first data stream is greater than or equal to 100 gigabits per second.

12. The method according to claim 11, characterized in that The transmission rate of the first data stream is greater than or equal to 200 Gbps.

13. The method according to claim 11 or 12, characterized in that: The first data stream is transmitted to the multiple delay units of the convolution interleaver through at least one channel of the connection unit interface AUI.

14. The method according to any one of claims 5 to 8, characterized in that: The plurality of delay units are a plurality of delay rows.

15. The method according to claim 14, characterized in that The number of bits corresponding to the delay blocks included in each delay row is 40 bits.

16. A data transmission method, characterized in that: The method comprises: Receive n second code words, where the n second code words are obtained by encoding bits corresponding to n first bit groups according to a second forward error correction (FEC) code, the number of bits corresponding to the n first bit groups is equal to the number of bits included in the information bits of the n second code words, and n is a positive integer; Decoding the n second code words to obtain the n first bit groups; Convolution deinterleaving is performed on bits corresponding to the n first bit groups to obtain a plurality of first codewords, where the first codewords are encoded using a first FEC code.

17. The method according to claim 16, characterized in that The second FEC code is a Hamming code.

18. The method according to claim 16, characterized in that The second codeword includes codeword boundary information, and the codeword boundary information indicates a starting interleaving position for performing convolution interleaving on symbols included in the plurality of first codewords.

19. The method according to any one of claims 16 to 18, characterized in that: The decoding of the n second code words to obtain the n first bit groups comprises: A starting interleaving position for performing convolution interleaving on the symbols included in the multiple first codewords and the n first bit groups are obtained according to the codeword boundary information of the second codeword.

20. The method according to claim 19, characterized in that The step of obtaining, according to the codeword boundary information of the second codeword, a starting interleaving position for performing convolution interleaving on the symbols included in the plurality of first codewords and the n first bit groups comprises: Acquire at least one second codeword according to the codeword boundary information of the second codeword; Obtaining a starting position of the at least one second codeword, and using the starting position as a starting interleaving position for performing convolution interleaving on symbols included in the plurality of first codewords; The at least one second codeword is decoded to obtain bits corresponding to the n first bit groups.

21. The method according to claim 18, characterized in that The performing convolution deinterleaving on the bits corresponding to the n first bit groups to obtain a plurality of first codewords includes: Obtaining a starting deinterleaving position corresponding to the starting interleaving position in a plurality of delay units of a convolutional deinterleaver; Input the bits corresponding to the n first bit groups from the starting deinterleaving position into the multiple delay units of the convolutional deinterleaver, and perform convolutional deinterleaving on the polled bits corresponding to the n first bit groups through the multiple delay units of the convolutional deinterleaver; The symbols included in the multiple first codewords polled and output by the multiple delay units of the convolutional deinterleaver are obtained, and the multiple first codewords are obtained according to the symbols included in the multiple first codewords.

22. The method according to claim 21, characterized in that The multiple delay units of the convolutional deinterleaver output the symbols included in the multiple first codewords in the form of a second data stream, and the transmission rate of the second data stream is greater than or equal to 100 gigabits per second.

23. The method according to claim 22, characterized in that The transmission rate of the second data stream is greater than or equal to 200 Gbps.

24. The method according to claim 22 or 23, characterized in that The multiple delay units of the convolutional deinterleaver output the second data stream through at least one channel of the connection unit interface AUI.

25. A data transmission device, characterized in that: include: A convolution interleaver, configured to perform convolution interleaving on the symbols included in the plurality of first codewords to obtain an interleaved result, wherein the interleaved result includes n first bit groups, and the first codeword is encoded using a first forward error correction FEC code; A forward error correction FEC encoder is used to encode the bits corresponding to the n first bit groups according to a second FEC code to obtain n second code words, where the number of bits corresponding to the n first bit groups is equal to the number of bits included in the information bits of the n second code words, and n is a positive integer.

26. The data transmission device according to claim 25, characterized in that: The four adjacent symbols in the interleaving result are from different first code words.

27. The data transmission device according to claim 25, characterized in that: The second codeword includes codeword boundary information, and the codeword boundary information indicates a starting position for performing the convolution interleaving on the symbols included in the multiple first codewords.

28. The data transmission device according to claim 25, characterized in that: The second FEC code is a Hamming code.

29. The data transmission device according to claim 25, characterized in that: The convolution interleaver includes a plurality of delay units, and the plurality of delay units of the convolution interleaver are used to perform convolution interleaving on symbols included in the plurality of first code words input in a polling manner to obtain the interleaving result.

30. The data transmission device according to claim 26, characterized in that: The convolution interleaver includes a plurality of delay units, and the plurality of delay units of the convolution interleaver are used to perform convolution interleaving on symbols included in the plurality of first code words input in a polling manner to obtain the interleaving result.

31. The data transmission device according to claim 29, characterized in that: One of the first bit groups includes symbols output by the plurality of delay units polling once.

32. The data transmission device according to claim 30, characterized in that: One of the first bit groups includes symbols output by the plurality of delay units polling once.

33. The data transmission device according to any one of claims 25 to 32, characterized in that: The starting interleaving position for performing convolution interleaving on the symbols included in the multiple first code words is the polling starting position when the symbols of the first code words are polled and input to the multiple delay units of the convolution interleaver.

34. The data transmission device according to any one of claims 25 to 32, characterized in that: The symbols included in the multiple first codewords are input into the multiple delay units of the convolution interleaver in the form of a first data stream, and the transmission rate of the first data stream is greater than or equal to 100 gigabits per second.

35. The data transmission device according to claim 33, characterized in that: The symbols included in the multiple first codewords are input into the multiple delay units of the convolution interleaver in the form of a first data stream, and the transmission rate of the first data stream is greater than or equal to 100 gigabits per second.

36. The data transmission device according to claim 34, characterized in that: The transmission rate of the first data stream is greater than or equal to 200 Gbps.

37. The data transmission device according to claim 35, characterized in that: The transmission rate of the first data stream is greater than or equal to 200 Gbps.

38. The data transmission device according to claim 34, characterized in that: The first data stream is transmitted to the multiple delay units of the convolution interleaver through at least one channel of the connection unit interface AUI.

39. The data transmission device according to any one of claims 29 to 32, characterized in that: The plurality of delay units are a plurality of delay rows.

40. The data transmission device according to claim 39, characterized in that: The number of bits corresponding to the delay blocks included in each delay row is 40 bits.

41. A data transmission device, characterized in that: include: Acquisition unit for: Receive n second code words, where the n second code words are obtained by encoding bits corresponding to n first bit groups according to a second forward error correction (FEC) code, the number of bits corresponding to the n first bit groups is equal to the number of bits included in the information bits of the n second code words, and n is a positive integer; Decoding the n second code words to obtain the n first bit groups; A deinterleaving unit is used to perform convolution deinterleaving on bits corresponding to the n first bit groups to obtain multiple first code words, where the first code words are encoded using a first FEC code.

42. The data transmission device according to claim 41, characterized in that: The second FEC code is a Hamming code.

43. The data transmission device according to claim 41, characterized in that: The second codeword includes codeword boundary information, and the codeword boundary information indicates a starting interleaving position for performing convolution interleaving on symbols included in the plurality of first codewords.

44. The data transmission device according to any one of claims 41 to 43, characterized in that: The acquisition unit is further used for: A starting interleaving position for performing convolution interleaving on the symbols included in the multiple first codewords and the n first bit groups are obtained according to the codeword boundary information of the second codeword.

45. The data transmission device according to claim 44, characterized in that: The acquisition unit is further used for: Acquire at least one second codeword according to the codeword boundary information of the second codeword; Obtaining a starting position of the at least one second codeword, and using the starting position as a starting interleaving position for performing convolution interleaving on symbols included in the plurality of first codewords; The at least one second codeword is decoded to obtain bits corresponding to the n first bit groups.

46. ​​The data transmission device according to claim 43, characterized in that: The de-interleaving unit is used for: Obtaining a starting deinterleaving position corresponding to the starting interleaving position in a plurality of delay units of a convolutional deinterleaver; Input the bits corresponding to the n first bit groups from the starting deinterleaving position into the multiple delay units of the convolutional deinterleaver, and perform convolutional deinterleaving on the polled bits corresponding to the n first bit groups through the multiple delay units of the convolutional deinterleaver; The symbols included in the multiple first codewords polled and output by the multiple delay units of the convolutional deinterleaver are obtained, and the multiple first codewords are obtained according to the symbols included in the multiple first codewords.

47. The data transmission device according to claim 46, characterized in that: The multiple delay units of the convolutional deinterleaver output the symbols included in the multiple first codewords in the form of a second data stream, and the transmission rate of the second data stream is greater than or equal to 100 gigabits per second.

48. The data transmission device according to claim 47, characterized in that: The transmission rate of the second data stream is greater than or equal to 200 Gbps.

49. The data transmission device according to claim 47, characterized in that: The multiple delay units of the convolutional deinterleaver output the second data stream through at least one channel of the connection unit interface AUI.

50. The data transmission device according to claim 46, characterized in that: The plurality of delay units are a plurality of delay rows.

51. A data transmission system, characterized in that: It comprises a first data transmission device and a second data transmission device, wherein the first data transmission device is used to execute the method according to any one of claims 1 to 15, and the second data transmission device is used to execute the method according to any one of claims 16 to 24.

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