Data processing method and data processing device

Abstract

Embodiments of this application disclose a data processing method and a data processing device, which can achieve good performance of a connected FEC-based solution in low-latency scenarios. In a connected FEC-based transmission solution, before convolutional interleaving is performed on a first data stream, interleaved alignment must first be performed to determine the boundaries of each bit set in the first data stream and the boundaries of each bit subset within each bit set. Furthermore, in the convolutional interleaving process, bit subsets are transmitted to each storage unit as granularity. In other words, each bit subset contains d bits, and each storage unit is configured to store d bits. The bits in each bit subset come from v symbols, and each of the v symbols comes from v first codewords. In other words, one symbol is selected from each of the v first codewords to form a bit subset.

Description

[Technical Field]

[0001] This application relates to the field of optical communications, and more particularly to data processing methods and data processing devices. [Background technology]

[0002] With the relentless advancement of 5G, cloud computing, big data, artificial intelligence, and similar technologies, optical communication systems and optical transport networks (OTNs) are evolving in a direction characterized by high capacity and ultra-high speed. Forward error correction (FEC) coding is used to correct transmitted data, eliminate transmission bit errors, and reconstruct the original data transmitted by the transmitter from the received data.

[0003] Currently, a concatenated FEC-based transmission solution is proposed, in which the transmitter device is connected to a transmitter processing module via an attachment unit interface (AUI). The transmitter device performs a first FEC encoding on the data to be transmitted and sends the data obtained through the first FEC encoding to the transmitter processing module. The transmitter processing module then performs a second FEC encoding on the data obtained through the first FEC encoding and transmits the data obtained through the second FEC encoding to the data receiver via the channel. Specifically, the transmitter processing module receives data streams from multiple lanes, first performs convolutional interleaving separately on the data streams from multiple lanes, and then performs a second FEC encoding on each data stream obtained through the convolutional interleaving. However, in current solutions, convolutional interleaving requires high latency to achieve good performance, and its effectiveness is not ideal in scenarios requiring low latency. [Overview of the Initiative]

[0004] Embodiments of this application provide a data processing method and a data processing device that enable good performance of a connected FEC-based solution in low-latency scenarios.

[0005] According to a first aspect, an embodiment of the present application provides a data processing method. The method comprises the following steps: First, m first data streams are obtained, where m is an integer greater than 1. Each of the first data streams is obtained by interleaving v lanes of a first codeword obtained through first FEC coding, and each of the first data streams contains a plurality of consecutive bit sets. Each bit set contains t bit subsets, where t is an integer greater than 1. Each bit subset contains d bits, where d = v × s, where v is an integer greater than 1, and s is an integer greater than or equal to 1, indicating the number of bits contained in each symbol in the first codeword. The bits in each bit subset come from v symbols, each of the v symbols comes from v first codewords, and each of the v first codewords comes from v lanes of the first codeword. Furthermore, the first data stream is delayed based on p delay lines to obtain a second data stream, resulting in a total of m second data streams. p is an integer greater than 1, and the number of memory units contained in the delay lines differs from one another, with the delay line having the fewest memory units containing zero. The difference between the number of memory units in every pair of adjacent delay lines is Q, where Q is an integer greater than or equal to 1, and each memory unit is configured to store d bits. The bits in each of the first data streams are sequentially input into the p delay lines based on the sequence number of the p delay lines, with d bits in one bit subset being input into each delay line at once, and d bits being output from each delay line at once.

[0006] In this implementation, for a connected FEC-based transmission solution, before convolutional interleaving is performed on the first data stream, interleaving alignment must first be performed to determine the boundaries of each bit set and each bit subset within the first data stream. Furthermore, the bit subsets are sent to each memory unit as granularity during the convolutional interleaving operation. In other words, each bit subset contains d bits, and each memory unit is configured to store d bits. The bits in each bit subset come from v symbols, and each of the v symbols comes from v first codewords. In other words, one symbol is selected from each of the v first codewords to form a bit subset. In conjunction with subsequent convolutional interleaves, complete outer codeword symbols can be mapped to inner codewords with minimal interleaving delays, resulting in an uncorrectable inner codeword containing at most one incorrect symbol of the outer codeword associated with it. This avoids error dispersion across multiple symbols of the outer codeword, improving the performance of concatenated codes.

[0007] In some possible implementations, p × d consecutive bits in each of the second data streams originate from v × p first codewords. Then, internal code coding is performed for each of the p × d consecutive bits in each of the second data streams to obtain an internal codeword, and as a result, the bits in each internal codeword can be mapped to the maximum number of external codewords. In this way, the performance of the concatenated code is optimized.

[0008] In some possible implementations, among p delay lines, the delay line with the largest sequence number contains zero memory units, and (p × Q + 1) ≥ t. Specific implementation solutions are provided to achieve optimal performance of concatenated code, and the implementability of the solutions is enhanced.

[0009] In some possible implementations, among p delay lines, the delay line with the smallest sequence number contains zero memory units and (p × Q-1) ≥ t. A different specific implementation solution is provided to achieve optimal performance for concatenated code, increasing the flexibility of the solution.

[0010] In some possible implementations, Q is a multiple of 2, and as a result, the convolutional interleaver is performed by using a low-frequency clock.

[0011] In some possible implementations, m first data streams are obtained by multiplexing n lane data streams, where n is an integer multiple of m, and the first FEC encoding is performed on each of the lane data streams. Each lane data stream contains multiple alignment markers (AMs), each first data stream contains multiple AM ​​sets, each AM set contains n / m AMs, and an integer number of bit sets are contained between the starting positions of every two adjacent AM sets.

[0012] In some possible implementations, the step of obtaining m first data streams includes: performing interleaved alignment on the first data streams based on at least one AM set to determine the boundary positions of each bit set in the first data stream. In other words, in the first data stream, the boundary positions of bit sets are determined by identifying the AM sets. Also, since the length of each bit set is fixed, the boundary of each of the other bit sets is determined based on the boundary of one bit set. Furthermore, the boundary of each bit subset in a bit set may be determined based on each bit set whose position has been determined.

[0013] In some possible implementations, multiple bit sets include a first bit set and a second bit set that are adjacent to each other, where the bits in the first bit set are from v first codewords obtained through a first FEC coding, and the bits in the second bit set are from another v first codewords obtained through a first FEC coding.

[0014] In some possible implementations, every v consecutive bits in a bit subset each come from v first codewords, or every s consecutive bits in a bit subset come from the same first codeword.

[0015] In some possible implementations, m=8, v=4, t=68, s=10, p=3, and Q=23 or 24; or m=4, v=4, t=136, s=10, p=3, and Q=46.

[0016] In some possible implementations, after obtaining a total of m second data streams, the method further: The process includes the step of performing a second FEC coding separately on m second data streams to obtain m third data streams, where K information bits in each second codeword obtained through the second FEC coding come from at most p × v different first codewords, where K is an integer multiple of p × d.

[0017] According to a second aspect, an embodiment of the present application provides a data processing device. The data processing device includes a processing unit and a convolutional interleaver. The processing unit is configured to acquire m first data streams, where m is an integer greater than 1, and each of the first data streams is acquired by interleaving v lanes of a first codeword acquired through first FEC coding. First FEC coding is performed on each of the first data streams, each of the first data streams containing a plurality of consecutive bit sets, each bit set containing t bit subsets, where t is an integer greater than 1. Each bit subset contains d bits, where d = v × s, where v is an integer greater than 1, and s is an integer greater than or equal to 1, indicating the number of bits contained in each symbol in the first codeword. The bits in each bit subset come from v symbols, each of the v symbols comes from v first codewords, and each of the v first codewords comes from v lanes of the first codeword. The convolutional interleaver is configured to obtain a second data stream by delaying a first data stream based on p delay lines, resulting in a total of m second data streams. p is an integer greater than 1, and the number of memory units contained in the delay lines differs from one another, with the delay line having the fewest memory units containing zero. The difference between the number of memory units in every pair of adjacent delay lines is Q, which is an integer greater than or equal to 1, and each memory unit is configured to store d bits. The bits in each of the first data streams are sequentially input into the p delay lines based on the sequence number of the p delay lines, with d bits in one bit subset being input into each delay line at once, and d bits being output from each delay line at once.

[0018] In some possible implementations, p × d consecutive bits in each of the second data streams come from v × p first codewords.

[0019] In some possible implementations, the delay line having the largest sequence number among the p delay lines includes zero memory units, and (p×Q + 1) ≥ t.

[0020] In some possible implementations, the delay line having the smallest sequence number among the p delay lines includes zero memory units, and (p×Q - 1) ≥ t.

[0021] In some possible implementations, Q is a multiple of 2.

[0022] In some possible implementations, m first data streams are obtained by multiplexing n lane data streams. n is an integer multiple of m, and the first FEC encoding is performed for each of the lane data streams. Each of the lane data streams includes a plurality of AMs, each of the first data streams includes a plurality of AM sets, each of the AM sets includes n / m AMs, and an integer number of bit sets are included between the start positions of all adjacent two AM sets.

[0023] In some possible implementations, the processing unit is specifically configured to perform interleaving alignment on the first data stream based on at least one AM set to determine the boundary position of each bit set in the first data stream.

[0024] In some possible implementations, the plurality of bit sets include the first bit set and the second bit set that are adjacent to each other. The bits in the first bit set are from v first codewords obtained through the first FEC encoding, and the bits in the second bit set are from another v first codewords obtained through the first FEC encoding.

[0025] In some possible implementations, every v consecutive bits in a bit subset each come from v first codewords, or every s consecutive bits in a bit subset come from the same first codeword.

[0026] In some possible implementations, m=8, v=4, t=68, s=10, p=3, and Q=23 or 24; or m=4, v=4, t=136, s=10, p=3, and Q=46.

[0027] In some possible implementations, the data processing unit further includes an encoder, and the encoder is: The system is configured to obtain m third data streams by separately performing a second FEC encoding on m second data streams, where K information bits in each second codeword obtained through the second FEC encoding come from at most p × v different first codewords, and K is an integer multiple of p × d. [Brief explanation of the drawing]

[0028] Figure 1 is a diagram of a communication system to which the embodiment of this application is applied.

[0029] Figure 2 is a diagram illustrating the data transmission process in the communication system shown in Figure 1.

[0030] Figure 3 shows the data processing of the transmitter processing module according to the embodiment of the present application.

[0031] Figure 4 is a flowchart of the data processing method according to the embodiment of the present application.

[0032] Figure 5 shows the first structure of the first data stream according to an embodiment of the present application.

[0033] Figure 6 shows the second structure of the first data stream according to the embodiment of the present application.

[0034] Figure 7 shows the third structure of the first data stream according to the embodiment of the present application.

[0035] Figure 8 shows the fourth structure of the first data stream according to the embodiment of the present application.

[0036] Figure 9 shows how convolutional interleaving is performed separately on m first data streams according to an embodiment of the present application.

[0037] Figure 10(a) is a diagram of the first structure of a convoluted interleaver according to an embodiment of the present application.

[0038] Figure 10(b) shows a second structure of a convoluted interleaver according to an embodiment of the present application.

[0039] Figure 11 shows the application of a second FEC encoding process for m second data streams according to an embodiment of the present invention.

[0040] Figure 12 shows a diagram of 32 PCS lane data streams when the transmitter device uses a 1 x 800G interface.

[0041] Figure 13 shows the fifth structure of the first data stream according to an embodiment of the present application.

[0042] Figure 14 shows the sixth structure of the first data stream according to an embodiment of the present application.

[0043] Figure 15 shows a third structure of a convoluted interleaver according to an embodiment of the present application.

[0044] Figure 16 shows a fourth structure of a convoluted interleaver according to an embodiment of the present application.

[0045] Figure 17 shows a fifth structure of a convoluted interleaver according to an embodiment of the present application.

[0046] Figure 18 is a diagram of the seventh structure of the first data stream according to an embodiment of the present application.

[0047] Figure 19 shows a sixth structure of a convoluted interleaver according to an embodiment of the present application.

[0048] Figure 20 shows a diagram of 16 PCS lane data streams in a 1600GbE scenario.

[0049] Figure 21 is a diagram of the eighth structure of the first data stream according to an embodiment of the present application.

[0050] Figure 22 is another diagram illustrating the data processing of the transmitter processing module according to the embodiment of the present application.

[0051] Figure 23 shows the multiplexing of the first data stream according to the embodiment of the present application.

[0052] Figure 24 is a diagram showing the structure of a data processing device according to an embodiment of the present application.

[0053] Figure 25 shows another structure of the data processing device according to the embodiment of the present application. [Modes for carrying out the invention]

[0054] The embodiments of this application provide a data processing method and a data processing device that enable good performance of connected FEC-based solutions in low-latency scenarios. It should be noted that the terms “First,” “Second,” and similar terms in the specification, claims, and accompanying drawings of this application are intended to distinguish similar subjects but do not necessarily indicate a specific order or sequence. The aforementioned terms are interchangeable in appropriate contexts, and it should be understood that the embodiments described in this application may be implemented in an order other than that described herein. Furthermore, the terms “includes,” “has,” or any other variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device including a series of steps or units may include, but is not limited to, other steps and units not explicitly listed, or that are specific to the process, method, product, or device.

[0055] Figure 1 is a diagram of a communication system to which an embodiment of the present application applies. As shown in Figure 1, the communication system includes a transmitter device 01, a transmitter processing module 02, a channel transmission medium 03, a receiver processing module 04, and a receiver device 05. For example, the communication system is a data center network. The transmitter device 01 and the receiver device 05 may each be devices such as a switch or a router, the transmitter device 01 is also called a host chip located in the transmitter, the receiver device 05 is also called a host chip located in the receiver device, and the channel transmission medium 03 may be an optical fiber. The host chip is also sometimes called a host device. The transmitter device 01 may be connected to the transmitter processing module 02 via an attachment unit interface (AUI), and the receiver device 05 may be connected to the receiver processing module 04 via an AUI. The transmitter processing module 02 and the receiver processing module 04 may each be an optical module, an electrical module, a connector, or another module that processes data in the data transmission process. For example, the processing module may be an 800GEFR module. Furthermore, the transmitter device 01, transmitter processing module 02, channel transmission medium 03, receiver processing module 04, and receiver device 05 in the communication system may all support bidirectional or unidirectional transmission. This is not particularly limited in this invention.

[0056] Figure 2 is a diagram of the data transmission process in the communication system shown in Figure 1. As shown in Figure 2, in the process of transmitting data from transmitter device 01 to receiver device 05, transmitter device 01 is configured to perform external code coding on the data and then transmit the externally coded data to transmitter processing module 02. Transmitter processing module 02 is configured to perform internal code coding on the externally coded data to obtain the externally coded and internally coded data and transmit the externally coded and internally coded data to channel transmission medium 03. Channel transmission medium 03 is configured to transmit the externally coded and internally coded data to receiver processing module 04. Receiver processing module 04 is configured to perform internal code decoding on the externally coded and internally coded data and transmit the internally coded decoded data to receiver device 05. Receiver device 05 is configured to perform external code decoding on the internally coded decoded data.

[0057] It should be understood that the distinction between "internal" in internal coding and "external" in external coding is merely based on the distance between the channel transmission medium 03 and the executing entity that performs operations on the data. The executing entity that performs operations on internal coding is closer to the channel transmission medium, while the executing entity that performs operations on external coding is further away from the channel transmission medium. In the embodiments of this application, data is transmitted from the transmitter device 01 to the channel transmission medium 03 via the transmitter processing module 02, and then transmitted from the channel transmission medium 03 to the receiver device 05 via the receiver processing module 04. The distance between the data encoded by the transmitter device 01 and the channel transmission medium 03 is greater than the distance between the data encoded by the transmitter processing module 02 and the channel transmission medium 03, and the distance between the data decoded by the receiver device 05 and the channel transmission medium 03 is greater than the distance between the data decoded by the receiver processing module 04 and the channel transmission medium 03. Therefore, the data encoded by the transmitter device 01 is called the data after external coding, the data encoded by the transmitter processing module 02 is called the data after internal coding, the data decoded by the receiver device 05 is called the data after external coding decoding, and the data decoded by the receiver processing module 04 is called the data after internal coding decoding. In possible implementations, both internal coding and external coding use FEC coding schemes to form a connected FEC-based transmission solution. For example, the transmitter device 01 can perform external coding by using RS coding, and the transmitter processing module 02 can perform internal coding by using Hamming coding.In another example, the transmitter device 01 may perform external coding by using RS coding, and the transmitter processing module 02 may perform internal coding by using Bose Chaudhuri Hocquenghem (BCH) coding.

[0058] It should be noted that the foregoing is an illustrative description of application scenarios for the data processing method provided in the embodiments of this application and does not constitute any limitation to the application scenarios of the data processing method. Those skilled in the art will know that as service requirements change, the application scenarios for the data interleaving method may be adjusted according to the application requirements. Application scenarios are not enumerated in the embodiments of this application.

[0059] Regarding the aforementioned interconnected FEC-based transmission solution, a data processing method including interleaved alignment and convolutional interleaving is designed in this application, resulting in an interconnected FEC with extremely low latency and good performance that can meet the requirements of a wider range of transmission scenarios, and is particularly applicable to transmission scenarios requiring low transmission latency, such as low-latency data center internal interconnection scenarios. The data processing method is carried out by the aforementioned transmitter processing module 02.

[0060] Figure 3 is a diagram illustrating the data processing of a transmitter processing module according to an embodiment of the present application. As shown in Figure 3, the transmitter processing module receives data from an AUI-m interface, which includes m data lanes, where m is a positive integer greater than 1, and each of the m data lanes is used to transmit m first encoded data streams. It should be understood that external coding is performed for each of the first encoded data streams. In one example, transmitter device 01 performs external coding to obtain n Physical Coding Sublayer (PCS) lane data streams or FEC lane data streams, which may be abbreviated as n lane data streams, each lane data stream being obtained by interleaving u lanes of first FEC codewords. Interleaving or multiplexing is performed on n lane data streams to obtain m first encoded data streams, where each first data stream is obtained by interleaving v lanes of first FEC codewords, where v is exactly divisible by u. First, receive processing such as Clock and Data Recovery (CDR), equalization, and demodulation is performed on the m first encoded data streams. Then, interleaved alignment, convolutional interleaving, and internal code coding are performed sequentially and separately on the m first encoded data streams to obtain m second encoded data streams. Furthermore, data processing is performed on the data streams after internal code coding, and the processed data streams are then transmitted to a channel transmission medium for transmission. Data processing may include modulation mapping, channel interleaving, and similar processes.

[0061] It should be noted that the convolutional interleaving operation specifically involves disordering the input bits and then sending the bits to the internal code encoder for internal code coding. Interleaving alignment specifically involves dividing the boundaries in each of the first coded data streams based on specific requirements, and based on this division scheme, sending the bits in the first coded data streams in batches to the memory units of the convolutional interleaver, so that the bit sequences sent in batches to the memory units of the convolutional interleaver satisfy the design requirements. The design requirements are described in detail below. In other words, the interleaving alignment operation may be considered as preparation for the convolutional interleaving to ensure that the convolutional interleaving is performed on the premise of the data alignment designed in this application.

[0062] Figure 4 is a schematic flowchart of the data processing method according to the embodiment of the present application. Specifically, the data processing method may be performed by the transmitter processing module 02.

[0063] Retrieve 101:m first data streams.

[0064] In this embodiment, the first FEC coding, i.e., external code coding, is performed on all m first data streams, where m is an integer greater than 1. It should be noted that the m first data streams are obtained by multiplexing n lane data streams, the first FEC coding is performed on each lane data stream, where n is an integer multiple of m, and the codeword obtained through the first FEC coding is called the first FEC codeword. In possible implementations, the transmitter device 01 periodically inserts alignment markers (AM) into the data to be transmitted and performs the first FEC coding. Then, after the first FEC codewords for u lanes are interleaved, the first FEC codewords are assigned to n PCS lanes to form n lane data streams. By using a Physical Medium Attachment (PMA) sublayer, after n lane data streams are multiplexed, m lane first data streams are obtained by interleaving the first FEC codewords of v lanes, and these m lane first data streams are transmitted to the transmitter processing module 02 via the AUI-m interface. Each of the m lanes in the AUI-m interface is used to transmit the m first data streams. It should be understood that each of the first data streams is a data stream that has undergone interleaved alignment. The characteristics of the first data streams obtained through interleaved alignment are described below.

[0065] Figure 5 is a diagram of the first structure of a first data stream according to an embodiment of the present application. As shown in Figure 5, each of the first data streams includes a plurality of consecutive bit sets, e.g., bit set 1, bit set 2, ... Each bit set contains t bit subsets, where t is an integer greater than 1. Each bit subset contains d bits, where d = v × s, where v is an integer greater than 1. s is an integer greater than or equal to 1, where s represents the number of bits contained in each symbol of the first codeword obtained through the first FEC coding. For example, if the first FEC codeword is RS(544,514), then s = 10. It should be understood that the bits in each bit subset come from v symbols, and each of the v symbols comes from v first codewords. In other words, one symbol is selected from each of the v first codewords to form a bit subset. It should be understood that each of the first data streams is obtained by interleaving v lanes of the first codeword, and each lane of the first codeword contains multiple first codewords. Here, the v first codewords are each from the v lanes of the first codeword. This is equivalent to the v first codewords being obtained by selecting one codeword from each of the v lanes of the first codeword. Therefore, L = v × t × s consecutive bits in a bit set are from the v first codewords. It should be understood that this is equivalent to the t symbols from the same first FEC codeword each being located in t bit subsets. It should also be understood that two consecutive bit sets are each from different first FEC codewords. For example, the bits in bit set 1 come from v first codewords obtained through a first FEC coding, and the bits in bit set 2 come from other v first codewords obtained through a first FEC coding.

[0066] It should be noted that bit sets and bit subsets are merely concepts introduced for the sake of clarity. In actual applications, each of the first data streams is a whole and not divided. It should also be noted that in some possible scenarios, bit sets may be called interleaved blocks, and bit subsets may be called interleaved subblocks. The names bit sets and bit subsets are not particularly limited in this context.

[0067] Figure 6 is a diagram of the second structure of the first data stream according to an embodiment of the present application. As shown in Figure 6, bit set 1 in the first data stream is used as an example. AM sets are arranged starting from the start boundary of bit set 1. Since each lane data stream contains multiple AMs, and n lane data streams are multiplexed to obtain m first data streams, it should be understood that the AM set in the bit set of the first data stream contains n / m AMs, and the AM set is obtained by multiplexing / interleaving n / m AMs. It is possible to obtain specific data based on the specific multiplexing scheme used when n lane data streams are multiplexed into m first data streams, and specific data in the AMs. In other words, the distribution or arrangement scheme of n / m AMs in the AM set is not limited in this application. For example, n / m = 4, and n lane data streams are multiplexed in a symbol multiplexing scheme to obtain m first data streams. The 4i-th symbol in the AM set is from AM0, the (4i+1)-th symbol in the AM set is from AM1, the (4i+2)-th symbol in the AM set is from AM2, the (4i+3)-th symbol in the AM set is from AM3, where i is an integer. As shown in Figure 6, different patterns within a block indicate that the symbols are from different AMs. In another example, n / m=4, and n lane data streams are multiplexed in a bit multiplexing scheme to obtain m first data streams. The 4i-th bit in the AM set is from AM0, the (4i+1)-th bit in the AM set is from AM1, the (4i+2)-th bit in the AM set is from AM2, the (4i+3)-th bit in the AM set is from AM3, where i is an integer. As shown in Figure 6, different patterns within a block indicate that the bits are from different AMs.

[0068] It should be further understood that the first data stream contains multiple AM ​​sets, with an integer number of bit sets contained between the starting positions of every two adjacent AM sets. In other words, in a real application, an AM set is not necessarily placed at the starting position of each bit set in the first data stream; the next AM set may exist after bit set 1 at intervals of multiple bit sets.

[0069] It should be noted that in this application, the boundaries of bit sets are defined by using the starting positions of AM sets. Therefore, the interleaving placement operation may be understood as determining the boundaries of corresponding bit sets based on at least one AM set. This is equivalent to determining the boundary positions of bit sets in the first data stream by identifying the AM sets. Furthermore, since the length of each bit set is fixed, the boundaries of each other bit set are determined based on the boundaries of one bit set. In addition, the boundaries of each bit subset within a bit set can be determined based on each bit set whose position has been determined.

[0070] Figure 7 shows a third structure of the first data stream according to an embodiment of the present application. As shown in Figure 7, in possible implementations, a bit subset of bit set 1 is used as an example. Each v consecutive bits in the bit subset are from v first codewords. Each block in the bit subset shown in Figure 7 represents one bit, and different patterns within the block indicate that the bits are from different first codewords. In Figure 7, v=4 is used as an example.

[0071] Figure 8 is a diagram of the fourth structure of the first data stream according to an embodiment of the present application. As shown in Figure 8, in another possible implementation, a bit subset of bit set 1 is used as an example. Every s consecutive bits in the bit subset are from the same first codeword. Each block in the bit subset shown in Figure 8 represents s bits, i.e., one symbol, and different patterns within the block indicate that the symbols are from different first codewords.

[0072] 102: Perform convolutional interleaving separately on m first data streams to obtain m second data streams.

[0073] Figure 9 shows a diagram illustrating the separate execution of convolutional interleaving on m first data streams according to an embodiment of the present application. As shown in Figure 9, convolutional interleaving can be performed separately on m first data streams via m convolutional interleavers, and a second data stream of a non-ordered data sequence may be obtained through convolutional interleaving on each of the first data streams. It should be noted that in this embodiment, each convolutional interleaver performs convolutional interleaving on the input first data stream in a similar manner. Specifically, each convolutional interleaver includes p delay lines, and each convolutional interleaver delays the input first data stream based on the p delay lines to obtain the second data stream. p is an integer greater than 1, the number of memory units contained in each delay line differs from one another, the delay line with the fewest number of memory units contains 0 memory units, and the difference between the number of memory units for every two adjacent delay lines is Q, where Q is an integer greater than or equal to 1. Each memory unit is configured to store d bits, in other words, each memory unit is configured to store bits within one bit subset. In other words, each of the p delay lines corresponds to p delay values, which include 0 bits, V bits, 2V bits, ..., and (p-1)V bits, where V = Q × d. The more bits contained in the delay value of a delay line, the longer the delay (also called latency) caused by the delay line to the data stream. It should be understood that if a delay line does not contain any memory units, the delay caused by the delay line is 0 bits, in other words, a transparent transmission without delay is performed.

[0074] It should be noted that the bits in each of the first data streams are sequentially input to p delay lines based on the sequence numbers of the p delay lines, with d bits in one bit subset being input to each delay line at once, and d bits being output from each delay line at once. The parameter Q is selected such that p × d consecutive bits in each of the second data streams are from v × p first codewords. Then, internal code coding is performed for every p × d consecutive bits in the second data stream to obtain an internal codeword, and as a result, the bits in each internal codeword can be mapped to the maximum number of external codewords. In this way, the performance of the concatenated code is optimized.

[0075] The specific configuration of the convolutional interleaver will be explained below with reference to the attached diagrams.

[0076] Figure 10(a) is a diagram of the first structure of a convolutional interleaver according to an embodiment of the present application. As shown in Figure 10(a), the number of memory units in p delay lines decreases sequentially based on the sequence number of the p delay lines. In other words, delay line 0 has (p-1) × Q memory units, and Q memory units decrease sequentially from each delay line, with delay line (p-1) having 0 memory units. In this implementation, the parameters p, Q, and d satisfy (p × Q + 1) ≥ t, and as a result, p × d consecutive bits in the second data stream are derived from v × p first codewords.

[0077] Figure 10(b) shows a second structure of a convolutional interleaver according to an embodiment of the present application. As shown in Figure 10(b), the number of memory units in p delay lines increases sequentially based on the sequence number of the p delay lines. In other words, delay line 0 has 0 memory units, and for each delay line, the number of memory units increases sequentially by Q, so that delay line (p-1) has (p-1) × Q memory units. In this implementation, the parameters p, Q, and d satisfy (p × Q-1) ≥ t, and therefore, p × d consecutive bits in the second data stream are derived from v × p first codewords.

[0078] It should be noted that at the same moment, the input and output switches of the convolutional interleaver are on the same delay line. After d bits are input to the current delay line and output from the current delay line, the switch position changes to the next delay line, ensuring that the bits in each of the first data streams are sequentially input to the p delay lines based on the sequence number of the p delay lines, and that p × d consecutive bits in the first data streams include the d bits output from each delay line. The specific data read / write operations performed by the convolutional interleaver are as follows: d bits are read from the memory unit closest to the output port that is on the current delay line. The d bits stored in each memory unit on the current delay line are transferred to the next memory unit. Then, d bits are written to the memory unit closest to the input port that is on the current delay line. Then, a switch to the next delay line is performed, and the above operations are repeated. The rest can be inferred by analogy.

[0079] When the same parameters p, Q, and d are used, the convolutional interleaving process in Figure 10(a) and the convolutional interleaving process in Figure 10(b) operate in opposite directions. In other words, if the transmitter processing module uses the convolutional interleaving structure shown in Figure 10(a), the convolutional de-interleaving corresponding to the receiver processing module corresponding to the transmitter processing module uses the structure shown in Figure 10(b). Similarly, if the transmitter processing module uses the convolutional interleaving structure shown in Figure 10(b), the convolutional de-interleaving corresponding to the receiver processing module corresponding to the transmitter processing module uses the structure shown in Figure 10(a).

[0080] It should be further understood that any one of the m convolutional interleavers may use one of the structures shown in Figure 10(a) or Figure 10(b). In actual applications, all m convolutional interleavers may use the structure shown in Figure 10(a); all m convolutional interleavers may use the structure shown in Figure 10(b); or some convolutional interleavers may use the structure shown in Figure 10(a) and the remaining convolutional interleavers may use the structure shown in Figure 10(b).

[0081] 103: Perform a second FEC encoding separately on m second data streams to obtain m third data streams.

[0082] Figure 11 shows a second FEC coding being performed on m second data streams according to an embodiment of the present application. As shown in Figure 11, the second FEC coding, i.e., the internal code coding described above, is performed separately for the m second data streams. Specifically, w × p × d consecutive bits in each second data stream, which is output w times from p delay lines in a round-robin manner, are used as information data for the internal code word, and M bits of redundant data are added through internal code coding to obtain an internal code word with a code length of N = K + M. The information in K = p × w × d information bits in each second code word obtained through the second FEC coding comes from up to p × v different first code words. In particular, when w = 1, the concatenated code can achieve optimal performance.

[0083] The internally coded data stream undergoes data processing and is then sent to a channel transmission medium for transmission. Data processing may include modulation mapping, channel interleaving, polarization distribution, DSP framing, or similar processes. For example, the internally coded data stream may be interleaved and then transmitted to improve the system's ability to withstand burst errors.

[0084] In the embodiments of this application, in the case of a connected FEC-based transmission solution, before convolutional interleaving is performed on the first data stream, interleaved alignment must first be performed to determine the boundaries of each bit set in the first data stream and the boundaries of each bit subset within each bit set. Furthermore, the bit subsets are sent as granularity to each storage unit in the convolutional interleaving process. In other words, each bit subset contains d bits, and each storage unit is configured to store d bits. The bits in each bit subset come from v symbols, and each of the v symbols comes from v first codewords. In other words, one symbol is selected from each of the v first codewords to form a bit subset. Working in conjunction with subsequent convolutional interleaves, complete outer codeword symbols can be mapped to inner codewords with minimal interleaving delay, resulting in an uncorrectable inner codeword being at most one incorrect symbol of the outer codeword associated with it. This avoids error distribution across multiple symbols of the outer codeword, improving the performance of concatenated codes.

[0085] The procedure for the data processing method described in Figure 4 will be further explained below with reference to several specific embodiments.

[0086] Embodiment 1: The application scenario is a 1×800G interface, with m=8, v=4, t=68, s=10, and p=3.

[0087] Figure 12 shows a diagram of 32 PCS lane data streams when a transmission device uses a 1×800G interface. As shown in Figure 12, when transmitter device 01 transmits a 1×800 GE service, in a possible implementation, transmitter device 01 periodically inserts AM into the data stream to be transmitted, then performs RS coding (specifically, external code coding or first FEC coding), then performs interleaving of two lanes of RS codewords to assign the codewords to the 32 PCS lanes, so that the RS codeword arrangement on the 32 PCS lanes is as shown in Figure 12. PCS lane data streams 0 through 15 are formed by interleaving two lanes of RS codewords, and PCS lane data streams 16 through 31 are formed by interleaving the other two lanes of RS codewords. For example, as shown in Figure 12, the first dashed box corresponding to PCS lane data streams 0 through 15 indicates that the portion of the first dashed box is obtained by interleaving RS codeword 1 and RS codeword 2, and the second dashed box corresponding to PCS lane data streams 0 through 15 indicates that the portion of the second dashed box is obtained by interleaving RS codeword 3 and RS codeword 4, where RS codeword 1 and RS codeword 3 come from one lane of the RS codeword, and RS codeword 2 and RS codeword 4 come from the other lane of the RS codeword. The rest can be inferred by analogy. Similarly, the first dashed boxes corresponding to PCS lane data streams 16 through 31 indicate that RS codewords 5 and 6 are used for interleaving, and the second dashed boxes corresponding to PCS lane data streams 16 through 31 indicate that RS codewords 7 and 8 are used for interleaving, with RS codewords 5 and 7 coming from one lane of the RS codeword and RS codewords 6 and 8 coming from the other lane of the RS codeword.The rest can be inferred by analogy.

[0088] Therefore, any symbols from PCS lane data streams 0 through 15 and any symbols from PCS lane data streams 16 through 31 are not from the same RS codeword. Furthermore, two adjacent symbols a=2 within each PCS lane data stream are from different RS codewords, two symbols at the same position within two adjacent PCS lane data streams are from different RS codewords, and 68 consecutive symbols on each PCS lane are from two different RS codewords. The transmitter / device 01 multiplexes the 32 PCS lane data streams into eight data streams using 32:8PMA and transmits the data to the transmitter processing module 02 via the 800GAUI-8 interface. The transmitter processing module 02 performs receive processing such as clock recovery, equalization, and demodulation on the eight data streams from the 800GAUI-8 interface and outputs eight first data streams. Since bidirectional RS interleaving and 32:8 PMA bit multiplexing are performed for each lane data stream within the transmitter device 01, each of the first data streams is obtained by interleaving the RS codewords of v=4 lanes.

[0089] Figure 13 is a diagram of the fifth structure of the first data stream according to an embodiment of the present application. As shown in Figure 13, L1 = 11141120 bits, i.e., 4096 bit sets are included between the start positions of all two AM sets in the first data stream, with each bit set containing 2720 bits. The length of an AM set is four times the length of the AM in the PCS lane data stream. An example is used where the length of the AM is 120 bits, and the length of the AM set is equal to 4 × 120 = 480 bits. The bits in each bit set are obtained by interleaving data from four RS codewords, and the bits in two consecutive bit sets are from different RS codewords. Each bit set contains t = 68 bit subsets, each bit subset containing 40 bits, which are obtained by interleaving RS symbols obtained from the four RS codewords, respectively. In other words, each bit subset contains four RS symbols, each of which comes from a different RS codeword, and each of the four consecutive bits within the bit subset comes from one of four different RS codewords.

[0090] Figure 14 is a diagram of the sixth structure of the first data stream according to an embodiment of the present application. As shown in Figure 14, in a possible implementation, the AM set in the first data stream is initially locked, and then the first data stream is divided by using the AM set as the start to obtain multiple bit subsets, each bit subset containing d=40 bits. This is equivalent to each memory unit in the convolutional interleaver being aligned at the granularity of the bit subset. Thus, this is called interleaved alignment.

[0091] FIG. 15 is a diagram of a third structure of a convolutional interleaver according to an embodiment of the present application. As shown in FIG. 15, p = 3 delay lines are included. The p = 3 delay lines each include 2Q memory units, Q memory units, and 0 memory units, and each memory unit is configured to store one bit subset (d = 40 bits). In other words, the delay value of delay line 0 is 80 × Q bits, the delay value of delay line 1 is 40 × Q bits, and the delay value of delay line 2 is 0 bits, that is, no delay occurs.

[0092] As shown in FIG. 15, C r (·) indicates a bit subset within the first data stream r (0 ≦ r ≦ m - 1). For example, C r (3t) indicates the bit subset currently input from the first data stream r to delay line 0, and C r (3t - 6Q) is the bit subset output from delay line 0. C r (3t + 1) indicates the next bit subset input from the first data stream r to delay line 1, and C r (3t - 3Q + 1) is the bit subset output from delay line 1. C r (3t + 2) indicates the next bit subset input from the first data stream r to delay line 2, and C r (3t + 2) is the bit subset output from delay line 2. C r (3t + 3) indicates the subsequent bit subset input from the first data stream r to delay line 0, and C r (3t - 6Q + 3) is the bit subset output from delay line 0. The rest can be inferred by analogy. According to the RS allocation rule in the first FEC - encoded data stream, two consecutive bit sets in the first data stream are from different RS codewords, and the bit sets are divided into 68 bit subsets. In other words, the bit subset C in the first data streamr (A) Bits and bit subset C r The (A+68) bit is from a different RS codeword. If p×Q+1≧68, i.e., Q≧23, then C is output from the three delay lines of the convolutional interleaver in a round-robin manner. r (3t-6Q), C r (3t-3Q+1), and C r The total of 120 bits in (3t+2) could come from 12 different RS codewords.

[0093] Figure 16 is a diagram of a fourth structure of the convolutional interleaver according to an embodiment of the present application. As shown in Figure 16, in a possible embodiment, Q=23 is selected, and the corresponding total interleaved and deinterleaved latency is approximately 46 × 40 × 3 = 5520 bits. This is equivalent to a total interleaved and deinterleaved latency of approximately 52 ns in a 1 × 800 GE service.

[0094] Figure 17 is a diagram of a fifth structure of a convolutional interleaver according to an embodiment of the present application. As shown in Figure 17, in order to implement the convolutional interleaver by using a low-frequency clock, Q may be further restricted to a multiple of 2, for example, Q=24 is selected. The corresponding total interleaved and deinterleaved latency is 48 × 40 × 3 = 5760 bits. This is equivalent to the total interleaved and deinterleaved delay being about 54 ns in a 1 × 800GE service. In the corresponding hardware implementation, a clock of about 885 MHz may be used. At each clock, three consecutive bit subsets are input to memory units having a 40-bit memory width in three delay lines, and then one bit subset is read from each of the memory units in the three delay lines. This is equivalent to the delay unit of delay line 0 of the convolutional interleaver shown in Figure 17 being implemented using memory with a bit width of 40 bits and a depth of 48 bits, and the delay unit of delay line 1 being implemented using memory with a bit width of 40 bits and a depth of 24 bits. Alternatively, a clock of approximately 442 MHz may be used. At each clock, the i-th and (i+3)-th bit subsets from six consecutive bit subsets are output to a memory unit with an 80-bit memory width on delay line i, and the two bit subsets are simultaneously read from each of the memory units on the three delay lines. This is equivalent to the delay unit of delay line 0 of the convolutional interleaver shown in Figure 17 being implemented using memory with a bit width of 80 bits and a depth of 24 bits, and the delay unit of delay line 1 being implemented using memory with a bit width of 80 bits and a depth of 12 bits.

[0095] Internal code coding is performed separately for the eight second data streams mentioned above, with a length of 120 bits of information used for internal code coding. Specifically, the internal code encoder separately adds redundancy to a total of 120 bits in three consecutive bit subsets within the second data stream to obtain a third data stream, where these 120 bits are the three bit subsets C r (3t-6Q), C r (3t-3Q+1), and C r This is (3t+2) and is output simultaneously from the three delay lines of the convolutional interleaver in a round-robin manner. In this way, de-convolutional interleaving synchronization can be performed after internal code synchronization is complete. In possible implementations, internal code coding is performed by using Hamming(128,120), and 8 bits of redundancy are added to 120 consecutive bits in each of the second data streams to obtain a 128-bit codeword. The pre-FEC bit error rate BER corresponding to a post-FEC BER of 1E-15 is approximately 4.8E-3, and the solution of Embodiment 1 is used so that the performance approaches the optimal performance of concatenated FEC-based solutions and the interleaver latency is within 54ns, and the KP4 RS(544,514)+Hamming(128,120) concatenated code is under AWGN.

[0096] In Embodiment 1, interleaved alignment and convolutional interleaving are performed separately for the eight physical lanes of the data stream from the 800GAUI-8 interface. This embodiment has lower complexity compared to conventional techniques in which AM locking and convolutional interleaving are performed separately on 32 PCS lanes. Furthermore, compared to conventional techniques in which convolutional interleaving is performed on PCS lane data streams acquired through the interleaving of two RS codewords, this solution, in which convolutional interleaving is performed by directly using a first data stream acquired through the interleaving of four RS codewords, can have lower latency. As a result, the connected FEC-based transmission solution can be applied to a number of transmission scenarios, and is particularly applicable to transmission scenarios requiring low transmission latency, such as low-latency data center interconnection scenarios.

[0097] Embodiment 2: The application scenario is a 1×800G interface, with m=4, v=4, t=136, s=10, and p=3.

[0098] The transmitter device 01 multiplexes 32 PCS lane data streams into four data streams using a 32:4 PMA and transmits the data to the transmitter processing module 02 via the 800GAUI-4 interface. The transmitter processing module 02 performs receive processing such as clock recovery, equalization, and demodulation on the four data streams from the 800GAUI-4 interface and outputs four first data streams.

[0099] Figure 18 is a diagram of the seventh structure of the first data stream according to an embodiment of the present application. As shown in Figure 18, L1 = 22,282,240 bits, i.e., 4,096 bit sets are contained between the starting positions of all two AM sets in the first data stream, with each bit set containing 5,440 bits. The length of an AM set is eight times the length of the AM in the PCS lane data stream. An example is used where the length of the AM is 120 bits, and the length of the AM set is equal to 8 × 120 = 960 bits. The bits in each bit set are obtained by interleaving multiple RS symbols from four RS codewords, and the bits in two consecutive bit sets are from different RS codewords. Each bit set contains 136 bit subsets, each bit subset containing 40 bits, which are obtained by interleaving RS symbols obtained from each of the four RS codewords. In other words, each bit subset contains four RS symbols, each of which comes from a different RS codeword, and ten consecutive bits within a bit subset come from the same RS codeword.

[0100] Figure 19 shows a sixth structure of the convolutional interleaver according to an embodiment of the present application. As shown in Figure 19, according to the RS distribution rule in the first encoded stream, bit subset C r (A) Bits and C r This is from a different RS codeword than the bit in (A+136). When p×Q+1≧136, i.e., when Q≧45, C is output from the three delay lines of the convolutional interleaver in a round-robin manner. r (3t-6Q), C r (3t-3Q+1), and C rThe total of 120 bits in (3t+2) may come from 12 different RS codewords. Furthermore, to implement the convolutional interleaver by using a lower frequency clock, Q may also be a multiple of 2 or 4. For example, Q = 46. In hardware implementations, a clock of approximately 1.77 GHz may be used. At each clock, three consecutive bit subsets are input to memory units having a 40-bit memory width in three delay lines, and then one bit subset is read from each of the memory units in the three delay lines. This is equivalent to the delay unit of delay line 0 in the convolutional interleaver shown in Figure 19 being implemented using memory with a bit width of 40 bits and a depth of 92 bits, and the delay unit of delay line 1 being implemented using memory with a bit width of 40 bits and a depth of 46 bits. Alternatively, a clock of approximately 885 MHz may be used. At each clock cycle, the i-th and (i+3)th bit subsets from six consecutive bit subsets are output to a memory unit with an 80-bit memory width on delay line i, and the two bit subsets are simultaneously read from each of the memory units on the three delay lines. This is equivalent to the delay unit on delay line 0 of the convolutional interleaver shown in Figure 19, which is implemented using memory with a bit width of 80 bits and a depth of 46 bits, and the delay unit on delay line 1, which is implemented using memory with a bit width of 80 bits and a depth of 23 bits.

[0101] In Embodiment 2, interleaved alignment and convolutional interleaving are performed separately for the four physical lanes of the data stream from the 800GAUI-8 interface. This embodiment has lower complexity compared to conventional techniques in which 32 PCS lanes are first recovered from four physical lanes from the 800GAUI-4 interface, and then AM locking and convolutional interleaving are performed separately. Furthermore, compared to conventional techniques in which convolutional interleaving is performed on PCS lane data streams acquired through the interleaving of two RS codewords, this solution, in which convolutional interleaving is performed by directly using the first data stream acquired through the interleaving of four RS codewords, may have lower latency. As a result, the connected FEC-based transmission solution can be applied to a number of transmission scenarios, particularly those requiring low transmission latency, such as low-latency data center interconnection scenarios.

[0102] Embodiment 3: The application scenario is a 1600G interface, with m=8, v=4, t=68, s=10, and p=3.

[0103] Figure 20 shows a diagram of 16 PCS lane data streams in a 1600GbE scenario. As shown in Figure 20, transmitter device 01 periodically inserts AM into the data stream to be transmitted, then performs RS coding (specifically, external code coding or first FEC coding), then performs interleaving of 4-lane RS codewords to assign the codewords to the 16 PCS lanes, so that the RS codeword arrangement on the 16 PCS lanes is as shown in Figure 20. Four adjacent a=4 symbols in each PCS lane data stream are from different RS codewords, two symbols in the same position in two adjacent PCS lane data streams are from different RS codewords, and 136 consecutive symbols on each PCS lane are from four RS codewords. The transmitter device 01 performs symbol multiplexing on 16 PCS lane data streams using a 16:8 PMA and then transmits the data to the transmitter processing module 02 via the 1600GAUI-8 interface. The transmitter processing module 02 performs receive processing such as clock recovery, equalization, and demodulation on the eight data streams from the 1600GAUI-8 interface and outputs eight first data streams.

[0104] Figure 21 is a diagram of the eighth structure of the first data stream according to an embodiment of the present application. As shown in Figure 21, L1 = 22,282,240 bits, i.e., 8,192 bit sets are included between the start positions of all two AM sets in the first data stream, with each bit set containing 2,720 bits. The length of an AM set is twice the length of the AM in the PCS lane data stream. An example is used where the length of the AM is 120 bits, and the length of the AM set is equal to 2 × 120 = 240 bits. The bits in each bit set are obtained by interleaving multiple RS symbols from four RS codewords, and the bits in two consecutive bit sets are from different RS codewords. Each bit set contains t = 68 bit subsets, each bit subset contains 40 bits, which are obtained by interleaving RS symbols obtained from each of the four RS codewords. In other words, each bit subset contains four RS symbols, each of which comes from a different RS codeword, and ten consecutive bits within a bit subset come from the same RS codeword.

[0105] In Embodiment 3, the convolutional interleaver shown in Figure 15 may be used. According to the RS distribution rule in the first encoded stream, bit subset C r (A) Bits and C r This is from a different RS codeword than the bit in (A+68). In this case, if p×Q+1≧68, i.e., Q≧23, then C is output from the three delay lines of the convolutional interleaver in a round-robin manner. r (3t-6Q), C r (3t-3Q+1), and C rThe total 120 bits in (3t+2) could be from 12 different RS codewords. Furthermore, to implement the convolutional interleaver by using a lower frequency clock, Q may also be a multiple of 2 or 4. For example, a specific implementation of the convolutional interleaver when Q=24 is shown in Figure 17. The corresponding total interleaving and deinterleaving latency is 48 × 40 × 3 = 5760 bits. This is equivalent to an overall interleaving and deinterleaving latency of approximately 27 ns in a 1 × 1600 GE service.

[0106] In the hardware implementation, a clock of approximately 1.77 GHz may be used. At each clock, three consecutive bit subsets are input to memory units with a 40-bit memory width in three delay lines, and then one bit subset is read from each of the memory units in the three delay lines. This is equivalent to the delay unit of delay line 0 in the convolutional interleaver shown in Figure 17, which is implemented using memory with a 40-bit width and a depth of 48 bits, and the delay unit of delay line 1, which is implemented using memory with a 40-bit width and a depth of 24 bits. Alternatively, a clock of approximately 885 MHz may be used. At each clock, the i-th and (i+3)-th bit subsets from six consecutive bit subsets are output to a memory unit with an 80-bit memory width in delay line i, and two bit subsets are read simultaneously from each of the memory units in the three delay lines. This is equivalent to the delay unit of delay line 0 of the convolutional interleaver shown in Figure 17 being implemented using memory with a bit width of 80 bits and a depth of 24 bits, and the delay unit of delay line 1 being implemented using memory with a bit width of 80 bits and a depth of 12 bits. Alternatively, a clock of approximately 442.5 MHz may be used. At each clock, the i-th, (i+3), (i+6), and (i+9) bit subsets from 12 consecutive bit subsets are output to a memory unit with a memory bit width of 160 bits on delay line i, and four bit subsets are simultaneously read from each of the memory units on the three delay lines. This is equivalent to the delay unit of delay line 0 of the convolutional interleaver shown in Figure 17 being realized by using memory with a bit width of 160 bits and a depth of 12 bits, and the delay unit of delay line 1 being realized by using memory with a bit width of 160 bits and a depth of 6 bits.

[0107] In Embodiment 3, interleaved alignment and convolutional interleaving are performed separately for the eight physical lanes of the data stream from the 1600GAUI-8 interface. This embodiment has lower complexity compared to conventional techniques in which 16 PCS lanes are first restored from the eight physical lanes from the 800GAUI-8 interface, and then AM locking and convolutional interleaving are performed separately.

[0108] In actual applications, it should be noted that after interleaving alignment is complete, the transmitter processing module can further multiplex m first data streams and then perform convolutional interleaving, thereby increasing the rate of a single physical lane of the AUI-m interface while maintaining the invariance of subsequent convolutional interleaving and encoding. This implementation will be described below.

[0109] Figure 22 is another diagram of the data processing of the transmitter processing module according to an embodiment of the present application. As shown in Figure 22, after performing interleaved alignment on m first encoded data streams to obtain m first data streams, the transmitter processing module first multiplexes the m first data streams to obtain m / 2 multiplexed data streams, and then separately performs convolutional interleaving on the m / 2 multiplexed data streams to obtain m / 2 second data streams. Furthermore, internal coding is performed on the m / 2 second data streams to obtain m / 2 second encoded data streams.

[0110] Figure 23 shows the multiplexing of the first data stream according to the embodiment of the present application. As shown in Figure 23, the multiplexing process involves multiplexing each of the two first data streams into one multiplexed data stream. Specifically, one bit subset is output from the two first data streams to one multiplexed data stream in a round-robin manner; in other words, two consecutive bit subsets in the multiplexed data stream come from the first data stream 2i and the first data stream (2i+1), respectively.

[0111] The data processing device provided in the embodiments of this application will be described below.

[0112] Figure 24 is a diagram of the structure of a data processing device according to an embodiment of the present application. As shown in Figure 24, the data processing device includes a processing unit 201, a convolutional interleaver 202, and an encoder 203. The processing unit 201 is configured to perform the operation of step 101. The convolutional interleaver 202 is configured to perform the operation of step 102. The encoder 203 is configured to perform the operation of step 103. For specific operations, please refer to the relevant description of the data processing method described above. Details will not be described again here.

[0113] It should be understood that the device provided in this application may be implemented in an alternative manner. For example, the division into units in the aforementioned device is merely a logical functional division, and other divisions may be used in actual implementations. For example, multiple units or components may be combined or integrated into another system. Furthermore, the functional units in the embodiments of this application may be integrated into a single physical unit, be independent physical units, or two or more functional units may be integrated into a single physical unit. The integrated unit may be implemented in hardware form or in the form of a software functional unit.

[0114] Figure 25 is a diagram of another structure of a data processing device according to an embodiment of the present application. As shown in Figure 25, the data processing device includes a processor 301, a memory 302, and a transceiver 303. The processor 301, the memory 302, and the transceiver 303 are interconnected via a line. The memory 302 is configured to store program instructions and data. Specifically, the transceiver 303 is configured to perform data reception and transmission operations. The processor 301 is configured to perform the operations of the data processing method described above. In possible implementations, the processor 301 may include a processing unit 201, a convolutional interleaver 202, and an encoder 203, as shown in Figure 24.

[0115] It should be noted that the processor shown in Figure 24 may be a Central Processing Unit (CPU), a general-purpose processor, a Digital Signal Processor (DSP), an Application-Specific Integrated Circuit (ASIC), a Field-Programmable Gate Array (FPGA) or another programmable logic device, a transistor logic device, a hardware component, or any combination thereof. The memory shown in Figure 24 is capable of storing an operating system and another application program. If the technical solution provided in the embodiments of this application is implemented by software or firmware, the program code used to implement the technical solution provided in the embodiments of this application is stored in memory and executed by the processor. In embodiments, the processor may include memory internally. In another embodiment, the processor and memory are two separate structures.

[0116] For the sake of convenient and concise explanation, it will be readily apparent to those skilled in the art that the detailed operating processes of the aforementioned systems, devices, and units should be referred to in the corresponding processes in the embodiments of the methods described above. Further details are not provided here.

[0117] Those skilled in the art will understand that all or part of the steps in the embodiments described above may be performed by hardware or a program directing the associated hardware. The program may be stored on a computer-readable storage medium. The storage medium may be read-only memory, random-access memory, or similar. Whether the function is performed by hardware or by software depends on the specific application and design constraints of the technical solution. Those skilled in the art may use various methods to implement the described functions for each specific application, but such implementations should not be considered to extend beyond the scope of this application.

[0118] Where software is used for implementation, all or part of the method steps described in the embodiments described above may be implemented in the form of a computer program product. A computer program product includes one or more computer instructions. When the computer program instructions are loaded onto a computer and executed, the procedure or function according to the embodiments of this application occurs, in whole or in part. The computer may be a general-purpose computer, a dedicated computer, a computer network, or another programmable device. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by wired (e.g., coaxial cable, optical fiber, or digital subscriber line (DSL)) or wireless (e.g., infrared, radio, or microwave). The computer-readable storage medium may be any available medium accessible by a computer, or a data storage device that integrates one or more available media, such as a server or data center. The usable media may be magnetic media (e.g., floppy disks, hard disks, or magnetic tapes), optical media (e.g., DVDs), semiconductor media (e.g., solid-state disks (SSDs)), or similar media.

Claims

1. A data processing method: Steps include: obtaining m first data streams, where m is an integer greater than 1, each of the first data streams being obtained by interleaving v lanes of a first codeword obtained through first forward error correction FEC coding, each of the first data streams containing a plurality of consecutive bit sets, each of the bit sets containing t bit subsets, where t is an integer greater than 1, each of the bit subsets containing d bits, where d = v × s, where v is an integer greater than 1, s representing the number of bits contained in each symbol in the first codeword, where s is an integer greater than or equal to 1, the bits in each of the bit subsets coming from v symbols, each of the v symbols coming from v first codewords, and each of the v first codewords coming from v lanes of the first codeword; and The step of obtaining m second data streams by separately delaying the m first data streams based on p delay lines, where p is an integer greater than 1, the number of memory units included in the delay lines differs from one another, the delay line having the fewest number of memory units contains zero memory units, the difference between the number of memory units in all adjacent pairs of delay lines is Q, where Q is an integer greater than or equal to 1, each memory unit is configured to store d bits, the bits in each of the first data streams are sequentially input to the p delay lines based on the sequence number of the p delay lines, d bits in one bit subset are input to each delay line at once, and d bits are output from each delay line at once; A method that includes this.

2. The method according to claim 1, wherein p × d consecutive bits in each of the second data streams are derived from v × p first codewords.

3. The method according to claim 1 or 2, wherein the delay line having the largest sequence number among the p delay lines includes zero memory units, and (p × Q + 1) ≥ t.

4. The method according to claim 1 or 2, wherein the delay line having the smallest sequence number among the p delay lines comprises zero memory units, and (p × Q-1) ≥ t.

5. A method according to any one of claims 1 to 4, wherein Q is a multiple of 2.

6. A method according to any one of claims 1 to 5, wherein the m first data streams are obtained by multiplexing n lane data streams, where n is an integer multiple of m, the first FEC coding is performed on each of the lane data streams, each of the lane data streams includes a plurality of alignment markers AM, each of the first data streams includes a plurality of AM sets, each of the AM sets includes n / m AMs, and an integer number of bit sets are included between the starting positions of all adjacent pairs of AM sets.

7. The method according to claim 6, the step of obtaining the m first data streams is: A method comprising the step of performing interleaved alignment on the first data stream based on at least one AM set to determine the boundary position of each bit set in the first data stream.

8. A method according to any one of claims 1 to 7, wherein the plurality of bit sets include a first bit set and a second bit set which are adjacent to each other, the bits in the first bit set are from v first codewords obtained through the first FEC coding, and the bits in the second bit set are from another v first codewords obtained through the first FEC coding.

9. A method according to any one of claims 1 to 8, wherein every v consecutive bits in the bit subset each come from v first codewords, or every s consecutive bits in the bit subset come from the same first codeword.

10. A method according to any one of claims 1 to 9, wherein m=8, v=4, t=68, s=10, p=3, and Q=23,24; or m=4, v=4, t=136, s=10, p=3, and Q=46.

11. In the method according to any one of claims 1 to 10, after obtaining a total of m second data streams, the method: A method comprising the step of separately performing a second FEC encoding on the m second data streams to obtain m third data streams, wherein K information bits in each second codeword obtained through the second FEC encoding are from at most p × v different first codewords, where K is an integer multiple of p × d.

12. A data processing device including a processing unit and a convolutional interleaver: The processing unit is configured to acquire m first data streams, where m is an integer greater than 1, each of the first data streams is acquired by interleaving v lanes of a first codeword acquired through first forward error correction FEC coding, each of the first data streams contains a plurality of consecutive bit sets, each of the bit sets contains t bit subsets, where t is an integer greater than 1, each of the bit subsets contains d bits, where d = v × s, where v is an integer greater than 1, s indicates the number of bits contained in each symbol in the first codeword, where s is an integer greater than or equal to 1, the bits in each of the bit subsets come from v symbols, each of the v symbols comes from v first codewords, and each of the v first codewords comes from v lanes of the first codeword; and A data processing device comprising a convolutional interleaver configured to obtain m second data streams by separately delaying the m first data streams based on p delay lines, where p is an integer greater than 1, the number of memory units included in the delay lines differs from one another, the delay line having the fewest number of memory units contains zero memory units, the difference between the number of memory units in all adjacent pairs of delay lines is Q, where Q is an integer greater than or equal to 1, each memory unit is configured to store d bits, the bits in each of the first data streams are input sequentially to the p delay lines based on the sequence number of the p delay lines, d bits in one bit subset are input to each delay line at once, and d bits are output from each delay line at once.

13. A data processing device according to claim 12, wherein p × d consecutive bits in each of the second data streams are derived from v × p first codewords.

14. A data processing device according to claim 12 or 13, wherein the storage unit includes zero delay lines having the largest sequence number among the p delay lines, and (p × Q + 1) ≥ t.

15. A data processing device according to claim 12 or 13, wherein the storage unit comprises zero delay lines having the smallest sequence number among the p delay lines, and (p × Q - 1) ≥ t.

16. A data processing device according to any one of claims 12 to 15, wherein Q is a multiple of 2.

17. A data processing device according to any one of claims 12 to 16, wherein the m first data streams are obtained by multiplexing n lane data streams, where n is an integer multiple of m, the first FEC coding is performed on each of the lane data streams, each of the lane data streams includes a plurality of alignment markers AM, each of the first data streams includes a plurality of AM sets, each of the AM sets includes n / m AMs, and an integer number of bit sets are included between the starting positions of all adjacent pairs of AM sets.

18. In the data processing apparatus according to claim 17, the processing unit is: A data processing device specifically configured to perform interleaved alignment on the first data stream based on at least one AM set to determine the boundary position of each bit set in the first data stream.

19. A data processing device according to any one of claims 12 to 18, wherein the plurality of bit sets include a first bit set and a second bit set which are adjacent to each other, the bits in the first bit set are from v first codewords obtained through the first FEC coding, and the bits in the second bit set are from another v first codewords obtained through the first FEC coding.

20. A data processing device according to any one of claims 12 to 19, wherein every v consecutive bits in the bit subset each come from v first codewords, or every s consecutive bits in the bit subset come from the same first codeword.

21. A data processing device according to any one of claims 12 to 20, wherein m=8, v=4, t=68, s=10, p=3, and Q=23,24; or m=4, v=4, t=136, s=10, p=3, and Q=46.

22. A data processing device according to any one of claims 12 to 21, wherein the data processing device further includes an encoder, the encoder is: A data processing device configured to obtain m third data streams by separately performing a second FEC encoding on m second data streams, wherein K information bits in each second codeword obtained through the second FEC encoding are from at most p × v different first codewords, and K is an integer multiple of p × d.

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