A time interval measuring device based on time-amplitude conversion

Abstract

The application discloses a time interval measuring device based on time-amplitude conversion, which generates a control signal according to a control word from a host computer to control the operation of the device; then, the FPGA controls an analog channel to measure the channel delay τ AB or τ BA , and completes the input signal preprocessing; then, a waveform comparison transformation integrates the output signal of the analog channel into a to-be-measured pulse signal which can be correctly processed by the FPGA; then, the FPGA performs time coarse counting, sub-period time extraction, sub-period time pulse widening and error correction on the to-be-measured pulse signal; finally, a time-amplitude conversion unit is used for sampling and quantization.

Description

Technical Field

[0001] This invention belongs to the field of signal measurement and processing technology, and more specifically, relates to a time interval measurement device based on time amplitude conversion. Background Technology

[0002] Time interval measurement devices have wide applications in many fields such as high-energy physics experiments, radar identification, time and frequency measurement, and integrated circuit testing. A time interval is a continuous process, a period of time between two moments. Time interval measurement is also called time measurement. Time interval measurement devices need to meet certain accuracy requirements. Early time measurement devices were relatively simple in principle, similar to frequency measurement, relying on the principle of direct counting in the time domain. By counting a standard reference clock, the number of clock cycles within a certain period was obtained, and the measured time interval was calculated based on the standard clock period and the count value. This method is characterized by its simplicity and convenience, and the measurement resolution is proportional to the counting clock frequency. However, due to factors such as device materials and manufacturing processes, the reference counting clock frequency has an upper limit. The measurement resolution and accuracy based on the reference clock counting method cannot be better than one counting clock cycle, thus limiting the improvement in measurement resolution and accuracy. With technological advancements, modern time interval measurement devices have continuously improved measurement resolution and accuracy, while the measurement time has gradually decreased, enabling them to adapt to and meet the ever-increasing time and time interval measurement requirements of various electronic devices.

[0003] Furthermore, time interval measurement devices also need to possess a certain real-time calibration capability to ensure the normal operation of various technical functions and that parameter indicators meet requirements. Traditional time interval measurement devices typically employ direct counting methods or use vernier methods or digital device tap delay methods to improve measurement resolution and accuracy. These methods have drawbacks such as relatively low measurement accuracy, relatively long measurement time, and high cost. More importantly, these devices lack real-time calibration capabilities. When changes in the measurement environment cause changes in device parameters, it may further lead to a decrease in time interval measurement accuracy, making them unsuitable for current time interval measurement needs. Therefore, fully utilizing the internal hardware resources of time interval measurement devices to design a time interval measurement device with high resolution and high accuracy, while also possessing real-time calibration capabilities, has significant theoretical and engineering application value. Summary of the Invention

[0004] The purpose of this invention is to overcome the shortcomings of the prior art and provide a time interval measurement device based on time amplitude conversion. It uses a field-programmable gate array (FPGA) as the core device of the time interval measurement device to complete the high-precision time interval measurement and correction of the measured signal.

[0005] To achieve the above-mentioned objectives, the present invention provides a time interval measurement device based on time-amplitude conversion, characterized in that it comprises: a signal preprocessing unit, a waveform comparison and transformation unit, a time-amplitude conversion unit, a programmable logic array (FPGA), and a host computer;

[0006] The signal preprocessing unit includes two analog channels, A and B, which are used to condition the input signal and set the measurement time interval between the two analog channels A and B according to the control signal sent by the FPGA.

[0007] The host computer sends control signals to the preprocessing unit, which then controls the preprocessing unit to set the reference channel. When the preprocessing unit sets analog channel A as the reference channel, it sets the measurement time interval τ between analog channel B and analog channel A. AB Conversely, set the measurement time interval τ between analog channel A and analog channel B. BA ;

[0008] The waveform comparison and transformation unit includes a hysteresis comparator and a level converter;

[0009] The system receives control signals from the FPGA and controls the trigger level of the hysteresis comparator. This causes the input signals of the two analog channels A and B to pass through the hysteresis comparator and obtain two differential pulse signals with an unchanged time interval relationship. After the two differential pulse signals are level-converted by the level converter, two pulse signals under test with steep edges that can be received by the FPGA are obtained.

[0010] The FPGA includes a time interval measurement module, a control unit, a sub-cycle time stretching module, and a data integration module; wherein, the time interval measurement module further includes a frequency division delay module, a sub-cycle time extraction module, an error correction module, and a coarse counting module;

[0011] After the two pulse signals to be tested are input to the FPGA, they are divided and delayed by a frequency division and delay module. The process is as follows: first, the two pulse signals to be tested are divided to reduce the frequency; then, using the input signal of the reference channel in the signal preprocessing unit as the standard, the input signal of the other channel is delayed by a fixed time T through a frequency division and delay chain. delay The process yields two pulse signals with correct timing that can be used to measure zero time intervals, denoted as pulse signal S. a and pulse signal S b Then the pulse signal S a and S b The input is sent to the coarse counting module, with a fixed delay T. delay Input to the error correction module;

[0012] In the coarse counting module, the pulse signal S a and Sb Perform a logical AND operation to obtain the original gate signal S. OriG ; The control signal S output by the control unit En With the original gate signal S Ori Perform a logical AND operation to obtain the time interval signal S to be measured. TI The time interval signal S to be measured TI The pulse width of each pulse is exactly the measurement time interval τ, τ∈(τ AB ,τ BA The time interval signal S to be measured TI Synchronization with the standard clock CLK inside the FPGA yields a synchronization gate pulse used for coarse counting to widen the measurement range, with a gate width T. Rg When the rising edge of the synchronization gate pulse arrives, at the gate width T Rg Internally, a counter is used to count the pulse width of the synchronization gate pulse to obtain a coarse count value N0, which is then sent to the data integration module; additionally, the time interval signal S to be measured is... TI The synchronous gate pulse is sent to the sub-cycle time extraction module;

[0013] In the sub-period time extraction module, the time interval signal S to be measured is... TI The pulse is XORed with the synchronous gate pulse to obtain the sub-period time pulse, which is then input to the sub-period widening module.

[0014] The sub-period broadening module widens the leading-edge sub-period time T on the sub-period time pulse. SubFr and the sub-period time T of the trailing edge SubRe ;

[0015] The sub-cycle time stretching module will extend the leading sub-cycle time T SubFr Stretching the pulse by several standard clock cycles yields a pulse width of T. ExtFr The broadened pulse S ExtFr Additionally, the period stretching module uses an internal standard clock CLK to control the leading-edge sub-period stretching time T. ExtFr Processing to generate a representative pulse width lower limit T FlLiFr The broadened pulse S FlLiFr And represents the upper limit of pulse width T UpLiFr The broadened pulse S UpLiFr Then, the broadened pulse S ExtFr S FlLiFr S UpLiFr Input to the time-amplitude conversion unit;

[0016] In addition, the sub-period time stretching module will extend the trailing sub-period time T. SubRe Stretching the pulse by several standard clock cycles yields a pulse width of T. ExtRe The broadened pulse S ExtReAdditionally, the period stretching module uses its internal standard clock CLK to stretch the trailing edge sub-period time T. ExtRe Processing to generate a representative pulse width lower limit T FlLiRe The broadened pulse S FlLiRe And represents the upper limit of pulse width T UpLiRe The broadened pulse S UpLiRe Then, the broadened pulse S ExtRe S FlLiRe S UpLiRe Input to the time-amplitude conversion unit;

[0017] In the error correction module, the FPGA calculates the error based on the inherent delay T. Delay Generate a standard delay chain to produce a correction pulse S Delay Additionally, the FPGA uses its internal standard clock CLK to control the inherent delay T. Delay Processing to generate a representative pulse width lower limit T FlLi The correction pulse S FlLi And represents the upper limit of pulse width T UpLi The correction pulse S UpLi Then the correction pulse S Delay S FlLi S UpLi Input to the time-amplitude conversion unit;

[0018] The time-amplitude conversion unit includes a charge-discharge unit and an ADC. The single-cycle operation of the time-amplitude conversion unit is charging, sampling, and discharging. Specifically, the charge-discharge unit receives control signals from the FPGA and sequentially controls each pulse to linearly charge the capacitor in the charge-discharge unit. When the capacitor is fully charged, the ADC is controlled to sample the charging result and then the sampling result is fed back to the FPGA. After sampling, the capacitor in the charge-discharge unit is immediately controlled to fully discharge.

[0019] After a single operation is completed, a set of digital voltage values ​​is sampled, in which the pulse S is stretched. ExtFr S FlLiFr S UpLiFr After sequential linear charging, the digital voltage N is sampled. ExtFr N FlLiFr and N UpLiFr ; Utilizing the pulse broadening S ExtRe S FlLiRe S UpLiRe After sequential linear charging, the digital voltage N is sampled. ExtRe N FlLiRe and N UpLiRe Using the correction pulse S Delay S FlLi S UpLi After sequential linear charging, the digital voltage N is sampled.Delay N FlLi and N UpLi ;

[0020] Finally, the time-amplitude conversion unit packages the measured digital voltage and sends it to the data integration module.

[0021] The data integration module sends the coarse count data and the voltage digital quantity packet to the host computer.

[0022] The host computer controls the entire device's operation by sending control words to the FPGA's control unit and using control signals corresponding to the control unit's parameters. Simultaneously, the host computer calculates the final measurement time interval τ based on the coarse count data and the voltage digital packet.

[0023]

[0024] Where T0 is the delay difference between the standard delay chain and the frequency division signal delay chain.

[0025] The objective of this invention is achieved as follows:

[0026] This invention relates to a time interval measurement device based on time-amplitude conversion. First, it generates a control signal based on a control word from a host computer to control the device's operation. Then, it uses an FPGA to control an analog channel and measures the channel delay τ. AB Or τ BA The input signal preprocessing is completed; then, the waveform comparison and transformation transforms the output signal of the analog channel into a test pulse signal that the FPGA can process correctly. Then, the FPGA performs time coarse counting, sub-period time extraction, sub-period time pulse broadening and error correction on the test pulse signal. Finally, the time amplitude conversion unit samples and quantizes the signal.

[0027] Meanwhile, the time interval measurement device based on time amplitude conversion of the present invention also has the following beneficial effects:

[0028] (1) The time amplitude conversion measurement method adopted in this invention has high measurement accuracy and high measurement resolution. Combined with coarse counting, it can measure a wide range of time intervals and has a wide measurement range.

[0029] (2) Based on FPGA programmable logic devices and host computer test software, the functions can be easily expanded and upgraded, and the test environment adaptability is better.

[0030] (3) The present invention has excellent signal conditioning capabilities and can process signals with a wide range of frequency variations and large amplitude variations. The efficient design ensures low cost.

[0031] (4) The present invention provides real-time error correction and can accurately quantify the impact of environmental factors, thus having higher measurement stability and accuracy. Attached Figure Description

[0032] Figure 1 This is a diagram of the time interval measurement device based on time amplitude conversion according to the present invention;

[0033] Figure 2 This is a time interval extraction timing diagram of the time interval measurement device based on time amplitude conversion according to the present invention;

[0034] Figure 3 This is a timing diagram of the charging pulse of the time interval measurement device based on time amplitude conversion according to the present invention;

[0035] Figure 4 This is a timing diagram of the error correction for the time interval measurement device based on time amplitude conversion according to the present invention;

[0036] Figure 5 This is a circuit diagram of the time amplitude conversion circuit of the time interval measurement device based on time amplitude conversion of the present invention; Detailed Implementation

[0037] The specific embodiments of the present invention will now be described with reference to the accompanying drawings to enable those skilled in the art to better understand the invention. It should be particularly noted that in the following description, detailed descriptions of known functions and designs that might obscure the main content of the invention will be omitted here.

[0038] Example

[0039] Figure 1 This invention relates to a time interval measurement device based on time amplitude conversion.

[0040] In this embodiment, as Figure 1 As shown, the present invention provides a time interval measurement device based on time-amplitude conversion, comprising: a signal preprocessing unit, a waveform comparison and transformation unit, a time-amplitude conversion unit, a programmable logic array (FPGA), and a host computer;

[0041] In this embodiment, the signal preprocessing unit includes two analog signal input channels, A and B, for time interval measurement. These channels are used to condition the input signal. The signal conditioning process includes impedance matching, gain control, AC / DC coupling, signal compensation, and signal distribution. Impedance matching can be selected in 1MΩ or 50Ω mode according to the input signal frequency. Gain control can control whether to attenuate the input signal based on the amplitude of the input signal. AC / DC coupling can control the passage of AC and DC signals. Signal compensation is implemented through the principle of high and low frequency path separation. Signal distribution sets the measurement time interval of the two analog channels A and B according to the control signal sent by the FPGA.

[0042] The host computer sends control signals to the preprocessing unit, which then controls the preprocessing unit to set the reference channel. When the preprocessing unit sets analog channel A as the reference channel, it sets the measurement time interval τ between analog channel B and analog channel A. AB Conversely, set the measurement time interval τ between analog channel A and analog channel B. BA ;

[0043] The waveform comparison and transformation unit includes a hysteresis comparator and a level converter;

[0044] The system receives control signals from the FPGA and controls the trigger level of the hysteresis comparator. This causes the input signals of the two analog channels A and B to pass through the hysteresis comparator and obtain two differential pulse signals with an unchanged time interval relationship. The two differential pulse signals are then converted from ECL level to LVECL level by a level converter to obtain two pulse signals under test with steep edges that can be received by the FPGA.

[0045] The FPGA includes a time interval measurement module, a control unit, a sub-cycle time stretching module, and a data integration module; the time interval measurement module further includes a frequency division delay module, a sub-cycle time extraction module, an error correction module, and a coarse counting module.

[0046] After the two pulse signals to be tested are input to the FPGA, they are divided and delayed by a frequency division and delay module. The process is as follows: first, the two pulse signals to be tested are divided to reduce the frequency; then, using the input signal of the reference channel in the signal preprocessing unit as the standard, the input signal of the other channel is delayed by a fixed time T through a frequency division and delay chain. delay The process yields two pulse signals with correct timing that can be used to measure zero time intervals, denoted as pulse signal S. a and pulse signal S b Then the pulse signal S a and S b The input is sent to the coarse counting module, with a fixed delay T. delay Input to the error correction module;

[0047] In this embodiment, because delay processing of high-frequency signals can lead to timing errors, to ensure the correct system timing, the frequencies of the two pulse signals to be measured need to be reduced by frequency division before delay processing. The frequency division operation does not change the relative measurement time interval τ between the two signals, and the following relationship exists:

[0048] Measurement time interval τ and the period T of the pulse signal to be measured x The relationship is shown in formula (1).

[0049] τ≤T x (1)

[0050] Add a fixed delay T to the measurement time interval τ delay The period T after frequency division with the pulse signal to be measured d The relationship is shown in formula (2).

[0051] τ+T delay ≤T d =nT x (2)

[0052] Where n is a positive integer;

[0053] From formulas (1) and (2), we can obtain the following relationship:

[0054]

[0055] When the delay T delay Certainly, sufficient timing margin must be allowed based on the input signal frequency. Low-frequency signals should be divided by a smaller factor, and high-frequency signals should be divided by a larger factor to resolve timing relationship errors. This also enables the device to measure the time interval of high-frequency input signals.

[0056] In the coarse counting module, such as Figure 2 As shown, the pulse signal S a and S b Perform a logical AND operation to obtain the original gate signal S. OriG ; The control signal S output by the control unit En With the original gate signal S Ori Perform a logical AND operation to obtain the time interval signal S to be measured. TI The time interval signal S to be measured TI The pulse width of each pulse is exactly the measurement time interval τ, τ∈(τ AB ,τ BA The time interval signal S to be measured TI Synchronization with the standard clock CLK inside the FPGA yields a synchronization gate pulse used for coarse counting to widen the measurement range, with a gate width T. Rg When the rising edge of the synchronization gate pulse arrives, at the gate width T Rg Internally, a counter is used to count the pulse width of the synchronization gate pulse to obtain a coarse count value N0, which is then sent to the data integration module; additionally, the time interval signal S to be measured is... TI The synchronous gate pulse is sent to the sub-cycle time extraction module;

[0057] In the sub-period time extraction module, the time interval signal S to be measured is... TI The pulse is XORed with the synchronous gate pulse to obtain the sub-period time pulse, which is then input to the sub-period widening module.

[0058] The sub-period broadening module widens the leading-edge sub-period time T on the sub-period time pulse. SubFr and the sub-period time T of the trailing edge SubRe ;

[0059] like Figure 3 As shown, the sub-cycle time stretching module will stretch the leading sub-cycle time T SubFr Stretching the pulse by several standard clock cycles yields a pulse width of T. ExtFr The broadened pulse S ExtFr Additionally, the period stretching module uses an internal standard clock CLK to control the leading-edge sub-period stretching time T. ExtFr Processing to generate a representative pulse width lower limit T FlLiFr The broadened pulse S FlLiFr And represents the upper limit of pulse width T UpLiFr The broadened pulse S UpLiFr Then, the broadened pulse S ExtFr S FlLiFr S UpLiFr Input to the time-amplitude conversion unit;

[0060] In addition, such as Figure 3 As shown, the sub-period time stretching module stretches the trailing edge sub-period time T. SubRe Stretching the pulse by several standard clock cycles yields a pulse width of T. ExtRe The broadened pulse S ExtRe Additionally, the period stretching module uses its internal standard clock CLK to stretch the trailing edge sub-period time T. ExtRe Processing to generate a representative pulse width lower limit T FlLiRe The broadened pulse S FlLiRe And represents the upper limit of pulse width T UpLiRe The broadened pulse S UpLiRe Then, the broadened pulse S ExtRe S FlLiRe S UpLiRe Input to the time-amplitude conversion unit;

[0061] like Figure 4 As shown, in the error correction module, the FPGA calculates the error based on the inherent delay T. Delay Generate correction pulse S Delay Additionally, the FPGA uses its internal standard clock CLK to control the inherent delay T. Delay Processing to generate a representative pulse width lower limit T FlLi The correction pulse S FlLi And represents the upper limit of pulse width T UpLi The correction pulse S UpLi Then the correction pulse S Delay S FlLi S UpLi Input to the time-amplitude conversion unit;

[0062] like Figure 5 As shown, the time-amplitude conversion unit includes a charge-discharge unit and an ADC. The single-cycle operation of the time-amplitude conversion unit consists of charging, sampling, and discharging. Specifically, the charge-discharge unit receives control signals from the FPGA and sequentially controls each pulse to linearly charge the capacitor in the charge-discharge unit. When the capacitor is fully charged, the ADC is controlled to sample the charging result and then the sampling result is fed back to the FPGA. After sampling, the capacitor in the charge-discharge unit is immediately controlled to fully discharge.

[0063] After a single operation is completed, a set of digital voltage values ​​is sampled. Among them, such as... Figure 3 As shown, using the stretched pulse S ExtFr S FlLiFr S UpLiFr After sequential linear charging, the digital voltage N is sampled. ExtFr N FlLiFr and N UpLiFr ; Utilizing the pulse broadening S ExtRe S FlLiRe S UpLiRe After sequential linear charging, the digital voltage N is sampled. ExtRe N FlLiRe and N UpLiRe ;like Figure 4 As shown, using the correction pulse S Delay S FlLi S UpLi After sequential linear charging, the digital voltage N is sampled. Delay N FlLi and N UpLi ;

[0064] Finally, the time-amplitude conversion unit packages the measured digital voltage and sends it to the data integration module.

[0065] The data integration module sends the coarse count data and the voltage digital data packet to the host computer.

[0066] The host computer controls the entire device by sending control words to the FPGA control unit and using the control signals corresponding to the control unit parameters. Simultaneously, the host computer calculates the final measurement time interval τ based on the coarse count data and the voltage digital packet.

[0067]

[0068] Where T0 is the delay difference between the standard delay chain and the frequency division signal delay chain.

[0069] Although the illustrative specific embodiments of the present invention have been described above to enable those skilled in the art to understand the invention, it should be understood that the invention is not limited to the scope of the specific embodiments. For those skilled in the art, various changes are obvious as long as they are within the spirit and scope of the invention as defined and determined by the appended claims, and all inventions utilizing the concept of the present invention are protected.

Claims

1. A time interval measurement device based on time-amplitude conversion, characterized in that, include: Signal preprocessing unit, waveform comparison and transformation unit, time-amplitude conversion unit, programmable logic array (FPGA) and host computer; The signal preprocessing unit includes two analog channels, A and B, which are used to condition the input signal and set the measurement time interval between the two analog channels A and B according to the control signal sent by the FPGA. The host computer sends control signals to the preprocessing unit, which then controls the preprocessing unit to set the reference channel. When the preprocessing unit sets analog channel A as the reference channel, it sets the measurement time interval τ between analog channel B and analog channel A. AB Conversely, set the measurement time interval τ between analog channel A and analog channel B. BA ; The waveform comparison and transformation unit includes a hysteresis comparator and a level converter; The system receives control signals from the FPGA and controls the trigger level of the hysteresis comparator. This causes the input signals of the two analog channels A and B to pass through the hysteresis comparator and obtain two differential pulse signals with an unchanged time interval relationship. After the two differential pulse signals are level-converted by the level converter, two pulse signals under test with steep edges that can be received by the FPGA are obtained. The FPGA includes a time interval measurement module, a control unit, a sub-cycle time stretching module, and a data integration module; wherein, the time interval measurement module further includes a frequency division delay module, a sub-cycle time extraction module, an error correction module, and a coarse counting module; After the two pulse signals to be tested are input to the FPGA, they are divided and delayed by a frequency division and delay module. The process is as follows: first, the two pulse signals to be tested are divided to reduce the frequency; then, using the input signal of the reference channel in the signal preprocessing unit as the standard, the input signal of the other channel is delayed by a fixed time T through a frequency division and delay chain. delay The process yields two pulse signals with correct timing that can be used to measure zero time intervals, denoted as pulse signal S. a and pulse signal S b Then the pulse signal S a and S b The input is sent to the coarse counting module, with a fixed delay T. delay Input to the error correction module; In the coarse counting module, the pulse signal S a and S b Perform a logical AND operation to obtain the original gate signal S. OriG ; The control signal S output by the control unit En With the original gate signal S Ori Perform a logical AND operation to obtain the time interval signal S to be measured. TI The time interval signal S to be measured TI The pulse width of each pulse is exactly the measurement time interval τ, τ∈(τ AB ,τ BA The time interval signal S to be measured TI Synchronization with the standard clock CLK inside the FPGA yields a synchronization gate pulse used for coarse counting to widen the measurement range, with a gate width T. Rg When the rising edge of the synchronization gate pulse arrives, at the gate width T Rg Internally, a counter is used to count the pulse width of the synchronization gate pulse to obtain a coarse count value N0, which is then sent to the data integration module; additionally, the time interval signal S to be measured is... TI The synchronous gate pulse is sent to the sub-cycle time extraction module; In the sub-period time extraction module, the time interval signal S to be measured is... TI The pulse is XORed with the synchronous gate pulse to obtain the sub-period time pulse, which is then input to the sub-period widening module. The sub-period broadening module widens the leading-edge sub-period time T on the sub-period time pulse. SubFr and the sub-period time T of the trailing edge SubRe ; The sub-cycle time stretching module will extend the leading sub-cycle time T SubFr Stretching the pulse by several standard clock cycles yields a pulse width of T. ExtFr The broadened pulse S ExtFr Additionally, the period stretching module uses an internal standard clock CLK to control the leading-edge sub-period stretching time T. ExtFr Processing to generate a representative pulse width lower limit T FlLiFr The broadened pulse S FlLiFr And represents the upper limit of pulse width T UpLiFr The broadened pulse S UpLiFr Then, the broadened pulse S ExtFr S FlLiFr S UpLiFr Input to the time-amplitude conversion unit; In addition, the sub-period time stretching module will extend the trailing sub-period time T. SubRe Stretching the pulse by several standard clock cycles yields a pulse width of T. ExtRe The broadened pulse S ExtRe Additionally, the period stretching module uses its internal standard clock CLK to stretch the trailing edge sub-period time T. ExtRe Processing to generate a representative pulse width lower limit T FlLiRe The broadened pulse S FlLiRe And represents the upper limit of pulse width T UpLiRe The broadened pulse S UpLiRe Then, the broadened pulse S ExtRe S FlLiRe S UpLiRe Input to the time-amplitude conversion unit; In the error correction module, the FPGA calculates the error based on the inherent delay T. Delay Generate a standard delay chain to produce a correction pulse S Delay Additionally, the FPGA uses its internal standard clock CLK to control the inherent delay T. Delay Processing to generate a representative pulse width lower limit T FlLi The correction pulse S FlLi And represents the upper limit of pulse width T UpLi The correction pulse S UpLi Then the correction pulse S Delay S FlLi S UpLi Input to the time-amplitude conversion unit; The time-amplitude conversion unit includes a charge-discharge unit and an ADC. The single-cycle operation of the time-amplitude conversion unit is charging, sampling, and discharging. Specifically, the charge-discharge unit receives control signals from the FPGA and sequentially controls each pulse to linearly charge the capacitor in the charge-discharge unit. When the capacitor is fully charged, the ADC is controlled to sample the charging result and then the sampling result is fed back to the FPGA. After sampling, the capacitor in the charge-discharge unit is immediately controlled to fully discharge. After a single operation is completed, a set of digital voltage values ​​is sampled, in which the pulse S is stretched. ExtFr S FlLiFr S UpLiFr After sequential linear charging, the digital voltage N is sampled. ExtFr N FlLiFr and N UpLiFr ; Utilizing the pulse broadening S ExtRe S FlLiRe S UpLiRe After sequential linear charging, the digital voltage N is sampled. ExtRe N FlLiRe and N UpLiRe Using the correction pulse S Delay S FlLi S UpLi After sequential linear charging, the digital voltage N is sampled. Delay N FlLi and N UpLi ; Finally, the time-amplitude conversion unit packages the measured digital voltage and sends it to the data integration module. The data integration module sends the coarse count data and the voltage digital quantity packet to the host computer. The host computer controls the entire device's operation by sending control words to the FPGA's control unit and using control signals corresponding to the control unit's parameters. Simultaneously, the host computer calculates the final measurement time interval τ based on the coarse count data and the voltage digital packet. Where T0 is the delay difference between the standard delay chain and the frequency division signal delay chain.

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