Instruction generation method, apparatus and storage medium

Abstract

This application provides an instruction generation method, apparatus, and storage medium. It receives instruction parameters through a unified interface of a preset instruction category, whereby the instruction parameters include at least two operands and an output address. The method determines the representation of each operand based on the instruction parameters and generates a corresponding target instruction based on the operand representation and the instruction parameters. This application provides only a unified interface for receiving instruction parameters from the user for the preset instruction category. The compiler automatically selects and generates target hardware instructions adapted to the user-input instruction parameters. Users do not need to concern themselves with multiple hardware instructions, nor do they need to select or write corresponding API interface programs for each hardware instruction, thus providing convenience for users and avoiding the cumbersome process of writing corresponding APIs for each hardware instruction, and reducing the complexity of programs and documentation.

Description

Technical Field

[0001] This application relates to the fields of compilation technology and artificial intelligence technology, and in particular to an instruction generation method, apparatus and storage medium. Background Technology

[0002] In the design of processor hardware (such as graphics processing units (GPUs) or artificial intelligence processors), in order to improve the computational efficiency of the hardware processor and its versatility in multiple application scenarios, processor hardware often provides different hardware instructions for the same type of operation according to different computational requirements. For example, for addition-related operations, the hardware can provide multiple instructions such as element-wise add, broadcasting add, and addconstant, depending on different needs.

[0003] Users need to write corresponding programs for each hardware instruction during use, such as API (Application Programming Interface). This results in a large number of APIs, which makes it more troublesome for users to use, and the programming and documentation are also more complicated. Summary of the Invention

[0004] This application provides an instruction generation method, apparatus, and storage medium that provides a unified API interface for a certain type of operation. By parsing the parameters of the API interface, the specific type of hardware instruction is automatically selected, thereby simplifying programming and making it convenient for users.

[0005] In a first aspect, embodiments of this application provide an instruction generation method, including:

[0006] Instruction parameters are received through a unified interface of a preset instruction category; wherein the instruction parameters include at least two operands and an output address;

[0007] The representation of each operand is determined according to the instruction parameters;

[0008] Based on the representation of each operand and the instruction parameters, a corresponding target instruction is generated.

[0009] In one possible design, generating the corresponding target instruction based on the representation of each operand and the instruction parameters includes:

[0010] The target category is determined from the preset instruction categories based on the representation of each operand;

[0011] Based on the instruction parameters and the target category, a corresponding target instruction is generated.

[0012] In one possible design, determining the target category from the preset instruction categories based on the representation of each operand includes:

[0013] Determine whether each operand is represented as a memory address;

[0014] If each operand is represented as a memory address, then the data shape of each operand is determined based on the memory address.

[0015] The target category is determined based on the data shape of each operand.

[0016] In one possible design, determining the target category based on the data shape of each operand includes:

[0017] If the data shape relationship between the operands satisfies a preset rule, then the target category is determined to be the category corresponding to the preset rule; or

[0018] If the data shape relationship between the operands does not meet the preset rules, an error message will be output.

[0019] In one possible design, the target category includes a first category, the preset rule includes a first preset rule, and the step of determining the target category as the category corresponding to the preset rule if the data shape relationship between the operands satisfies the preset rule includes:

[0020] If the data shape relationship between the operands satisfies the first preset rule, then the target category is determined to be the first category.

[0021] In one possible design, the target category includes a second category, the preset rule further includes a second preset rule, and the step of determining the target category as the category corresponding to the preset rule if the data shape relationship between the operands satisfies the preset rule further includes:

[0022] If the data shape relationship between the operands satisfies the second preset rule, then the target category is determined to be the second category.

[0023] In one possible design, the data shape includes at least one dimension; the method further includes:

[0024] Compare the dimension values ​​of each corresponding dimension in the data shape of each operand;

[0025] If at least one dimension of the data shape of the operand has the same dimension value, then the data shape relationship of the operand is determined to satisfy the first preset rule;

[0026] If at least one dimension of the data shape of the operand has the same value, and the other dimension values ​​are compatible, then the data shape of the operand is determined to satisfy the second preset rule.

[0027] In one possible design, the method further includes:

[0028] If the dimension value of any corresponding dimension in the data shape of each operand is a constant, then the data shape relationship between each operand is determined by comparing the constants of the corresponding dimensions.

[0029] If the dimension value of any corresponding dimension in the data shape of each operand is an expression, then the data shape relationship between each operand is determined by comparing the expressions of the corresponding dimensions.

[0030] In one possible design, if the dimension value of any corresponding dimension in the data shape of each operand is an expression, the method further includes:

[0031] Each expression is transformed according to a preset transformation rule to obtain the corresponding transformed expression, and the transformed expressions have the same form of expression.

[0032] The data shape relationship between each operand is determined by comparing the transformed expressions.

[0033] In one possible design, the preset transformation rules include one or more combinations of the following rules:

[0034] For any expression, if parentheses are present in the expression, then remove the parentheses in the expression according to the rules of mathematical operations;

[0035] If there are constant operations in the expression, calculate the result of the constant operations and replace it in the expression;

[0036] The order of parameters in an expression is adjusted based on mathematical operation rules so that the parameters are arranged in the target order.

[0037] In one possible design, determining the target category from the preset instruction categories based on the representation of each operand further includes:

[0038] If the representation of each operand includes a memory address and a constant, then the target category is determined to be the third category.

[0039] Secondly, embodiments of this application provide an instruction generation apparatus, comprising:

[0040] An interface module is used to receive instruction parameters through a unified interface of a preset instruction category; wherein the instruction parameters include at least two operands and an output address;

[0041] A determining module is used to determine the representation of each operand based on the instruction parameters;

[0042] The generation module is used to generate a corresponding target instruction based on the representation of each operand and the instruction parameters.

[0043] Thirdly, embodiments of this application provide an instruction generation apparatus, including: at least one processor and a memory;

[0044] The memory stores computer-executed instructions;

[0045] The at least one processor executes computer execution instructions stored in the memory, causing the at least one processor to perform the method as described in the first aspect.

[0046] Fourthly, embodiments of this application provide a computer-readable storage medium storing a computer program that, when executed by at least one processor, implements the method described in the first aspect.

[0047] The instruction generation method, apparatus, and storage medium provided in this application receive instruction parameters through a unified interface of a preset instruction category. The instruction parameters include at least two operands and an output address. The representation of each operand is determined based on the instruction parameters. A corresponding target instruction is generated based on the representation of each operand and the instruction parameters. This embodiment provides only a unified interface for receiving instruction parameters from the user for the preset instruction category. The compiler automatically selects and generates target hardware instructions adapted to the user-input instruction parameters. Users do not need to concern themselves with multiple hardware instructions, nor do they need to select or write corresponding API interface programs for each hardware instruction. This provides convenience for users and avoids the need to write corresponding APIs for each hardware instruction, thus avoiding cumbersome programs and documentation. Attached Figure Description

[0048] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0049] Figure 1 A schematic diagram of a scenario for an instruction generation method provided in an embodiment of this application;

[0050] Figure 2 A flowchart illustrating an instruction generation method provided in one embodiment of this application;

[0051] Figure 3A flowchart illustrating an instruction generation method provided in another embodiment of this application;

[0052] Figure 4 A flowchart illustrating an instruction generation method provided in another embodiment of this application;

[0053] Figure 5 A flowchart illustrating an instruction generation method provided in another embodiment of this application;

[0054] Figure 6 This is a schematic diagram of the structure of an instruction generation apparatus provided in one embodiment of this application;

[0055] Figure 7 A schematic diagram of the structure of an instruction generation apparatus provided in another embodiment of this application;

[0056] Figure 8 This is a structural diagram of a board according to an embodiment of this application;

[0057] Figure 9 This is a structural diagram illustrating a combined processing apparatus according to an embodiment of this application;

[0058] Figure 10 This is a schematic diagram showing the internal structure of a single-core computing device according to an embodiment of this application;

[0059] Figure 11 This is a schematic diagram showing the internal structure of a multi-core computing device according to an embodiment of this application;

[0060] Figure 12 This is a schematic diagram illustrating the internal structure of a processor core according to an embodiment of this application.

[0061] These accompanying drawings and textual descriptions are not intended to limit the scope of the present disclosure in any way, but rather to illustrate the concepts of the disclosure to those skilled in the art by reference to specific embodiments. Detailed Implementation

[0062] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this disclosure as detailed in the appended claims.

[0063] To clearly understand the technical solution of this application, the solutions of the prior art will be described in detail first.

[0064] In the design of processor hardware (such as graphics processing units (GPUs) or artificial intelligence processors), in order to improve the computational efficiency of the hardware processor and its versatility in multiple application scenarios, processor hardware often provides different hardware instructions for the same type of operation according to different computational requirements. For example, for addition-related operations, the hardware can provide multiple hardware addition instructions such as element-wise add, broadcasting add, and addconstant, depending on different needs.

[0065] Users need to write corresponding programs, such as APIs (Application Programming Interfaces), for each hardware instruction to call the corresponding hardware instructions. However, providing a corresponding API interface for each hardware instruction results in a large number of APIs, which not only leads to complex and cumbersome programs and documentation, but also makes it inconvenient for users.

[0066] To address the aforementioned technical problems, this application provides an instruction generation method. The method receives instruction parameters through a unified interface for a preset instruction category. These parameters include at least two operands and an output address. The representation of each operand is determined based on the instruction parameters. A corresponding target instruction is generated based on the representation of each operand and the instruction parameters. This application provides a unified interface for receiving instruction parameters from the user for the same instruction category. The compiler automatically selects and generates target hardware instructions adapted to the user-input parameters. Users do not need to concern themselves with multiple hardware instructions or select or write corresponding API interface programs for each hardware instruction, thus providing convenience and avoiding the need to write corresponding APIs for each hardware instruction, reducing the complexity of programs and documentation. The instruction generation method and compiler disclosed herein improve efficiency by increasing the level of programming abstraction.

[0067] This application provides an instruction generation method applicable to, for example, Figure 1 The application scenario shown includes a compiler (or other electronic devices with compilation capabilities). The compiler provides a unified interface for preset instruction categories. Users can configure instruction parameters through this unified interface. The compiler can receive program code containing this unified interface and determine the representation of each operand based on the instruction parameters in the unified interface. Based on the representation of each operand and the instruction parameters, it generates the corresponding target instruction. This target instruction can be a hardware instruction that the hardware processor can execute. Optionally, the compiler can generate target instructions corresponding to the hardware instructions of the hardware processor, based on the type of hardware processor.

[0068] The technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will now be described with reference to the accompanying drawings.

[0069] Figure 2 This is a flowchart illustrating an embodiment of an instruction generation method provided in this application. The execution entity in this embodiment is a compiler or other electronic device with compilation capabilities. Figure 2 As shown, the instruction generation method provided in this embodiment includes the following steps:

[0070] S201. Receive instruction parameters through a unified interface of a preset instruction category; wherein the instruction parameters include at least two operands and an output address.

[0071] In this embodiment, for certain specific instruction categories, the hardware processor will provide different operation instructions according to different needs. The instruction category is determined according to the operation performed by the operation instruction. For example, different operation instructions used to perform addition operations belong to the same instruction category, and different instructions used to perform multiplication operations belong to the same instruction category. This will not be elaborated on here.

[0072] Operation instructions within a specific instruction category include, but are not limited to, element-wise (operations on corresponding elements of vectors or matrices of the same dimension), broadcasting (operations between vectors or matrices of different dimensions), and operations between vectors or matrices and constants. For example, addition-related operations may include multiple different instructions such as element-wise add, broadcasting add, and add constant. To avoid requiring users to write corresponding programs (APIs) for each operation instruction within the same instruction category, resulting in numerous APIs, user inconvenience, and cumbersome documentation, this embodiment provides a unified interface for different operation instructions within the same category. For any operation instruction within this category, users can input instruction parameters through this unified interface. Instruction parameters indicate the data to be operated on by the instruction and may include at least two operands and an output address. The at least two operands indicate the input data involved in the operation, and the output address indicates the storage location of the output data of the operation instruction.

[0073] For example, for the instruction category of addition operation, a unified interface Add(out, inp1, inp2) can be pre-encapsulated, where out is the output address, and inp1 and inp2 are the operands. When a user needs to use any operation instruction in the addition operation instruction category, they only need to input the operands and output address through the unified interface, without needing to know the specific operation instruction in the addition operation instruction category. This example only uses binary addition operation; in other embodiments, the operands may not be limited to two.

[0074] S202. Determine the representation of each operand according to the instruction parameters.

[0075] In this embodiment, the operands in the instruction parameters can have different representations. For example, an operand can be a vector or a matrix, and the vector or matrix can be represented as a memory address. An operand can also be a constant, in which case it can be represented as an immediate value, i.e., the input data itself. The compiler can identify whether each operand is a memory address and / or a constant based on the instruction parameters, thereby determining the representation of each operand.

[0076] S203. Generate the corresponding target instruction according to the representation of each operand and the instruction parameters.

[0077] In this embodiment, after determining the representation of each operand, the compiler can analyze the representation of each operand through optimization pass, and generate a target instruction that is adapted to the representation of the operand and the instruction parameters based on the representation of each operand and the instruction parameters, such as element-wise add(out,inp1,inp2).

[0078] The instruction generation method provided in this embodiment receives instruction parameters through a unified interface of a preset instruction category. These instruction parameters include at least two operands and an output address. The representation of each operand is determined based on the instruction parameters. Then, based on the representation of each operand and the instruction parameters, a corresponding target instruction is generated. This embodiment provides only a unified interface for receiving instruction parameters from the user for the preset instruction category. The compiler automatically selects and generates target instructions adapted to the user-input parameters. Users do not need to concern themselves with multiple hardware instructions, nor do they need to select or write corresponding API interface programs for each hardware instruction. This provides convenience for users and avoids the need to write corresponding APIs for each hardware instruction, thus avoiding cumbersome programs and documentation.

[0079] Based on any of the above embodiments, the compiler can directly generate target instructions that the hardware processor can execute, according to the representation of operands and instruction parameters in the unified interface. Alternatively, the compiler can first automatically select the corresponding target instruction based on the representation of operands and instruction parameters in the unified interface, and then generate the target instruction corresponding to that selected target instruction.

[0080] like Figure 3 As shown, generating the corresponding target instruction based on the representation of each operand and the instruction parameters may specifically include:

[0081] S301. Determine the target category from the preset instruction categories according to the representation of each operand;

[0082] S302. Generate the corresponding target instruction based on the instruction parameters and the target category.

[0083] In this embodiment, after determining the representation of each operand, the compiler can analyze the representation of each operand through optimization passes. Since the representation of operands for different operations in the preset instruction categories meets different rules, the target category of the operation instruction can be determined from the preset instruction categories based on the representation of each operand. For example, from the instruction category of addition operations, it can be determined which specific category the target instruction belongs to, such as element-wise add, broadcasting add, or addconstant. Furthermore, based on the instruction parameters and the target category, the corresponding target instruction is generated. For example, assuming the unified interface Add(out, inp1, inp2), where the instruction parameters include the output address out and operands inp1 and inp2, the target category can be determined to be the element-wise category based on the representation of the instruction parameters. Furthermore, based on the instruction parameters and the target category, the corresponding target instruction element-wise add(out, inp1, inp2) is generated.

[0084] Based on the above embodiments, such as Figure 4 As shown, determining the target category from the preset instruction categories based on the representation of each operand may specifically include:

[0085] S401. Determine whether the representation of each operand is a memory address;

[0086] S402. If each of the operands is represented as a memory cell address, then the data shape of each operand is determined based on the memory cell address.

[0087] S403. Determine the target category based on the data shape of each operand.

[0088] In this embodiment, operation instructions of the element-wise and broadcasting categories involve operations between vectors or matrices. In this case, the operation instructions can represent the vectors or matrices involved in the operation using the storage addresses of tensor data such as vectors or matrices. That is, the operands are all represented as storage unit addresses. Therefore, it can be determined whether each operand's representation is a storage unit address based on its representation. If each operand's representation is a storage unit address, it indicates that the target category may be one of the element-wise or broadcasting categories of operation instructions.

[0089] Since operation instructions of the element-wise, broadcasting, and other categories have different requirements for the data shape of operands, the data shape of each operand can be determined based on the memory unit address (that is, the size of the vector or matrix can be determined by the storage address of tensors such as vectors or matrices), and the target category can be determined in the end.

[0090] Specifically, if the data shape relationship between each operand meets the preset rule, then the target category is determined to be the category corresponding to the preset rule; if the data shape relationship between each operand does not meet the preset rule, it indicates that each operand does not meet the requirements of any category of operation instruction, and an error message can be output to prompt the user that there may be an error in the operand, so that the user can check and re-enter.

[0091] In one optional embodiment, the target category includes a first category, and the preset rule includes a first preset rule, which is the data shape relationship rule between the operands of the first category operation instruction. Therefore, if the data shape relationship between each operand satisfies the first preset rule, the target category is determined to be the first category.

[0092] In another optional embodiment, the target category further includes a second category, and the preset rules further include a second preset rule, which is the data shape relationship rule between the operands of the second category operation instructions. Therefore, if the data shape relationship between each operand satisfies the second preset rule, the target category is determined to be the second category.

[0093] By pre-setting preset rules corresponding to different categories and determining which preset rule corresponds to the data shape relationship between each operand, the target category can be accurately determined. Of course, the target category is not limited to the first category and the second category, and the preset rules are not limited to the first preset rule and the second preset rule.

[0094] For tensor data such as vectors or matrices that have at least one dimension, it is assumed that the data shape of each operand includes at least one dimension, wherein the at least one dimension can be arranged in ascending order, and the dimension value in each dimension direction can be used to represent the data size in that dimension direction.

[0095] In the above embodiments, the first preset rule can be that the data shapes of all operands are completely identical. If the corresponding dimension values ​​in at least one dimension of the data shape of each operand are the same, then it can be determined that the data shapes of all operands are identical, satisfying the first preset rule. For example, operands inp1 and inp2 are two-dimensional matrices, each including two dimensions: a first dimension and a second dimension. If the dimension values ​​of the first dimension of inp1 and the first dimension of inp2 are the same, and the dimension values ​​of the second dimension of inp1 and the second dimension of inp2 are the same, then it is determined that the data shape relationship of the operands satisfies the first preset rule. Optionally, the above first category can be an element-wise category. Therefore, if the data shapes of all operands are completely identical, that is, the corresponding dimension values ​​of the data shapes of each operand are the same, then the first preset rule is satisfied, and the target category is determined to be the first category (element-wise category).

[0096] In the above embodiments, the second preset rule can be that the operands have different data shapes. This difference in data shape can be that the operands have different numbers of dimensions, or that they have the same number of dimensions but different dimensional values ​​in at least one dimension. In this case, if at least one dimension of the operands' data shapes has the same value, and the other dimension values ​​have a compatibility relationship, then the data shape relationship of the operands is determined to satisfy the second preset rule. This compatibility relationship can be expressed as a high-dimensional data encompassing low-dimensional data, or as a multiple relationship between dimension values ​​of the same dimension.

[0097] For example, operands inp3 and inp4 both include two dimensions: a first dimension and a second dimension. The data shape of inp3 is 4*3, and the data shape of inp4 is 4*1. Therefore, the second dimension of inp3 and the second dimension of inp4 have the same dimension value, which is 4. The first dimension of inp3 is a multiple of the dimension value of the first dimension of inp4. Thus, the data shape relationship of the operands is determined to satisfy the second preset rule.

[0098] For example, the low-dimensional operand inp3 includes two dimensions: the first dimension and the second dimension, and the data shape of inp3 is 4*1; the high-dimensional operand inp4 includes three dimensions: the first dimension, the second dimension, and the third dimension, and the data shape of inp4 is 5*4*1. Then the first dimension of inp3 and the first dimension of inp4 have the same dimension value, which is 1. The second dimension of inp3 and the second dimension of inp4 have the same dimension value, which is 4. Therefore, the high-dimensional operand inp4 can be compatible with the low-dimensional operand inp3. In this case, the data shape relationship of the operands is determined to satisfy the second preset rule.

[0099] For example, operand inp3 includes two dimensions: a first dimension and a second dimension, and the data shape of inp3 is 4*1; operand inp4 includes three dimensions: a first dimension, a second dimension, and a third dimension, and the data shape of inp4 is 5*4*3. Then, the dimension value of the first dimension of inp4 is a multiple of the dimension value of the first dimension of inp3. The dimension values ​​of the second dimensions of inp3 and inp4 are the same, both being 4. Therefore, the data shape relationship of the operands is determined to satisfy the second preset rule.

[0100] Optionally, the second category can be the broadcasting category. Therefore, if the data shape of each operand has the same value in at least one dimension, and the values ​​of the remaining dimensions are compatible with each other, such as by multiples, then the second preset rule is satisfied, and the target category is determined to be the second category (broadcasting category).

[0101] In the above embodiments, when comparing the data shape relationships of each operand, considering that the dimension value may be a constant or dynamically represented by an expression, this embodiment can be processed separately through the following process:

[0102] If the dimension value of any corresponding dimension in the data shape of each operand is a constant, the data shape relationship between each operand is determined by comparing the constants of the corresponding dimensions; that is, the corresponding dimension values ​​are determined directly by comparing the constants to determine whether they are the same or whether the corresponding dimension values ​​have a compatibility relationship.

[0103] If the dimension value of any corresponding dimension in the data shape of each operand is an expression, then the data shape relationship between each operand is determined by comparing the expressions of the corresponding dimensions. That is, since the specific values ​​of each parameter in the expression can only be obtained at runtime and cannot be determined at this time, it is not possible to calculate the results of each expression first and then compare the results of each expression. Therefore, it is possible to determine whether the corresponding dimension values ​​are the same or whether the corresponding dimension values ​​have a compatibility relationship by comparing the expressions.

[0104] Furthermore, if the dimension value of any corresponding dimension in the data shape of each operand is an expression, the method further includes:

[0105] Each expression is transformed according to a preset transformation rule to obtain a corresponding transformed expression, and the transformed expressions have the same form of expression; the data shape relationship between each operand is determined by comparing the transformed expressions.

[0106] In this embodiment, since there may be cases where expressions with the same dimension value but different operands appear to have different forms but actually produce the same result, for example, the expressions x*m+y*c–a+b*m and c*y+m*x–a+m*b appear to have different forms but are actually the same after transformation, and the result is also the same, in order to facilitate the compiler's comparison of expressions, each expression can be transformed according to the same transformation rules so that each expression follows the same expression method, thereby making it easier to compare. The compiler only needs to compare the transformed expressions in a way similar to string comparison.

[0107] Optionally, the preset transformation rules include one or more combinations of the following rules:

[0108] For any expression, if there are parentheses in the expression, the parentheses in the expression are removed according to the mathematical operation rules; where, optionally, the data operation rules can be associative laws, etc., for example, the expression (a*b)*c can be transformed into a*b*c according to the associative law of multiplication.

[0109] If there are constant operations in the expression, calculate the result of the constant operations and replace it in the expression; for example, if the expression is 4*a*3*b, which contains constant operations, we can first calculate the result of the constant operations, which is 4*3, and then convert the expression to 12*a*b.

[0110] The order of parameters in an expression is adjusted based on mathematical operation rules so that the parameters are arranged in a target order. Optionally, the mathematical operation rules can be commutative laws, etc., and the target order can be alphabetical order. For example, the expression x*a*c can be converted to a*c*x after adjusting the parameter order according to the commutative law, thus facilitating comparison between expressions.

[0111] Based on any of the above embodiments, when determining the target category from the preset instruction categories according to the representation of each operand, the method may further include:

[0112] If the representation of each operand includes a memory address and a constant, then the target category is determined to be the third category.

[0113] In this embodiment, after determining the representation of each operand, it is determined that the representation of each operand includes a memory cell address and a constant, that is, the operation between the data stored in the memory cell and the constant. The target category can be determined as the third category, such as the constant operation type. Taking the instruction category of addition operation as an example, the third category is addconstant, that is, the addition operation between the data stored in the memory cell and the constant.

[0114] Based on the above embodiments, such as Figure 5 As shown, this embodiment provides an instruction generation method, including the following steps:

[0115] S501, Receive instruction parameters through a unified interface of preset instruction categories;

[0116] The instruction parameters include at least two operands and the output address;

[0117] S502. Determine the representation of each operand based on the instruction parameters;

[0118] S503. Determine whether each operand is represented as a memory address;

[0119] If all operands are represented as memory addresses, then execute S504; otherwise, execute S508.

[0120] S504. If each operand is represented as a memory address, then the data shape of each operand is determined based on the memory address.

[0121] S505, S506 or S507 are executed depending on the different data shape relationships of each operand;

[0122] S505. If the data shape relationship between each operand satisfies the first preset rule, then the target category is determined to be the first category;

[0123] S506. If the data shape relationship between each operand satisfies the second preset rule, then the target category is determined to be the second category;

[0124] S507. If the data shape relationship between the operands does not meet the preset rules, an error message will be output.

[0125] S508. If the representation of each operand includes a memory address and a constant, then the target category is determined to be the third category.

[0126] S509. Generate the corresponding target instruction based on the instruction parameters and target category;

[0127] After the target category is determined in S505, S506 or S508, S509 can be executed.

[0128] Figure 6 This is a schematic diagram of the structure of an instruction generation apparatus provided in one embodiment of this application, as shown below. Figure 6 As shown, the instruction generation device provided in this embodiment can be a compiler or other electronic devices with compilation functions. The instruction generation device 60 provided in this embodiment includes: an interface module 61, a determination module 62, and a generation module 63.

[0129] The interface module 61 is used to receive instruction parameters through a unified interface of a preset instruction category; wherein the instruction parameters include at least two operands and an output address.

[0130] The determining module 62 is used to determine the representation of each operand based on the instruction parameters;

[0131] The generation module 63 is used to generate a corresponding target instruction based on the representation of each operand and the instruction parameters.

[0132] In one or more embodiments of this application, when the generation module 63 generates a corresponding target instruction based on the representation of each operand and the instruction parameters, it is used to:

[0133] The target category is determined from the preset instruction categories based on the representation of each operand;

[0134] Based on the instruction parameters and the target category, a corresponding target instruction is generated.

[0135] In one or more embodiments of this application, when the generation module 63 determines the target category from the preset instruction categories according to the representation of each operand, it is configured to:

[0136] Determine whether each operand is represented as a memory address;

[0137] If each operand is represented as a memory address, then the data shape of each operand is determined based on the memory address.

[0138] The target category is determined based on the data shape of each operand.

[0139] In one or more embodiments of this application, the generation module 63, when determining the target category based on the data shape of each operand, is configured to:

[0140] If the data shape relationship between the operands satisfies a preset rule, then the target category is determined to be the category corresponding to the preset rule; or

[0141] If the data shape relationship between the operands does not meet the preset rules, an error message will be output.

[0142] In one or more embodiments of this application, the target category includes a first category, and the preset rule includes a first preset rule. If the data shape relationship between each operand satisfies the preset rule, then when the generation module 63 determines that the target category is the category corresponding to the preset rule, it is used to:

[0143] If the data shape relationship between the operands satisfies the first preset rule, then the target category is determined to be the first category.

[0144] In one or more embodiments of this application, the target category includes a second category, and the preset rule further includes a second preset rule. If the data shape relationship between each operand satisfies the preset rule, then when the generation module 63 determines that the target category is the category corresponding to the preset rule, it is further configured to:

[0145] If the data shape relationship between the operands satisfies the second preset rule, then the target category is determined to be the second category.

[0146] In one or more embodiments of this application, the data shape includes at least one dimension; the generation module 63 is further configured to:

[0147] Compare the dimension values ​​of each corresponding dimension in the data shape of each operand;

[0148] If at least one dimension of the data shape of the operand has the same dimension value, then the data shape relationship of the operand is determined to satisfy the first preset rule;

[0149] If at least one dimension of the data shape of the operand has the same value, and the other dimension values ​​are compatible, then the data shape of the operand is determined to satisfy the second preset rule.

[0150] In one or more embodiments of this application, the generation module 63 is further configured to:

[0151] If the dimension value of any corresponding dimension in the data shape of each operand is a constant, then the data shape relationship between each operand is determined by comparing the constants of the corresponding dimensions.

[0152] If the dimension value of any corresponding dimension in the data shape of each operand is an expression, then the data shape relationship between each operand is determined by comparing the expressions of the corresponding dimensions.

[0153] In one or more embodiments of this application, if the dimension value of any corresponding dimension in the data shape of each operand is an expression, the generation module 63 is further configured to:

[0154] Each expression is transformed according to a preset transformation rule to obtain the corresponding transformed expression, and the transformed expressions have the same form of expression.

[0155] The data shape relationship between each operand is determined by comparing the transformed expressions.

[0156] In one or more embodiments of this application, the preset transformation rule includes a combination of one or more of the following rules:

[0157] For any expression, if parentheses are present in the expression, then remove the parentheses in the expression according to the rules of mathematical operations;

[0158] If there are constant operations in the expression, calculate the result of the constant operations and replace it in the expression;

[0159] The order of parameters in an expression is adjusted based on mathematical operation rules so that the parameters are arranged in the target order.

[0160] In one or more embodiments of this application, when the generation module 63 determines the target category from the preset instruction categories according to the representation of each operand, it is further configured to:

[0161] If the representation of each operand includes a memory address and a constant, then the target category is determined to be the third category.

[0162] The instruction generation device provided in this embodiment can execute... Figure 2-5 The technical solutions of the method embodiments shown are similar in principle and in effect, and will not be described again here.

[0163] Figure 7 This is a schematic diagram of the structure of an instruction generation apparatus provided in another embodiment of this application, as shown below. Figure 7 As shown, the instruction generation apparatus 70 provided in this application embodiment includes: at least one processor 71 and a memory 72;

[0164] Memory 72 stores instructions executed by the computer;

[0165] At least one processor 71 executes computer execution instructions stored in memory 72, causing at least one processor to execute... Figure 2-5 The instruction generation method provided in any embodiment.

[0166] In one possible implementation, a computer-readable storage medium is also disclosed, in which a computer program is stored, which, when executed by at least one processor, implements... Figure 2 and Figure 3 The instruction generation method provided in any embodiment.

[0167] In one possible implementation, a board is also disclosed, which can be a device-side board. Figure 8 This diagram illustrates the structure of a board 60 according to an embodiment of this application. Figure 8 As shown, board 60 includes chip 601, which is a system-on-chip (SoC) integrating one or more combined processing units. These combined processing units are artificial intelligence computing units used to support various deep learning and machine learning algorithms, meeting the intelligent processing needs of complex scenarios in fields such as computer vision, speech, natural language processing, and data mining. In particular, deep learning technology is widely used in cloud intelligence. A significant characteristic of cloud intelligence applications is the large volume of input data, placing high demands on the platform's storage and computing capabilities. Board 60 in this embodiment is suitable for cloud intelligence applications, possessing massive off-chip storage, on-chip storage, and powerful computing capabilities.

[0168] Chip 601 is connected to external device 603 via external interface device 602. External device 603 may be, for example, a server, computer, camera, monitor, mouse, keyboard, network card, or Wi-Fi interface. Data to be processed can be transmitted from external device 603 to chip 601 via external interface device 602. The calculation results from chip 601 can be transmitted back to external device 603 via external interface device 602. Depending on the application scenario, external interface device 602 may have different interface forms, such as a PCIe interface.

[0169] The board 60 also includes a storage device 604 for storing data, which includes one or more memory cells 605. The storage device 604 is connected to and transmits data with the controller 606 and the chip 601 via a bus. The controller 606 in the board 60 is configured to regulate the state of the chip 601. Therefore, in one application scenario, the controller 606 may include a microcontroller (MCU).

[0170] In one possible implementation, a combined processing device is also provided. Figure 9 This is a structural diagram illustrating the combined processing device in chip 601 of this embodiment. (As shown...) Figure 9As shown, the combined processing device 70 includes a computing device 701, an interface device 702, a processing device 703, and a storage device 704.

[0171] The computing device 701 is configured to perform user-specified operations. It is mainly implemented as a single-core intelligent processor or a multi-core intelligent processor to perform deep learning or machine learning calculations. It can interact with the processing device 703 through the interface device 702 to jointly complete the user-specified operations.

[0172] Interface device 702 is used to transmit data and control commands between computing device 701 and processing device 703. For example, computing device 701 can obtain input data from processing device 703 via interface device 702 and write it to on-chip storage device of computing device 701. Further, computing device 701 can obtain control commands from processing device 703 via interface device 702 and write them to on-chip control cache of computing device 701. Alternatively or optionally, interface device 702 can also read data from storage device of computing device 701 and transmit it to processing device 703.

[0173] The processing device 703, as a general-purpose processing device, performs basic controls including but not limited to data transfer and starting / stopping the computing device 701. Depending on the implementation, the processing device 703 can be one or more types of processors, such as a central processing unit (CPU), a graphics processing unit (GPU), or other general-purpose and / or special-purpose processors. These processors include, but are not limited to, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc., and their number can be determined according to actual needs. As mentioned above, the computing device 701 of this application can be considered as having a single-core structure or a homogeneous multi-core structure. However, when the computing device 701 and the processing device 703 are considered together, they are regarded as forming a heterogeneous multi-core structure.

[0174] The storage device 704 is used to store the data to be processed. It may be DRAM 704, which is DDR memory, typically 16G or larger in size, and is used to store the data of the computing device 701 and / or the processing device 703.

[0175] Figure 10The diagram shows the internal structure of a single-core computing device 701. The single-core computing device 801 is used to process input data from computer vision, speech, natural language processing, data mining, etc. The single-core computing device 801 includes three main modules: a control module 81, a processing module 82, and a storage module 83.

[0176] The control module 81 coordinates and controls the operation of the computation module 82 and the storage module 83 to complete the deep learning task. It includes an instruction fetch unit (IFU) 811 and an instruction decode unit (IDU) 812. The instruction fetch unit 811 fetches instructions from the processing device 1203, and the instruction decode unit 812 decodes the fetched instructions and sends the decoding result as control information to the computation module 82 and the storage module 83.

[0177] The computation module 82 includes a vector operation unit 821 and a matrix operation unit 822. The vector operation unit 821 is used to perform vector operations and can support complex operations such as vector multiplication, addition, and nonlinear transformations; the matrix operation unit 822 is responsible for the core computations of deep learning algorithms, namely matrix multiplication and convolution.

[0178] Storage module 83 is used to store or move relevant data, including neuron RAM (NRAM) 831, weight RAM (WRAM) 832, and direct memory access (DMA) module 833. NRAM 831 is used to store input neurons, output neurons, and intermediate results after computation; WRAM 832 is used to store the convolution kernels of the deep learning network, i.e., the weights; DMA 833 is connected to DRAM 704 through bus 84 and is responsible for data transfer between the single-core computing device 801 and DRAM 704.

[0179] Figure 11 A schematic diagram of the internal structure of the computing device 701 as a multi-core is shown. The multi-core computing device 901 adopts a hierarchical structure design. As a system-on-a-chip, the multi-core computing device 901 includes at least one cluster, and each cluster includes multiple processor cores. In other words, the multi-core computing device 901 is constructed in a hierarchical structure of system-on-a-chip, cluster, and processor core.

[0180] From the perspective of system-on-a-chip hierarchy, such as Figure 11 As shown, the multi-core computing device 901 includes an external storage controller 901, a peripheral communication module 902, an on-chip interconnect module 903, a synchronization module 904, and multiple clusters 905.

[0181] There can be multiple external storage controllers 901; two are shown as an example in the figure. These controllers are used to respond to access requests from the processor core to access external storage devices, such as… Figure 9 The DRAM 704 in the chip allows data to be read from or written to external memory. The peripheral communication module 902 receives control signals from the processing unit 703 via the interface device 702, initiating the computing unit 701 to execute tasks. The on-chip interconnect module 903 connects the external memory controller 901, the peripheral communication module 902, and multiple clusters 905 to transmit data and control signals between modules. The synchronization module 904 is a global barrier controller (GBC) used to coordinate the working progress of each cluster and ensure information synchronization. The multiple clusters 905 are the computing cores of the multi-core computing device 901; four are exemplarily shown in the figure, forming a structure like... Figure 1 The four quadrants are shown. With hardware advancements, the multi-core computing device 901 of this application can also include clusters 905 with 8, 16, 64, or even more cores. Clusters 905 are used to efficiently execute deep learning algorithms.

[0182] From the perspective of cluster hierarchy, such as Figure 11 As shown, each cluster 905 includes multiple processor cores (IPU cores) 906 and one memory core (MEM core) 907. For example, each cluster 905 includes four processor cores and one memory, which can be DRAM 704. Each processor core is equivalent to... Figure 1 One of the processing units, each memory is equivalent to Figure 1 One of the storage units.

[0183] Four processor cores 906 are shown in the figure as an example; this application does not limit the number of processor cores 906. Its internal architecture is as follows: Figure 12 As shown. Each processor core 906 is similar to Figure 10The single-core computing device 801 also includes three main modules: a control module 1001, an arithmetic module 1002, and a storage module 1003. The functions and structures of the control module 1001, arithmetic module 1002, and storage module 1003 are largely the same as those of the control module 81, arithmetic module 82, and storage module 83. The control module 1001 includes an instruction fetch unit 10011 and an instruction decode unit 10012. The arithmetic module 1002 includes a vector operation unit 10021 and a matrix operation unit 10022. Further details are omitted. It should be noted that the storage module 1003 includes an input / output direct memory access (IODMA) module 10033 and a move direct memory access (MVDMA) module 10034. IODMA10033 controls memory access of NRAM 10031 / WRAM10032 and DRAM 704 via broadcast bus 909; MVDMA 10034 is used to control memory access of NRAM 10031 / WRAM 10032 and SRAM 908.

[0184] Back Figure 9 The storage core 907 is primarily used for storage and communication, namely storing shared data or intermediate results among processor cores 906, and performing communication between cluster 905 and DRAM 704, communication between clusters 905, and communication between processor cores 906. In other embodiments, the storage core 907 has scalar operation capabilities and is used to perform scalar operations.

[0185] The storage core 907 includes an SRAM 908, a broadcast bus 909, a cluster direct memory access (CDMA) module 910, and a global direct memory access (GDMA) module 911. The SRAM 908 acts as a high-performance data relay station. Data multiplexed between different processor cores 906 within the same cluster 905 does not need to be obtained from the DRAM 704 by each processor core 906. Instead, it is relayed between processor cores 906 via the SRAM 908. The storage core 907 only needs to quickly distribute the multiplexed data from the SRAM 908 to multiple processor cores 906 to improve inter-core communication efficiency and greatly reduce on-chip and off-chip I / O access.

[0186] Broadcast bus 909, CDMA 910, and GDMA 911 are used to perform communication between processor cores 906, communication between clusters 905, and data transfer between cluster 905 and DRAM 704, respectively. These will be explained separately below.

[0187] The broadcast bus 909 is used to complete high-speed communication between the processor cores 906 within the cluster 905. In this embodiment, the broadcast bus 909 supports inter-core communication methods including unicast, multicast, and broadcast. Unicast refers to point-to-point (e.g., data transmission from one processor core to another) data transmission. Multicast is a communication method that transmits data from SRAM 908 to several specific processor cores 906. Broadcast is a communication method that transmits data from SRAM 908 to all processor cores 906, and is a special case of multicast.

[0188] CDMA 910 is used to control SRAM 908 access between different clusters 905 within the same computing device 701.

[0189] The GDMA 911 works in conjunction with the external memory controller 901 to control memory access from the SRAM 908 to the DRAM 704 in the cluster 905, or to read data from the DRAM 704 into the SRAM 908. As mentioned above, communication between the DRAM 704 and the NRAM 10031 or WRAM 10032 can be achieved through two channels. The first channel is a direct connection between the DRAM 704 and the NRAM 10031 or WRAM 10032 via the IODAM 10033; the second channel involves first transmitting data between the DRAM 704 and SRAM 908 via the GDMA 911, and then transmitting data between the SRAM 908 and the NRAM 10031 or WRAM 10032 via the MVDMA 10034. Although the second channel appears to require more components and has a longer data flow, in some embodiments, the bandwidth of the second channel is actually much greater than that of the first channel. Therefore, communication between DRAM 704 and NRAM 10031 or WRAM 10032 may be more efficient through the second channel. Embodiments of this application may select the data transmission channel based on their hardware capabilities.

[0190] In other embodiments, the functions of GDMA 911 and IODMA 10033 can be integrated into the same component. For ease of description, this application treats GDMA 911 and IODMA 10033 as different components. For those skilled in the art, as long as the functions implemented and the technical effects achieved are similar to those of this application, they fall within the protection scope of this application. Furthermore, the functions of GDMA 911, IODMA 10033, CDMA 910, and MVDMA 10034 can also be implemented by the same component.

[0191] The foregoing may be better understood in view of the following clauses:

[0192] Clause 1. A method for generating instructions, comprising:

[0193] Instruction parameters are received through a unified interface of a preset instruction category; wherein the instruction parameters include at least two operands and an output address;

[0194] The representation of each operand is determined according to the instruction parameters;

[0195] Based on the representation of each operand and the instruction parameters, a corresponding target instruction is generated.

[0196] Clause 2. The method described in Clause 1, wherein generating the corresponding target instruction based on the representation of each operand and the instruction parameters, includes:

[0197] The target category is determined from the preset instruction categories based on the representation of each operand;

[0198] Based on the instruction parameters and the target category, a corresponding target instruction is generated.

[0199] Clause 3. The method described in Clause 2, wherein determining the target category from the preset instruction categories based on the representation of each operand, includes:

[0200] Determine whether each operand is represented as a memory address;

[0201] If each operand is represented as a memory address, then the data shape of each operand is determined based on the memory address.

[0202] The target category is determined based on the data shape of each operand.

[0203] Clause 4. The method described in Clause 3, wherein determining the target category based on the data shape of each operand includes:

[0204] If the data shape relationship between the operands satisfies a preset rule, then the target category is determined to be the category corresponding to the preset rule; or

[0205] If the data shape relationship between the operands does not meet the preset rules, an error message will be output.

[0206] Clause 5. According to the method described in Clause 4, the target category includes a first category, the preset rule includes a first preset rule, and the step of determining the target category as the category corresponding to the preset rule if the data shape relationship between each of the operands satisfies the preset rule includes:

[0207] If the data shape relationship between the operands satisfies the first preset rule, then the target category is determined to be the first category.

[0208] Clause 6. According to the method described in Clause 4 or 5, the target category includes a second category, the preset rule further includes a second preset rule, and the step of determining the target category as the category corresponding to the preset rule if the data shape relationship between the operands satisfies the preset rule further includes:

[0209] If the data shape relationship between the operands satisfies the second preset rule, then the target category is determined to be the second category.

[0210] Clause 7. The data shape comprising at least one dimension as described in Clause 4 or 5; the method further comprising:

[0211] Compare the dimension values ​​of each corresponding dimension in the data shape of each operand;

[0212] If at least one dimension of the data shape of the operand has the same dimension value, then the data shape relationship of the operand is determined to satisfy the first preset rule;

[0213] If at least one dimension of the data shape of the operand has the same value, and the other dimension values ​​are compatible, then the data shape of the operand is determined to satisfy the second preset rule.

[0214] Clause 8. The method described in accordance with Clause 4 or 5 further includes:

[0215] If the dimension value of any corresponding dimension in the data shape of each operand is a constant, then the data shape relationship between each operand is determined by comparing the constants of the corresponding dimensions.

[0216] If the dimension value of any corresponding dimension in the data shape of each operand is an expression, then the data shape relationship between each operand is determined by comparing the expressions of the corresponding dimensions.

[0217] Clause 9. According to the method described in Clause 8, if the dimension value of any corresponding dimension in the data shape of each operand is an expression, the method further includes:

[0218] Each expression is transformed according to a preset transformation rule to obtain the corresponding transformed expression, and the transformed expressions have the same form of expression.

[0219] The data shape relationship between each operand is determined by comparing the transformed expressions.

[0220] Clause 10. The preset transformation rule, as described in Clause 9, includes one or more combinations of the following rules:

[0221] For any expression, if parentheses are present in the expression, then remove the parentheses in the expression according to the rules of mathematical operations;

[0222] If there are constant operations in the expression, calculate the result of the constant operations and replace it in the expression;

[0223] The order of parameters in an expression is adjusted based on mathematical operation rules so that the parameters are arranged in the target order.

[0224] Clause 11. The method according to Clause 2, wherein determining the target category from the preset instruction categories based on the representation of each of the operands further includes:

[0225] If the representation of each operand includes a memory address and a constant, then the target category is determined to be the third category.

[0226] Clause 12. An instruction generation apparatus, comprising:

[0227] An interface module is used to receive instruction parameters through a unified interface of a preset instruction category; wherein the instruction parameters include at least two operands and an output address;

[0228] A determining module is used to determine the representation of each operand based on the instruction parameters;

[0229] The generation module is used to generate a corresponding target instruction based on the representation of each operand and the instruction parameters.

[0230] Clause 13. An instruction generation apparatus, comprising: at least one processor and a memory;

[0231] The memory stores computer-executed instructions;

[0232] The at least one processor executes computer execution instructions stored in the memory, causing the at least one processor to perform the method as described in any one of clauses 1-11.

[0233] Clause 14. A computer-readable storage medium storing a computer program that, when executed by at least one processor, implements the method as described in any one of Clauses 1-11.

[0234] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, as some steps may be performed in other orders or simultaneously according to this application. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are all optional embodiments, and the actions and modules involved are not necessarily essential to this application.

[0235] It should be further noted that although the steps in the flowchart are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowchart may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the sub-steps or stages of other steps.

[0236] It should be understood that the above-described device embodiments are merely illustrative, and the device of this application can also be implemented in other ways. For example, the division of units / modules in the above embodiments is only a logical functional division, and there may be other division methods in actual implementation. For example, multiple units, modules, or components may be combined, or integrated into another system, or some features may be ignored or not executed.

[0237] Furthermore, unless otherwise specified, the functional units / modules in the various embodiments of this application can be integrated into one unit / module, or each unit / module can exist physically separately, or two or more units / modules can be integrated together. The integrated units / modules described above can be implemented in hardware or as software program modules.

[0238] When integrated units / modules are implemented in hardware, the hardware can be digital circuits, analog circuits, etc. The physical implementation of the hardware structure includes, but is not limited to, transistors, memristors, etc. Unless otherwise specified, an AI processor can be any suitable hardware processor, such as a CPU, GPU, FPGA, DSP, and ASIC, etc. Unless otherwise specified, storage units can be any suitable magnetic or magneto-optical storage medium, such as resistive random access memory (RRAM), dynamic random access memory (DRAM), static random access memory (SRAM), enhanced dynamic random access memory (EDRAM), high-bandwidth memory (HBM), hybrid memory cube (HMC), etc.

[0239] If the integrated unit / module is implemented as a software program module and sold or used as an independent product, it can be stored in a computer-readable storage device (CMD). Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a memory and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned memory includes various media capable of storing program code, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard drive, magnetic disk, or optical disk.

[0240] In the above embodiments, the descriptions of each embodiment have their own emphasis. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments. The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as the combination of these technical features does not contradict each other, it should be considered within the scope of this specification.

Claims

1. A method for generating instructions, characterized in that, include: Receive command parameters through a unified interface for preset command categories; The instruction parameters include at least two operands and an output address; The representation of each operand is determined according to the instruction parameters; If each operand is represented as a storage unit address, the data shape of each operand is determined based on the storage unit address, and the dimension value of each corresponding dimension in the data shape of each operand is compared to determine the target category in the preset instruction category; wherein, the data shape includes at least one dimension, and the dimension value of each dimension is a constant or an expression; Based on the instruction parameters and the target category, a corresponding target instruction is generated.

2. The method according to claim 1, characterized in that, Also includes: Determine whether each operand is represented as a memory address.

3. The method according to claim 2, characterized in that, The step of comparing the dimension values ​​of each corresponding dimension in the data shape of each operand to determine the target category in the preset instruction category includes: Based on the comparison results of the dimension values, it is determined whether the data shape relationship between each operand satisfies a preset rule; If the data shape relationship between the operands satisfies a preset rule, then the target category is determined to be the category corresponding to the preset rule; or If the condition is not met, an error message will be output.

4. The method according to claim 3, characterized in that, The target category includes a first category, the preset rule includes a first preset rule, and the step of determining the target category as the category corresponding to the preset rule if the data shape relationship between the operands satisfies the preset rule includes: If the data shape relationship between the operands satisfies the first preset rule, then the target category is determined to be the first category.

5. The method according to claim 3 or 4, characterized in that, The target category includes a second category, and the preset rule further includes a second preset rule. The step of determining the target category as the category corresponding to the preset rule if the data shape relationship between the operands satisfies the preset rule also includes: If the data shape relationship between the operands satisfies the second preset rule, then the target category is determined to be the second category.

6. The method according to claim 3 or 4, characterized in that, Based on the comparison results of the dimension values, it is determined whether the data shape relationship between the operands satisfies a preset rule, including: If at least one dimension of the data shape of the operand has the same dimension value, then the data shape relationship of the operand is determined to satisfy the first preset rule; If at least one dimension of the data shape of the operand has the same value, and the other dimension values ​​are compatible, then the data shape of the operand is determined to satisfy the second preset rule.

7. The method according to claim 3 or 4, characterized in that, The method further includes: If the dimension value of any corresponding dimension in the data shape of each operand is a constant, then the data shape relationship between each operand is determined by comparing the constants of the corresponding dimensions. If the dimension value of any corresponding dimension in the data shape of each operand is an expression, then the data shape relationship between each operand is determined by comparing the expressions of the corresponding dimensions.

8. The method according to claim 7, characterized in that, If the dimension value of any corresponding dimension in the data shape of each operand is an expression, the method further includes: Each expression is transformed according to a preset transformation rule to obtain the corresponding transformed expression, and the transformed expressions have the same form of expression. The data shape relationship between each operand is determined by comparing the transformed expressions.

9. The method according to claim 8, characterized in that, The preset transformation rules include one or more combinations of the following rules: For any expression, if parentheses are present in the expression, then remove the parentheses in the expression according to the rules of mathematical operations; If there are constant operations in the expression, calculate the result of the constant operations and replace it in the expression; The order of parameters in an expression is adjusted based on mathematical operation rules so that the parameters are arranged in the target order.

10. The method according to claim 1, characterized in that, Also includes: If the representation of each operand includes a memory address and a constant, then the target category is determined to be the third category.

11. An instruction generation apparatus, characterized in that, include: The interface module is used to receive instruction parameters through a unified interface of preset instruction categories; The instruction parameters include at least two operands and an output address; A determining module is used to determine the representation of each operand based on the instruction parameters; A generation module is configured to determine the data shape of each operand based on the storage unit address if the representation of each operand is a storage unit address, and compare the dimension value of each corresponding dimension in the data shape of each operand to determine the target category in the preset instruction category; wherein, the data shape includes at least one dimension, and the dimension value of each dimension is a constant or an expression; Based on the instruction parameters and the target category, a corresponding target instruction is generated.

12. An instruction generation apparatus, characterized in that, include: At least one processor and memory; The memory stores computer-executed instructions; The at least one processor executes computer execution instructions stored in the memory, causing the at least one processor to perform the method as described in any one of claims 1-10.

13. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by at least one processor, implements the method as described in any one of claims 1-10.

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