A digital integrated circuit line delay prediction method, device and storage medium

Abstract

The present invention discloses a method, device and storage medium for predicting line delay of digital integrated circuits. First, the circuit is physically designed using a physical design tool, and the parasitic parameter information of the layout after circuit wiring is extracted as the input feature of the prediction model. Then, the path topology information is extracted from the spef netlist, and sequence feature preprocessing is performed. The processed features are used as the input of a moment matching model to establish a connection between the netlist topology structure and the line delay. The output of the moment matching model and the output of the netlist topology information preprocessing are combined and used as the feature input of the XGboost model and the random forest model. Finally, the Bayesian optimization method is used to perform hyperparameter optimization to obtain a delay prediction model with strong robustness, and the delay prediction value is output. Compared with the traditional precise model method, the present invention can achieve a more accurate prediction effect under a lower simulation overhead, which is of great significance for the timing sign-off of digital integrated circuits.

Description

Technical Field

[0001] The present invention relates to a method, device and storage medium for predicting line delay of a digital integrated circuit, and belongs to the technical field of integrated circuit design automation. Background Art

[0002] With the continuous advancement of integrated circuit technology and the continuous increase in chip application scenarios, designers often need to consider various possible complex operating scenarios of the chip, which places high demands on integrated circuit design and verification. Timing optimization is repeatedly performed throughout the design process. The long turnaround time for querying the sign-off timer has become a bottleneck. To break through this bottleneck, a fast and accurate timing estimator is needed to speed up the timing closure. Unlike calculating gate timing by inserting a lookup table in the cell library, wire timing calculation remains a mystery in timing analysis. The mysterious formula and complex network structure increase the difficulty of correlating with the results generated by the sign-off timer, further preventing the incremental timing optimization engine from making accurate timing estimates without querying the sign-off timer.

[0003] In the field of integrated circuit design and verification, although existing technologies such as random forests and XGBoost models (eXtreme Gradient Boosting) perform well in processing complex data sets, high-dimensional data, and nonlinear relationships, providing high prediction accuracy and effectively preventing overfitting, they still face some significant challenges when used alone to solve specific problems, especially in wire timing estimation. First, although random forests can handle a large number of input features and unbalanced data, their efficiency and accuracy in processing extremely complex network structures still need to be improved. Second, although XGBoost can effectively process high-dimensional sparse data, its performance in timing prediction of complex wire network structures is limited by the difficulty and time cost of model parameter adjustment.

[0004] Therefore, how to overcome the shortcomings of existing line delay prediction is a technical problem that those skilled in the art urgently need to solve. Summary of the Invention

[0005] Objective: To overcome the deficiencies in the prior art, the present invention provides a method, device, and storage medium for predicting line delay in a digital integrated circuit, which can more accurately predict circuit delay in a shorter time.

[0006] Technical solution: To solve the above technical problems, the technical solution adopted by the present invention is:

[0007] In a first aspect, a method for predicting line delay of a digital integrated circuit comprises the following steps:

[0008] Step 1: Obtain a parasitic parameter netlist for the specified circuit. Each output cell node of the same circuit corresponds to a netlist. Extract the parasitic parameters of each input cell node in each netlist. Use a simulation tool to simulate the parasitic parameters of each input cell node, and obtain the delay information of each path between the output cell node and the input cell node in each netlist as the actual line delay.

[0009] Step 2: Perform sequence feature preprocessing on all parasitic parameters to obtain the simplified topology information of the netlist.

[0010] Step 3: All parasitic parameters are used as inputs of the moment matching algorithm. By performing moment matching operations on the transfer functions of the parasitic parameters, the relationship between the netlist topology and the moment matching theoretical line delay is obtained.

[0011] Step 4: Combine the relationship between the netlist topology and the moment-matching theoretical line delay with the netlist's simplified topology information as input features, and use the netlist's corresponding real line delay as the input label. Cleanse the input features and labels to obtain the cleaned input features and labels.

[0012] Step 5: Use the Bayesian optimization method to adjust the hyperparameters of the XGboost model and the random forest model to obtain the optimal parameters of the XGboost model and the random forest model. Substitute the optimal parameters into the XGboost model and the random forest model respectively to obtain the optimized XGboost model and the random forest model.

[0013] Step 6: Use the cleaned input features and input labels to train the optimized XGboost model and random forest model respectively to obtain the trained XGboost model and random forest model.

[0014] Step 7: Get the input features, delete one of the input features one by one, input the remaining input features into the XGboost model and the random forest model respectively, calculate the prediction indicators of the XGboost model and the random forest model respectively according to the output results, when the change range of the prediction indicator is greater than the threshold, retain the deleted input features, when the change range of the prediction indicator is less than the threshold, remove the deleted input features, and finally obtain the retained input features.

[0015] Step 8: Obtain a standard parasitic parameter format netlist of the circuit to be predicted, obtain the input features of the circuit to be predicted based on the standard parasitic parameter format netlist of the circuit to be predicted, find the optimal input features from the input features of the circuit to be predicted based on the retained input features, input the optimal input features into the weighted neural network, and obtain the XGboost model weights and the random forest model weights.

[0016] Step 9: Input the optimal input features into the trained XGboost model and random forest model respectively to obtain the line delay prediction value of the XGboost model and the line delay prediction value of the random forest model. Perform a weighted sum of the line delay prediction value of the XGboost model and the random forest model with the XGboost model weight and the random forest model weight to obtain the final line delay prediction value of the circuit to be predicted.

[0017] As a preferred solution, the parasitic parameters include: interconnection resistance and interconnection capacitance of the connection characteristics between the output unit node and the input unit node, and grounding capacitance of the output unit node and the input unit node themselves.

[0018] As a preferred solution, the step 2 specifically includes:

[0019] All parasitic parameters are searched through forward nodes to determine the main path and other RC tree branches between each output unit node and the input unit node, and simplified topology information is obtained based on the main path and other RC tree branches.

[0020] As a preferred solution, step S3 specifically includes:

[0021] All parasitic parameters are set as an N-node RC tree, where the nodes are: v0,…,v k ,…,v N , 0≤k≤N, where: v0 is the source node.

[0022] Get the jth moment of the impulse response of node P(i) The recursive model is expressed as follows:

[0023]

[0024] Among them, C k For node v k The ground capacitance at For node v k The j-1th order moment of the impulse response of node v k Forward node, 0≤i≤N, R ki From node v0 to node v k The total resistance of the portion of the unique path from node v0 that overlaps with the unique path from node v0 to node P(i).

[0025] The transfer function is approximated by a simplified set of approximating q poles and a constant numerator Transfer function The expression is as follows:

[0026]

[0027] Where: k ′ 1,k ′ 2,…,k ′ q is related to the extreme point 0>p1≥p2≥p q The corresponding constant numerator.

[0028] According to the transfer function and the step input voltage, the voltage response V(s) under the step input is obtained, and then the voltage response V(s) under the step input is converted into a time domain function v(t).

[0029] The voltage response V(s) under step input is calculated as follows:

[0030]

[0031] Where: U(s) is the Laplace transform of the step input voltage, and s is the complex frequency domain unit.

[0032] The calculation formula of the time domain function v(t) is as follows:

[0033]

[0034] Where t represents the time domain unit and e represents a natural constant.

[0035] Let k i =-k i ′ / p i , the simplified time domain function v(t) is obtained, and the expression is as follows:

[0036]

[0037] According to the simplified time domain function v(t), the zero-order moment m0, first-order moment m1, first-order moment m2, ..., 2q-1 order moment m of node P(i) are obtained. 2q-1 , the expression is as follows:

[0038]

[0039]

[0040]

[0041]

[0042] Calculate the input node v m Theoretical line delay t to node P(i) , 1. Obtain the relationship between the netlist topology and the theoretical line delay of the moment matching. The theoretical line delay t , 1The calculation formula is as follows:

[0043] t, 1=t1*U(t)

[0044] Where, U(t) represents the correction function, which is obtained by fitting the real line delay with a power function.

[0045] in, For input node v m First-order moment m1.

[0046] As a preferred solution, the data cleaning includes: missing value processing, outlier processing and data standardization.

[0047] The missing value processing includes removing any rows containing missing values ​​in the data set.

[0048] The outlier processing includes: calculating the Z-score of all data in the data set, and deleting data points with Z-score values ​​higher than a threshold as outliers.

[0049] The data normalization includes: subtracting the mean value of all data in the normalized data set, and dividing the result by the standard deviation of all data, so that the mean value of each feature value in the data set is 0 and the standard deviation is 1.

[0050] As a preferred solution, the Bayesian optimization method is used to adjust the hyperparameters of the XGboost model and the random forest model to obtain the optimal parameters of the XGboost model and the random forest model, specifically including:

[0051] Step 5.1: Choose the initial parameter space.

[0052] Step 5.2: Train the surrogate model using the parameters in the initial parameter space to approximate the unknown target function.

[0053] Step 5.3: Based on the current proxy model, use the acquisition function to determine the next sampling point.

[0054] Step 5.4: Evaluate the true objective function at the selected sampling points and add the newly obtained sampling points to the existing sampling point set to obtain an updated sampling point set. Retrain the proxy model using the updated sampling point set.

[0055] Step 5.5: Repeat steps 5.3 and 5.4 until the stopping condition is met, such as reaching a predetermined number of iterations or the improvement is less than a certain threshold, to obtain a trained proxy model. The parameters in the trained proxy model are used as the optimal parameters of the XGboost model and the random forest model.

[0056] As a preferred solution, the method of using the cleaned input features and input labels to train the optimized XGboost model to obtain a trained XGboost model specifically includes:

[0057] Use the cleaned input features and input labels as training data, and calculate the mean of the training data as the initial prediction value.

[0058] Using the training data and the current predicted value, calculate the first and second derivatives of the loss function with respect to the predicted value.

[0059] The XGBoost model uses a gradient boosting algorithm to gradually improve predictions by fitting a series of decision tree models. Each iteration fits a new tree model, and the structure of the tree model and the values ​​of the leaf nodes are determined by minimizing the loss function.

[0060] In the process of fitting the tree model, the XGBoost model will regularize the tree structure, including pruning and penalizing the weights of leaf nodes.

[0061] Update the current prediction value based on the newly fitted tree model. Each iteration adds the current prediction value to the prediction result of the newly fitted tree model to obtain the new prediction value.

[0062] The XGBoost model uses an optimization method of the objective function to determine the best tree model at each iteration to minimize the loss function.

[0063] The XGBoost model uses an early stopping strategy, which monitors the performance of the model on the validation set and ends training early when the performance no longer improves, resulting in a trained XGBoost model.

[0064] As a preferred solution, the optimized random forest model is trained using the cleaned input features and input labels to obtain a trained random forest model, specifically including:

[0065] Randomly select a portion of sample data from the cleaned input features and input labels.

[0066] In the process of building each decision tree, the sample data is randomly selected. Usually, at each node split, a feature subset is randomly selected from all the sample data, and then the best feature is selected from this feature subset for splitting.

[0067] Build a decision tree using the selected subsample data and feature subsets by recursively splitting the feature subset into smaller subsets until the data in the smaller subsets belong to the same category or the predefined tree depth is reached.

[0068] When all decision trees are built, the trained random forest model is obtained.

[0069] As a preferred solution, the prediction indicators include: Pearson correlation coefficient, R square, mean square error, root mean square error, relative root mean square error, mean absolute error, relative mean absolute error or maximum error.

[0070] In a second aspect, a computer-readable storage medium stores a computer program, which, when executed by a processor, implements a digital integrated circuit line delay prediction method as described in any one of the first aspects.

[0071] According to a third aspect, a computer device includes:

[0072] Memory, used to store instructions.

[0073] The processor is configured to execute the instructions so that the computer device performs the operations of the digital integrated circuit line delay prediction method as described in any one of the first aspects.

[0074] Beneficial effect: The present invention provides a method, device and storage medium for predicting line delay of digital integrated circuits, which can be applied to timing sign-off problems. First, the circuit is physically designed by a physical design tool, and the parasitic parameter information of the layout after circuit wiring is extracted as the input feature of the prediction model. Then, the path topology information is extracted from the spef (Standard Parasitic Exchange Format) netlist, and sequence feature preprocessing is performed. The processed features are used as the input of the matrix matching model to establish the connection between the netlist topology structure and the line delay. The output of the matrix matching model and the output of the netlist topology information preprocessing are merged and used as the feature input of the XGboost model and the random forest model. Finally, the Bayesian optimization method is used to optimize the hyperparameters to obtain a more robust delay prediction model and output the delay prediction value.

[0075] Compared with traditional precise modeling methods, this method significantly reduces simulation overhead and time. Compared with traditional machine learning methods, this method uses more effective feature engineering to achieve higher-precision predictions at lower simulation overhead, which is of great significance for the timing signoff of digital integrated circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0076] Figure 1 This is a schematic diagram of the digital integrated circuit multi-process corner wire delay prediction framework of the present invention.

[0077] Figure 2 Schematic diagram of the Bayesian optimization process.

[0078] Figure 3 Schematic diagram of the random forest model structure.

[0079] Figure 4 Schematic diagram of the XGBOOST model structure.

[0080] Figure 5 Schematic diagram of the neural network topology of the integrated model. DETAILED DESCRIPTION

[0081] The following is a clear and complete description of the technical solutions in the examples of the present invention, in conjunction with the accompanying drawings. Obviously, the embodiments described are only some of the embodiments of the present invention, not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative work are within the scope of protection of the present invention.

[0082] The present invention will be further described below with reference to specific embodiments.

[0083] Example 1:

[0084] like Figure 1 As shown, this embodiment introduces a method for predicting line delay of a digital integrated circuit, where the line delay refers to the path delay between gate units. The method includes the following steps:

[0085] Step 1: Use a timing analysis tool to obtain a standard parasitic extraction format netlist for the specified circuit. Each output unit node of the same circuit corresponds to a netlist. Extract the parasitic parameters of each input unit node in each netlist. Use a simulation tool to simulate the parasitic parameters of each input unit node and obtain the delay information of each path between the output unit node and the input unit node in each netlist as the actual line delay.

[0086] In one embodiment, the parasitic parameters in step 1 include: interconnect resistance and capacitance between the output unit node and the input unit node, as well as ground capacitance between the output unit node and the input unit node. The nodes in the netlist include wire nodes, output unit nodes, and input unit nodes. When simulating the parasitic parameters of each netlist using a simulation tool, loop checks need to be performed on each netlist, and netlists with loops must be captured.

[0087] Step 2: Perform sequence feature preprocessing on all parasitic parameters to obtain the simplified topology information of the netlist.

[0088] In one embodiment, step 2 specifically includes:

[0089] For all parasitic parameters, the main path between each output unit node and the input unit node and other RC tree (interconnection line model) branches are determined through forward node search. Simplified topology information is obtained based on the main path and other RC tree branches.

[0090] The simplified topology information includes: the total resistance of the main path, the resistance of the main path segment, the total capacitance of the main path, the capacitance of the main path segment, the total capacitance sequence of the RC tree backward from the main path point, the total resistance sequence of the RC tree backward from the main path point, the number of main path segments, the number of the longest branch segments, the total resistance of the longest branch, the total capacitance of the longest branch, the layer number of the minimum capacitance, the layer number of the minimum resistance, the layer number of the maximum capacitance, and the layer number of the maximum resistance.

[0091] Compared with the existing sequence feature preprocessing method, this method innovatively selects four feature quantities: the number of layers where the minimum capacitance is located, the number of layers where the minimum resistance is located, the number of layers where the maximum capacitance is located, and the number of layers where the maximum resistance is located. Compared with the existing sequence feature preprocessing method, this method can more efficiently and concisely reflect the original parasitic parameter characteristics.

[0092] Step 3: All parasitic parameters are used as inputs of the moment matching algorithm. By performing moment matching operations on the transfer functions of the parasitic parameters, the relationship between the netlist topology and the moment matching theoretical line delay is established.

[0093] In one embodiment, step 3 specifically includes:

[0094] All parasitic parameters are set as an N-node RC tree, where the nodes are: v0,…,v k ,…,v N , 0≤k≤N, where v0 is the source node. C k For node v k The ground capacitance at node v k Forward node, 0≤i≤N, R i For nodes P(i) and v k The resistance between nodes is , assuming that the resistance between nodes v0 and v k The total resistance of the overlapped portion of the unique path from node v0 to node P(i) is R ki .

[0095] Get the jth moment of the impulse response of node P(i) The recursive model is expressed as follows:

[0096]

[0097] in, For node v k The j-1th order moment of the impulse response of , and the 0th order moment of any node is defined as 1.

[0098] The transfer function is approximated by a simplified set of approximating q poles and a constant numerator Transfer function The expression is as follows:

[0099]

[0100] Where: k ′ 1,k ′ 2,…,k ′ q is related to the extreme point 0>p1≥p2≥p q The corresponding constant numerator is used to represent the weight of each extreme point.

[0101] According to the transfer function and the step input voltage, the voltage response V(s) under the step input is obtained, and then the voltage response V(s) under the step input is converted into a time domain function v(t).

[0102] The voltage response V(s) under step input is calculated as follows:

[0103]

[0104] Where: U(s) is the Laplace transform of the step input voltage, and s is the complex frequency domain unit.

[0105] For RC trees, the poles are located only on the negative real axis of the s-plane (Laplace transform complex frequency domain plane).

[0106] The calculation formula of the time domain function v(t) is as follows:

[0107]

[0108] Where t represents the time domain unit and e represents a natural constant.

[0109] Let k i =-k i ′ / p i , then formula (4) can be simplified to the simplified time domain function v(t), which is expressed as follows:

[0110]

[0111] According to the simplified time domain function v(t), the zero-order moment m0, first-order moment m1, first-order moment m2, ..., 2q-1 order moment m of node P(i) are obtained. 2q-1 , the expression is as follows:

[0112]

[0113]

[0114]

[0115]

[0116] Calculate the input node v m Theoretical line delay t to node P(i) , 1. Obtain the relationship between the netlist topology and the theoretical line delay of the matrix matching. The theoretical line delay t , 1The calculation formula is as follows:

[0117] t , 1=t1*U(t)

[0118] Where, U(t) represents the correction function, which is obtained by fitting the real line delay with a power function.

[0119] in, For input node v m First-order moment m1.

[0120] We have made innovative corrections to the original moment matching calculation. Regarding the t1 feature calculated by moment matching, since the moment matching model is only based on the driving point voltage step signal, it does not match the actual charging time of the driving point voltage. When the moment matching delay is shorter and the driving point branches are more numerous and longer, its t1 deviates from the actual delay. Therefore, we use the power function to fit the actual delay to obtain the correction function U(t), and correct the moment matching delay t1, so that the updated moment matching delay t , 1=t1*U(t). Compared with the original uncorrected result, the maximum percentage error of its small value is reduced from 300% to 30%.

[0121] Step 4: Combine the relationship between the netlist topology and the moment-matching theoretical line delay with the netlist's simplified topology information as input features, and use the netlist's corresponding real line delay as the input label. Cleanse the input features and labels to obtain the cleaned input features and labels.

[0122] In one embodiment, the data cleaning includes: missing value processing, outlier processing and data standardization.

[0123] The missing value processing includes removing any rows containing missing values ​​in the data set to ensure that the data format is correct.

[0124] Outlier processing involves calculating the Z-score of all data points in the dataset and deleting data points with Z-scores above a threshold as outliers. The Z-score measures the distance of a data point from the mean, measured in standard deviations. The threshold is the distance from the mean.

[0125] Data normalization involves subtracting the mean of all data in the normalized dataset (to centralize the data), and then dividing the result by the standard deviation of all data, so that the mean of each feature value in the dataset is 0 and the standard deviation is 1. This helps improve the generalization ability of the model, making the model more accurate and reliable when applied to unknown data.

[0126] like Figure 2 As shown, step 5: Use the Bayesian optimization method to adjust the hyperparameters of the XGboost model and the random forest model to obtain the optimal parameters of the XGboost model and the random forest model, and substitute the optimal parameters into the XGboost model and the random forest model respectively to obtain the optimized XGboost model and the random forest model.

[0127] In one embodiment, the Bayesian optimization method is used to adjust the hyperparameters of the XGboost model and the random forest model to obtain the optimal parameters of the XGboost model and the random forest model, specifically including:

[0128] Step 5.1: Choose the initial parameter space.

[0129] Step 5.2: Use the parameters in the initial parameter space to train the surrogate model. Here, a Gaussian process model is used to approximate the unknown target function.

[0130] Step 5.3: Based on the current proxy model, use the acquisition function to decide the next sampling point. This step is to find a point that is most likely to bring significant improvement to the objective function while taking into account the balance between exploration and exploitation.

[0131] Step 5.4: Evaluate the true objective function at the selected sampling points and add the newly obtained sampling points to the existing sampling point set to obtain an updated sampling point set. Retrain the proxy model using the updated sampling point set.

[0132] Step 5.5: Repeat steps 5.3 and 5.4 until the stopping condition is met, such as reaching a predetermined number of iterations or the improvement is less than a certain threshold, to obtain a trained proxy model. The parameters in the trained proxy model are used as the optimal parameters of the XGboost model and the random forest model.

[0133] Step 6: Use the cleaned input features and input labels to train the optimized XGboost model and random forest model respectively to obtain the trained XGboost model and random forest model.

[0134] like Figure 3As shown, in one embodiment, the method of using the cleaned input features and input labels to train the optimized XGboost model to obtain a trained XGboost model specifically includes:

[0135] Use the cleaned input features and input labels as training data, and calculate the mean of the training data as the initial prediction value, that is, the initial prediction value of all samples is the same.

[0136] Using the training data and the current predicted value, the first-order derivative (gradient) and second-order derivative (Hessian matrix) of the loss function with respect to the predicted value are calculated, and this information is used to fit a new tree model.

[0137] The XGBoost model uses a gradient boosting algorithm to gradually improve predictions by fitting a series of decision tree models. Each iteration fits a new tree model, and the structure of the tree model and the values ​​of the leaf nodes are determined by minimizing the loss function.

[0138] In the process of fitting the tree model, the XGBoost model regularizes the tree structure, including pruning and penalizing leaf node weights to prevent overfitting.

[0139] Update the current prediction value based on the newly fitted tree model. Each iteration adds the current prediction value to the prediction result of the newly fitted tree model to obtain the new prediction value.

[0140] The XGBoost model uses an optimization method of the objective function to determine the best tree model at each iteration to minimize the loss function.

[0141] The XGBoost model uses an early stopping strategy, which monitors the performance of the model on the validation set and stops training early when the performance stops improving, obtaining a trained XGBoost model to prevent overfitting.

[0142] XGBoost combines the gradient boosting algorithm and regularization method in the training process, which can effectively handle high-dimensional sparse data and large-scale data sets.

[0143] like Figure 4 As shown, in one embodiment, the use of the cleaned input features and input labels to train the optimized random forest model to obtain a trained random forest model specifically includes:

[0144] A subset of sample data is randomly selected from the cleaned input features and input labels, so that each decision tree is trained on a different subset. This process is called bootstrap sampling.

[0145] During the construction of each decision tree, sample data is randomly selected. This increases the diversity of each tree. Typically, at each node split, a subset of features is randomly selected from all sample data, and then the best feature from this subset is selected for the split.

[0146] Use the selected subsample data and feature subsets to build a decision tree. The CART (Classification and Regression Trees) algorithm is used here to recursively split the feature subset into smaller subsets until the data in the smaller subsets belong to the same category or the predefined tree depth is reached.

[0147] When all decision trees are built, a trained random forest model is obtained. For regression problems, the random forest will average the prediction results of each tree to obtain the final prediction value.

[0148] Randomness is introduced into the construction process of random forest, which makes each tree different. This randomness helps to reduce the variance of the model, improve the generalization ability of the model, and reduce the risk of overfitting.

[0149] Step 7: Obtain input features, delete certain features one by one, and input the remaining input features into the XGboost model and the random forest model respectively. Based on the output results, calculate the prediction indicators of the XGboost model and the random forest model respectively. When the change in the prediction indicator is greater than the threshold, retain the deleted input feature. When the change in the prediction indicator is less than the threshold, remove the deleted input feature and obtain the retained input feature. This is used to shorten prediction time by reducing the model input features.

[0150] In one embodiment, the prediction indicators include: Pearson correlation coefficient, R square, mean square error, root mean square error, relative root mean square error, mean absolute error, relative mean absolute error or maximum error.

[0151] Pearson correlation coefficient: This measures the linear correlation between two variables. Its value range is between -1 and 1, where 1 indicates a perfect positive correlation, -1 indicates a perfect negative correlation, and 0 indicates no correlation.

[0152] R-squared: R-squared is a measure of how well a model fits the data. It indicates what percentage of the variation in the dependent variable is explained by the independent variables. R-squared values ​​range from 0 to 1, with values ​​closer to 1 indicating a better model fit.

[0153] Mean Squared Error (MSE): The mean squared error is the average of the squares of the differences between the predicted values ​​and the true values. A smaller MSE indicates a more accurate model’s predictions.

[0154] Root Mean Squared Error (RMSE): The RMSE is the square root of the mean squared error, and has the same units as the original data. A smaller RMSE indicates a more accurate model prediction.

[0155] Relative Root Mean Squared Error (RRMSE): RRMSE is the ratio of RMSE to the mean of the target variable. It helps us measure the degree of fluctuation of the model's prediction error relative to the target variable.

[0156] Mean Absolute Error (MAE): The mean absolute error is the average of the absolute differences between the predicted values ​​and the true values. A smaller MAE indicates a more accurate model’s predictions.

[0157] Relative Mean Absolute Error (RMAE): RMAE is the ratio of MAE to the mean of the target variable, similar to RRMSE, and is used to measure the fluctuation of the model's prediction error relative to the target variable.

[0158] Maximum Error: The maximum error is the maximum difference between the predicted value and the true value. It represents the maximum deviation of the model prediction.

[0159] These evaluation indicators can help us comprehensively evaluate the performance of the model, including the model's prediction accuracy, degree of fit, stability and other aspects.

[0160] Step 8: Obtain a standard parasitic parameter format netlist of the circuit to be predicted, obtain the input features of the circuit to be predicted based on the standard parasitic parameter format netlist of the circuit to be predicted, find the optimal input features from the input features of the circuit to be predicted based on the retained input features, input the optimal input features into the weighted neural network, and obtain the XGboost model weights and the random forest model weights.

[0161] Step 9: Input the optimal input features into the trained XGboost model and random forest model respectively to obtain the line delay prediction value of the XGboost model and the line delay prediction value of the random forest model. Perform a weighted sum of the line delay prediction value of the XGboost model and the random forest model with the XGboost model weight and the random forest model weight to obtain the final line delay prediction value of the circuit to be predicted.

[0162] Adopt a distributed training method. First, train two different models (XGboost and random forest), and then use a neural network for integration, so as to obtain a fitting result with smaller errors, higher accuracy and lower cost.

[0163] As Figure 5 shown, in one embodiment, the neural network specifically includes:

[0164] The main body is a fully connected layer (FC), the input feature is a feature vector of m×1 (denoted as f or f i : i represents the i-th feature, where 1 < i < m), and the output is a weight matrix of n×2 (denoted as F or k represents the k-th feature, where 1 < k < n, l = 1 represents the weight of the random forest model, and l = 2 represents the weight of the XGboost model), specifically a fully connected layer composed of three hidden layers with 2m feature numbers (denoted as where i = 1, 2, 3, represents the i-th layer; j represents the j-th feature, where 1 < i < 2m), without bias.

[0165] The specific calculation process of the model is as follows:

[0166] F = softmax{O[H3.H2(H1(f)) / ]}

[0167] Among them:

[0168]

[0169] q is the number of features in the previous layer, x p is the value of the p-th feature in the (i - 1)-th layer, is the coefficient corresponding to the p-th feature in the (i - 1)-th layer and the j-th feature in the i-th layer, and will be optimized during the network training process. O[] represents the fully connected output layer. softmax represents performing a softmax operation on the whole, and the summation object is the two values corresponding to each output feature.

[0170] After obtaining the corresponding weights through the fully connected layer, the final output is:

[0171]

[0172] Among them, RF represents the predicted value output by the random forest model, and XGB represents the predicted value output by the XGboost model.

[0173] Embodiment 2:

[0174] A computer-readable storage medium stores a computer program, which, when executed by a processor, implements a digital integrated circuit line delay prediction method as described in any one of the first embodiments.

[0175] Example 3:

[0176] A computer device comprising:

[0177] Memory, used to store instructions.

[0178] The processor is configured to execute the instructions so that the computer device performs the operations of the digital integrated circuit line delay prediction method as described in any one of the embodiments 1.

[0179] Example 4:

[0180] The present invention discloses a method for predicting line delays in digital integrated circuits that can be applied to timing signoff problems. First, a physical design tool is used to physically design the circuit, extracting the parasitic parameter information of the circuit layout after wiring as input features for the prediction model. Path topology information is then extracted from the SPEF netlist. Data from 104,564 nodes are first extracted. After data optimization, data from 11,364 nodes are extracted a second time. Sequence feature preprocessing is performed, and the processed features are used as input to a moment matching model to establish a connection between the netlist topology and line delays. The output of the moment matching model and the output of the netlist topology information preprocessing are combined and used as feature inputs for the XGBoost model and the random forest model. Finally, hyperparameter optimization is performed using the Bayesian optimization method to obtain a robust delay prediction model and output the delay prediction value. Compared with traditional precise model methods, this method can significantly reduce simulation overhead and time. Compared with traditional machine learning methods, the present invention uses more effective feature engineering processing to achieve higher-precision prediction results at lower simulation overhead, which is of great significance for the timing signoff of digital integrated circuits.

[0181] After adjusting the parameters using the Bayesian optimization method, the optimal parameter combination of xgboost is obtained:

[0182] learning_rate = 0.12986727034268092.

[0183] max_depth (maximum depth of the tree) = 7.

[0184] min_samples_leaf (the minimum number of samples required for the terminal node of the decision tree) = 9.

[0185] min_samples_split (the minimum number of samples required to split an internal node (non-leaf node)) = 8.

[0186] n_estimators (number of trees in the ensemble) = 994.

[0187] The optimal parameter combination of the random forest model is:

[0188] max_depth (maximum depth of the tree) = 7,

[0189] min_samples_leaf (the minimum number of samples required for the end node of the decision tree) = 1,

[0190] min_samples_split (the minimum number of samples required to split an internal node (non-leaf node)) = 2,

[0191] n_estimators (number of trees in the ensemble) = 955

[0192] The most important features are selected for training, and the evaluation indicators of XGboost are:

[0193] Pearson coefficient: 0.998258.

[0194] R-squared: 0.996503.

[0195] Mean Squared Error (MSE): 0.000006.

[0196] Root Mean Squared Error (RMSE): 0.002347.

[0197] Relative Root Mean Squared Error (RRMSE): 0.037162.

[0198] Mean Absolute Error (MAE): 0.001377.

[0199] Relative Mean Absolute Error (RMAE): 0.021797.

[0200] Maximum Error: 0.039579.

[0201] The evaluation indicators of random forest are:

[0202] Pearson coefficient: 0.998259.

[0203] R-squared: 0.996517.

[0204] Mean Squared Error (MSE): 0.000005.

[0205] Root Mean Squared Error (RMSE): 0.002287.

[0206] Relative Root Mean Squared Error (RRMSE): 0.036746.

[0207] Mean Absolute Error (MAE): 0.001548.

[0208] Relative Mean Absolute Error (RMAE): 0.024874.

[0209] Maximum Error: 0.020186.

[0210] After comprehensive consideration, we believe that using the maximum percentage error as the criterion for judging feature importance can best balance the overall effect of the model. We also realize that the more features, the better the training effect. Therefore, we selected 10-20 most important features for testing. We found that when the 15 most important features were selected, the training effect was optimal.

[0211] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A method for predicting line delay of a digital integrated circuit, characterized by: The steps include: Step 1: Obtain a parasitic parameter format netlist for the specified circuit. Each output unit node of the same circuit corresponds to a netlist. Extract the parasitic parameters of each input unit node in each netlist. Use a simulation tool to simulate the parasitic parameters of each input unit node and obtain the delay information of each path between the output unit node and the input unit node in each netlist as the real line delay. Step 2: Perform sequence feature preprocessing on all parasitic parameters to obtain simplified topology information of the netlist; Step 3: All parasitic parameters are used as inputs to the moment matching algorithm. By performing moment matching operations on the transfer functions of the parasitic parameters, the relationship between the netlist topology and the moment matching theoretical line delay is obtained. Step 4: Combine the relationship between the netlist topology and the moment matching theoretical line delay with the netlist simplified topology information as input features, and use the actual line delay corresponding to the netlist as the input label; perform data cleaning on the input features and input labels to obtain the cleaned input features and input labels; Step 5: Use the Bayesian optimization method to adjust the hyperparameters of the XGboost model and the random forest model to obtain the optimal parameters of the XGboost model and the random forest model. Substitute the optimal parameters into the XGboost model and the random forest model respectively to obtain the optimized XGboost model and the random forest model; Step 6: Use the cleaned input features and input labels to train the optimized XGboost model and random forest model respectively to obtain the trained XGboost model and random forest model; Step 7: Obtain input features, delete one of the input features one by one, input the remaining input features into the XGboost model and the random forest model respectively, and calculate the prediction indicators of the XGboost model and the random forest model respectively based on the output results. When the change range of the prediction indicator is greater than the threshold, retain the deleted input feature. When the change range of the prediction indicator is less than the threshold, remove the deleted input feature, and finally obtain the retained input feature; Step 8: Obtain a standard parasitic parameter format netlist of the circuit to be predicted, obtain the input features of the circuit to be predicted based on the standard parasitic parameter format netlist of the circuit to be predicted, find the optimal input features from the input features of the circuit to be predicted based on the retained input features, input the optimal input features into the weighted neural network, and obtain the XGboost model weights and the random forest model weights; Step 9: Input the optimal input features into the trained XGboost model and random forest model respectively to obtain the line delay prediction value of the XGboost model and the line delay prediction value of the random forest model. Perform a weighted sum of the line delay prediction value of the XGboost model and the random forest model with the XGboost model weight and the random forest model weight to obtain the final line delay prediction value of the circuit to be predicted.

2. The method for predicting line delay of a digital integrated circuit according to claim 1, wherein: The parasitic parameters include: interconnection resistance and capacitance of the connection characteristics between the output unit node and the input unit node, and grounding capacitance of the output unit node and the input unit node itself.

3. The method for predicting line delay of a digital integrated circuit according to claim 1, wherein: The step 3 specifically includes: All parasitic parameters are set as an N-node RC tree, where the nodes are: , ,in: is the source node; Get Node The j-th moment of the impulse response The recursive model is expressed as follows: ； in, For nodes The ground capacitance at For nodes The j-1th moment of the impulse response, For nodes The forward node of , For slave nodes To Node The only path from the node To Node The total resistance of the overlapping portion of the unique path; The transfer function is approximated by a simplified set of approximating q poles and a constant numerator , transfer function The expression is as follows: ； in: Is with the extreme The corresponding constant numerator; Based on the transfer function and the step input voltage, the voltage response under the step input is obtained. , then the voltage response under step input Convert to time domain function ; Among them, the voltage response under step input is The calculation formula is as follows: ； Where: is the Laplace transform of the step input voltage, is a complex frequency domain unit; Time domain function The calculation formula is as follows: ； in, Indicates the time domain unit, represents a natural constant; make , we get the simplified time domain function , the expression is as follows: ； According to the simplified time domain function , get the node Zero-order moment , first-order moment , first-order moment , ..., 2q-1 moment , the expression is as follows: ； ； ； ； Compute Input Node To Node Theoretical line delay , we get the relationship between the netlist topology and the matrix matching theoretical line delay, the theoretical line delay The calculation formula is as follows: ； Where, , represents the correction function, which is obtained by fitting the real line delay with a power function; in, For input nodes First-order moment .

4. The method for predicting line delay of a digital integrated circuit according to claim 1, wherein: The data cleaning includes: missing value processing, outlier processing and data standardization; The missing value processing includes: removing any rows containing missing values ​​in the data set; The outlier processing includes: calculating the Z-score of all data in the data set, and deleting data points with Z-score values ​​higher than a threshold as outliers; The data normalization includes: subtracting the mean value of all data in the normalized data set, and dividing the result by the standard deviation of all data, so that the mean value of each feature value in the data set is 0 and the standard deviation is 1.

5. The method for predicting line delay of a digital integrated circuit according to claim 1, wherein: The Bayesian optimization method is used to adjust the hyperparameters of the XGboost model and the random forest model to obtain the optimal parameters of the XGboost model and the random forest model, specifically including: Step 5.1: Select the initial parameter space; Step 5.2: Train the surrogate model using the parameters in the initial parameter space to approximate the unknown target function. Step 5.3: Based on the current proxy model, use the acquisition function to determine the next sampling point; Step 5.4: Evaluate the true objective function at the selected sampling points and add the newly obtained sampling points to the existing sampling point set to obtain an updated sampling point set; retrain the proxy model using the updated sampling point set; Step 5.5: Repeat steps 5.3 and 5.4 until the stopping condition is met. The stopping condition is that the predetermined number of iterations is reached or the improvement is less than a certain threshold. The trained proxy model is obtained and the parameters in the trained proxy model are used as the optimal parameters of the XGboost model and the random forest model.

6. The method for predicting line delay of a digital integrated circuit according to claim 1, wherein: The method uses the cleaned input features and input labels to train the optimized XGboost model to obtain a trained XGboost model, specifically including: Use the cleaned input features and input labels as training data, and calculate the mean of the training data as the initial prediction value; Using the training data and the current predicted value, calculate the first and second derivatives of the loss function with respect to the predicted value; The XGBoost model uses a gradient boosting algorithm to gradually improve the prediction value by fitting a series of decision tree models. Each iteration fits a new tree model, and the structure of the tree model and the values ​​of the leaf nodes are determined by minimizing the loss function. In the process of fitting the tree model, the XGBoost model will regularize the tree structure, including pruning and penalizing the weight of leaf nodes; Update the current prediction value according to the newly fitted tree model; each iteration adds the current prediction value to the prediction result of the newly fitted tree model to obtain a new prediction value; The XGBoost model uses an optimization method of the objective function to determine the best tree model for each iteration to minimize the loss function; The XGBoost model uses an early stopping strategy, which monitors the performance of the model on the validation set and ends training early when the performance no longer improves, resulting in a trained XGBoost model.

7. The method for predicting line delay of a digital integrated circuit according to claim 1, wherein: The optimized random forest model is trained using the cleaned input features and input labels to obtain a trained random forest model, specifically including: Randomly select a portion of sample data from the cleaned input features and input labels; In the process of building each decision tree, sample data is randomly selected; usually at each node split, a feature subset is randomly selected from all sample data, and then the best feature is selected from this feature subset for splitting; Build a decision tree using the selected subsample data and feature subsets by recursively splitting the feature subset into smaller subsets until the data in the smaller subsets belong to the same category or the predefined tree depth is reached; When all decision trees are built, the trained random forest model is obtained.

8. The method for predicting line delay of a digital integrated circuit according to claim 1, wherein: The prediction indicators include: Pearson correlation coefficient, R square, mean square error, root mean square error, relative root mean square error, mean absolute error, relative mean absolute error or maximum error.

9. A computer-readable storage medium, characterized in that: A computer program is stored thereon, and when the computer program is executed by a processor, a digital integrated circuit line delay prediction method as claimed in any one of claims 1 to 8 is implemented.

10. A computer device, characterized in that: include: a memory for storing instructions; The processor is configured to execute the instructions so that the computer device performs the operation of the digital integrated circuit line delay prediction method as described in any one of claims 1 to 8.

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