Frame flip driving method, driving circuit and display device

Abstract

The present application discloses a frame flip driving method, a driving circuit and a display device, wherein the frame flip driving method includes determining whether the polarity control signal of the next frame is positive or negative according to the polarity control signal of the current frame; if it is positive, the polarity control signal of the next frame is controlled to be output according to a first set phase; if it is negative, the polarity control signal of the next frame is controlled to be output according to a second set phase; wherein the first set phase is different from the second set phase. The above method solves the screen flickering problem under frame flipping.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a frame flip driving method, a driving circuit and a display device. Background Art

[0002] The display device may generally include a display panel and a driving circuit for driving the display panel. The driving circuit may include a timing controller (TCON for short), a gate driving circuit and a source driving circuit.

[0003] In the related art, the source driving circuit can convert the digital signal input by TCON into an analog signal corresponding to the grayscale voltage according to the gamma reference voltage and output it to each pixel unit of the display panel. At present, in order to improve the display effect of the display device, the display panel is generally driven by frame inversion, that is, the voltage polarity stored in each pixel unit in the display panel is opposite in the cycle of two adjacent frames. In the frame inversion driving mode, the timing controller can output a polarity control signal to the source driving circuit, and the source driving circuit can adjust the polarity of the analog signal output to the display panel according to the level of the polarity control signal.

[0004] Currently in the panel display industry, there is a serious problem of flickering under frame flipping. The reason is that when the polarity is switched, the charging time difference between the positive and negative polarities is too large, resulting in a large difference in brightness and darkness changes and flickering. Summary of the invention

[0005] The main technical problem solved by the present application is to provide a frame flip driving method, a driving circuit and a display device to solve the problem of severe flickering under frame flipping.

[0006] To solve the above problems, the first aspect of the present application provides a frame flipping driving method, which includes: determining whether the polarity control signal of the next frame is positive or negative according to the polarity control signal of the current frame; if it is positive, controlling the polarity control signal of the next frame to be output according to a first set phase; if it is negative, controlling the polarity control signal of the next frame to be output according to a second set phase; wherein the first set phase is different from the second set phase.

[0007] Preferably, the frame flipping is flipping every frame; the step of determining whether the polarity control signal of the next frame is positive or negative according to the polarity control signal of the current frame comprises: identifying whether the polarity control signal of the current frame is positive or negative; if the polarity control signal of the current frame is positive, determining that the polarity control signal of the next frame is negative; if the polarity control signal of the current frame is negative, determining that the polarity control signal of the next frame is positive.

[0008] Preferably, the frame flipping is flipping every frame; the step of determining whether the polarity control signal of the next frame is positive or negative based on the polarity control signal of the current frame comprises: identifying whether the polarity control signal of the current frame is flipped from positive to negative, or from negative to positive; if the polarity control signal of the current frame is flipped from positive to negative, then determining that the polarity control signal of the next frame is positive; if the polarity control signal of the current frame is flipped from negative to positive, then determining that the polarity control signal of the next frame is negative.

[0009] Preferably, the second set phase is delayed from the first set phase.

[0010] Preferably, the step of outputting the polarity control signal for controlling the next frame according to the first set phase includes: outputting the polarity control signal of the first set phase through a timing controller; the step of outputting the polarity control signal for controlling the next frame according to the second set phase includes: outputting the polarity control signal of the second set phase delayed from the first set phase through a timing controller; wherein the time by which the second set phase is delayed from the first set phase is adjustable.

[0011] Preferably, the step of controlling the polarity control signal of the next frame to be output according to the second set phase includes: determining the second set phase of the polarity control signal output to each group of data lines according to the distance between the output position of the polarity control signal and the gate driving circuit.

[0012] Preferably, the farther the output position is from the gate driving circuit, the longer the delay time of the polarity control signal of the second set phase output to each group of data lines.

[0013] To solve the above-mentioned problem, the second aspect of the present application provides a driving circuit, which at least includes: a trigger module and a timing controller; the trigger module is used to determine whether the polarity control signal of the next frame is positive or negative according to the polarity control signal of the current frame; the timing controller is connected to the trigger module, and is used to control the polarity control signal of the next frame to be output according to a first set phase when it is determined that the polarity control signal of the next frame is positive; and control the polarity control signal of the next frame to be output according to a second set phase when it is determined that the polarity control signal of the next frame is negative.

[0014] Preferably, the driving circuit further comprises a source driver, wherein the source driver is connected to the trigger module and is used for identifying a polarity control signal of a current frame and sending the polarity control signal of the current frame to the trigger module.

[0015] To solve the above-mentioned problem, the third aspect of the present application provides a display device, which includes the driving circuit and the display panel described in any embodiment of the second aspect, and the driving circuit and the display panel are electrically connected.

[0016] The beneficial effect of the present application is: according to the polarity control signal of the current frame, it is determined whether the polarity control signal of the next frame is positive or negative. When it is determined to be positive, the polarity control signal of the next frame is controlled to be output according to the first set phase, and when it is determined to be negative, the polarity control signal of the next frame is controlled to be output according to the second set phase, so that the phase of the polarity control signal of the positive polarity or the negative polarity (mainly the negative polarity) can be adjusted separately, and then the charging time of the sub-pixel under the positive polarity or the negative polarity (mainly the negative polarity) is adjusted, so that the charging time of the sub-pixel under different polarities is the same, thereby improving the problem of flickering / screen flashing caused by excessive brightness difference under frame flipping. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0018] Figure 1 A timing diagram of a driving signal of a certain sub-pixel of a display panel in the prior art;

[0019] Figure 2 This is a flow chart of an embodiment of a frame flip driving method of the present application;

[0020] Figure 3 This is a timing diagram of an embodiment of the polarity control signal of the present application;

[0021] Figure 4 This is a flow chart of a first specific embodiment of the frame flipping driving method of the present application;

[0022] Figure 5 This is a flow chart of a second specific embodiment of the frame flipping driving method of the present application;

[0023] Figure 6 A relationship diagram between the delay time and output position of a polarity control signal of a second set phase provided by the present application;

[0024] Figure 7 This is a schematic diagram of the structure of an embodiment of the driving circuit of the present application;

[0025] Figure 8 This is a schematic structural diagram of a specific embodiment of the driving circuit of the present application;

[0026] Fig. 9 This is a timing diagram of a specific embodiment of the driving signal of the present application;

[0027] Fig.10 It is a structural schematic diagram of an embodiment of a display device of the present application.

[0028] gate; data; 70 control circuit; 71 trigger module; 72 timing controller; 73 source driver; 100 display panel. DETAILED DESCRIPTION

[0029] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0030] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the present application. The singular forms of "a", "said", and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms, unless otherwise clearly indicated above, and "multiple" generally includes at least two, but does not exclude the inclusion of at least one.

[0031] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the objects associated with each other are in an "or" relationship. The terms "first", "second", etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0032] It should be understood that the terms "include", "comprises" or any other variations used herein are intended to cover non-exclusive inclusion, so that a process, method, article or device that includes a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of more restrictions, the elements defined by the sentence "includes..." do not exclude the presence of other identical elements in the process, method, article or device that includes the elements.

[0033] It should be noted that if the embodiments of the present application involve directional indications (such as up, down, left, right, front, back...), such directional indications are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0034] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The presence of the phrase at each location in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0035] Please refer to Figure 1 , Figure 1 is a timing diagram of a driving signal of a certain sub-pixel of a display panel in the prior art. Figure 1 Figure ① is the timing diagram of the driving signal of the GDL near end + Data near end. Figure 1 ② in the middle is the driving signal timing diagram of GDL far end + Data near end. Figure 1 ③ in the middle is the driving signal timing diagram of GDL near end + Data far end. Figure 1 ④ is the driving signal timing diagram of GDL far end + Data far end. It should be noted that the GDL near end refers to the sub-pixel set near one end of the GDL (gate drive circuit), and its characteristics are: the gate drive signal (that is, gate) input to the sub-pixel is less affected by the RC (resistance, capacitance) load, and is basically considered to have no effect, that is, the signal has no delay. The GDL far end refers to the sub-pixel set far away from the GDL end, and its characteristics are: the gate signal input to the sub-pixel is greatly affected by RC, and the gate drive signal has a delay. The Data near end refers to the sub-pixel set near one end of the source drive signal (Data), and its characteristics are: the data signal input to the sub-pixel is less affected by RC, and the data signal input to the sub-pixel has no delay. The Data far end refers to the sub-pixel set far away from the source drive signal end, and its characteristics are: the data signal input to the sub-pixel is greatly affected by RC, and the data signal has a delay. Among them, VGL and VGH are both gate drive signals, and VGH is used to control the opening of the pixel circuit to charge the data voltage into the sub-pixel; VGL is used to control the closing of the pixel circuit to end the charging of the data voltage of the sub-pixel. like Figure 1As shown in ② and ④, when the gate drive signal gate is greatly affected by RC, the charging time of the positive and negative data signals charged into the sub-pixels will be inconsistent, which will cause the charging time difference of the positive and negative data voltages at the far end of GDL to reach the maximum under frame flipping (Frame switching), resulting in the problem of screen flickering due to the difference in brightness.

[0036] In order to solve the problem of severe flickering of the display panel under frame flipping, the present application provides a frame flipping driving method. Figure 2 , Figure 2 FIG. 1 is a flow chart of an embodiment of a frame flip driving method of the present application. Figure 2 As shown, the frame flip driving method includes:

[0037] Step S11: determining whether the polarity control signal of the next frame is positive or negative according to the polarity control signal of the current frame.

[0038] This step specifically includes: determining the polarity control signal of the next frame according to the polarity (or reverse polarity) of the polarity control signal of the current frame. The polarity control signal is a control signal output by the timing controller to the source driving circuit, which is used to control the time when the source driving circuit inputs data signals to each data line in the display panel.

[0039] If it is determined that the polarity control signal of the next frame is positive polarity, step S12 is executed. If it is determined that the polarity control signal of the next frame is negative polarity, step S13 is executed.

[0040] Step S12: Control the polarity control signal of the next frame to be output according to the first set phase.

[0041] This step specifically includes: outputting a polarity control signal of a first set phase to the source driving circuit through a timing controller.

[0042] Step S13: Control the polarity control signal of the next frame to be output according to the second set phase.

[0043] This step specifically includes: outputting a polarity control signal having a second set phase to the source driving circuit through the timing controller.

[0044] Among them, the first set phase is different from the second set phase. Specifically, it means that the time (phase) of the first set phase and the second set phase is different. Specifically, there are two situations: the first set phase is delayed from the second set phase; or, the second phase is delayed from the first set phase. It should be noted that the phase widths of the first set phase and the second set phase are the same, the difference is that the rising edge of the first set phase and the rising edge of the second set phase are different relative to the scanning signal. It can be compared with the rising edge of the scanning signal or with the falling edge of the scanning signal.

[0045] In a specific embodiment, the second set phase is delayed from the first set phase, that is, the second set phase is later than the first set phase. Figure 3 , Figure 3 FIG. 1 is a timing diagram of an embodiment of the polarity control signal of the present application. Figure 3 As shown, Figure 3 ① is the case when the first setting phase and the second setting phase are the same, and ② is the case when the second setting phase is later than the first setting phase. HVAA is the reference potential. VGH is the high potential of the gate, that is, the voltage to open the gate. VGL is the low potential of the gate, that is, the voltage to close the gate. Figure 3 As shown, the gate lines of a row of sub-pixels are turned on by the VGH voltage, and then the data voltage is input into the sub-pixels through the data line data, thereby realizing voltage writing. When it is determined that the next frame is to input positive polarity, the Data signal located above HVAA is input into the data line, and when it is determined that the next frame is to input negative polarity, the Data signal located below HVAA is input into the data line. Figure 3It can be seen from ① that because the voltage starting points of the positive and negative polarities of the Data (data signal) are inconsistent, the charging time difference of the positive / negative polarity occurs when the GDL (gate drive circuit) is affected by RC (resistance and capacitance load). Because the voltage starting point of the positive polarity is higher, it is less affected by the Failing (falling edge) of the GDL RC, and the positive polarity charging difference is small, but the voltage starting point of the negative polarity is lower, and it is more affected by the Failing of the GDL RC, and the negative polarity charging difference is large. After the Frame (frame) is switched, the charging time difference of the positive and negative polarities at the far end of the GDL will also reach the maximum, resulting in the problem of screen flicker due to the difference in brightness. In other words, when charging the sub-pixels of the same row, when the positive polarity data voltage is charged, the gate voltage reaches the turn-off voltage faster, and when the negative polarity data voltage is charged, the gate voltage falls more slowly due to the influence of the RC load, resulting in a longer charging time for the negative polarity than the positive polarity, which leads to uneven charging time for two adjacent frames, and then the problem of screen flicker occurs when the frame is flipped. Therefore, the present application improves the screen flickering problem caused by uneven charging time of positive and negative polarities by making the charging time of negative polarity pixels adjustable separately. Figure 3 As shown in ②, the phase of the negative polarity data signal is delayed backwards, thereby shortening the charging time of the negative polarity data signal and making the charging time of the positive polarity and the negative polarity consistent, thereby solving the problem of screen flickering.

[0046] In other embodiments, the first set phase may be delayed relative to the second set phase, so that the charging time of the positive and negative polarities are consistent. For example, under the same gate voltage, when the charging time of the positive polarity data voltage is longer than the charging time of the negative polarity, the first set phase may be delayed relative to the second set phase. For example, in a specific application scenario, the gate in the display panel is turned on under the action of VGL (low potential) and turned off under the action of VGH. In this case, the transmission of the data signal is gradually turned off at the rising edge of VGL to VGH. At this time, when the positive polarity data voltage is rushed in, the gate is closed more slowly, so that the positive polarity charging time is longer than the negative polarity charging time.

[0047] It should be noted that the next frame is relative to the current frame. When the next frame is the current frame, it is determined according to the polarity control signal of the previous frame. In other words, the present embodiment determines whether the polarity control signal of the current frame is positive or negative according to the polarity control signal of the previous frame. If it is positive, the polarity control signal of the current frame is controlled to be output according to the first set phase; if it is negative, the polarity control signal of the current frame is controlled to be output according to the second set phase. The next frame is not limited here.

[0048] The control method is applicable to a display panel with frame inversion. The following describes a specific implementation method with the second set phase delayed from the first set phase.

[0049] In a specific implementation, step S11 specifically includes: identifying whether the polarity control signal of the current frame is positive or negative. Figure 4 , Figure 4 FIG. 1 is a flow chart of the first specific embodiment of the frame flip driving method of the present application. Figure 4 As shown, including:

[0050] Step S31: Identify whether the polarity control signal of the current frame is positive or negative.

[0051] If the polarity control signal of the current frame is positive, execute step S32; if the polarity control signal of the current frame is negative, execute step S33.

[0052] Step S32: Determine that the polarity control signal of the next frame is negative polarity, and control the polarity control signal of the next frame to be output according to the second set phase.

[0053] Specifically, this step includes: determining that the polarity control signal of the next frame is negative polarity through a trigger, and sending the determination (i.e., judgment) result to the timing controller, the timing controller receives the signal sent by the trigger, modifies the phase of the polarity control signal of the next frame, and sends a phase-delayed polarity control signal to the data line. That is, the second set phase is delayed from the first set phase. The trigger can be a module inside the timing controller, or a component outside the timing controller, which is not limited here.

[0054] Step S33: Determine that the polarity control signal of the next frame is positive polarity, and control the polarity control signal of the next frame to be output according to the first set phase.

[0055] This step specifically includes: determining that the polarity control signal of the next frame is positive polarity, and sending the initially set polarity control signal to the data line through the timing controller.

[0056] In another specific embodiment, step S11 specifically further includes: identifying whether the polarity control signal of the current frame is the result of a flip from positive polarity to negative polarity, or the result of a flip from negative polarity to positive polarity. Figure 5 , Figure 5 This is a flow chart of the second specific embodiment of the frame flip driving method of the present application. Figure 5 As shown, the frame flip driving method includes:

[0057] Step S41: Identify whether the polarity control signal of the current frame is flipped from positive polarity to negative polarity or from negative polarity to positive polarity.

[0058] If the polarity control signal of the current frame is flipped from positive polarity to negative polarity, that is, the polarity control signal outputted by the current frame is negative polarity, then the polarity control signal of the next frame is positive polarity, and step S42 is executed. If the polarity control signal of the current frame is flipped from negative polarity to positive polarity, it means that the polarity control signal outputted by the current frame should be positive polarity, then the polarity control signal of the next frame is negative polarity, and step S43 is executed.

[0059] Step S42: Determine that the polarity control signal of the next frame is positive.

[0060] Further executing step S12: controlling the polarity control signal of the next frame to be output according to the first set phase.

[0061] Step S43: Determine that the polarity control signal of the next frame is negative.

[0062] Further executing step S13: controlling the polarity control signal of the next frame to be output according to the second set phase. The second set phase is delayed from the first set phase. This step specifically includes: outputting the polarity control signal of the second set phase delayed from the first set phase to the source driving circuit through the timing controller.

[0063] Further, it can be extended to when the frame flip is flipped every two frames, the specific implementation also includes: identifying whether the polarity control signal of the current two frames is positive, or negative, or one positive and one negative, or one negative and one positive. If the polarity control signal of the current two frames is positive, the polarity control signal of the next frame is determined to be negative; if the polarity control signal of the current two frames is negative, the polarity control signal of the next frame is determined to be positive; if the polarity control signal of the current two frames is one positive and one negative, the polarity control signal of the next frame is determined to be negative; if the polarity control signal of the current two frames is one negative and one positive, the polarity control signal of the next frame is determined to be positive. Then, the polarity control signal of the corresponding phase is output through the timing controller. It also includes: identifying whether the polarity control signal of the current two frames has one polarity reversal or two polarity reversals. If one polarity reversal occurs, further determining whether it is a reversal from positive to negative polarity or from negative to positive polarity; if two polarity reversals occur, determining whether the current frame (that is, the most recent polarity) is a reversal from positive to negative polarity or from negative to positive polarity, and then determining the polarity of the polarity control signal of the next frame. For details, please refer to the implementation methods in the first specific embodiment and the second specific embodiment, and no specific limitation is made here.

[0064] It should be noted that, in this embodiment, a polarity control signal with an initial phase may be set in the timing controller first, and then the phase of the polarity control signal may be delayed based on the initial phase to obtain a polarity control signal with a second set phase. Alternatively, a polarity control signal with two phases may be set in the timing controller, and a polarity control signal with one phase may be selectively called according to the positive or negative polarity, which is not limited here.

[0065] The present application also provides a further implementation scheme, which further determines the delay time of the polarity control signal output to each group of data lines according to the output position of the polarity control signal. That is, the delay time of the second set phase. In the present embodiment, the second set phase is mainly regulated. This is because the data signal of negative polarity is more affected by the RC load, and the gate signal delay is more serious the further away from the gate drive circuit. Of course, further, the first set phase can also be regulated, and the regulation method is the same as the negative polarity regulation method. It should be noted that in the present embodiment, the first set phase is a general term for the phase of the polarity control signal of the positive polarity; the second set phase is a general term for the phase of the polarity control signal of the negative polarity. However, the phase of the polarity control signal input to each data line may be different.

[0066] Specifically, the data lines may be grouped according to each data line, or may be grouped according to n adjacent data lines, wherein n≥2, which is not limited here.

[0067] In a specific embodiment, the farther the output position is from the gate driving circuit, the longer the delay time of the polarity control signal of the second set phase output to each group of data lines.

[0068] Among them, the output position of the polarity control signal refers to the distance between each group of data lines corresponding to the polarity control signal and the gate drive circuit. Specifically, each data line may correspond to a polarity control signal, or each group of data lines may correspond to a polarity control signal, which is not limited here. Since the farther the distance from the gate drive circuit, the greater the influence of RC, the slower the gate voltage drops, resulting in a longer negative polarity charging time at a farther distance. Therefore, by further shortening the charging time on each group of data lines, sub-pixels at different positions can have the same charging time, so that the charging time of sub-pixels at different positions will not differ too much.

[0069] In a specific implementation, this step specifically includes determining the distance between the output position of the polarity control signal and the gate drive circuit; and controlling the polarity control signal to be output according to the second set phase corresponding to the output position according to the distance. The second set phase is adjustable, which means that the phase (delay time) of the second set phase is adjustable.

[0070] In a specific application scenario, the display panel may be driven by a double-sided gate drive circuit. The closer the output position of the polarity control signal is to the middle, the more delayed the polarity control signal of the second set phase is. Figure 6 , Figure 6 This is a relationship diagram between the delay time and output position of a polarity control signal of a second set phase provided by the present application. Figure 6 As shown, 1 and 12 are data lines close to the left and right sides, which are closer to the gate drive circuit, and the delay time of the second set phase is smaller. 6-7 are data lines close to the middle column, which are farther from the gate drive circuits on the left and right sides, so the delay time of the second set phase is longer. Among them, from left to right (along the scanning direction from one side of the gate drive circuit to the other side of the gate drive circuit), the delay time of the second set phase increases first and then decreases.

[0071] In another application scenario, the display panel may also be driven by a single-side driven gate driving circuit. In this embodiment, the further away the output position of the polarity control signal is from the gate driving circuit, the more delayed the polarity control signal of the second set phase is, which is not specifically limited here.

[0072] This application also provides a driving circuit. Figure 7 , Figure 7 FIG. 1 is a schematic diagram of the structure of an embodiment of the driving circuit of the present application. Figure 7 As shown, the driving circuit 70 at least includes: a trigger module 71 and a timing controller 72. It can be understood that the trigger module 71 is the trigger mentioned in the above method embodiment. Among them, the trigger module 71 is connected to the timing controller 72 by signal. The trigger module 71 can be a module in the timing controller 72, or it can be an independent device arranged outside the timing controller 72, which is not limited here.

[0073] Specifically, the trigger module 71 is used to determine whether the polarity control signal of the next frame is positive or negative according to the polarity control signal of the current frame.

[0074] The timing controller 72 is also connected to the output end of the trigger module 71, and receives the polarity control signal sent by the trigger module 71, and is used to control the polarity control signal of the next frame to be output according to the first set phase when it is determined that the polarity control signal of the next frame is positive polarity; when it is determined that the polarity control signal of the next frame is negative polarity, control the polarity control signal of the next frame to be output according to the second set phase. In a specific embodiment, the output end of the trigger module 71 outputs a digital signal of 1 or 0, wherein 1 is a polarity control signal of positive polarity and 0 is a polarity control signal of negative polarity. When the timing controller 72 receives 1, it calls the polarity control signal of the first set phase for output, and when it receives 0, it calls the polarity control signal of the second set phase for output.

[0075] For further information, see Figure 8 , Figure 8 FIG. 1 is a schematic diagram of a specific embodiment of the driving circuit of the present application. Figure 8 As shown, the driving circuit 70 further includes a source driver 73 . The source driver 73 is connected to the trigger module 71 , and is used to identify the polarity control signal POL of the current frame, and send the polarity control signal POL of the current frame to the trigger module 71 .

[0076] In this embodiment, specifically, the trigger module 71 includes a first receiving terminal D, a second receiving terminal CK, and an output terminal Q. The first receiving terminal D of the trigger module 71 is connected to the source driver 73, and is used to receive the polarity control signal POL of the current frame sent by the source driver 73. The second receiving terminal CK of the trigger module 71 is connected to the timing controller 72, and is used to receive the reset signal (GDL_RST) of the timing controller 72, and triggers the execution of the judgment step of judging whether the polarity control signal of the next frame is positive or negative according to the received reset signal.

[0077] For details, please refer to the following table.

[0078] Table 1 is the work table of the trigger module of this application

[0079] CK D Q ↓0 X - ↑1 0 0 ↑1 1 1

[0080] Among them, when the reset signal (GDL_RST) is triggered (that is, when the reset signal is at the rising edge and between the rising edge and the falling edge), the second receiving end CK receives a digital signal of 1 (specifically, the digital signal can be sensed and output by the timing controller 72). At this time, the first receiving end D of the trigger module 71 can receive the polarity control signal POL of the current frame fed back by the source driver 73. When the polarity control signal POL of the current frame is positive (or the negative polarity is flipped to the positive polarity), the first receiving end D receives a digital signal of 1; specifically, when the polarity control signal POL of the current frame is negative (or the positive polarity is flipped to the negative polarity), the first receiving end D receives a digital signal of 0. When the digital signals received by the second receiving end CK are all 1, the output end Q outputs a digital signal of 1; when the digital signal received by the first receiving end D is 0, the output end Q outputs a digital signal of 0. When the reset signal (GDL_RST) is not triggered (that is, the reset signal is at the falling edge and between the falling edge and the rising edge), the digital signal received by the second receiving end CK is 0. At this time, the first receiving end D of the trigger module 71 does not work (that is, does not receive the feedback signal of the source driver 73).

[0081] Among them, the reset signal of the timing controller 72 is the starting signal for the completion of scanning of all rows in the display panel. When all rows are scanned, the reset signal is turned on (that is, the rising edge) to reset the signals of all rows. After the reset is completed, the reset signal is turned off (that is, the falling edge) to realize the signal scanning of the next frame. In other words, the trigger module 71 performs the judgment work when the previous frame (or the current frame) is scanned and the next frame has not yet started to scan, that is, the judgment of the polarity control signal is completed in the "black insertion" stage, so that the phase of the polarity control signal can be switched in time. In other embodiments, the phase of the polarity control signal of the next frame can also be switched when the current frame is displayed, which is not limited here.

[0082] Furthermore, the output end of the trigger module 71 is connected to the timing controller 72. When the output end Q of the trigger module 71 outputs a digital signal 1 (positive polarity), the timing controller 72 outputs a polarity control signal according to the initial phase (that is, the phase is not modified). When the timing controller 72 receives the digital signal 0 output by the trigger module 71, the initial phase is delayed to obtain a polarity control signal of a second set phase, and the signal is output according to the second set phase. The timing controller 72 can also be connected to the source driver 73 to directly send the polarity control signal of the first set phase / second set phase to the source driver 73, or it can be sent indirectly through the trigger module 71, which is not limited here.

[0083] For more details, please refer to Fig. 9 , Fig. 9 This is a timing diagram of a specific embodiment of the driving signal of the present application. Fig. 9 As shown, STV is the start scan signal of the display panel, Gate is the scan signal of each row, including N rows, which is only for illustration and is not limited to 5 rows. When all rows are scanned, the reset signal GDL-RST outputs a reset signal. When the trigger or trigger module detects the reset signal GDL-RST, it determines what kind of change to make to the setting phase of the polarity control signal of the next frame according to the polarity of the polarity control signal of the current frame. After receiving the change signal of the trigger, the timing controller changes the polarity control signal POL of the next frame. The change is made in the "black insertion" screen, which is the dotted line stage in the figure.

[0084] The present application also provides a display device. Fig.10 , Fig.10 FIG. 1 is a schematic diagram of the structure of an embodiment of a display device of the present application. Fig.10As shown, the display device includes the driving circuit 70 described in any of the above embodiments. Specifically, the display device includes a display panel 100 and a driving circuit 70, and the driving circuit 70 is used to output a driving signal (the driving signal includes a scanning driving signal and a data driving signal) to the display panel 100. Figure 7 and Figure 8 , I will not go into details here.

[0085] The beneficial effect of the present application is: according to the polarity control signal of the current frame, it is determined whether the polarity control signal of the next frame is positive or negative. When it is determined to be positive, the polarity control signal of the next frame is controlled to be output according to the first set phase, and when it is determined to be negative, the polarity control signal of the next frame is controlled to be output according to the second set phase, so that the phase of the polarity control signal of the positive polarity or the negative polarity (mainly the negative polarity) can be adjusted separately, and then the charging time of the sub-pixel under the positive polarity or the negative polarity (mainly the negative polarity) is adjusted, so that the charging time of the sub-pixel under different polarities is the same, thereby improving the problem of flickering / screen flashing caused by excessive brightness difference under frame flipping.

[0086] The above are merely embodiments of the present application and are not intended to limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A frame flip driving method, characterized in that: The driving method comprises: Determine whether the polarity control signal of the next frame is positive or negative according to the polarity control signal of the current frame through a trigger module in the timing controller; If it is positive polarity, a polarity control signal of a first set phase is outputted through the timing controller; If it is a negative polarity, the timing controller outputs a polarity control signal of a second set phase that is delayed from the first set phase; wherein the time that the second set phase is delayed from the first set phase is adjustable, specifically including: the timing controller determines the time that the second set phase of the polarity control signal output to each group of data lines is delayed from the first set phase according to the distance between the output position of the polarity control signal and the gate drive circuit.

2. The frame flip driving method according to claim 1, characterized in that: The frame flipping is flipping every frame; the step of determining whether the polarity control signal of the next frame is positive or negative according to the polarity control signal of the current frame includes: Identify whether the polarity control signal of the current frame is positive or negative; If the polarity control signal of the current frame is positive, determining that the polarity control signal of the next frame is negative; If the polarity control signal of the current frame is negative polarity, the polarity control signal of the next frame is determined to be positive polarity.

3. The frame flip driving method according to claim 1, characterized in that: The frame flipping is flipping every frame; the step of determining whether the polarity control signal of the next frame is positive or negative according to the polarity control signal of the current frame includes: Identify whether the polarity control signal of the current frame is flipped from positive polarity to negative polarity, or from negative polarity to positive polarity; If the polarity control signal of the current frame is flipped from positive polarity to negative polarity, then determining the polarity control signal of the next frame to be positive polarity; If the polarity control signal of the current frame is flipped from negative polarity to positive polarity, it is determined that the polarity control signal of the next frame is negative polarity.

4. The frame flip driving method according to claim 1, characterized in that: The farther the output position is from the gate driving circuit, the longer the delay time of the polarity control signal of the second set phase output to each group of data lines.

5. A driving circuit, characterized in that: The driving circuit at least comprises: a timing controller and a trigger module located in the timing controller; The trigger module is used to determine whether the polarity control signal of the next frame is positive or negative according to the polarity control signal of the current frame; The timing controller is connected to the trigger module, and is used to output a polarity control signal of a first set phase when it is determined that the polarity control signal of the next frame is positive polarity; when it is determined that the polarity control signal of the next frame is negative polarity, output a polarity control signal of a second set phase delayed from the first set phase; wherein the timing controller determines the time by which the second set phase of the polarity control signal output to each group of data lines is delayed from the first set phase based on the distance between the output position of the polarity control signal and the gate drive circuit.

6. The driving circuit according to claim 5, characterized in that: The driving circuit further includes a source driver, which is connected to the trigger module and is used to identify the polarity control signal of the current frame and send the polarity control signal of the current frame to the trigger module.

7. A display device, characterized in that: It comprises the driving circuit and the display panel according to any one of claims 5 to 6, wherein the driving circuit and the display panel are electrically connected.

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