Display panel, display device and driving method

Abstract

The display panel, the display device and the driving method provided by the embodiments of the present disclosure comprise a gate driving circuit, a conduction control circuit and a plurality of gate lines; the gate driving circuit is coupled with the plurality of gate lines through the conduction control circuit; the gate driving circuit is configured to output a plurality of initial gate scanning signals; wherein the plurality of initial gate scanning signals correspond to the plurality of gate lines one by one; the conduction control circuit is configured to receive the plurality of initial gate scanning signals, input the plurality of initial gate scanning signals to the corresponding gate lines one by one when a first driving mode is adopted, and input the plurality of initial gate scanning signals to the plurality of gate lines after processing the plurality of initial gate scanning signals into a plurality of target gate scanning signals when a second driving mode is adopted; wherein the plurality of target gate scanning signals correspond to the plurality of gate lines one by one.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular, to a display panel, a display device and a driving method. BACKGROUND

[0002] In a display such as a Liquid Crystal Display (LCD) and an Organic Light Emitting Diode (OLED) display, a plurality of pixel units are generally included. Each pixel unit can include a plurality of sub-pixels of different colors. By controlling the brightness of each sub-pixel, a color image is displayed by mixing the required display color. SUMMARY

[0003] The display panel provided by the embodiments of the present disclosure includes a gate driving circuit, a conduction control circuit and a plurality of gate lines; the gate driving circuit is coupled with the plurality of gate lines through the conduction control circuit.

[0004] The gate driving circuit is configured to output a plurality of initial gate scanning signals; wherein the plurality of initial gate scanning signals correspond one-to-one to the plurality of gate lines.

[0005] The conduction control circuit is configured to receive the plurality of initial gate scanning signals, input the plurality of initial gate scanning signals one-to-one to the corresponding gate lines when a first driving mode is adopted, and input the plurality of initial gate scanning signals to the plurality of gate lines after processing the plurality of initial gate scanning signals into a plurality of target gate scanning signals when a second driving mode is adopted; wherein the plurality of target gate scanning signals correspond one-to-one to the plurality of gate lines.

[0006] Wherein the difference between the start time of the effective pulse of the initial gate scanning signal corresponding to each adjacent two gate lines is the same.

[0007] For at least one of the plurality of gate lines, the effective pulse of the target gate scanning signal loaded on the gate line has a first overlap duration with the effective pulse of the target gate scanning signal loaded on the adjacent previous gate line, and the effective pulse of the target gate scanning signal loaded on the gate line has a second overlap duration with the effective pulse of the target gate scanning signal loaded on the adjacent next gate line, and the first overlap duration is different from the second overlap duration.

[0008] In some possible implementations, the conduction control circuit includes a first conduction circuit and a second conduction circuit.

[0009] The gate drive circuit is coupled with the plurality of gate lines through the first conduction circuit, and the first conduction circuit is configured to input the plurality of initial gate scanning signals to the corresponding gate lines one by one in response to a signal of a first control signal end;

[0010] The gate drive circuit is coupled with the plurality of gate lines through the second conduction circuit, and the second conduction circuit is configured to input the plurality of target gate scanning signals to the plurality of gate lines after processing the plurality of initial gate scanning signals in response to a signal of a second control signal end;

[0011] When the first driving mode is adopted, the first control signal end is loaded with a signal of a valid pulse, and the second control signal end is loaded with a signal of an invalid pulse.

[0012] When the second driving mode is adopted, the first control signal end is loaded with a signal of a valid pulse, and the second control signal end is loaded with a signal of an invalid pulse.

[0013] In some possible implementation manners, the gate drive circuit comprises a plurality of shift register units.

[0014] The first conduction circuit comprises a plurality of first conduction sub-circuits; and one of the shift register units is coupled with one of the gate lines through one of the first conduction sub-circuits.

[0015] The first conduction sub-circuit is configured to conduct the coupled shift register unit and the coupled gate line in response to the signal of the first control signal end, so that the corresponding initial gate scanning signal is input to the gate line.

[0016] In some possible implementation manners, the first conduction sub-circuit comprises a first transistor; a gate of the first transistor is coupled with the first control signal end, a first pole of the first transistor is coupled with the shift register unit, and a second pole of the first transistor is coupled with the gate line.

[0017] In some possible implementation manners, the second conduction circuit comprises a plurality of second conduction sub-circuit groups, each of the plurality of second conduction sub-circuit groups comprises N second conduction sub-circuits.

[0018] The gate drive circuit comprises a plurality of shift register units, the plurality of shift register units are divided into a plurality of shift register unit groups, each of the plurality of shift register unit groups comprises N shift register units; wherein the plurality of second conduction sub-circuit groups correspond to the plurality of shift register unit groups one by one, and the shift register unit groups are coupled with N gate lines through the corresponding second conduction sub-circuit groups; N is a positive integer not less than 4;

[0019] At least part of the second conduction sub-circuit in the second conduction sub-circuit group is misalignedly coupled with at least part of the shift register units in the corresponding shift register unit group;

[0020] The second conduction sub-circuit is configured to conduct the coupled shift register unit and the coupled gate line in response to the signal of the second control signal end, so that the initial gate scanning signal is processed into the target gate scanning signal and then input into the gate line.

[0021] In some possible implementation manners, N=4, the first second conduction sub-circuit in the second conduction sub-circuit group is coupled with the first shift register unit in the corresponding shift register unit group, the second second conduction sub-circuit in the second conduction sub-circuit group is coupled with the third shift register unit in the corresponding shift register unit group, the third second conduction sub-circuit in the second conduction sub-circuit group is coupled with the second shift register unit in the corresponding shift register unit group, and the fourth second conduction sub-circuit in the second conduction sub-circuit group is coupled with the fourth shift register unit in the corresponding shift register unit group.

[0022] In some possible implementation manners, the second conduction sub-circuit comprises a second transistor, the gate of the second transistor is coupled with the second control signal end, the first pole of the second transistor is coupled with the shift register unit, and the second pole of the second transistor is coupled with the gate line.

[0023] In some possible implementation manners, the display panel further comprises a first control signal line and a second control signal line, the first control signal line is coupled with the first control signal end, and the second control signal line is coupled with the second control signal end.

[0024] In some possible implementation manners, the display panel further comprises a frame start signal line and a plurality of clock signal lines, the gate drive circuit is coupled with the frame start signal line and the plurality of clock signal lines respectively, and the gate drive circuit is further configured to output the plurality of initial gate scanning signals according to a frame start signal transmitted on the frame start signal line and clock signals transmitted on the plurality of clock signal lines.

[0025] The display device provided by the embodiments of the present disclosure includes the display panel.

[0026] The driving method of the display panel provided by the embodiments of the present disclosure includes: when it is determined to use the first driving mode, the gate driving circuit outputs a plurality of initial gate scanning signals, and the conduction control circuit inputs the plurality of initial gate scanning signals to the corresponding gate lines one by one.

[0027] When it is determined to use the second driving mode, the gate driving circuit outputs a plurality of initial gate scanning signals, and the conduction control circuit inputs the plurality of initial gate scanning signals to the plurality of gate lines after processing the plurality of initial gate scanning signals into a plurality of target gate scanning signals.

[0028] In some possible implementation manners, the conduction control circuit includes a first conduction circuit and a second conduction circuit.

[0029] The inputting the plurality of initial gate scanning signals to the corresponding gate lines one by one includes:

[0030] loading a valid pulse signal on the first control signal end and a non-valid pulse signal on the second control signal end, so that the first conduction circuit inputs the plurality of initial gate scanning signals to the corresponding gate lines one by one in response to the signal of the first control signal end, and the second conduction circuit is not operated.

[0031] In some possible implementation manners, the conduction control circuit includes a first conduction circuit and a second conduction circuit.

[0032] The inputting the plurality of initial gate scanning signals to the plurality of gate lines after processing the plurality of initial gate scanning signals into a plurality of target gate scanning signals includes:

[0033] loading a non-valid pulse signal on the first control signal end and a valid pulse signal on the second control signal end, so that the second conduction circuit is configured to input the plurality of initial gate scanning signals to the plurality of gate lines after processing the plurality of initial gate scanning signals into a plurality of target gate scanning signals in response to the signal of the second control signal end, and the first conduction circuit is not operated. BRIEF DESCRIPTION OF DRAWINGS

[0034] Figure 1 Some structural schematic diagrams of the display device in the embodiments of the present disclosure are shown.

[0035] Figure 2 Some structural schematic diagrams of the display panel in the embodiments of the present disclosure are shown.

[0036] Figure 3 Some signal timing diagrams in the embodiments of the present disclosure are shown.

[0037] Figure 4 Some structural schematic diagrams of a sub-pixel in a display panel in embodiments of the present disclosure;

[0038] Figure 5 Some structural schematic diagrams of a sub-pixel in a display panel in embodiments of the present disclosure;

[0039] Figure 6 Some other signal timing diagrams in embodiments of the present disclosure;

[0040] Figure 7 Some other signal timing diagrams in embodiments of the present disclosure;

[0041] Figure 8 Some other structural schematic diagrams of a sub-pixel in a display panel in embodiments of the present disclosure;

[0042] Figure 9 Some other structural schematic diagrams of a display panel in embodiments of the present disclosure;

[0043] Figure 10 Some other structural schematic diagrams of a display panel in embodiments of the present disclosure;

[0044] Figure 11 A flowchart of a driving method of a display panel in embodiments of the present disclosure;

[0045] Figure 12 Some other signal timing diagrams in embodiments of the present disclosure;

[0046] Figure 13 Some other signal timing diagrams in embodiments of the present disclosure. DETAILED DESCRIPTION

[0047] In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are some but not all of the embodiments of the present disclosure. And the embodiments in the present disclosure and the features in the embodiments can be combined with each other without conflict, if necessary. Based on the described embodiments of the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative work belong to the protection scope of the present disclosure.

[0048] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that an element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0049] It should be noted that the dimensions and shapes of the figures in the accompanying drawings do not reflect actual scale and are intended only to illustrate the content of this disclosure. Furthermore, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.

[0050] In some embodiments of this disclosure, see Figure 1 as well as Figure 2 As shown, the display device may include a display panel 100 and a controller 400. The display panel 100 may include a plurality of pixel units arranged in an array; the controller 400 may include a timing controller 410 and a system controller 420. Exemplarily, each pixel unit includes multiple sub-pixels of different colors. Each sub-pixel may include a transistor and a pixel electrode. For example, a pixel unit may include red, green, and blue sub-pixels, allowing for color mixing to achieve color display. Alternatively, a pixel unit may include red, green, blue, and white sub-pixels, also allowing for color mixing to achieve color display. Of course, in practical applications, the emission color of the sub-pixels in a pixel unit can be designed and determined according to the actual application environment, and is not limited here. The following explanation uses a pixel unit including red, green, and blue sub-pixels as an example.

[0051] In some embodiments of this disclosure, such as Figure 1 and Figure 2As shown, a plurality of gate lines GA (for example, GA1-GA8), a plurality of data lines DA (for example, DA1, DA2, DA3). The gate driving circuit 200 is coupled with the gate lines GA (for example, GA1, GA2, GA3, GA4, GA5, GA6, GA7, GA8) respectively, and the source driving circuit can be coupled with the data lines DA (for example, DA1, DA2, DA3) respectively. Wherein, the controller 400 can input a control signal to the gate driving circuit 200, so that the gate driving circuit 200 inputs a signal to the gate lines GA (for example, GA1, GA2, GA3, GA4, GA5, GA6, GA7, GA8) to drive the gate lines GA (for example, GA1, GA2, GA3, GA4, GA5, GA6, GA7, GA8). And, the controller 400 can obtain the original display data of the to-be-displayed picture in the current display frame, and send the display data required to be displayed to the source driving circuit 110, so that the source driving circuit 110 loads the data voltage to the data lines DA (for example, DA1, DA2, DA3) in the display panel according to the display data, so as to charge the sub-pixels, so that the sub-pixels are charged with the corresponding data voltage, and the picture display function is realized.

[0052] In some embodiments of the present disclosure, the source driving circuit 110 can be provided in a plurality, and different source driving circuits are coupled with different data lines. For example, as shown in FIG. 2, the source driving circuit 110 can be provided in two, wherein one source driving circuit 110 is coupled with half of the data lines, and the other source driving circuit 110 is coupled with the other half of the data lines. Of course, the source driving circuit 110 can also be provided in three, four, or more, which can be designed and determined according to the actual application requirements, which is not limited here. Figure 1

[0053] In addition, it should be noted that the gate driving circuit can be provided as shown in FIG. 1, which is provided on both sides of the display panel, and the gate driving circuits on both sides of the display panel can jointly drive the same gate line, or only the gate driving circuit can be provided on one side of the display panel, or the gate driving circuits on both sides of the display panel can drive different rows of sub-pixels corresponding to the gate lines. In the embodiments of the present disclosure, the number of gate driving circuits provided in the display panel is not limited further here, which can be determined according to the actual application requirements. Figure 1

[0054] In some embodiments of the present disclosure, as shown in FIG. 2, the source driving circuit 110 can be provided in two, wherein one source driving circuit 110 is coupled with half of the data lines, and the other source driving circuit 110 is coupled with the other half of the data lines. Of course, the source driving circuit 110 can also be provided in three, four, or more, which can be designed and determined according to the actual application requirements, which is not limited here. Figure 2 ​​As shown, each sub-pixel row can correspond to two gate lines, so that the pixel array in the present disclosure is arranged as a double-gate structure, so as to reduce half of the data lines (i.e., some adjacent two columns of sub-pixels include data lines, and some adjacent two columns of sub-pixels do not include data lines). For example, the first sub-pixel row corresponds to gate lines GA1, GA2, the second sub-pixel row corresponds to gate lines GA3, GA4, the third sub-pixel row corresponds to gate lines GA5, GA6, and the fourth sub-pixel row corresponds to gate lines GA7, GA8. The first sub-pixel column R11-R41 and the second sub-pixel column G11-G41 include data lines, the second sub-pixel column G11-G41 and the third sub-pixel column B11-B41 do not include data lines, the third sub-pixel column B11-B41 and the fourth sub-pixel column R12-R42 include data lines, the fourth sub-pixel column R12-R42 and the fifth sub-pixel column G12-G42 do not include data lines, and the fifth sub-pixel column G12-G42 and the sixth sub-pixel column B12-B42 include data lines.

[0055] As an example, a plurality of sub-pixels in the display panel can be divided into a plurality of sub-pixel groups, each sub-pixel group can include two adjacent sub-pixels in the same row. And one sub-pixel in the sub-pixel group is coupled to one of the corresponding two gate lines, and the other sub-pixel is coupled to the other of the corresponding two gate lines; both sub-pixels in the sub-pixel group are coupled to the same data line; as an example, as shown, Figure 2 As shown, in the first sub-pixel row, the red sub-pixel R11 and the green sub-pixel G11 can form a sub-pixel group, and the red sub-pixel R11 is coupled to the gate line GA1, and the green sub-pixel G11 is coupled to the gate line GA2; the red sub-pixel R11 is coupled to the data line DA1, and the green sub-pixel G11 is coupled to the data line DA1. The blue sub-pixel B11 and the red sub-pixel R12 can form a sub-pixel group, and the blue sub-pixel B11 is coupled to the gate line GA1, and the red sub-pixel R12 is coupled to the gate line GA2; the blue sub-pixel B11 is coupled to the data line DA2, and the red sub-pixel R12 is coupled to the data line DA2. The green sub-pixel G12 and the blue sub-pixel B12 can form a sub-pixel group, and the green sub-pixel G12 is coupled to the gate line GA1, and the blue sub-pixel B12 is coupled to the gate line GA2; the green sub-pixel G12 is coupled to the data line DA3, and the blue sub-pixel B12 is coupled to the data line DA3.

[0056] In the second sub-pixel row, the red sub-pixel R21 and the green sub-pixel G21 can form a sub-pixel group, and the red sub-pixel R21 is coupled to the gate line GA3 and the green sub-pixel G21 is coupled to the gate line GA4; the red sub-pixel R21 is coupled to the data line DA1 and the green sub-pixel G21 is coupled to the data line DA1. The blue sub-pixel B21 and the red sub-pixel R22 can form a sub-pixel group, and the blue sub-pixel B21 is coupled to the gate line GA3 and the red sub-pixel R22 is coupled to the gate line GA4; the blue sub-pixel B21 is coupled to the data line DA2 and the red sub-pixel R22 is coupled to the data line DA2. The green sub-pixel G22 and the blue sub-pixel B22 can form a sub-pixel group, and the green sub-pixel G22 is coupled to the gate line GA3 and the blue sub-pixel B22 is coupled to the gate line GA4; the green sub-pixel G22 is coupled to the data line DA3 and the blue sub-pixel B22 is coupled to the data line DA3. The remaining sub-pixel rows are divided into sub-pixel groups in the same manner, which will not be described here.

[0057] It should be noted that the display panel in the embodiments of the present disclosure can be a liquid crystal display panel. Exemplarily, the liquid crystal display panel generally includes upper and lower substrates that are bonded together, and liquid crystal molecules encapsulated between the upper and lower substrates. When displaying a picture, there is a voltage difference between the data voltage loaded on the pixel electrode of each sub-pixel and the common electrode voltage on the common electrode, which can form an electric field, so that the liquid crystal molecules are deflected under the action of the electric field. Because different intensity electric fields cause different degrees of deflection of the liquid crystal molecules, the transmittance of the sub-pixels is different, so that the sub-pixels realize different gray scale brightness, and thus realize picture display. Of course, the display panel in the embodiments of the present disclosure can be an OLED display panel, which is not limited here.

[0058] Gray scale generally divides the luminance between the darkest and brightest into several parts in order to control the screen brightness. For example, the displayed image is composed of red, green and blue colors, each of which can show different brightness levels, and different brightness levels of red, green and blue combined together can form different colors. For example, the gray scale bit number of the liquid crystal display panel is 6 bits, and the three colors of red, green and blue have 64 (i.e. 2 6 ) gray scales, and the 64 gray scale values are 0-63 respectively. The gray scale bit number of the liquid crystal display panel is 8 bits, and the three colors of red, green and blue have 256 (i.e. 2 8 ) gray scales, and the 256 gray scale values are 0-255 respectively. The gray scale bit number of the liquid crystal display panel is 10 bits, and the three colors of red, green and blue have 1024 (i.e. 2 10 ) gray scales, and the 1024 gray scale values are 0-1023 respectively. The gray scale bit number of the liquid crystal display panel is 12 bits, and the three colors of red, green and blue have 4096 (i.e. 212 The 4096 gray scale values are 0-4093 respectively.

[0059] For example, the common electrode voltage can be 8.3V. If the data voltage input in the pixel electrode of the sub-pixel SPX is 8.8V-16V, the liquid crystal molecules at the sub-pixel SPX can be positive polarity, and the data voltage of 8.8V-16V is the data voltage corresponding to the positive polarity. If the data voltage input in the pixel electrode of the sub-pixel SPX is 0.6V-7.8V, the liquid crystal molecules at the sub-pixel SPX can be negative polarity, and the data voltage of 0.6V-7.8V is the data voltage corresponding to the negative polarity. For example, taking 0-255 gray scale of 8bit as an example, if the data voltage input in the pixel electrode of the sub-pixel SPX is 16V, the sub-pixel SPX can use the data voltage of positive polarity to realize the brightness of the maximum gray scale value (i.e. 255 gray scale value). If the data voltage input in the pixel electrode of the sub-pixel SPX is 0.6V, the sub-pixel SPX can use the data voltage of negative polarity to realize the brightness of the maximum gray scale value (i.e. 255 gray scale value). It should be noted that there can be a voltage difference between the data voltage of 0 gray scale value and the common electrode voltage. For example, the common electrode voltage is 8.3V, the data voltage corresponding to the positive polarity of 0 gray scale value can be 8.8V, and the data voltage corresponding to the negative polarity of 0 gray scale value can be 7.8V. In this way, the corresponding polarity of the sub-pixel can be controlled to realize the frame inversion mode, column inversion mode, row inversion mode, dot inversion mode and the like. Of course, the data voltage of 0 gray scale value and the common electrode voltage can also be the same. In actual application, it can be determined according to the actual application, which is not limited here.

[0060] In some examples, the system controller 420 can acquire original display data of a to-be-displayed picture in a current display frame (the original display data includes a digital signal form of a data voltage carrying a corresponding gray scale value corresponding to each sub-pixel), and send the original display data (i.e., the original display data includes a digital signal form of a data voltage carrying a corresponding gray scale value corresponding to each sub-pixel) to the timing controller 410 when it is determined to use the first driving mode. The timing controller 410 inputs a corresponding signal to the gate driving circuit in the display panel through the clock signal line, so that the gate line is loaded with an initial gate scanning signal, and the gate line in the display panel can be driven row by row to open the transistor in the sub-pixel row by row. Moreover, the timing controller 410 sends the original display data to the source driving circuit 110, so that the source driving circuit 110 loads a data voltage to the data line in the display panel according to the received original display data, thereby charging the sub-pixel, making each sub-pixel charge the corresponding data voltage, and realizing the picture display function.

[0061] Exemplarily, as shown in Figure 3 , ga1_1-ga8_1 respectively represent initial gate scanning signals loaded by the gate lines GA1-GA8. Among them, the difference between the start time of the effective pulse of the initial gate scanning signal corresponding to each adjacent two gate lines is the same. For example, the difference between the start time of the effective pulse (such as the pulse corresponding to the high level) of the initial gate scanning signal ga1_1 and the start time of the effective pulse (such as the pulse corresponding to the high level) of the initial gate scanning signal ga12_1 is t01, and the difference between the start time of the effective pulse (such as the pulse corresponding to the high level) of the initial gate scanning signal ga2_1 and the start time of the effective pulse (such as the pulse corresponding to the high level) of the initial gate scanning signal ga13_1 is also t01. The rest is the same, which can be deduced in the same way, and is not described here.

[0062] Exemplarily, when the first driving mode is used, the signal timing diagram of the initial gate scanning signals ga1_1-ga8_1 loaded by the gate lines GA1-GA8 is as shown in Figure 3 . Figure 2 , Figure 3 and Figure 4 , taking the sub-pixel coupled with the data line DA2 as an example, when the first driving mode is used, the process of the display panel displaying a picture can be described as follows. Taking the effective pulse of the initial gate scanning signal as high level as an example.

[0063] In the T11 stage, the signal ga1_1 transmitted on the gate line GA1 is high level, and the blue sub-pixel B11 inputs the data voltage D1. Meanwhile, the signal ga2_1 transmitted on the gate line GA2 is high level, and the red sub-pixel R12 inputs the data voltage D1 to perform pre-charge. In addition, the signal ga3_1 transmitted on the gate line GA3 is high level, and the blue sub-pixel B21 inputs the data voltage D1 to perform pre-charge.

[0064] In the T12 stage, the signal ga2_1 transmitted on the gate line GA2 is high level, and the red sub-pixel R12 inputs the data voltage D2. Meanwhile, the signal ga3_1 transmitted on the gate line GA3 is high level, and the blue sub-pixel B21 inputs the data voltage D2 to perform pre-charge. In addition, the signal ga4_1 transmitted on the gate line GA4 is high level, and the red sub-pixel R22 inputs the data voltage D2 to perform pre-charge.

[0065] In the T13 stage, the signal ga3_1 transmitted on the gate line GA3 is high level, and the blue sub-pixel B21 inputs the data voltage D3. Meanwhile, the signal ga4_1 transmitted on the gate line GA4 is high level, and the red sub-pixel R22 inputs the data voltage D3 to perform pre-charge. In addition, the signal ga5_1 transmitted on the gate line GA5 is high level, and the blue sub-pixel B31 inputs the data voltage D3 to perform pre-charge.

[0066] In the T14 stage, the signal ga4_1 transmitted on the gate line GA4 is high level, and the red sub-pixel R22 inputs the data voltage D4. Meanwhile, the signal ga5_1 transmitted on the gate line GA5 is high level, and the blue sub-pixel B31 inputs the data voltage D4 to perform pre-charge. In addition, the signal ga6_1 transmitted on the gate line GA6 is high level, and the red sub-pixel R32 inputs the data voltage D4 to perform pre-charge.

[0067] In the T15 stage, the signal ga5_1 transmitted on the gate line GA5 is high level, and the blue sub-pixel B31 inputs the data voltage D5. Meanwhile, the signal ga6_1 transmitted on the gate line GA6 is high level, and the red sub-pixel R32 inputs the data voltage D5 to perform pre-charge. In addition, the signal ga7_1 transmitted on the gate line GA7 is high level, and the blue sub-pixel B41 inputs the data voltage D5 to perform pre-charge.

[0068] The rest is the same, and the same can be applied in sequence, which is not described here.

[0069] In some examples, the original display data of the current display frame can be acquired, and when it is determined to use the second driving mode, data voltages corresponding to the original display data of the odd rows of sub-pixels can be loaded to the data lines in the display panel in the odd display frames, so as to charge the data voltages to each sub-pixel in the display panel. And the sub-pixels in the same column in adjacent two rows input the same data voltage. For example, when a monochrome picture is displayed, for example, a green picture is displayed, the data voltage input to the sub-pixels in the odd rows in the odd frames is the data voltage corresponding to 0 gray scale, and the data voltage input to the sub-pixels in the even rows in the even frames is the data voltage corresponding to 255 gray scale. Taking the sub-pixels coupled to the data line DA1 as an example, it can be seen from FIG. 6 that the data voltage D1 represents the data voltage corresponding to the red sub-pixel R21, the data voltage D3 represents the data voltage corresponding to the green sub-pixel G21, the data voltage D5 represents the data voltage corresponding to the blue sub-pixel B21, the data voltage D2 represents the data voltage corresponding to the green sub-pixel G21, and the data voltage D4 represents the data voltage corresponding to the green sub-pixel G41. When it is determined to use the second driving mode, if the initial gate scanning signals ga1_1-ga8_1 are loaded to the gate lines GA1-GA8 in the display panel, the red sub-pixel R21 and the green sub-pixel G21 both input the data voltage D3. The red sub-pixel R41 and the green sub-pixel G41 both input the data voltage D4. Therefore, it can be seen from FIG. 7 that if the initial gate scanning signals are used to drive the gate lines row by row, the data voltages charged in the sub-pixels will be dislocated, which will cause color mixing of the picture. Figure 5 With reference to FIG. 7, Figure 6 , the data voltage D2 represents the data voltage corresponding to the green sub-pixel G21, and the data voltage D4 represents the data voltage corresponding to the green sub-pixel G41. When it is determined to use the second driving mode, if the initial gate scanning signals ga1_1-ga8_1 are loaded to the gate lines GA1-GA8 in the display panel, the red sub-pixel R21 and the green sub-pixel G21 both input the data voltage D3. The red sub-pixel R41 and the green sub-pixel G41 both input the data voltage D4. Therefore, it can be seen from FIG. 7 that if the initial gate scanning signals are used to drive the gate lines row by row, the data voltages charged in the sub-pixels will be dislocated, which will cause color mixing of the picture. Figure 5 With reference to FIG. 7, Figure 6 , the data voltage D2 represents the data voltage corresponding to the green sub-pixel G21, and the data voltage D4 represents the data voltage corresponding to the green sub-pixel G41. When it is determined to use the second driving mode, if the initial gate scanning signals ga1_1-ga8_1 are loaded to the gate lines GA1-GA8 in the display panel, the red sub-pixel R21 and the green sub-pixel G21 both input the data voltage D3. The red sub-pixel R41 and the green sub-pixel G41 both input the data voltage D4. Therefore, it can be seen from FIG. 7 that if the initial gate scanning signals are used to drive the gate lines row by row, the data voltages charged in the sub-pixels will be dislocated, which will cause color mixing of the picture.

[0070] In order to solve the problem of dislocation of the data voltages, when it is determined to use the second driving mode, data voltages corresponding to the original display data of the odd rows of sub-pixels can be loaded to the data lines in the display panel in the odd display frames, so as to charge the data voltages to each sub-pixel in the display panel. And the target gate scanning signals are loaded to the gate lines. And data voltages corresponding to the original display data of the even rows of sub-pixels can be loaded to the data lines in the display panel in the even display frames, so as to charge the data voltages to each sub-pixel in the display panel. And the target gate scanning signals are loaded to the gate lines.

[0071] Exemplarily, as Figure 7As shown, ga1_2-ga8_2 represent target gate scanning signals loaded on the gate lines GA1-GA8, respectively. For at least one of the gate lines, the effective pulse of the target gate scanning signal loaded on the gate line has a first overlap duration with the effective pulse of the target gate scanning signal loaded on the adjacent previous gate line, and the effective pulse of the target gate scanning signal loaded on the gate line has a second overlap duration with the effective pulse of the target gate scanning signal loaded on the adjacent next gate line, and the first overlap duration is different from the second overlap duration. For example, the effective pulse (e.g., the pulse corresponding to the high level) of the target gate scanning signal ga1_2 and the target gate scanning signal ga2_2 has a first overlap duration t11, the effective pulse (e.g., the pulse corresponding to the high level) of the target gate scanning signal ga2_2 and the target gate scanning signal ga8_2 has a second overlap duration t21, and t11 is different from t21. The rest is similar, which will not be repeated here.

[0072] For example, when displaying a monochrome image, for example, a green image, taking the sub-pixel coupled to the data line DA1 as an example, in combination with Figure 7 and Figure 8 In the first odd frame, the data voltage input to the odd row sub-pixel is the data voltage corresponding to 0 gray scale, and in the second even frame, the data voltage input to the even row sub-pixel is the data voltage corresponding to 255 gray scale. The data voltage D2 represents the data voltage corresponding to the green sub-pixel G21, and the data voltage D4 represents the data voltage corresponding to the green sub-pixel G41. When it is determined to use the second driving mode, if the target gate scanning signals ga1_2-ga8_2 are loaded on the gate lines GA1-GA8 in the display panel, the green sub-pixel G11 and the green sub-pixel G21 both input the data voltage D2. The green sub-pixel G31 and the green sub-pixel G41 both input the data voltage D4. Therefore, in combination with Figure 7 and Figure 8 As shown, if the target gate scanning signal is used to drive the gate line row by row, the color mixing problem can be improved.

[0073] Based on this, the display panel provided by the embodiments of the present disclosure can be used to select whether to input the initial gate driving signal output by the gate driving circuit to the gate line or to input the target gate driving signal converted from the initial gate driving signal output by the gate driving circuit to the gate line through the control of the conduction control circuit when the first driving module or the second driving module is used, so that the display panel can be normally displayed in different driving modes, and the compatibility of the double-gate structure and the two driving modes is realized.

[0074] The display panel 100 provided by some embodiments of the present disclosure is as follows Figure 9As shown, it includes: a gate drive circuit 200, a turn-on control circuit 300, and multiple gate lines (e.g., Figure 9 (GA1 to GA8 in the example); the gate drive circuit 200 connects to multiple gate lines (e.g., GA1 to GA8) via the turn-on control circuit 300. Figure 9 GA1 to GA8) are coupled together;

[0075] The gate drive circuit 200 is configured to output multiple initial gate scan signals (such as...) Figure 3 (ga1_1~ga8_1 in the text); where multiple initial gate scan signals (such as...) Figure 3 (ga1_1~ga8_1) and multiple gate lines (e.g.) Figure 9 The numbers GA1 to GA8 correspond one-to-one.

[0076] The turn-on control circuit 300 is configured to receive multiple initial gate scan signals (such as...) Figure 3 In the first driving mode, multiple initial gate scan signals (such as ga1_1~ga8_1) are used to scan the gates. Figure 3 The ga1_1 to ga8_1 lines are input one by one to the corresponding gate lines (e.g., ga1_1 to ga8_1). Figure 9 In the second driving mode, GA1 to GA8) will have multiple initial gate scan signals (such as...) Figure 3 The signals ga1_1 to ga8_1 in the model are processed into multiple target gate scan signals (e.g., ... Figure 7 After inputting ga1_2~ga8_2) into multiple gate lines (e.g. Figure 9 GA1 to GA8); among them, multiple target gate scan signals (such as...) Figure 7 (ga1_2~ga8_2) and multiple gate lines (e.g. Figure 9 The numbers GA1 to GA8 correspond one-to-one.

[0077] In some embodiments of this disclosure, such as Figure 10 As shown, the conduction control circuit 300 includes a first conduction circuit 310 and a second conduction circuit 320. The gate drive circuit 200 is coupled to multiple gate lines GA1 to GA8 via the first conduction circuit 310. The first conduction circuit 310 is configured to input multiple initial gate scan signals to the corresponding gate lines GA1 to GA8 one by one in response to a signal from the first control signal terminal CS1. The gate drive circuit 200 is also coupled to the multiple gate lines GA1 to GA8 via the second conduction circuit 320. The second conduction circuit 320 is configured to process the multiple initial gate scan signals into multiple target gate scan signals and input them to the multiple gate lines GA1 to GA8 in response to a signal from the second control signal terminal CS2.

[0078] In the first driving mode, the first control signal terminal CS1 is loaded with a signal of an effective pulse, and the second control signal terminal CS2 is loaded with a signal of an ineffective pulse; in the second driving mode, the first control signal terminal CS1 is loaded with a signal of an effective pulse, and the second control signal terminal CS2 is loaded with a signal of an ineffective pulse.

[0079] Exemplarily, the effective pulse loaded by the first control signal terminal CS1 can be a pulse corresponding to a high level, and the ineffective pulse can be a pulse corresponding to a low level. Also, the effective pulse loaded by the second control signal terminal CS2 can be a pulse corresponding to a high level, and the ineffective pulse can be a pulse corresponding to a low level. Alternatively, the effective pulse loaded by the first control signal terminal CS1 can be a pulse corresponding to a low level, and the ineffective pulse can be a pulse corresponding to a high level. Also, the effective pulse loaded by the second control signal terminal CS2 can be a pulse corresponding to a low level, and the ineffective pulse can be a pulse corresponding to a high level.

[0080] In some embodiments of the present disclosure, as shown in Figure 10 The gate drive circuit 200 includes a plurality of shift register units (for example, SR1-SR8 in Figure 10 The first conduction circuit 310 includes a plurality of first conduction sub-circuits (for example, 310_1a-310_8a in Figure 10 One shift register unit is coupled with one gate line through one first conduction sub-circuit; the first conduction sub-circuit is configured to conduct the coupled shift register unit and the coupled gate line in response to the signal of the first control signal terminal, so as to input the corresponding initial gate scan signal to the gate line.

[0081] Exemplarily, as shown in Figure 10As shown, the shift register unit SR1 is coupled with the gate line GA1 through the first conduction sub-circuit 310_1a; the first conduction sub-circuit 310_1a is configured to conduct the output end of the coupled shift register unit SR1 with the coupled gate line GA1 in response to the signal of the first control signal end CS1, so that the corresponding initial gate scanning signal ga1_1 is input to the gate line GA1. The shift register unit SR2 is coupled with the gate line GA2 through the first conduction sub-circuit 310_2a; the first conduction sub-circuit 310_2a is configured to conduct the coupled shift register unit SR1 with the coupled gate line GA2 in response to the signal of the first control signal end CS1, so that the corresponding initial gate scanning signal ga2_1 is input to the gate line GA2. The shift register unit SR3 is coupled with the gate line GA3 through the first conduction sub-circuit 310_3a; the first conduction sub-circuit 310_3a is configured to conduct the coupled shift register unit SR3 with the coupled gate line GA3 in response to the signal of the first control signal end CS1, so that the corresponding initial gate scanning signal ga3_1 is input to the gate line GA3. The shift register unit SR7 is coupled with the gate line GA7 through the first conduction sub-circuit 310_7a; the first conduction sub-circuit 310_7a is configured to conduct the coupled shift register unit SR7 with the coupled gate line GA7 in response to the signal of the first control signal end CS1, so that the corresponding initial gate scanning signal ga7_1 is input to the gate line GA7. The shift register unit SR8 is coupled with the gate line GA8 through the first conduction sub-circuit 310_8a; the first conduction sub-circuit 310_8a is configured to conduct the coupled shift register unit SR8 with the coupled gate line GA8 in response to the signal of the first control signal end CS1, so that the corresponding initial gate scanning signal ga8_1 is input to the gate line GA8.

[0082] In some embodiments of the present disclosure, the first conduction sub-circuit comprises: a first transistor; a gate of the first transistor is coupled with the first control signal end, a first pole of the first transistor is coupled with the output end of the shift register unit, and a second pole of the first transistor is coupled with the gate line. For example, as shown in FIG. 3, the first conduction sub-circuit 310_1a comprises a first transistor T310_1a; a gate of the first transistor T310_1a is coupled with the first control signal end CS1, a first pole of the first transistor T310_1a is coupled with the output end of the shift register unit SR1, and a second pole of the first transistor T310_1a is coupled with the gate line GA1. Figure 10As shown, the first conduction sub-circuit 310_1a includes: a first transistor T1_a; a gate of the first transistor T1_a is coupled with the first control signal end CS1, a first electrode of the first transistor T1_a is coupled with an output end of the shift register unit SR1, and a second electrode of the first transistor T1_a is coupled with the gate line GA1. The first conduction sub-circuit 310_2a includes: a first transistor T2_a; a gate of the first transistor T2_a is coupled with the first control signal end CS1, a first electrode of the first transistor T2_a is coupled with an output end of the shift register unit SR2, and a second electrode of the first transistor T2_a is coupled with the gate line GA2. The first conduction sub-circuit 310_3a includes: a first transistor T3_a; a gate of the first transistor T3_a is coupled with the first control signal end CS1, a first electrode of the first transistor T3_a is coupled with an output end of the shift register unit SR3, and a second electrode of the first transistor T3_a is coupled with the gate line GA3. The first conduction sub-circuit 310_7a includes: a first transistor T7_a; a gate of the first transistor T7_a is coupled with the first control signal end CS1, a first electrode of the first transistor T7_a is coupled with an output end of the shift register unit SR7, and a second electrode of the first transistor T7_a is coupled with the gate line GA7. The first conduction sub-circuit 310_8a includes: a first transistor T8_a; a gate of the first transistor T8_a is coupled with the first control signal end CS1, a first electrode of the first transistor T8_a is coupled with an output end of the shift register unit SR8, and a second electrode of the first transistor T8_a is coupled with the gate line GA8.

[0083] For example, the first transistors T1_a-T8_a are turned on under the control of the effective pulse of the first control signal of the first control signal end CS1, and are turned off under the control of the ineffective pulse of the first control signal. Alternatively, the first transistors T1_a-T8_a can be N-type transistors, and the effective pulse of the first control signal can be high level, and the ineffective pulse of the first control signal can be low level. Alternatively, the first transistors T1_a-T8_a can also be P-type transistors, and the effective pulse of the first control signal can be low level, and the ineffective pulse of the first control signal can be high level.

[0084] In some embodiments of the present disclosure, as shown in Figure 10 The second conduction circuit 320 includes: a plurality of second conduction sub-circuit groups (for example, 3201, 3202 in Figure 10 each of the plurality of second conduction sub-circuit groups includes: N second conduction sub-circuits; for example, the second conduction sub-circuit group 3201 includes: 4 second conduction sub-circuits 320_1b-320_4b; and the second conduction sub-circuit group 3202 includes: 4 second conduction sub-circuits 320_5b-320_8b.

[0085] The gate drive circuit 200 includes a plurality of shift register units (for example, SR1-SR8 in FIG. 21), which are divided into a plurality of shift register unit groups (for example, 2101, 2102 in FIG. 21), each of which includes N shift register units; for example, the shift register unit group 2101 includes 4 shift register units SR1-SR4, and the shift register unit group 2102 includes 4 shift register units SR5-SR8; wherein the plurality of second conduction sub-circuit groups correspond one-to-one to the plurality of shift register unit groups, and the shift register unit groups are coupled to the N gate lines through the corresponding second conduction sub-circuit groups; N is a positive integer not less than 4. Figure 10 Figure 10 The gate drive circuit 200 includes a plurality of shift register units (for example, SR1-SR8 in FIG. 21), which are divided into a plurality of shift register unit groups (for example, 2101, 2102 in FIG. 21), each of which includes N shift register units; for example, the shift register unit group 2101 includes 4 shift register units SR1-SR4, and the shift register unit group 2102 includes 4 shift register units SR5-SR8; wherein the plurality of second conduction sub-circuit groups correspond one-to-one to the plurality of shift register unit groups, and the shift register unit groups are coupled to the N gate lines through the corresponding second conduction sub-circuit groups; N is a positive integer not less than 4.

[0086] For example, as shown in FIG. 22, the second conduction sub-circuit group 3201 corresponds to the shift register unit group 2101, and the shift register unit group 2101 is coupled to the 4 gate lines GA1-GA4 through the corresponding second conduction sub-circuit group 3201; the second conduction sub-circuit group 3202 corresponds to the shift register unit group 2102, and the shift register unit group 2102 is coupled to the 4 gate lines GA5-GA8 through the corresponding second conduction sub-circuit group 3202. Figure 10

[0087] And at least part of the second conduction sub-circuits in the second conduction sub-circuit group are misalignedly coupled to at least part of the shift register units in the corresponding shift register unit group. For example, as shown in FIG. 22, taking the second conduction sub-circuit group 3201 as an example, the second conduction sub-circuit 320_1b is coupled to the output end of the shift register unit SR1 in the corresponding shift register unit group 2101, the second conduction sub-circuit 320_2b is coupled to the output end of the shift register unit SR3 in the corresponding shift register unit group 2101, the second conduction sub-circuit 320_3b in the second conduction sub-circuit group 3201 is coupled to the output end of the shift register unit SR2 in the corresponding shift register unit group 2101, and the second conduction sub-circuit 320_4b is coupled to the output end of the shift register unit SR4 in the corresponding shift register unit group 2101. Figure 10 The second conduction sub-circuit is configured to conduct the coupled shift register unit and the coupled gate line in response to the signal of the second control signal end, so as to input the target gate scanning signal after processing the initial gate scanning signal. For example, as shown in FIG. 22, the second conduction sub-circuit 320_1b is coupled to the output end of the shift register unit SR1 in the corresponding shift register unit group 2101, the second conduction sub-circuit 320_2b is coupled to the output end of the shift register unit SR3 in the corresponding shift register unit group 2101, the second conduction sub-circuit 320_3b in the second conduction sub-circuit group 3201 is coupled to the output end of the shift register unit SR2 in the corresponding shift register unit group 2101, and the second conduction sub-circuit 320_4b is coupled to the output end of the shift register unit SR4 in the corresponding shift register unit group 2101.

[0088] Figure 10 ​​​As shown, the second conducting sub-circuit 320_1b is configured to conduct the output end of the coupled shift register unit SR1 to the coupled gate line GA1 in response to the signal of the second control signal end CS2, so as to input the gate line GA1 with the initial gate scanning signal processed as the target gate scanning signal. The second conducting sub-circuit 320_2b is configured to conduct the output end of the coupled shift register unit SR3 to the coupled gate line GA2 in response to the signal of the second control signal end CS2, so as to input the gate line GA2 with the initial gate scanning signal processed as the target gate scanning signal. The second conducting sub-circuit 320_3b is configured to conduct the output end of the coupled shift register unit SR2 to the coupled gate line GA3 in response to the signal of the second control signal end CS2, so as to input the gate line GA3 with the initial gate scanning signal processed as the target gate scanning signal. The second conducting sub-circuit 320_4b is configured to conduct the output end of the coupled shift register unit SR4 to the coupled gate line GA4 in response to the signal of the second control signal end CS2, so as to input the gate line GA4 with the initial gate scanning signal processed as the target gate scanning signal. The second conducting sub-circuit 320_5b is configured to conduct the output end of the coupled shift register unit SR5 to the coupled gate line GA5 in response to the signal of the second control signal end CS2, so as to input the gate line GA5 with the initial gate scanning signal processed as the target gate scanning signal. The second conducting sub-circuit 320_6b is configured to conduct the output end of the coupled shift register unit SR7 to the coupled gate line GA6 in response to the signal of the second control signal end CS2, so as to input the gate line GA6 with the initial gate scanning signal processed as the target gate scanning signal. The second conducting sub-circuit 320_7b is configured to conduct the output end of the coupled shift register unit SR6 to the coupled gate line GA7 in response to the signal of the second control signal end CS2, so as to input the gate line GA7 with the initial gate scanning signal processed as the target gate scanning signal. The second conducting sub-circuit 320_8b is configured to conduct the output end of the coupled shift register unit SR8 to the coupled gate line GA8 in response to the signal of the second control signal end CS2, so as to input the gate line GA8 with the initial gate scanning signal processed as the target gate scanning signal.

[0089] In some embodiments of the present disclosure, as Figure 10As shown, N=4, the first second-conducting sub-circuit 320_1b in the second-conducting sub-circuit group 3201 is coupled to the output terminal of the first shift register unit SR1 in the corresponding shift register unit group 2101, the second second-conducting sub-circuit 320_2b in the second-conducting sub-circuit group 3201 is coupled to the output terminal of the third shift register unit SR3 in the corresponding shift register unit group 2101, the third second-conducting sub-circuit 320_3b in the second-conducting sub-circuit group 3201 is coupled to the output terminal of the second shift register unit SR2 in the corresponding shift register unit group 2101, and the fourth second-conducting sub-circuit 320_4b in the second-conducting sub-circuit group 3201 is coupled to the output terminal of the fourth shift register unit SR4 in the corresponding shift register unit group 2101. The first second-conducting sub-circuit 320_5b in the second-conducting sub-circuit group 3202 is coupled to the output terminal of the first shift register unit SR5 in the corresponding shift register unit group 2102, the second second-conducting sub-circuit 320_6b in the second-conducting sub-circuit group 3202 is coupled to the output terminal of the third shift register unit SR7 in the corresponding shift register unit group 2102, the third second-conducting sub-circuit 320_7b in the second-conducting sub-circuit group 3202 is coupled to the output terminal of the second shift register unit SR6 in the corresponding shift register unit group 2102, and the fourth second-conducting sub-circuit 320_8b in the second-conducting sub-circuit group 3202 is coupled to the output terminal of the fourth shift register unit SR8 in the corresponding shift register unit group 2102.

[0090] In some embodiments of the present disclosure, the second-conducting sub-circuit comprises: a second transistor; a gate of the second transistor is coupled to a second control signal terminal, a first pole of the second transistor is coupled to a shift register unit, and a second pole of the second transistor is coupled to a gate line. For example, as shown in FIG. 3, the second-conducting sub-circuit 320_1b in the second-conducting sub-circuit group 3201 comprises a second transistor T320_1b, a gate of the second transistor T320_1b is coupled to the second control signal terminal 230, a first pole of the second transistor T320_1b is coupled to the first shift register unit SR1 in the corresponding shift register unit group 2101, and a second pole of the second transistor T320_1b is coupled to the gate line 220. Figure 10As shown, the second conduction sub-circuit 320_1b includes: a second transistor T1_b; a gate of the second transistor T1_b is coupled with the second control signal terminal CS2, a first pole of the second transistor T1_b is coupled with the output terminal of the shift register unit SR1, and a second pole of the second transistor T1_b is coupled with the gate line GA1. The second conduction sub-circuit 320_2b includes: a second transistor T2_b; a gate of the second transistor T2_b is coupled with the second control signal terminal CS2, a first pole of the second transistor T2_b is coupled with the output terminal of the shift register unit SR3, and a second pole of the second transistor T2_b is coupled with the gate line GA2. The second conduction sub-circuit 320_3b includes: a second transistor T3_b; a gate of the second transistor T3_b is coupled with the second control signal terminal CS2, a first pole of the second transistor T3_b is coupled with the output terminal of the shift register unit SR2, and a second pole of the second transistor T3_b is coupled with the gate line GA3. The second conduction sub-circuit 320_4b includes: a second transistor T4_b; a gate of the second transistor T4_b is coupled with the second control signal terminal CS2, a first pole of the second transistor T4_b is coupled with the output terminal of the shift register unit SR4, and a second pole of the second transistor T4_b is coupled with the gate line GA4. The second conduction sub-circuit 320_5b includes: a second transistor T5_b; a gate of the second transistor T5_b is coupled with the second control signal terminal CS2, a first pole of the second transistor T5_b is coupled with the output terminal of the shift register unit SR5, and a second pole of the second transistor T5_b is coupled with the gate line GA5. The second conduction sub-circuit 320_6b includes: a second transistor T6_b; a gate of the second transistor T6_b is coupled with the second control signal terminal CS2, a first pole of the second transistor T6_b is coupled with the output terminal of the shift register unit SR7, and a second pole of the second transistor T6_b is coupled with the gate line GA6. The second conduction sub-circuit 320_7b includes: a second transistor T7_b; a gate of the second transistor T7_b is coupled with the second control signal terminal CS2, a first pole of the second transistor T7_b is coupled with the output terminal of the shift register unit SR6, and a second pole of the second transistor T7_b is coupled with the gate line GA7. The second conduction sub-circuit 320_8b includes: a second transistor T8_b; a gate of the second transistor T8_b is coupled with the second control signal terminal CS2, a first pole of the second transistor T8_b is coupled with the output terminal of the shift register unit SR8, and a second pole of the second transistor T8_b is coupled with the gate line GA8.

[0091] Exemplarily, the second transistors T1_b~T8_b are turned on under the control of the active pulse of the second control signal at the second control signal end CS2, and are turned off under the control of the inactive pulse of the second control signal. Alternatively, the second transistors T1_b~T8_b can be set as N-type transistors, and the active pulse of the second control signal can be high level and the inactive pulse of the second control signal can be low level. Alternatively, the second transistors T1_b~T8_b can also be set as P-type transistors, and the active pulse of the second control signal can be low level and the inactive pulse of the second control signal can be high level.

[0092] In some embodiments of the present disclosure, as shown in Figure 10 The display panel 100 further includes a first control signal line S1 and a second control signal line S2. The first control signal line S1 is coupled with the first control signal end CS1. The second control signal line S2 is coupled with the second control signal end CS2.

[0093] In some embodiments of the present disclosure, as shown in Figure 10 The display panel 100 further includes a frame start signal line STV and a plurality of clock signal lines CLK1~CLK6. The gate drive circuit 200 is coupled with the frame start signal line STV and the plurality of clock signal lines CLK1~CLK6, respectively. The gate drive circuit 200 is further configured to output a plurality of initial gate scanning signals according to the frame start signal transmitted by the frame start signal line STV and the clock signals transmitted by the plurality of clock signal lines CLK1~CLK6. Exemplarily, if the display panel adopts a single gate drive circuit design, the gate drive circuit can be coupled with 6 clock signal lines CLK1~CLK6. If the display panel adopts a double gate drive circuit design, each gate drive circuit can be coupled with 6 clock signal lines CLK1~CLK6. It should be noted that Figure 11 Only 6 clock signal lines are taken as an example for description. In actual application, the specific number of clock signal lines can be determined according to the actual application requirements, which is not limited herein, for example, it can also be other number of clock signal lines which is an integer multiple of 2, such as 2, 4, 8, 10, etc.

[0094] The present disclosure further provides some display panel driving methods, as shown in Figure 10 The display panel driving method includes the following steps:

[0095] S100, when it is determined to adopt the first driving mode, the gate drive circuit outputs a plurality of initial gate scanning signals, and the control circuit inputs the plurality of initial gate scanning signals to the corresponding gate lines one by one;

[0096] S200. When the second driving mode is determined, the gate driving circuit outputs multiple initial gate scan signals, and the turn-on control circuit processes the multiple initial gate scan signals into multiple target gate scan signals and inputs them to multiple gate lines.

[0097] In some embodiments of this disclosure, such as Figure 10 As shown, the conduction control circuit 300 includes: a first conduction circuit 310 and a second conduction circuit 320; inputting multiple initial gate scan signals to the corresponding gate lines one by one, including: loading a valid pulse signal to the first control signal terminal CS1 and loading an invalid pulse signal to the second control signal terminal CS2, so that the first conduction circuit 310 responds to the signal of the first control signal terminal CS1 to input multiple initial gate scan signals to the corresponding gate lines one by one, and making the second conduction circuit 320 not work.

[0098] In some embodiments of this disclosure, in the first driving mode, Figure 12 The signal timing diagram corresponding to the gate drive circuit shown is as follows: Figure 12 As shown. For example, in combination Figure 10 As shown, stv represents the frame start signal on the frame start signal line STV, clk1 represents the clock signal input to the clock signal line CLK1, clk2 represents the clock signal input to the clock signal line CLK2, clk3 represents the clock signal input to the clock signal line CLK3, clk4 represents the clock signal input to the clock signal line CLK4, clk5 represents the clock signal input to the clock signal line CLK5, and clk6 represents the clock signal input to the clock signal line CLK6.

[0099] And, the signal ga1_1 represents the initial gate scanning signal output by the conduction control circuit 300 to the gate line GA1, the signal ga2_1 represents the initial gate scanning signal output by the conduction control circuit 300 to the gate line GA2, the signal ga3_1 represents the initial gate scanning signal output by the conduction control circuit 300 to the gate line GA3, the signal ga4_1 represents the initial gate scanning signal output by the conduction control circuit 300 to the gate line GA4, the signal ga5_1 represents the initial gate scanning signal output by the conduction control circuit 300 to the gate line GA5, the signal ga6_1 represents the initial gate scanning signal output by the conduction control circuit 300 to the gate line GA6, the signal ga7_1 represents the initial gate scanning signal output by the conduction control circuit 300 to the gate line GA7, and the signal ga8_1 represents the initial gate scanning signal output by the conduction control circuit 300 to the gate line GA8. And, taking the pulse corresponding to the high level as the effective pulse of the initial gate scanning signal as an example, the difference between the start time of the effective pulse of the signal ga1_a and the signal ga2_a is the same as the difference between the start time of the effective pulse of the signal ga2_a and the signal ga3_a. The difference between the start time of the effective pulse of the signal ga2_a and the signal ga3_a is the same as the difference between the start time of the effective pulse of the signal ga3_a and the signal ga4_a. The difference between the start time of the effective pulse of the signal ga4_a and the signal ga5_a is the same as the difference between the start time of the effective pulse of the signal ga5_a and the signal ga6_a. The rest is the same, and is not described here.

[0100] For example, the first transistors T1_a~T8_a in the first conducting circuit 310 in the conducting control circuit 300 are turned on under the action of the effective pulse signal loaded on the first control signal end CS1, and the plurality of signals ga1_a~ga8_a are input to the corresponding gate lines GA1~GA1 one by one; the second transistors T1_b~T8_b in the second conducting circuit 320 in the conducting control circuit 300 are turned off under the action of the ineffective pulse signal loaded on the second control signal end CS2, that is, the second conducting circuit 320 does not work. Then, the gate drive circuit 200 receives the first high level of the clock signal clk1 and processes it as an initial gate scanning signal output to the conducting control circuit 300, and the first transistor T1_a in the first conducting circuit 310 in the conducting control circuit 300 inputs the initial gate scanning signal to the gate line GA1 to generate the high level signal ga1_1; the gate drive circuit 200 receives the first high level of the clock signal clk2 and processes it as an initial gate scanning signal output to the conducting control circuit 300, and the second transistor T2_a in the first conducting circuit 310 in the conducting control circuit 300 inputs the initial gate scanning signal to the gate line GA2 to generate the high level signal ga2_1; …… the gate drive circuit 200 receives the first high level of the clock signal clk6 and processes it as an initial gate scanning signal output to the conducting control circuit 300, and the first transistor T6_a in the first conducting circuit 310 in the conducting control circuit 300 inputs the initial gate scanning signal to the gate line GA6 to generate the high level signal ga6_1; the gate drive circuit 200 receives the second high level of the clock signal clk1 and processes it as an initial gate scanning signal output to the conducting control circuit 300, and the first transistor T7_a in the first conducting circuit 310 in the conducting control circuit 300 inputs the initial gate scanning signal to the gate line GA7 to generate the high level signal ga7_1; the gate drive circuit 200 receives the second high level of the clock signal clk2 and processes it as an initial gate scanning signal output to the conducting control circuit 300, and the first transistor T8_a in the first conducting circuit 310 in the conducting control circuit 300 inputs the initial gate scanning signal to the gate line GA8 to generate the high level signal ga8_1; that is, the high level pulse of the initial gate scanning signal can be its effective pulse, and the low level pulse can be its ineffective pulse. Of course, when the low level of the initial gate scanning signal is output by the shift register to generate the low level signal for controlling the conduction of the transistor, the low level pulse of the initial gate scanning signal can be its effective pulse, and the high level pulse can be its ineffective pulse.

[0101] In some embodiments of the present disclosure, as Figure 10As shown, the conduction control circuit 300 comprises a first conduction circuit 310 and a second conduction circuit 320; the input of the plurality of target gate scanning signals to the plurality of gate lines after processing the plurality of initial gate scanning signals comprises: loading the signal of the invalid pulse to the first control signal end CS1, loading the signal of the valid pulse to the second control signal end CS2, and making the second conduction circuit 320 configured to respond to the signal of the second control signal end CS2 to process the plurality of initial gate scanning signals into the plurality of target gate scanning signals and input to the plurality of gate lines, and making the first conduction circuit 310 not work.

[0102] In some embodiments of the present disclosure, in the second driving mode, Figure 13 The signal timing diagram corresponding to the gate driving circuit shown as above is shown as Figure 13 Exemplarily, in combination with ​As shown in the figure, the signal ga1_2 represents the target gate scanning signal output by the conduction control circuit 300 to the gate line GA1, the signal ga2_2 represents the target gate scanning signal output by the conduction control circuit 300 to the gate line GA2, the signal ga3_2 represents the target gate scanning signal output by the conduction control circuit 300 to the gate line GA3, the signal ga4_2 represents the target gate scanning signal output by the conduction control circuit 300 to the gate line GA4, the signal ga5_2 represents the target gate scanning signal output by the conduction control circuit 300 to the gate line GA5, the signal ga6_2 represents the target gate scanning signal output by the conduction control circuit 300 to the gate line GA6, the signal ga7_2 represents the target gate scanning signal output by the conduction control circuit 300 to the gate line GA7, and the signal ga8_2 represents the target gate scanning signal output by the conduction control circuit 300 to the gate line GA8. The high level is the effective pulse thereof. Exemplarily, for the gate line GA2, the high level of the signal ga2_2 has a first overlap time t11 with the high level of the signal ga1_2, and the high level of the signal ga2_2 has a second overlap time t21 with the high level of the signal ga3_2, the first overlap time t11 and the second overlap time t21 corresponding to the gate line GA2 are different. For the gate line GA3, the high level of the signal ga3_2 has a first overlap time t12 with the high level of the signal ga2_2, and the high level of the signal ga3_2 has a second overlap time t22 with the high level of the signal ga4_2, the first overlap time t12 and the second overlap time t22 corresponding to the gate line GA3 are different. For the gate line GA4, the high level of the signal ga4_2 has a first overlap time t13 with the high level of the signal ga3_2, and the high level of the signal ga4_2 has a second overlap time t23 with the high level of the signal ga5_2, the first overlap time t13 and the second overlap time t23 corresponding to the gate line GA4 are different. For the gate line GA5, the high level of the signal ga5_2 has a first overlap time t14 with the high level of the signal ga4_2, and the high level of the signal ga5_2 has a second overlap time t24 with the high level of the signal ga6_2, the first overlap time t14 and the second overlap time t24 corresponding to the gate line GA5 are different. The rest are the same, and are not described here.

[0103] For example, the second transistors T1_b~T8_b in the second conducting circuit 320 of the conducting control circuit 300 are turned on under the action of the effective pulse signal loaded on the second control signal end CS2, and the plurality of signals ga1_2~ga8_2 are input to the corresponding gate lines GA1~GA1 one by one; the first transistors T1_a~T8_a in the first conducting circuit 310 of the conducting control circuit 300 are turned off under the action of the ineffective pulse signal loaded on the first control signal end CS1, that is, the first conducting circuit 310 does not work. Then, the gate drive circuit 200 receives the first high level of the clock signal clk1 and processes it as an initial gate scanning signal output to the conducting control circuit 300, and the second transistor T1_b in the second conducting circuit 320 of the conducting control circuit 300 inputs the initial gate scanning signal processed as a target gate scanning signal to the gate line GA1 to generate the high level in the signal ga1_2; the gate drive circuit 200 receives the first high level of the clock signal clk2 and processes it as an initial gate scanning signal output to the conducting control circuit 300, and the second transistor T2_b in the second conducting circuit 320 of the conducting control circuit 300 inputs the initial gate scanning signal processed as a target gate scanning signal to the gate line GA3 to generate the high level in the signal ga3_2; the gate drive circuit 200 receives the first high level of the clock signal clk3 and processes it as an initial gate scanning signal output to the conducting control circuit 300, and the second transistor T3_b in the second conducting circuit 320 of the conducting control circuit 300 inputs the initial gate scanning signal processed as a target gate scanning signal to the gate line GA2 to generate the high level in the signal ga2_2; the gate drive circuit 200 receives the first high level of the clock signal clk4 and processes it as an initial gate scanning signal output to the conducting control circuit 300, and the second transistor T4_b in the second conducting circuit 320 of the conducting control circuit 300 inputs the initial gate scanning signal processed as a target gate scanning signal to the gate line GA4 to generate the high level in the signal ga4_2; the gate drive circuit 200 receives the first high level of the clock signal clk5 and processes it as an initial gate scanning signal output to the conducting control circuit 300, and the second transistor T5_b in the second conducting circuit 320 of the conducting control circuit 300 inputs the initial gate scanning signal processed as a target gate scanning signal to the gate line GA5 to generate the high level in the signal ga5_2; the gate drive circuit 200 receives the first high level of the clock signal clk6 and processes it as an initial gate scanning signal output to the conducting control circuit 300, and the second transistor T6_b in the second conducting circuit 320 of the conducting control circuit 300 inputs the initial gate scanning signal processed as a target gate scanning signal to the gate line GA7 to generate the high level in the signal ga7_2;The gate drive circuit 200 receives the second high level of the clock signal clk1 and processes it as an initial gate scanning signal output to the turn-on control circuit 300, and the second transistor T7_b in the second turn-on circuit 320 in the turn-on control circuit 300 inputs the initial gate scanning signal processed as a target gate scanning signal to the gate line GA6 to generate a high level in the signal ga6_2; the gate drive circuit 200 receives the second high level of the clock signal clk2 and processes it as an initial gate scanning signal output to the turn-on control circuit 300, and the second transistor T8_b in the second turn-on circuit 320 in the turn-on control circuit 300 inputs the initial gate scanning signal processed as a target gate scanning signal to the gate line GA8 to generate a high level in the signal ga8_2;

[0104] Based on the same disclosure concept, the display device provided by the embodiments of the present disclosure also includes the display panel provided by the embodiments of the present disclosure. The display device solves the problem in the same principle as the display panel, and therefore the implementation of the display device can refer to the implementation of the display panel, and the repeated parts will not be described here.

[0105] In the embodiments of the present disclosure, the display device can be any product or component with display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, etc. Other essential components of the display device are understood by those skilled in the art, and will not be described here, nor should they be considered as a limitation on the present disclosure.

[0106] Although the preferred embodiments of the present disclosure have been described, those skilled in the art can make further changes and modifications to the embodiments once they understand the basic inventive concept. Therefore, the appended claims are intended to be interpreted as including all changes and modifications falling within the scope of the present disclosure.

[0107] Obviously, those skilled in the art can make various modifications and variations to the embodiments of the present disclosure without departing from the spirit and scope of the embodiments of the present disclosure. Thus, if these modifications and variations of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalent technologies, the present disclosure also intends to include these modifications and variations.

Claims

1. A display panel, characterized in that, include: The system includes a gate drive circuit, a turn-on control circuit, and multiple gate lines; the gate drive circuit is coupled to the multiple gate lines through the turn-on control circuit. The display panel is divided into multiple sub-pixels into multiple sub-pixel groups. Each sub-pixel group includes two adjacent sub-pixels in the same row. In addition, one sub-pixel in the sub-pixel group is coupled to one of the two corresponding gate lines, and the other sub-pixel is coupled to the other of the two corresponding gate lines. Both sub-pixels in the sub-pixel group are coupled to the same data line. The gate drive circuit is configured to output a plurality of initial gate scan signals; wherein the plurality of initial gate scan signals correspond one-to-one with the plurality of gate lines; The conduction control circuit is configured to receive the plurality of initial gate scan signals. In the first driving mode, the plurality of initial gate scan signals are input one by one to the corresponding gate lines. In the second driving mode, the plurality of initial gate scan signals are processed into a plurality of target gate scan signals and then input to the plurality of gate lines. The plurality of target gate scan signals correspond one-to-one with the plurality of gate lines. In the first driving mode, the difference between the start times of the effective pulses of the initial gate scan signal corresponding to each of the two adjacent gate lines is the same. When the second driving mode is adopted, for at least one of the plurality of gate lines, the effective pulse of the target gate scan signal loaded on the gate line has a first overlap duration with the effective pulse of the target gate scan signal loaded on the adjacent previous gate line, and the effective pulse of the target gate scan signal loaded on the gate line has a second overlap duration with the effective pulse of the target gate scan signal loaded on the adjacent next gate line, wherein the first overlap duration is different from the second overlap duration.

2. The display panel as described in claim 1, characterized in that, The conduction control circuit includes: a first conduction circuit and a second conduction circuit; The gate drive circuit is coupled to the plurality of gate lines through the first conduction circuit. The first conduction circuit is configured to input the plurality of initial gate scan signals to the corresponding gate lines one by one in response to the signal at the first control signal terminal. The gate drive circuit is coupled to the plurality of gate lines through the second conduction circuit. The second conduction circuit is configured to process the plurality of initial gate scan signals into a plurality of target gate scan signals and input them to the plurality of gate lines in response to the signal at the second control signal terminal. When the first driving mode is used, the first control signal terminal is loaded with a valid pulse signal, and the second control signal terminal is loaded with an invalid pulse signal. When the second driving mode is used, the first control signal terminal is loaded with an invalid pulse signal, and the second control signal terminal is loaded with a valid pulse signal.

3. The display panel as described in claim 2, characterized in that, The gate drive circuit includes: multiple shift register units; The first conducting circuit includes: a plurality of first conducting sub-circuits; wherein, one of the shift register units is coupled to a gate line through one of the first conducting sub-circuits; The first conduction sub-circuit is configured to, in response to a signal at the first control signal terminal, conduct the coupled shift register unit and the coupled gate line, so that the corresponding initial gate scan signal is input to the gate line.

4. The display panel as described in claim 3, characterized in that, The first conducting sub-circuit includes: a first transistor; the gate of the first transistor is coupled to the first control signal terminal, the first terminal of the first transistor is coupled to the shift register unit, and the second terminal of the first transistor is coupled to the gate line.

5. The display panel as described in any one of claims 2-4, characterized in that, The second conducting circuit includes: a plurality of second conducting sub-circuit groups, each of the plurality of second conducting sub-circuit groups including: N second conducting sub-circuits; The gate drive circuit includes: multiple shift register units, which are divided into multiple shift register unit groups. Each shift register unit group includes N shift register units. The multiple second conduction sub-circuit groups correspond one-to-one with the multiple shift register unit groups, and each shift register unit group is coupled to N gate lines through its corresponding second conduction sub-circuit group; N is a positive integer not less than 4. At least a portion of the second conducting sub-circuit in the second conducting sub-circuit group is misaligned with at least a portion of the shift register units in the corresponding shift register unit group; The second conduction sub-circuit is configured to, in response to a signal at the second control signal terminal, conduct the coupled shift register unit and the coupled gate line, so that the initial gate scan signal is processed into the target gate scan signal and then input to the gate line.

6. The display panel as described in claim 5, characterized in that, N=4, the first second conducting sub-circuit in the second conducting sub-circuit group is coupled to the first shift register unit in the corresponding shift register unit group, the second second conducting sub-circuit in the second conducting sub-circuit group is coupled to the third shift register unit in the corresponding shift register unit group, the third second conducting sub-circuit in the second conducting sub-circuit group is coupled to the second shift register unit in the corresponding shift register unit group, and the fourth second conducting sub-circuit in the second conducting sub-circuit group is coupled to the fourth shift register unit in the corresponding shift register unit group.

7. The display panel as described in claim 5, characterized in that, The second conducting sub-circuit includes: a second transistor; the gate of the second transistor is coupled to the second control signal terminal, the first terminal of the second transistor is coupled to the shift register unit, and the second terminal of the second transistor is coupled to the gate line.

8. The display panel as described in any one of claims 2-4, characterized in that, The display panel further includes: a first control signal line and a second control signal line; The first control signal line is coupled to the first control signal terminal; The second control signal line is coupled to the second control signal terminal.

9. The display panel as described in any one of claims 1-4, characterized in that, The display panel also includes: a frame start signal line and multiple clock signal lines; The gate drive circuit is coupled to the frame start signal line and the multiple clock signal lines respectively; The gate drive circuit is further configured to output the plurality of initial gate scan signals based on the frame start signal transmitted on the frame start signal line and the clock signals transmitted on the plurality of clock signal lines.

10. A display device, characterized in that, Includes the display panel as described in any one of claims 1-9.

11. A driving method for a display panel as described in any one of claims 1-9, characterized in that, include: When the first driving mode is determined to be used, the gate driving circuit outputs multiple initial gate scan signals, and the turn-on control circuit inputs the multiple initial gate scan signals one by one to the corresponding gate lines. When the second driving mode is determined to be used, the gate driving circuit outputs multiple initial gate scan signals, and the turn-on control circuit processes the multiple initial gate scan signals into multiple target gate scan signals and inputs them to the multiple gate lines.

12. The driving method for the display panel as described in claim 11, characterized in that, The conduction control circuit includes: a first conduction circuit and a second conduction circuit; The step of inputting the plurality of initial gate scan signals one by one to the corresponding gate lines includes: A valid pulse signal is applied to the first control signal terminal, and an invalid pulse signal is applied to the second control signal terminal, so that the first conduction circuit responds to the signal at the first control signal terminal, inputs the plurality of initial gate scan signals one by one to the corresponding gate lines, and disables the second conduction circuit.

13. The driving method for the display panel as described in claim 11, characterized in that, The conduction control circuit includes: a first conduction circuit and a second conduction circuit; The step of processing the plurality of initial gate scan signals into a plurality of target gate scan signals and then inputting them to the plurality of gate lines includes: An invalid pulse signal is applied to the first control signal terminal, and an valid pulse signal is applied to the second control signal terminal, so that the second conduction circuit is configured to respond to the signal at the second control signal terminal, process the plurality of initial gate scan signals into a plurality of target gate scan signals and input them to the plurality of gate lines, and disable the first conduction circuit.

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