Display panel and display device

Abstract

The application provides a display panel and a display device. Embodiments of the application divide a pixel unit into a main sub-pixel unit and a secondary sub-pixel unit to obtain a multi-domain structure to improve the large viewing angle of the display panel. Meanwhile, when the pixel unit displays a normal picture, the picture display brightness of the main sub-pixel unit is greater than that of the secondary sub-pixel unit in the same pixel unit, achieving the effect of low color cast under a large viewing angle. Secondly, when performing black insertion display, the main sub-pixel unit and the secondary sub-pixel unit in the same pixel unit display black pictures to improve the ghosting phenomenon when the display panel performs dynamic picture switching. That is, the display panel in the embodiments of the application can achieve both the low color cast effect and the black insertion function to improve the ghosting phenomenon when displaying a picture.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display panel and display device. Background Technology

[0002] Multi-domain design is a technology used to improve the viewing angle of a product. By dividing the ITO (Indium Tin Oxide) area of ​​a pixel unit into several domains during pixel design, the liquid crystal within a single pixel unit faces different directions during pixel alignment, thereby improving the visibility of the image from various angles, i.e., a wider viewing angle. During display, different domains have different brightness levels to achieve low color shift at a wide viewing angle.

[0003] However, when the display panel switches between dynamic images, ghosting is likely to occur, which affects the dynamic display quality of the LCD (Liquid Crystal Display). Summary of the Invention

[0004] The main technical problem addressed by this application is to provide a display panel and display device that solves the problem of ghosting in existing liquid crystal display panels.

[0005] To address the aforementioned technical problems, the first technical solution provided in this application is: to provide a display panel, comprising:

[0006] Gate line group;

[0007] A pixel unit includes a main sub-pixel unit and a secondary sub-pixel unit; each pixel unit is coupled to a gate line group; both the main sub-pixel unit and the secondary sub-pixel unit include a display switch and a black-insertion switch; the secondary sub-pixel unit also includes a discharge switch.

[0008] Within each frame, a pixel unit includes a normal display phase and a black-insertion display phase. During the normal display phase, the gate line group controls the display switch within the pixel unit to turn on in order to control the pixel unit to display a normal image, and controls the discharge switch to turn on so that the image display brightness of the main sub-pixel unit in the same pixel unit is greater than the image display brightness of the secondary sub-pixel unit.

[0009] During the black-insertion display phase, the gate line group controls the black-insertion switch in the pixel unit to turn on so that both the main sub-pixel unit and the secondary sub-pixel unit in the same pixel unit display a black image.

[0010] Among them, the conductivity types of the display switches are all the same, and the conductivity types of the black plug switches are all the same.

[0011] The gate line group includes display gate lines and black insertion gate lines; the discharge switch is coupled to the display gate line or black insertion gate line in the corresponding gate line group; in each pixel unit, the display switch of the main sub-pixel unit and the display switch of the secondary sub-pixel unit are coupled to the same display gate line, and the black insertion switch of the main sub-pixel unit and the black insertion switch of the secondary sub-pixel unit are coupled to the same black insertion gate line.

[0012] in,

[0013] The control terminal of the discharge switch is electrically connected to the display gate line in the corresponding gate line group, and the conductivity type of the discharge switch is the same as that of the display switch.

[0014] or,

[0015] The control terminal of the discharge switch is electrically connected to the black gate line in the corresponding gate line group. The conductivity type of the discharge switch is opposite to that of the display switch.

[0016] Within a single frame, in the same group of gate lines, the triggering time of the high potential of the inserted black gate line lags behind the triggering time of the high potential of the displayed gate line, and the high potential period of the inserted black gate line and the high potential period of the displayed gate line do not overlap in timing.

[0017] The display panel also includes data lines, which are arranged in a crisscross pattern with the gate line group;

[0018] Within each pixel unit, the main sub-pixel unit and the secondary sub-pixel unit are located on opposite sides of the gate line group and are arranged side by side along the extension direction of the data line;

[0019] or,

[0020] Within each pixel unit, the main sub-pixel unit and the secondary sub-pixel unit are located on the same side of the gate line group and are arranged side by side along the extension direction of the gate line group.

[0021] Each sub-pixel unit further includes a pixel electrode, a pixel capacitor, a storage capacitor, an array substrate-side common electrode, and a color filter substrate-side common electrode. In each sub-pixel unit, the input terminal of the display switch is electrically connected to the data line, the output terminal of the display switch is electrically connected to the pixel electrode, the control terminal of the display switch is electrically connected to the display gate line, one end of the pixel capacitor is electrically connected to the pixel electrode, the other end of the pixel capacitor is electrically connected to the color filter substrate-side common electrode, one end of the storage capacitor is electrically connected to the pixel electrode, the other end of the storage capacitor is electrically connected to the array substrate-side common electrode, the input terminal of the black bar switch is electrically connected to the pixel electrode, the output terminal of the black bar switch is electrically connected to the array substrate-side common electrode, and the control terminal of the black bar switch is electrically connected to the black bar gate line.

[0022] In the secondary pixel unit, the input terminal of the discharge switch is electrically connected to the pixel electrode, the output terminal of the discharge switch is electrically connected to the common electrode on the array substrate side, and the control terminal of the discharge switch is electrically connected to the display gate line or the black gate line in the corresponding gate line group.

[0023] In the secondary pixel unit, the channel width of the discharge switch is smaller than the channel width of the display switch.

[0024] The display panel also includes a driving circuit, which is used to scan the display gate lines line by line, and / or, the driving circuit is used to scan the black gate lines line by line.

[0025] To solve the above-mentioned technical problems, the second technical solution provided in this application is: to provide a display device, including a motherboard and the above-mentioned display panel.

[0026] The beneficial effects of this application are as follows: Unlike existing technologies, this application provides a display panel and a display device. The display panel includes gate line groups and pixel units. Each pixel unit includes main sub-pixel units and secondary sub-pixel units. Each pixel unit is coupled to a gate line group. Both the main and secondary sub-pixel units include a display switch and a black-insertion switch. The secondary sub-pixel unit also includes a discharge switch. Within each frame, the pixel unit includes a normal display phase and a black-insertion display phase. In the normal display phase, the gate line group controls the display switch within the pixel unit to turn on, thereby controlling the pixel unit to display a normal image, and controls the discharge switch to turn on, so that the image brightness of the main sub-pixel unit in the same pixel unit is greater than the image brightness of the secondary sub-pixel unit. In the black-insertion display phase, the gate line group controls the black-insertion switch within the pixel unit to turn on, thereby controlling both the main and secondary sub-pixel units in the same pixel unit to display a black image. This application embodiment achieves a multi-domain structure by dividing pixel units into primary and secondary sub-pixel units to improve the viewing angle of the display panel. Simultaneously, when a pixel unit displays a normal image, the brightness of the primary sub-pixel unit within the same pixel unit is greater than that of the secondary sub-pixel unit, achieving a low color shift effect at a wide viewing angle. Furthermore, during black-insertion display, both the primary and secondary sub-pixel units within the same pixel unit display black images to mitigate the ghosting phenomenon that occurs when the display panel performs dynamic image transitions. In other words, the display panel in this application embodiment achieves both low color shift and black-insertion functionality to reduce ghosting when displaying images. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without any creative effort.

[0028] Figure 1 This is a schematic diagram of the structure of the first embodiment of the display panel provided in this application;

[0029] Figure 2 yes Figure 1 A schematic diagram of the structure of a mid-pixel unit according to an embodiment;

[0030] Figure 3 yes Figure 1 A schematic diagram of another embodiment of the middle pixel unit;

[0031] Figure 4 This is a timing diagram of an embodiment of a single gate line group provided in this application;

[0032] Figure 5 This is a timing diagram of an embodiment of the display gate line and the black gate line provided in this application;

[0033] Figure 6 This is a schematic diagram of the structure of the second embodiment of the display panel provided in this application;

[0034] Figure 7 yes Figure 6 A schematic diagram of the structure of a mid-pixel unit according to an embodiment;

[0035] Figure 8 This is a schematic diagram of the structure of the third embodiment of the display panel provided in this application;

[0036] Figure 9 yes Figure 8 A schematic diagram of the structure of a mid-pixel unit according to an embodiment;

[0037] Figure 10 This is a schematic diagram of an embodiment of the display device provided in this application.

[0038] Explanation of icon numbers:

[0039] 100. Display panel; 101. Display area; 102. Bezel area; 10. Pixel unit; 10A. Main sub-pixel unit; 10B. Secondary sub-pixel unit; 110. Sub-pixel unit; t1. Normal display stage; t2. Black pixel insertion display stage; T1. Display switch; T2. Black pixel insertion switch; T3. Discharge switch; 11. Pixel electrode; Clc. Pixel capacitor; Cst. Storage capacitor; A-com. Array substrate side common electrode; CF-com. Color filter substrate side common electrode; Gate. Gate line group; Gate-1 / Gate1-1 / Gate2-1 / Gate-1. Display gate line; Gate-2 / Gate1-2 / Gate2-2 / Gate-2. Black pixel insertion gate line; Data. Data line; 30. Driving circuit; 31. Gate driving circuit; 32. Black pixel insertion driving circuit; 200. Main board; 300. Display device. Detailed Implementation

[0040] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0041] In the following description, specific details such as particular system architectures, interfaces, and technologies are presented for illustrative purposes rather than for limiting purposes, in order to provide a thorough understanding of this application.

[0042] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0043] The terms "first," "second," and "third" in this application are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. All directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of this application are only used to explain the relative positional relationships and movements between components in a specific orientation (as shown in the figures). If the specific orientation changes, the directional indications also change accordingly. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices.

[0044] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0045] Please see Figure 1 and Figure 2 , Figure 1 This is a schematic diagram of the structure of the first embodiment of the display panel provided in this application. Figure 2 yes Figure 1 A schematic diagram of the structure of one embodiment of the middle pixel unit.

[0046] This application provides a display panel 100. The display panel 100 includes a gate line group (Gate) and pixel units 10. The pixel unit 10 includes a main sub-pixel unit 10A and a secondary sub-pixel unit 10B. Each pixel unit 10 is coupled to a gate line group (Gate). Both the main sub-pixel unit 10A and the secondary sub-pixel unit 10B include a display switch T1 and a black button switch T2. The secondary sub-pixel unit 10B also includes a discharge switch T3. Within each frame, the pixel unit 10 includes a normal display phase t1 (see...). Figure 4 ) and black insertion display stage t2 (see Figure 4During the normal display phase t1, the gate line group controls the display switch T1 within the pixel unit 10 to turn on, thereby controlling the pixel unit 10 to display a normal image, and also controls the discharge switch T3 to turn on, so that the image display brightness of the main sub-pixel unit 10A in the same pixel unit 10 is greater than the image display brightness of the secondary sub-pixel unit 10B. During the black insertion display phase t2, the gate line group controls the black insertion switch T2 within the pixel unit 10 to turn on, thereby controlling both the main sub-pixel unit 10A and the secondary sub-pixel unit 10B in the same pixel unit 10 to display a black image.

[0047] This embodiment of the application improves the viewing angle of the display panel 100 by dividing the pixel unit 10 into a multi-domain structure of primary sub-pixel unit 10A and secondary sub-pixel unit 10B. Simultaneously, when the pixel unit 10 displays a normal image, the brightness of the primary sub-pixel unit 10A within the same pixel unit 10 is greater than that of the secondary sub-pixel unit 10B, achieving a low color shift effect at a wide viewing angle. Furthermore, during black-insertion display, both the primary sub-pixel unit 10A and the secondary sub-pixel unit 10B within the same pixel unit 10 display a black image to improve the ghosting phenomenon that occurs when the display panel 100 performs dynamic image switching. In other words, the display panel 100 in this embodiment of the application can achieve both a low color shift effect and a black-insertion function to improve the ghosting phenomenon when displaying an image.

[0048] It should be noted that in the embodiments of this application, both the primary sub-pixel unit 10A and the secondary sub-pixel unit 10B are sub-pixel units 110.

[0049] The sub-pixel unit 110 has a multi-domain structure, which can be understood as each main sub-pixel unit 10A having a multi-domain structure and each secondary sub-pixel unit 10B having a multi-domain structure.

[0050] Specifically, in this embodiment, all sub-pixel units 110 are 4-domain structures. That is, each pixel unit 10 is an 8-domain structure. The specific structure of the 4-domain structure is not limited here and can be selected according to actual needs.

[0051] In this embodiment, within each pixel unit 10, the area of ​​the main sub-pixel unit 10A is larger than the area of ​​the secondary sub-pixel unit 10B. The area ratio between the main sub-pixel unit 10A and the secondary sub-pixel unit 10B is not specifically limited here and can be selected according to actual needs.

[0052] Each pixel unit 10 is coupled to a gate line group. The gate line group is used to control the corresponding pixel unit 10 to display a black screen or a normal screen.

[0053] It should be noted that in this embodiment, the black screen and the normal screen are relative. The display screen of the sub-pixel unit 110 is only a black screen and a normal screen. That is, the sub-pixel unit 110 either displays a normal screen or a black screen. A black screen is a completely black display screen.

[0054] The display panel 100 also includes data lines Data, which are arranged in a crisscross pattern with the gate line group Gate.

[0055] Within each pixel unit 10, the main sub-pixel unit 10A and the secondary sub-pixel unit 10B are located on opposite sides of the gate line group Gate, and are arranged side by side along the extension direction of the data line Data; or, within each pixel unit 10, the main sub-pixel unit 10A and the secondary sub-pixel unit 10B are located on the same side of the gate line group Gate, and are arranged side by side along the extension direction of the gate line group Gate.

[0056] In this embodiment, the pixel units 10 are arranged in a matrix, with the row direction of the pixel units 10 being the extension direction of the gate line group (Gate) and the column direction of the pixel units 10 being the extension direction of the data line (Data). In each pixel unit 10, the main sub-pixel unit 10A and the secondary sub-pixel unit 10B are located on opposite sides of the gate line group (Gate), so that the main sub-pixel unit 10A and the secondary sub-pixel unit 10B can be coupled to the gate line group (Gate) respectively, reducing the trace length. The main sub-pixel unit 10A and the secondary sub-pixel unit 10B in the same pixel unit 10 are connected to the same data line (Data).

[0057] Please see Figure 3 , Figure 3 yes Figure 1 A schematic diagram of another embodiment of the middle pixel unit.

[0058] In other embodiments, such as Figure 3 As shown, within each pixel unit 10, the main sub-pixel unit 10A and the secondary sub-pixel unit 10B are located on the same side of the gate line group Gate and are arranged side by side along the extension direction of the gate line group Gate. This design can also reduce the trace length.

[0059] The display switch T1, the black plug switch T2, and the discharge switch T3 are all transistors.

[0060] The gate line group includes a display gate line Gate-1 and a black insertion gate line Gate-2. In each gate line group, the display gate line Gate-1 and the black insertion gate line Gate-2 are insulated from each other and spaced apart to avoid short-circuiting between the display gate line Gate-1 and the black insertion gate line Gate-2, which would affect the display effect of the sub-pixel unit 110.

[0061] All display switches T1 have the same conductivity type, and all black-insertion switches T2 have the same conductivity type. Discharge switch T3 is coupled to either display gate line Gate-1 or black-insertion gate line Gate-2 in the corresponding gate line group. In each pixel unit 10, the display switch T1 of the main sub-pixel unit 10A and the display switch T1 of the secondary sub-pixel unit 10B are coupled to the same display gate line Gate-1, and the black-insertion switch T2 of the main sub-pixel unit 10A and the black-insertion switch T2 of the secondary sub-pixel unit 10B are coupled to the same black-insertion gate line Gate-2.

[0062] All display switches T1 have the same conductivity type to ensure that, within the same pixel unit 10, the corresponding display gate line Gate-1 can simultaneously control the display switch T1 of the main sub-pixel unit 10A and the display switch T1 of the secondary sub-pixel unit 10B to be turned on, thereby reducing the number of display gate lines Gate-1. Similarly, all black insertion switches T2 have the same conductivity type to ensure that, within the same pixel unit 10, the corresponding black insertion gate line Gate-2 can simultaneously control the black insertion switch T2 of the main sub-pixel unit 10A and the black insertion switch T2 of the secondary sub-pixel unit 10B to be turned on, thereby reducing the number of black insertion gate lines Gate-2.

[0063] Specifically, in this embodiment, both the display switch T1 and the black-insertion switch T2 are N-type transistors. In other embodiments, the display switch T1 and / or the black-insertion switch T2 can be P-type transistors.

[0064] In this embodiment, the control terminal of the discharge switch T3 is electrically connected to the display gate line Gate-1 in the corresponding gate line group. The conductivity type of the discharge switch T3 is the same as that of the display switch T1, so as to ensure that in the same pixel unit 10, the corresponding display gate line Gate-1 can simultaneously control the display switch T1 of the sub-pixel unit 110 and the black-insertion switch T2 of the secondary sub-pixel unit 10B to be turned on, thereby reducing the number of display gate lines Gate-1. Specifically, in this embodiment, the discharge switch T3 is an N-type transistor.

[0065] Furthermore, each sub-pixel unit 110 also includes a pixel electrode 11, a pixel capacitor Clc, a storage capacitor Cst, an array substrate-side common electrode A-com, and a color filter substrate-side common electrode CF-com. In each sub-pixel unit 110, the input terminal of the display switch T1 is electrically connected to the data line Data, the output terminal of the display switch T1 is electrically connected to the pixel electrode 11, the control terminal of the display switch T1 is electrically connected to the display gate line Gate-1, one end of the pixel capacitor Clc is electrically connected to the pixel electrode 11, the other end of the pixel capacitor Clc is electrically connected to the color filter substrate-side common electrode CF-com, one end of the storage capacitor Cst is electrically connected to the pixel electrode 11, the other end of the storage capacitor Cst is electrically connected to the array substrate-side common electrode A-com, the input terminal of the black bar switch T2 is electrically connected to the pixel electrode 11, the output terminal of the black bar switch T2 is electrically connected to the array substrate-side common electrode A-com, and the control terminal of the black bar switch T2 is electrically connected to the black bar gate line Gate-2.

[0066] Specifically, pixel electrodes 11 are configured in a one-to-one correspondence with sub-pixel units 110, pixel capacitors Clc are configured in a one-to-one correspondence with sub-pixel units 110, and storage capacitors Cst are configured in a one-to-one correspondence with sub-pixel units 110. Main sub-pixel units 10A and secondary sub-pixel units 10B each correspond to different pixel electrodes 11, different pixel capacitors Clc, and different storage capacitors Cst.

[0067] In this embodiment, the array substrate-side common electrode A-com in the primary sub-pixel unit 10A is electrically connected to the array substrate-side common electrode A-com in the secondary sub-pixel unit 10B. The array substrate-side common electrode A-com can be a whole electrode controlled as a whole, or a partitioned electrode controlled in sections; there is no limitation here, and the selection is made according to actual needs. Similarly, the color filter substrate-side common electrode CF-com can be a partitioned electrode or a whole electrode; there is no limitation here, and the selection is made according to actual needs.

[0068] Liquid crystal molecules are disposed between each pixel electrode 11 and the common electrode CF-com on the color filter substrate side. When there is a potential difference between the pixel electrode 11 and the corresponding common electrode CF-com on the color filter substrate side, an electric field is generated. This electric field drives the corresponding liquid crystal molecules to deflect, so that the pixel unit 10 displays a normal image. When the potential between the pixel electrode 11 and the corresponding common electrode CF-com on the color filter substrate side is the same, the corresponding liquid crystal molecules do not deflect, and the pixel unit 10 displays a black image.

[0069] Specifically, when the display switch T1 is on and the black screen switch T2 is off, there is a potential difference between the common electrode CF-com on the color filter substrate side and the pixel electrode 11, thereby driving the sub-pixel unit 110 to display a normal image. When the display switch T1 is off and the black screen switch T2 is on, the potential between the common electrode CF-com on the color filter substrate side and the pixel electrode 11 is the same, thereby driving the sub-pixel unit 110 to display a black image.

[0070] It should be noted that in the same sub-pixel unit 110 of this application embodiment, the display switch T1 and the black insertion switch T2 are not turned on at the same time, so as to avoid the display screen brightness of the sub-pixel unit 110 being reduced due to the simultaneous turn-on of the display switch T1 and the black insertion switch T2, which would affect the display effect.

[0071] In the secondary sub-pixel unit 10B, the input terminal of the discharge switch T3 is electrically connected to the pixel electrode 11, the output terminal of the discharge switch T3 is electrically connected to the common electrode A-com on the array substrate side, and the control terminal of the discharge switch T3 is electrically connected to the display gate line Gate-1 or the black gate line Gate-2 in the corresponding gate line group. It can be understood that, compared to the primary sub-pixel unit 10A, the secondary sub-pixel unit 10B has an additional discharge switch T3, so that during the normal display phase t1, within the same pixel unit 10, the display brightness of the primary sub-pixel unit 10A is greater than that of the secondary sub-pixel unit 10B, achieving a low color cast effect at wide viewing angles.

[0072] Furthermore, in the secondary sub-pixel unit 10B, the channel width of the discharge switch T3 is smaller than the channel width of the display switch T1, so that in the secondary sub-pixel unit 10B, the charging speed of the pixel electrode 11 through the display switch T1 is faster than the discharging speed of the pixel electrode 11 through the discharge switch T3. This causes the secondary sub-pixel unit 10B to be able to display a normal image during the normal display phase t1, but the image display brightness will be reduced. As a result, when the pixel unit 10 displays a normal image, the image display brightness of the primary sub-pixel unit 10A is greater than the image display brightness of the secondary sub-pixel unit 10B, achieving a low color cast effect at a wide viewing angle.

[0073] Please see Figures 1 to 5 , Figure 4 This is a timing diagram of an embodiment of a single gate line group provided in this application. Figure 5 This is a timing diagram of an embodiment of the display gate line and the black gate line provided in this application.

[0074] like Figure 4As shown, within a single frame, in the same gate line group, the triggering time of the high potential of the black-inserted gate line Gate-2 lags behind the triggering time of the high potential of the display gate line Gate-1, and the high potential periods of the black-inserted gate line Gate-2 and the high potential periods of the display gate line Gate-1 do not overlap in timing. This can be understood as follows: in any pixel unit 10, the black-inserted switch T2 and the display switch T1 are not turned on simultaneously to avoid the black-inserted switch T2 and the display switch T1 being turned on at the same time, which would reduce the overall brightness of the pixel unit 10 or prevent it from displaying a normal image, thus affecting the display effect of the display panel 100.

[0075] Specifically, Gate1-1 to Gaten-1 represent the first display gate line Gate-1 to the nth display gate line Gate-1, respectively. Gate1-2 to Gaten-2 represent the first black insertion gate line Gate-2 to the nth black insertion gate line Gate-2, respectively. n is a natural number greater than 1.

[0076] In this embodiment, within a single frame, the trigger time of the high potential of the black gate line Gate-2 is delayed by the same amount of time after the trigger time of the high potential of the displayed gate line Gate-1.

[0077] The display panel 100 also includes a driving circuit 30, which is used to progressively scan the display gate line Gate-1, and / or, the driving circuit 30 is used to progressively scan the black gate line Gate-2.

[0078] The display panel 100 has a display area 101 and a border area 102 disposed on the side of the display area 101. Pixel units 10 are disposed in the display area 101, and driving circuits 30 are disposed in the border area 102.

[0079] Specifically, when there is only one driving circuit 30, the driving circuit 30 can scan and display the gate line Gate-1 and the black gate line Gate-2 line by line.

[0080] When there are multiple driving circuits 30, the display gate line Gate-1 and the black-insertion gate line Gate-2 are scanned line by line by different driving circuits 30. The structures of the multiple driving circuits 30 can be the same or different. The gate line can be scanned line by line on one side or on both sides simultaneously (in the embodiments of this application, the gate line refers to the display gate line Gate-1 or the black-insertion gate line Gate-2). The driving circuit 30 for scanning the display gate line Gate-1 line by line and the driving circuit 30 for scanning the black-insertion gate line Gate-2 line by line can be the same or different.

[0081] The specific structure of the drive circuit 30 is not limited here; it can be selected according to actual needs.

[0082] In this embodiment, there are two driving circuits 30, which are respectively represented as gate driving circuit 31 and black insertion driving circuit 32. Gate driving circuit 31 is used to progressively scan the gate line Gate-1, and black insertion driving circuit 32 is used to progressively scan the black insertion gate line Gate-2.

[0083] The gate driving circuit 31 and the black insertion driving circuit 32 are respectively disposed on the border areas 102 on both sides of the display area 101 along the extension direction of the gate line group.

[0084] Please see Figure 2 , Figure 4 , Figure 6 and Figure 7 , Figure 6 This is a schematic diagram of the structure of the second embodiment of the display panel provided in this application. Figure 7 yes Figure 6 A schematic diagram of the structure of one embodiment of the middle pixel unit.

[0085] The second embodiment of the display panel 100 provided in this application has a structure that is basically the same as that of the first embodiment of the display panel 100 provided in this application, except that the control terminal of the discharge switch T3 is electrically connected to the black gate line Gate-2 in the corresponding gate line group Gate.

[0086] In this embodiment, the control terminal of the discharge switch T3 is electrically connected to the black gate line Gate-2 in the corresponding gate line group Gate. The conductivity type of the discharge switch T3 is opposite to that of the display switch T1, so that the discharge switch T3 can still be turned on during the normal display stage t1, thereby making the screen display brightness of the main sub-pixel unit 10A greater than that of the secondary sub-pixel unit 10B within a single pixel unit 10.

[0087] Specifically, in this embodiment, the discharge switch T3 is a P-type transistor, and the display switch T1 is an N-type transistor.

[0088] This embodiment does not add any extra gate lines (gate lines refer to display gate line Gate-1 or black insertion gate line Gate-2). That is, compared with the above embodiment, the display panel 100 in this embodiment can not only achieve low color shift effect and black insertion function, but also reduce the number of gate lines.

[0089] Please see Figure 2 , Figure 4 , Figure 8 and Figure 9 , Figure 8 This is a schematic diagram of the structure of the third embodiment of the display panel provided in this application. Figure 9 yes Figure 8A schematic diagram of the structure of one embodiment of the middle pixel unit.

[0090] The third embodiment of the display panel 100 provided in this application has a structure that is basically the same as that of the first embodiment of the display panel 100 provided in this application. The difference is that in the same pixel unit 10, the main sub-pixel unit 10A and the secondary sub-pixel unit 10B share the same black switch T2.

[0091] In this embodiment, in the same pixel unit 10, the main sub-pixel unit 10A and the secondary sub-pixel unit 10B share the same black-insertion switch T2.

[0092] Specifically, in pixel unit 10, the input terminal of the black insertion switch T2 is electrically connected to the pixel electrode 11 of the main sub-pixel unit 10A and the pixel electrode 11 of the secondary sub-pixel unit 10B. The output terminal of the black insertion switch T2 is electrically connected to the common electrode A-com on the array substrate side. The control terminal of the black insertion switch T2 is electrically connected to the corresponding black insertion gate line Gate-2.

[0093] Compared to the first embodiment of the display panel 100 provided in this application, this embodiment reduces the number of black pixel switches T2 in the pixel unit 10, which can save costs. In other words, the display panel 100 in this embodiment can not only achieve a low color shift effect and a black pixel insertion function, but also save costs.

[0094] In other embodiments, the control terminal of the discharge switch T3 can be electrically connected to the black gate line Gate-2 in the corresponding gate line group Gate, which will not be described in detail here, please refer to the above description.

[0095] Please see Figure 10 , Figure 10 This is a schematic diagram of an embodiment of the display device provided in this application.

[0096] The display device 300 includes a motherboard 200 and the aforementioned display panel 100. The motherboard 200 is electrically connected to the display panel 100 and is used to transmit various required signals to the display panel 100 to control the display screen. For example, the clock signal CK, common voltage signal VSS, and power supply voltage signal VDD required by the drive circuit 30, as well as the data signals required by the data line Data.

[0097] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0098] The above are merely embodiments of this application and do not limit the scope of patent protection of this application. Any equivalent structural or procedural changes made using the content of this application’s specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the scope of patent protection of this application.

Claims

1. A display panel, characterized by, The display panel comprises: a gate line group; a pixel unit comprising a main sub-pixel unit and a secondary sub-pixel unit; each of the pixel units is coupled to one of the gate line groups; the main sub-pixel unit and the secondary sub-pixel unit each comprise a display switch and a black insertion switch; the secondary sub-pixel unit further comprises a discharge switch; in each frame, the pixel unit comprises a normal display stage and a black insertion display stage; in the normal display stage, the gate line group controls the display switch in the pixel unit to be turned on to control the pixel unit to display a normal picture, and controls the discharge switch to be turned on, so that the picture display brightness of the main sub-pixel unit is greater than that of the secondary sub-pixel unit in the same pixel unit; in the black insertion display stage, the gate line group controls the black insertion switch in the pixel unit to be turned on to control the main sub-pixel unit and the secondary sub-pixel unit in the same pixel unit to display a black picture.

2. The display panel of claim 1, wherein, The conductive types of the display switches are the same, and the conductive types of the black insertion switches are the same; the gate line group comprises a display gate line and a black insertion gate line; the discharge switch is coupled to the display gate line or the black insertion gate line in the corresponding gate line group; in each of the pixel units, the display switch of the main sub-pixel unit and the display switch of the secondary sub-pixel unit are coupled to the same display gate line, and the black insertion switch of the main sub-pixel unit and the black insertion switch of the secondary sub-pixel unit are coupled to the same black insertion gate line.

3. The display panel of claim 2, wherein: the control end of the discharge switch is electrically connected to the display gate line in the corresponding gate line group, and the conductive type of the discharge switch is the same as that of the display switch; or, the control end of the discharge switch is electrically connected to the black insertion gate line in the corresponding gate line group, and the conductive type of the discharge switch is opposite to that of the display switch.

4. The display panel of claim 3, wherein, In a frame, in the same gate line group, the triggering time of the high potential of the black insertion gate line lags behind the triggering time of the high potential of the display gate line, and the high potential period of the black insertion gate line does not overlap with the high potential period of the display gate line in time sequence.

5. The display panel of claim 2, wherein, The display panel further comprises a data line, and the data line and the gate line group are arranged in a vertical and horizontal manner; in each of the pixel units, the main sub-pixel unit and the secondary sub-pixel unit are located on opposite sides of the gate line group and are arranged side by side along the extension direction of the data line; or, in each of the pixel units, the main sub-pixel unit and the secondary sub-pixel unit are located on the same side of the gate line group and are arranged side by side along the extension direction of the gate line group.

6. The display panel of claim 5, wherein, Each of the sub-pixel units further comprises a pixel electrode, a pixel capacitor, a storage capacitor, an array substrate side common electrode and a color film substrate side common electrode; in each of the sub-pixel units, an input end of the display switch is electrically connected with the data line, an output end of the display switch is electrically connected with the pixel electrode, a control end of the display switch is electrically connected with the display gate line, one end of the pixel capacitor is electrically connected with the pixel electrode, the other end of the pixel capacitor is electrically connected with the color film substrate side common electrode, one end of the storage capacitor is electrically connected with the pixel electrode, the other end of the storage capacitor is electrically connected with the array substrate side common electrode, an input end of the black insertion switch is electrically connected with the pixel electrode, an output end of the black insertion switch is electrically connected with the array substrate side common electrode, and a control end of the black insertion switch is electrically connected with the black insertion gate line.

7. The display panel of claim 6, wherein, In the sub-pixel unit, an input end of the discharge switch is electrically connected with the pixel electrode, an output end of the discharge switch is electrically connected with the array substrate side common electrode, and a control end of the discharge switch is electrically connected with a display gate line or a black insertion gate line in the corresponding gate line group.

8. The display panel of claim 7, wherein, In the sub-pixel unit, a channel width of the discharge switch is smaller than a channel width of the display switch.

9. The display panel of claim 2, wherein, The display panel further comprises a driving circuit, the driving circuit is configured to scan the display gate lines row by row, and / or the driving circuit is configured to scan the black insertion gate lines row by row.

10. A display device, characterized by comprising: The display panel comprises a main board and the display panel according to any one of claims 1 to 9.

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