Enhanced-mode p-channel gallium nitride field-effect transistor and preparation method thereof

Abstract

The present invention discloses an enhancement-mode p-channel gallium nitride field-effect transistor and a method for preparing the same. The structure comprises a mesa structure formed by a substrate layer, a GaN buffer layer, an i-GaN channel layer, a first AlN layer, an InAlN barrier layer, a second AlN layer, and a p-GaN layer; source and drain electrodes are provided on either side of the upper surface of the p-GaN layer; a portion of the surface area between the two electrodes is formed with multiple T-shaped fin structures by etching multiple grooves parallel to the source and drain channels; the grooves are etched to a depth that reaches the i-GaN channel layer but does not exceed the lower surface of the layer; a gate dielectric layer covers the entire upper surface and side surfaces of the mesa structure, the gate dielectric layer covering the surface, side surfaces, and bottom surfaces of each groove; openings are provided in the gate dielectric layer on the surfaces of the source and drain electrodes; and a gate electrode is provided on the gate dielectric layer on the surface, side surfaces, and bottom surfaces of each groove of the T-shaped fin structure. The present invention can enhance gate control capability, reduce leakage, suppress short channel effects, regulate threshold voltage, and improve device performance.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor devices, and in particular relates to an enhancement mode p-channel gallium nitride field effect transistor and a preparation method thereof. Background Art

[0002] The wide-bandgap semiconductor material GaN is a typical representative of third-generation semiconductors. Compared with the previous two generations of semiconductor materials, the distance between the conduction band and the valence band of GaN is further widened. For the same volume, the current output capability is stronger, the temperature resistance is better, and the radiation resistance is stronger. This makes GaN power devices have advantages that traditional devices cannot match, such as high breakdown electric field, large current output, and low switching loss. Currently, many mature high-performance products have been developed in the field of n-channel GaN devices. As with silicon-based MOS devices, to fully realize the performance of GaN devices, matching p-channel GaN devices are required. For example, in applications such as electric vehicles and 6G, both bridge drive and push-pull drive require p-channel devices as pull-up devices. Therefore, high-performance p-channel GaN devices are an unavoidable issue in the development of third-generation semiconductors. However, current research on enhancement-mode p-channel GaN devices mainly faces problems such as difficulty in ohmic contact, low on-state current, large off-state leakage, high subthreshold slope, and difficulty in threshold voltage control. As a result, p-channel GaN devices are difficult to match well with n-channel GaN devices, hindering the integrated application of GaN-based complementary logic circuits.

[0003] To realize enhancement-mode p-channel GaN devices, the industry usually adopts groove gate structures. However, these technologies make it difficult to achieve uniform and controllable etching thickness, resulting in discrete device threshold voltages and difficulty in regulation, as well as poor subthreshold swing, transconductance and other characteristics. Summary of the Invention

[0004] To address the aforementioned issues in the prior art, the present invention provides an enhancement-mode p-channel gallium nitride field-effect transistor and a method for fabricating the same. The technical issues addressed by the present invention are achieved through the following technical solutions:

[0005] In a first aspect, an embodiment of the present invention provides an enhancement-mode p-channel gallium nitride field-effect transistor, comprising:

[0006] A mesa structure is formed by a substrate layer 1, a GaN buffer layer 2, an i-GaN channel layer 3, a first AlN layer 4, an InAlN barrier layer 5, a second AlN layer 6, and a p-GaN layer 7 arranged from bottom to top; wherein the mesa structure is divided by a preset horizontal position in the i-GaN channel layer 3, and the lower projection area is larger than the upper projection area; a source electrode 8 and a drain electrode 9 are respectively provided on both sides of the upper surface of the p-GaN layer 7; a portion of the surface area between the source electrode 8 and the drain electrode 9 is formed with multiple T-shaped fin junctions by etching multiple grooves parallel to the source and drain channels structure 10; the etching depth of all grooves reaches the i-GaN channel layer 3 and does not exceed the lower surface of the i-GaN channel layer 3; the upper surface and side surfaces of the mesa structure including the source electrode 8 and the drain electrode 9 are covered with a gate dielectric layer 11, and the gate dielectric layer 11 covers the surfaces, side surfaces and bottom surfaces of each groove of the multiple T-shaped Fin structures 10; openings are provided on the gate dielectric layer 11 on the surfaces of the source electrode 8 and the drain electrode 9; a layer of gate electrode 12 is provided on the gate dielectric layer 11 on the surfaces, side surfaces and bottom surfaces of each groove of the multiple T-shaped Fin structures 10.

[0007] In one embodiment of the present invention, the materials used for the substrate layer 1 include:

[0008] Sapphire, silicon carbide or silicon.

[0009] In one embodiment of the present invention, the thickness of the GaN buffer layer 2 is 1 to 5 μm;

[0010] The thickness of the i-GaN channel layer 3 is 100 to 500 nm;

[0011] The thickness of the first AlN layer 4 is 0.5-1 nm;

[0012] The InAlN barrier layer 5 is made of InAlN material and has a thickness of 15 to 30 nm;

[0013] The thickness of the second AlN layer 6 is 0.5-1 nm;

[0014] The thickness of the p-GaN layer 7 is 50-100 nm. The Mg doping concentration in the p-GaN layer 7 increases from bottom to top, and the Mg doping range is 1E19 cm -3 ~5E20 cm -3 .

[0015] In one embodiment of the present invention, the source electrode 8 and the drain electrode 9 are both made of nickel, gold, or platinum, gold from bottom to top, with a thickness of 100 to 300 nm; the source electrode 8 and the drain electrode 9 both form ohmic contact with the p-GaN layer 7.

[0016] In one embodiment of the present invention, the gate electrode 12 is made of nickel and gold from bottom to top, with a thickness of 100 nm to 300 nm.

[0017] In one embodiment of the present invention, the depth of the T-shaped Fin structure 10 is 200-300 nm; the length of the T-shaped Fin structure 10 along the direction parallel to the source-drain channel is 0.1-5 μm; the width of the T-shaped Fin structure 10 is 20-200 nm; and the distance between two adjacent T-shaped Fin structures 10 is 100-500 nm.

[0018] In one embodiment of the present invention, the gate dielectric layer 11 is made of Al 2 O 3 or HfO 2 and has a thickness of 10 to 30 nm.

[0019] In a second aspect, an embodiment of the present invention provides a method for fabricating an enhancement-mode p-channel gallium nitride field-effect transistor, the method comprising:

[0020] A GaN buffer layer 2, an i-GaN channel layer 3, a first AlN layer 4, an InAlN barrier layer 5, a second AlN layer 6, and a p-GaN layer 7 are sequentially grown on a substrate layer 1 by a metal organic chemical vapor deposition process to obtain a stacked structure.

[0021] Performing mesa etching on a portion of the i-GaN channel layer 3 above a preset horizontal position in the stacked structure using photolithography and inductively coupled plasma etching processes to form a mesa structure with a lower projected area larger than an upper projected area to achieve device isolation;

[0022] The source electrode 8 and the drain electrode 9 of the p-channel GaN field effect transistor are prepared on both sides of the upper surface of the p-GaN layer 7 in the obtained mesa structure by electron beam evaporation process, and the source electrode 8 and the drain electrode 9 are annealed to form ohmic contact with the p-GaN layer 7;

[0023] In a portion of the surface area between the source electrode 8 and the drain electrode 9, a plurality of grooves parallel to the source and drain channels are etched using an inductively coupled plasma etching process to form a plurality of T-shaped Fin structures 10, wherein the etching depth of the grooves reaches the i-GaN channel layer 3 and does not exceed the lower surface of the i-GaN channel layer 3;

[0024] Depositing a gate dielectric layer 11 on the entire sample using an atomic layer deposition process, so that the gate dielectric layer 11 covers the upper surface and side surfaces of the mesa structure including the source electrode 8 and the drain electrode 9, the surface and side surfaces of the multiple T-shaped Fin structures 10, and the bottom surface of each groove;

[0025] Removing the gate dielectric layer 11 from a portion of the upper surface of the source electrode 8 and the drain electrode 9 to form a hole;

[0026] A gate electrode 12 is provided on the gate dielectric layer 11 on the surface, side surfaces and bottom surfaces of the plurality of T-shaped Fin structures 10 to obtain an enhanced p-channel GaN field effect transistor with a T-shaped Fin structure.

[0027] In one embodiment of the present invention, an inductively coupled plasma etching process is used to etch a plurality of grooves parallel to the source and drain channels in a partial surface area between the source electrode 8 and the drain electrode 9 to form a plurality of T-shaped Fin structures 10, including:

[0028] Using electron beam lithography and silicon dioxide or silicon nitride as a hard mask layer, a plurality of groove exposure areas are defined in a partial surface area between the source electrode 8 and the drain electrode 9 in parallel with the source-drain channel direction;

[0029] Using inductively coupled plasma etching to remove the hard mask layer in the exposed area of ​​the groove until the p-GaN layer 7 is exposed;

[0030] Using inductively coupled plasma to etch the p-GaN layer 7 in the groove exposure area to a designated position of the i-GaN channel layer 3 to form a plurality of grooves; wherein the designated position does not exceed the lower surface of the i-GaN channel layer 3;

[0031] The obtained sample is immersed in a tetramethylammonium hydroxide solution at 80°C to 90°C for 1 to 30 minutes, and multiple T-shaped Fin structures 10 are formed by utilizing the anisotropic corrosion property of TMAH on different crystal planes of GaN.

[0032] The remaining hard mask layer is removed using BOE solution.

[0033] In one embodiment of the present invention, a gate electrode 12 is provided on the gate dielectric layer 11 on the surface, side surfaces and bottom surfaces of each groove of the plurality of T-shaped Fin structures 10 to obtain an enhancement mode p-channel GaN field effect transistor with a T-shaped Fin structure, comprising:

[0034] Defining gate regions on the plurality of T-shaped Fin structures 10 by photolithography;

[0035] Using an electron beam evaporation process, nickel metal with a thickness of 10 to 50 nm and gold metal with a thickness of 100 to 200 nm were sequentially deposited on the gate dielectric layer 11 on the surface, side surfaces, and bottom surfaces of each groove of the multiple T-shaped Fin structures 10 to form a gate electrode 12. The gate electrode 12 was then annealed in a nitrogen atmosphere at a temperature of 400° C. for 5 minutes to obtain an enhancement-mode p-channel GaN field-effect transistor with a T-shaped Fin structure.

[0036] Beneficial effects of the present invention:

[0037] Compared with the enhanced p-channel GaN field-effect transistor with a traditional groove gate structure, the present invention adopts a T-type Fin structure to better surround the hole channel, enhance gate controllability, reduce off-state leakage, suppress short channel effect, and greatly improve the performance of p-channel GaN field-effect transistors. At the same time, by adjusting the Fin width of the T-type Fin structure, the holes in the p-GaN layer can be depleted to form an enhanced device, and the threshold voltage can be regulated by the Fin width of the T-type Fin structure, which can be well matched with the n-channel GaN device. It can be seen that the present invention can solve the problems of large off-state leakage, high subthreshold slope, difficult threshold voltage regulation, poor gate control, etc. in the prior art, and achieve characteristics such as high threshold voltage and low off-state leakage. It has the advantages of adjustable threshold voltage, suppression of short channel effect, and can be monolithically integrated with n-channel GaN-based electronic devices. It can be used as a basic device for high-power, high-frequency systems and logic applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 A schematic cross-sectional view of the source and drain channels of an enhancement-mode p-channel gallium nitride field-effect transistor provided by an embodiment of the present invention;

[0039] Figure 2 A schematic cross-sectional view of the Fin of an enhancement-mode p-channel GaN field-effect transistor provided by an embodiment of the present invention;

[0040] Figure 3 In the embodiment of the present invention Figure 1 A top view of

[0041] Figure 4 A schematic diagram of the three-dimensional structure of an enhancement-mode p-channel gallium nitride field-effect transistor provided by an embodiment of the present invention;

[0042] Figure 5 A schematic diagram illustrating the T-shaped Fin structure of an enhancement-mode p-channel GaN field-effect transistor provided by an embodiment of the present invention;

[0043] Figure 6 A schematic flow chart of a method for fabricating an enhancement-mode p-channel gallium nitride field-effect transistor provided by an embodiment of the present invention;

[0044] Figure 7(a) to Figure 7(h) A schematic diagram of the process steps in the method for fabricating an enhancement-mode p-channel gallium nitride field-effect transistor provided by an embodiment of the present invention, viewed from a cross-sectional perspective of the source and drain channels;

[0045] Figure 8(a) to Figure 8(g) Schematic diagram of the formation process of the T-shaped Fin structure according to an embodiment of the present invention;

[0046] Reference numerals:

[0047] 1: Substrate layer; 2: GaN buffer layer; 3: i-GaN channel layer; 4: First AlN layer; 5: InAlN barrier layer; 6: Second AlN layer; 7: p-GaN layer; 8: Source electrode; 9: Drain electrode; 10: T-type Fin structure; 11: Gate dielectric layer; 12: Gate electrode. DETAILED DESCRIPTION

[0048] The present invention will be further described in detail below with reference to specific examples, but the embodiments of the present invention are not limited thereto.

[0049] Example 1

[0050] An embodiment of the present invention provides an enhancement mode p-channel gallium nitride field effect transistor, such as Figures 1 to 5 As shown, the enhancement mode p-channel gallium nitride field effect transistor includes:

[0051] A mesa structure is formed by a substrate layer 1, a GaN buffer layer 2, an i-GaN channel layer 3, a first AlN layer 4, an InAlN barrier layer 5, a second AlN layer 6, and a p-GaN layer 7 arranged from bottom to top; wherein the mesa structure is divided by a preset horizontal position in the i-GaN channel layer 3, and the lower projection area is larger than the upper projection area; a source electrode 8 and a drain electrode 9 are respectively provided on both sides of the upper surface of the p-GaN layer 7; a portion of the surface area between the source electrode 8 and the drain electrode 9 is formed with multiple T-shaped fin junctions by etching multiple grooves parallel to the source and drain channels structure 10; the etching depth of all grooves reaches the i-GaN channel layer 3 and does not exceed the lower surface of the i-GaN channel layer 3; the upper surface and side surfaces of the mesa structure including the source electrode 8 and the drain electrode 9 are covered with a gate dielectric layer 11, and the gate dielectric layer 11 covers the surfaces, side surfaces and bottom surfaces of each groove of the multiple T-shaped Fin structures 10; openings are provided on the gate dielectric layer 11 on the surfaces of the source electrode 8 and the drain electrode 9; a layer of gate electrode 12 is provided on the gate dielectric layer 11 on the surfaces, side surfaces and bottom surfaces of each groove of the multiple T-shaped Fin structures 10.

[0052] Specifically, the Fin structure is a fin-type structure; the source electrode 8 , the drain electrode 9 , and the gate electrode 12 are represented by S, D, and G, respectively. Figure 1 Corresponding to the source-drain channel cross-sectional view, that is, Figure 4 FIG 8 is a diagram showing the device structure observed from a perspective of simultaneously observing the source electrode 8 and the drain electrode 9 in the forward direction; Figure 2 This is a structural diagram observed from the perspective of multiple T-shaped Fin structures 10 cross-sections, that is, Figure 4 , the device structure is viewed from the source electrode 8 toward the drain electrode 9 or from the drain electrode 9 toward the source electrode 8 by dividing along the length of the yellow portion corresponding to the gate electrode; Figure 3 yes Figure 1 A top view of Figure 4 , a diagram showing the device structure viewed from top to bottom; Figure 4 Corresponding to the three-dimensional structure diagram of the entire device, Figure 4 For simplicity, the T-shaped Fin structure 10 is not shown. For details of the T-shaped Fin structure 10 and the gate dielectric layer 11 and gate electrode 12 thereon, please refer to Figure 5 understand, Figure 5 Yes and Figure 2 The same perspective, for simplicity, Figure 5 The substrate layer 1 and the GaN buffer layer 2 are not shown in the figure. It can be seen that there is a gap between the gate electrodes 12 of adjacent T-shaped Fin structures 10, and there are grooves between the upper surfaces of the gate electrodes 12.

[0053] from Figure 1 It can be seen that the enhancement-mode p-channel GaN field-effect transistor comprises, from bottom to top, a substrate layer 1, a GaN buffer layer 2, an i-GaN channel layer 3, a first AlN layer 4, an InAlN barrier layer 5, a second AlN layer 6, and a p-GaN layer 7. Above a predetermined horizontal position in the i-GaN channel layer 3, the device layer in the edge region is removed, thus forming a mesa structure with a smaller top and a larger bottom. Figure 4 It is understood that the orange part and the part above it are the smaller part of the mesa structure, while the area below the orange part is the larger part of the mesa structure. It can be seen that the device layer in the edge areas on both sides above the preset horizontal position in the i-GaN channel layer 3 is removed; in the embodiment of the present invention, the preset horizontal position is a horizontal position in the i-GaN channel layer 3, except for the upper and lower surfaces, which can be set as needed and is not limited here.

[0054] like Figure 1 As shown, a source electrode 8 and a drain electrode 9 are respectively provided on both sides of the upper surface of the p-GaN layer 7; the source electrode 8 and the drain electrode 9 are at a certain distance from the edge of the device on their respective sides. Figure 2 Each protruding structure formed by a portion of the i-GaN channel layer 3, the first AlN layer 4, the InAlN barrier layer 5, the second AlN layer 6 and the p-GaN layer 7 is a T-shaped Fin structure 10, which is wide at the top and narrow at the bottom. The blank area beside the T-shaped Fin structure 10 corresponds to the etched groove part, see Figure 2 The etching depth of all grooves reaches the i-GaN channel layer 3 and does not exceed the lower surface of the i-GaN channel layer 3. It can be the same as or different from the preset horizontal position in the i-GaN channel layer 3, and there is no limitation here.

[0055] For the gate dielectric layer 11, see Figure 2 ,as well as Figure 5 The blue area in FIG. 1 covers the upper surface and side surfaces of the mesa structure including the source electrode 8 and the drain electrode 9, and covers the surface, side surfaces and bottom surfaces of each groove of the multiple T-shaped Fin structures 10; however, openings are provided in the gate dielectric layer 11 on the surfaces of the source electrode 8 and the drain electrode 9 to facilitate subsequent metal connection;

[0056] For gate electrode 12, see Figure 2 、 Figure 4 ,as well as Figure 5 The yellow area is understood to cover the gate dielectric layer 11 on the surface, side surfaces and bottom surfaces of each groove of the multiple T-shaped Fin structures 10. As mentioned above, there is a gap between the gate dielectric layers 11 of adjacent T-shaped Fin structures 10, and the gate electrodes 12 also have a gap.

[0057] The following is a description of each layer in the embodiment of the present invention.

[0058] In an optional embodiment, the material used for the substrate layer 1 includes:

[0059] Sapphire, silicon carbide or silicon. The thickness of the substrate layer 1 can be set as needed and is not limited here.

[0060] In an optional embodiment, the thickness of the GaN buffer layer 2 is 1 to 5 μm;

[0061] In an optional embodiment, the thickness of the i-GaN channel layer 3 is 100 to 500 nm;

[0062] In an optional embodiment, the thickness of the first AlN layer 4 is 0.5-1 nm;

[0063] In an optional embodiment, the InAlN barrier layer 5 is made of InAlN material and has a thickness of 15 to 30 nm;

[0064] In an optional embodiment, the thickness of the second AlN layer 6 is 0.5-1 nm;

[0065] In an optional embodiment, the thickness of the p-GaN layer 7 is 50-100 nm; the Mg doping concentration in the p-GaN layer 7 increases from bottom to top, and the Mg doping range is 1E19 cm -3 ~5E20 cm -3 .

[0066] In an optional embodiment, the source electrode 8 and the drain electrode 9 are both made of nickel, gold, or platinum, gold from bottom to top, and have a thickness of 100 to 300 nm; the source electrode 8 and the drain electrode 9 both form ohmic contact with the p-GaN layer 7.

[0067] In an optional embodiment, the gate electrode 12 is made of nickel and gold from bottom to top, with a thickness of 100 nm to 300 nm.

[0068] In an optional embodiment, the gate dielectric layer 11 is made of Al2O3 or HfO2 and has a thickness of 10 to 30 nm.

[0069] In an optional embodiment, the depth of the T-shaped Fin structure 10 is 200-300 nm; the length of the T-shaped Fin structure 10 in the direction parallel to the source and drain channels is 0.1-5 μm; the width of the T-shaped Fin structure 10 is 20-200 nm; and the distance between two adjacent T-shaped Fin structures 10 is 100-500 nm. Figure 4 and Figure 5 It is understood that the depth of the T-shaped Fin structure 10 corresponds to h; the width of the T-shaped Fin structure 10 corresponds to W. Since the T-shaped Fin structure 10 is wide at the top and narrow at the bottom, the upper and lower widths are different; the spacing between two adjacent T-shaped Fin structures 10 corresponds to p, which represents the distance between Fins.

[0070] Compared with the enhanced p-channel GaN field-effect transistor with a traditional groove gate structure, the present invention adopts a T-type Fin structure to better surround the hole channel, enhance gate controllability, reduce off-state leakage, suppress short channel effect, and greatly improve the performance of p-channel GaN field-effect transistors. At the same time, by adjusting the Fin width of the T-type Fin structure, the holes in the p-GaN layer can be depleted to form an enhanced device, and the threshold voltage can be controlled by the Fin width of the T-type Fin structure, which can be well matched with the n-channel GaN device. It can be seen that the present invention can solve the problems of large off-state leakage, high subthreshold slope, difficult threshold voltage control, poor gate control, etc. in the prior art, and achieve characteristics such as high threshold voltage and low off-state leakage. It has the advantages of adjustable threshold voltage, suppression of short channel effect, and can be monolithically integrated with n-channel GaN-based electronic devices. It can be used as a basic device for high-power, high-frequency systems and logic applications.

[0071] Example 2

[0072] The embodiment of the present invention provides a method for preparing an enhancement mode p-channel gallium nitride field effect transistor, such as Figure 6 As shown, the method may include the following steps:

[0073] S1, using a metal organic chemical vapor deposition process, sequentially growing a GaN buffer layer 2, an i-GaN channel layer 3, a first AlN layer 4, an InAlN barrier layer 5, a second AlN layer 6, and a p-GaN layer 7 on a substrate layer 1 to obtain a stacked structure;

[0074] In an optional embodiment,

[0075] The materials used in the substrate layer 1 include:

[0076] Sapphire, silicon carbide or silicon.

[0077] The thickness of the GaN buffer layer 2 is 1 to 5 μm;

[0078] The thickness of the i-GaN channel layer 3 is 100 to 500 nm;

[0079] The thickness of the first AlN layer 4 is 0.5-1 nm;

[0080] The InAlN barrier layer 5 is made of InAlN material and has a thickness of 15 to 30 nm;

[0081] The thickness of the second AlN layer 6 is 0.5-1 nm;

[0082] The thickness of the p-GaN layer 7 is 50-100 nm. The Mg doping concentration in the p-GaN layer 7 increases from bottom to top, and the Mg doping range is 1E19 cm-3 to 5E20 cm-3.

[0083] The device obtained in this step is shown in FIG7( a ); Figure 7(a) to Figure 7(h) Schematic diagram of the process steps from the source-drain channel cross-sectional perspective.

[0084] S2, performing mesa etching on a portion of the i-GaN channel layer 3 above a preset horizontal position in the stacked structure using a photolithography and inductively coupled plasma etching process to form a mesa structure with a lower projected area larger than an upper projected area to achieve device isolation;

[0085] Specifically, etching can be performed on all sides of the i-GaN channel layer 3 above a predetermined horizontal position in the stacked structure to form a mesa structure with a larger bottom and a smaller top. The predetermined horizontal position can be selected as needed at any horizontal position between the upper and lower surfaces of the i-GaN channel layer 3. This step is shown in FIG7(b).

[0086] S3, forming a source electrode 8 and a drain electrode 9 of a p-channel GaN field effect transistor on both sides of the upper surface of the p-GaN layer 7 in the obtained mesa structure by an electron beam evaporation process, and performing an annealing process so that the source electrode 8 and the drain electrode 9 form an ohmic contact with the p-GaN layer 7;

[0087] Specifically, photolithography is used to define the source and drain regions, and BOE is used to clean the sample and remove the oxide in the ohmic region. Using an electron beam evaporation process, 10 to 50 nm thick platinum (nickel) metal and 100 to 250 nm thick gold metal are sequentially deposited on the p-GaN layer 7 to form the source electrode 8 and drain electrode 9 of the p-channel field effect transistor. The source electrode 8 and the drain electrode 9 have the same thickness of 100 to 300 nm, and are annealed in an oxygen atmosphere at a temperature of 550°C for 10 minutes, so that the source electrode 8 and the drain electrode 9 form an ohmic contact with the p-GaN layer 7. Please refer to Figure 7(c) and understand it in conjunction with Figure 8(a). Figure 8(a) to Figure 8(g) This is a schematic diagram of the formation process of the T-type Fin structure. Figure 2 For ease of understanding, Figures 8(a) to 8(g) The electrodes are not shown.

[0088] S4, etching a plurality of grooves parallel to the source and drain channels in a portion of the surface area between the source electrode 8 and the drain electrode 9 using an inductively coupled plasma etching process to form a plurality of T-shaped Fin structures 10, wherein the etching depth of the grooves reaches the i-GaN channel layer 3 but does not exceed the lower surface of the i-GaN channel layer 3;

[0089] Among them, S4 may include:

[0090] S41, using electron beam lithography and silicon dioxide or silicon nitride as a hard mask layer, a plurality of groove exposure areas are defined in a partial surface area between the source electrode 8 and the drain electrode 9 parallel to the source-drain channel direction; please understand in conjunction with Figure 7(d) and Figure 8(b).

[0091] S42 , using inductively coupled plasma etching to remove the hard mask layer in the exposed area of ​​the groove until the p-GaN layer 7 is exposed; please understand this in conjunction with FIG. 8( c ).

[0092] S43, using inductively coupled plasma to etch the p-GaN layer 7 in the groove exposure area to a designated position of the i-GaN channel layer 3, to form a plurality of grooves; wherein the designated position does not exceed the lower surface of the i-GaN channel layer 3;

[0093] S44, immersing the obtained sample in a tetramethylammonium hydroxide (TMAH) solution at 80° C. to 90° C. for 1 to 30 minutes, utilizing the anisotropic corrosion property of TMAH on different crystal planes of GaN to form a plurality of T-shaped Fin structures 10;

[0094] In an optional embodiment, the depth of the T-shaped Fin structure 10 is 200 to 300 nm; the length of the T-shaped Fin structure 10 along the direction parallel to the source and drain channel is 0.1 to 5 μm; the width of the T-shaped Fin structure 10 is 20 to 200 nm; and the distance between two adjacent T-shaped Fin structures 10 is 100 to 500 nm.

[0095] Please understand this step in conjunction with Figure 8(d).

[0096] S45, removing the remaining hard mask layer using a BOE solution.

[0097] Please refer to FIG7(e) and FIG8(e) to understand the device structure obtained in this step.

[0098] S5, depositing a gate dielectric layer 11 on the entire sample using an atomic layer deposition process, so that the gate dielectric layer 11 covers the upper surface and side surfaces of the mesa structure including the source electrode 8 and the drain electrode 9, the surface and side surfaces of the multiple T-shaped Fin structures 10, and the bottom surface of each groove;

[0099] The gate dielectric layer 11 may have a thickness of 10 to 30 nm and may be made of aluminum oxide (Al2O3) or hafnium dioxide (HfO2).

[0100] S6, removing the gate dielectric layer 11 from a portion of the upper surface of the source electrode 8 and the drain electrode 9 to form a hole;

[0101] Specifically, photolithography and BOE wet etching or reactive ion dry etching are used to remove the gate dielectric layer 11 from a portion of the upper surface of the source electrode 8 and the drain electrode 9 to form an opening. This step is described in detail in FIG.

[0102] S7 , disposing a gate electrode 12 on the gate dielectric layer 11 on the surfaces, side surfaces and bottom surfaces of the plurality of T-shaped Fin structures 10 , and obtaining an enhanced p-channel GaN field effect transistor with a T-shaped Fin structure.

[0103] Among them, S7 may include:

[0104] S71: Using an electron beam evaporation process, nickel metal with a thickness of 10 to 50 nm and gold metal with a thickness of 100 to 200 nm are sequentially deposited on the gate dielectric layer 11 on the surfaces, side surfaces, and bottom surfaces of each groove of the plurality of T-shaped fin structures 10 to form a gate electrode 12, so that the thickness of the gate electrode 12 is 100 nm to 300 nm. The gate electrode 12 is then annealed in a nitrogen atmosphere at a temperature of 400°C for 5 minutes to obtain an enhancement mode p-channel GaN field-effect transistor with a T-shaped fin structure. Please refer to Figures 7(h) and 8(g) for an understanding of this step.

[0105] The preparation method provided by the embodiment of the present invention uses a T-shaped Fin structure to realize an enhancement-mode p-channel GaN field-effect transistor. Compared with the traditional groove gate enhancement-mode p-channel GaN field-effect transistor, the T-shaped Fin structure can better surround the hole channel. While achieving enhancement mode, it also enhances gate controllability, reduces off-state leakage, and suppresses the short-channel effect. This can significantly improve the performance of p-channel GaN devices in GaN-based complementary logic circuits. By adjusting the Fin width of the T-shaped Fin structure, the holes in the p-GaN layer can be depleted to form an enhancement-mode device. The threshold voltage can be controlled by the Fin width of the T-shaped Fin structure, which can well match the n-channel GaN device. The enhancement-mode p-channel GaN field-effect transistor prepared by the present invention can be used as a basic component of high-frequency monolithic gallium nitride CMOS devices and logic circuits.

[0106] Example 3

[0107] Based on the second embodiment, a process example of a method for fabricating an enhancement mode p-channel GaN field effect transistor with a T-type Fin structure based on a p-GaN / InAlN heterojunction on a silicon substrate is provided. The method may include the following steps:

[0108] Step 1, preparing p-GaN / AlN / InAlN / AlN / i-GaN / GaN buffer layer / substrate substrate;

[0109] Specifically, a metal organic chemical vapor deposition process is used to sequentially grow a GaN buffer layer 2, an i-GaN channel layer 3, a first AlN layer 4, an InAlN barrier layer 5, a second AlN layer 6 and a p-GaN layer 7 on a substrate layer 1 to obtain a p-GaN / AlN / InAlN / AlN / i-GaN / GaN buffer layer / silicon substrate substrate; please refer to S1 in Example 2 for understanding this step.

[0110] Step 2, mesa etching;

[0111] Photolithography and inductively coupled plasma etching processes are used to perform mesa etching to form device isolation; this step should be understood in accordance with S2 in Example 2.

[0112] Step 3, making source electrode and drain electrode;

[0113] Photolithography was used to define the source and drain regions, and the sample was cleaned with a BOE solution to remove the oxide in the ohmic region. Using an electron beam evaporation process, 30nm thick platinum or nickel metal and 150nm thick gold metal were sequentially deposited on the p-GaN layer 7 to form the source electrode 8 and drain electrode 9 of the p-channel GaN field-effect transistor. Annealing was then performed in an oxygen atmosphere at a temperature of 550°C for 10 minutes, so that both the source electrode 8 and the drain electrode 9 formed ohmic contacts with the p-GaN layer 7. Please refer to S3 in Example 2 for understanding this step.

[0114] Step 4, forming a T-shaped Fin structure;

[0115] Specifically, electron beam lithography and a silicon nitride (SiN) hard mask are used to define the grooves of the T-shaped fin structure, referred to as fin grooves. Inductively coupled plasma etching is used to completely remove the SiN in the exposed area up to the p-GaN layer 7. Inductively coupled plasma etching is then used to further remove the p-GaN layer 7 in the exposed area up to the fin groove of the i-GaN layer 3, thereby forming a T-shaped fin structure 10. The T-shaped fin structure 10 has a depth of 200 nm, a length parallel to the source and drain channels of 800 nm, a width of 30 nm, and a spacing of 200 nm between adjacent T-shaped fin structures 10. The sample is then immersed in a 90°C tetramethylammonium hydroxide (TMAH) solution for 5 minutes, utilizing the anisotropic etching property of TMAH on different crystal planes of GaN to ultimately form the T-shaped fin structure 10. A BOE solution is then used to remove the remaining SiN. This step should be understood in accordance with S4 in Example 2.

[0116] Step 5, growing a gate dielectric layer;

[0117] A 20 nm thick aluminum oxide layer is deposited on the entire sample using an atomic layer deposition process as the gate dielectric layer 11 . Please refer to S5 in Example 2 for understanding this step.

[0118] Step 6: Opening the gate dielectric layer

[0119] Photolithography and reactive ion dry etching processes are used to remove aluminum oxide on the source electrode 8 and the drain electrode 9 to complete the gate dielectric layer opening. Please refer to S6 in Example 2 for understanding this step.

[0120] Step 7, making a gate electrode;

[0121] The gate region is defined by photolithography, and a 30 nm thick layer of nickel metal and a 100 nm thick layer of gold metal are sequentially deposited on the gate dielectric layer 11 by electron beam evaporation to form a gate electrode 12 of the p-channel GaN field-effect transistor. The gate electrode 12 is then annealed in a nitrogen atmosphere at a temperature of 400° C. for 5 minutes to obtain an enhanced-mode p-channel GaN field-effect transistor with a T-type Fin structure. Please refer to S7 in Example 2 for understanding this step.

[0122] The preparation method provided by the embodiment of the present invention uses a T-shaped Fin structure to realize an enhancement-mode p-channel GaN field-effect transistor. Compared with the traditional groove gate enhancement-mode p-channel GaN field-effect transistor, the T-shaped Fin structure can better surround the hole channel. While achieving enhancement mode, it also enhances gate controllability, reduces off-state leakage, and suppresses the short-channel effect. This can significantly improve the performance of p-channel GaN devices in GaN-based complementary logic circuits. By adjusting the Fin width of the T-shaped Fin structure, the holes in the p-GaN layer can be depleted to form an enhancement-mode device. The threshold voltage can be controlled by the Fin width of the T-shaped Fin structure, which can well match the n-channel GaN device. The enhancement-mode p-channel GaN field-effect transistor prepared by the present invention can be used as a basic component of high-frequency monolithic gallium nitride CMOS devices and logic circuits.

[0123] It should be noted that, in the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like to indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present invention.

[0124] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature identified as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined.

[0125] In the description of this specification, the reference terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" mean that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in any appropriate manner in any one or more embodiments or examples. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification.

[0126] The above description is only a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention are included in the scope of protection of the present invention.

Claims

1. An enhancement-mode p-channel gallium nitride field-effect transistor, characterized in that: include: A mesa structure formed by a substrate layer (1), a GaN buffer layer (2), an i-GaN channel layer (3), a first AlN layer (4), an InAlN barrier layer (5), a second AlN layer (6) and a p-GaN layer (7) arranged from bottom to top; The mesa structure is demarcated by a preset horizontal position in the i-GaN channel layer (3), and the lower projection area is larger than the upper projection area; the two side areas of the upper surface of the p-GaN layer (7) are respectively provided with a source electrode (8) and a drain electrode (9); a portion of the surface area between the source electrode (8) and the drain electrode (9) is formed with a plurality of T-shaped Fin structures (10) by etching a plurality of grooves parallel to the source and drain channels; wherein each protrusion-shaped structure formed by a portion of the i-GaN channel layer (3), the first AlN layer (4), the InAlN barrier layer (5), the second AlN layer (6) and the p-GaN layer (7) is a T-shaped Fin structure (10), which presents A T-shaped pattern with a width at the top and a narrowness at the bottom; the etching depth of all grooves reaches the i-GaN channel layer (3) and does not exceed the lower surface of the i-GaN channel layer (3); the upper surface and side surfaces of the mesa structure including the source electrode (8) and the drain electrode (9) are covered with a gate dielectric layer (11), and the gate dielectric layer (11) covers the surface, side surfaces and bottom surfaces of each groove of the multiple T-shaped Fin structures (10); openings are provided on the gate dielectric layer (11) on the surface of the source electrode (8) and the drain electrode (9); and a layer of gate electrode (12) is provided on the gate dielectric layer (11) on the surface, side surfaces and bottom surfaces of each groove of the multiple T-shaped Fin structures (10).

2. The enhancement-mode p-channel gallium nitride field-effect transistor according to claim 1, wherein: The materials used in the substrate layer (1) include: Sapphire, silicon carbide or silicon.

3. The enhancement-mode p-channel GaN field-effect transistor according to claim 1, wherein: The thickness of the GaN buffer layer (2) is 1 to 5 μm; The thickness of the i-GaN channel layer (3) is 100 to 500 nm; The thickness of the first AlN layer (4) is 0.5-1 nm; The InAlN barrier layer (5) is made of InAlN material and has a thickness of 15 to 30 nm; The thickness of the second AlN layer (6) is 0.5-1 nm; The thickness of the p-GaN layer (7) is 50-100 nm; the Mg doping concentration inside the p-GaN layer (7) increases from bottom to top, and the Mg doping range is 1E19 cm -3 ~5E20 cm -3 .

4. The enhancement-mode p-channel GaN field-effect transistor according to claim 1, wherein: The source electrode (8) and the drain electrode (9) are both made of nickel, gold, or platinum, gold from bottom to top, and have a thickness of 100 to 300 nm; the source electrode (8) and the drain electrode (9) both form ohmic contact with the p-GaN layer (7).

5. The enhancement-mode p-channel gallium nitride field-effect transistor according to claim 1 or 4, characterized in that: The gate electrode (12) is made of nickel and gold from bottom to top, and has a thickness of 100nm to 300nm.

6. The enhancement-mode p-channel GaN field-effect transistor according to claim 1, wherein: The depth of the T-shaped Fin structure (10) is 200-300 nm; the length of the T-shaped Fin structure (10) in a direction parallel to the source-drain channel is 0.1-5 μm; the width of the T-shaped Fin structure (10) is 20-200 nm; and the spacing between two adjacent T-shaped Fin structures (10) is 100-500 nm.

7. The enhancement-mode p-channel GaN field-effect transistor according to claim 1, wherein: The gate dielectric layer (11) is made of Al2O3 or HfO2 and has a thickness of 10 to 30 nm.

8. A method for preparing an enhancement mode p-channel gallium nitride field effect transistor, characterized in that: include: A GaN buffer layer (2), an i-GaN channel layer (3), a first AlN layer (4), an InAlN barrier layer (5), a second AlN layer (6) and a p-GaN layer (7) are sequentially grown on a substrate layer (1) using a metal organic chemical vapor deposition process to obtain a stacked structure; Using photolithography and inductively coupled plasma etching processes to perform mesa etching on a portion of the i-GaN channel layer (3) above a preset horizontal position in the stacked structure, forming a mesa structure with a lower projection area larger than an upper projection area to achieve device isolation; A source electrode (8) and a drain electrode (9) of a p-channel GaN field effect transistor are prepared on both sides of the upper surface of the p-GaN layer (7) in the obtained mesa structure by using an electron beam evaporation process, and an annealing process is performed so that both the source electrode (8) and the drain electrode (9) form ohmic contact with the p-GaN layer (7); In a partial surface area between the source electrode (8) and the drain electrode (9), a plurality of grooves parallel to the source and drain channels are etched using an inductively coupled plasma etching process to form a plurality of T-shaped Fin structures (10), wherein each protruding structure formed by a portion of the i-GaN channel layer (3), the first AlN layer (4), the InAlN barrier layer (5), the second AlN layer (6) and the p-GaN layer (7) is a T-shaped Fin structure (10), which presents a T-shaped pattern that is wide at the top and narrow at the bottom; the etching depth of the groove reaches the i-GaN channel layer (3) and does not exceed the bottom surface of the i-GaN channel layer (3); Depositing a gate dielectric layer (11) on the entire sample using an atomic layer deposition process, so that the gate dielectric layer (11) covers the upper surface and side surfaces of the mesa structure including the source electrode (8) and the drain electrode (9), the surfaces and side surfaces of the plurality of T-shaped Fin structures (10), and the bottom surface of each groove; Removing the gate dielectric layer (11) from a portion of the upper surface area of ​​the source electrode (8) and the drain electrode (9) to achieve opening; A gate electrode (12) is provided on the gate dielectric layer (11) on the surface, side surfaces and bottom surfaces of each groove of the plurality of T-shaped Fin structures (10) to obtain an enhanced p-channel GaN field effect transistor with a T-shaped Fin structure.

9. The method for preparing an enhancement mode p-channel gallium nitride field effect transistor according to claim 8, wherein: In a partial surface area between the source electrode (8) and the drain electrode (9), a plurality of grooves parallel to the source and drain channels are etched using an inductively coupled plasma etching process to form a plurality of T-shaped Fin structures (10), including: Electron beam lithography is used, and silicon dioxide or silicon nitride is used as a hard mask layer, to define a plurality of groove exposure areas in a partial surface area between the source electrode (8) and the drain electrode (9) parallel to the source-drain channel direction; Using inductively coupled plasma etching to remove the hard mask layer in the exposed area of ​​the groove until the p-GaN layer (7) is exposed; Inductively coupled plasma is used to etch the p-GaN layer (7) in the groove exposure area until a designated position of the i-GaN channel layer (3) is reached, thereby forming a plurality of grooves; wherein the designated position does not exceed the lower surface of the i-GaN channel layer (3); The obtained sample is immersed in a tetramethylammonium hydroxide solution at 80° C. to 90° C. for 1 to 30 minutes, and multiple T-shaped Fin structures (10) are formed by utilizing the anisotropic corrosion property of TMAH on different crystal planes of GaN. The remaining hard mask layer is removed using BOE solution.

10. The method for preparing an enhancement mode p-channel gallium nitride field effect transistor according to claim 1 or 9, characterized in that: A gate electrode (12) is provided on the gate dielectric layer (11) on the surface, side surface and bottom surface of each groove of the plurality of T-shaped Fin structures (10) to obtain an enhanced p-channel GaN field effect transistor with a T-shaped Fin structure, comprising: Defining gate regions on the plurality of T-shaped Fin structures (10) using photolithography; By adopting an electron beam evaporation process, nickel metal with a thickness of 10 to 50 nm and gold metal with a thickness of 100 to 200 nm are sequentially deposited on the gate dielectric layer (11) on the surface, side surface and bottom surface of each groove of the plurality of T-shaped Fin structures (10) to form a gate electrode (12), and annealing is performed in a nitrogen atmosphere at a temperature of 400° C. for 5 minutes to obtain an enhanced p-channel GaN field effect transistor with a T-shaped Fin structure.

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