Testing Method, Device, Electronic Device and Storage Medium for Keypad Circuit

Abstract

The present invention discloses a test method, device, electronic device and storage medium for a key circuit, relating to circuit test technology. The method includes: obtaining a target waveform diagram corresponding to a target key to be tested in the key circuit, where the target waveform diagram includes at least two output levels; sequentially marking the at least two output levels to obtain level sequence codes, with one level sequence code corresponding to one output level; respectively counting the output levels of all odd-numbered bits and all even-numbered bits in the level sequence codes to obtain a test mechanism for the target key to be tested, and testing the target key to be tested based on the test mechanism. By separately analyzing the output levels of all odd-numbered bits and all even-numbered bits in the level sequence codes to determine the test mechanism of the target key to be tested, the present invention achieves the beneficial effects of simplifying the test process and improving the test efficiency of the key circuit.

Description

Technical Field

[0001] The present invention relates to the technical field of circuit testing, and in particular, to a method, device, electronic device and storage medium for testing a key circuit. Background Art

[0002] In the field of integrated circuit testing, for a key circuit, such as a remote control circuit, it is necessary to test whether each key is qualified, so as to ensure the practicability of the product and improve the user experience of the product.

[0003] The existing method for testing a key circuit is generally as follows: for any key to be tested, the test machine obtains the code value corresponding to the key to be tested (generally composed of 0 and 1). To distinguish each test key, the code value corresponding to each test key contains multiple bits (the specific number of bits is related to the coding format). For example, the code value of the key to be tested is "1001010100001111". Optionally, according to industry rules, there are three level periods in the code value "1", namely H-L-L; there are two level periods in the code value "0", namely H-L, where H represents high level and L represents low level. Thus, the code value "1001010100001111" of the test key can be decoded to obtain the corresponding coding vector:[[]]

[0004] "HLLHLHLHLLHLHLLHLHLLHLHLHLHLHLLHLLHLLHLLHLL"

[0005] Optionally, the waveform diagram corresponding to the key to be tested can also be obtained according to the high and low levels corresponding to the coding vector. When testing whether the key to be tested meets the specifications, the corresponding preset code value is imported from the database according to the chip model used in the key circuit in advance (further, the corresponding preset coding vector or preset waveform diagram of the preset code value can be obtained), and then compared with the actual code value (or actual coding vector, or actual waveform diagram) measured by the current test machine for the key to be tested. When the comparison is completely consistent, it is determined that the key to be tested is qualified; otherwise, it is determined that the key to be tested is unqualified.

[0006] The above method of testing through the code value (or coding vector, or waveform diagram) of the key to be tested has the problem of cumbersome testing process, thus reducing the testing efficiency of the key circuit. Summary of the Invention

[0007] The present invention provides a method, device, electronic device and storage medium for testing a key circuit, which can improve the existing scheme for testing a key circuit.

[0008] In a first aspect, the present invention provides a method for testing a key circuit, including: obtaining a target waveform diagram corresponding to a target key to be tested in the key circuit, where the target waveform diagram includes at least two output levels; sequentially marking at least two of the output levels to obtain a level sequence code, with one level sequence code corresponding to one of the output levels; separately counting all the output levels at odd positions and all the output levels at even positions in the level sequence code to obtain a test mechanism for the target key to be tested, and testing the target key to be tested based on the test mechanism.

[0009] Optionally, the sequentially marking at least two of the output levels to obtain a level sequence code includes: determining a starting code value of the level sequence code, where the starting code value is even or odd; sequentially marking at least two of the output levels according to whether the starting code value is even or odd to obtain the level sequence code.

[0010] Optionally, when the starting code value is even, the output levels corresponding to all even positions in the level sequence code are preset output levels, and the output levels corresponding to all odd positions in the level sequence code include high levels or low levels;

[0011] The separately counting all the output levels at odd positions and all the output levels at even positions in the level sequence code to obtain a test mechanism for the target key to be tested includes: performing a number system conversion algorithm on the high levels or low levels corresponding to all odd positions to obtain test codes for all odd positions in the level sequence code; obtaining the test mechanism for the target key to be tested based on the test codes for all odd positions and the preset output levels for all even positions.

[0012] Optionally, the performing a number system conversion algorithm on the high levels or low levels corresponding to all odd positions to obtain test codes for all odd positions in the level sequence code includes: sequentially marking all odd positions to obtain odd position sequence codes, where there are at least two odd position sequence codes, with one odd position sequence code corresponding to one low level or one high level; representing each low level or high level in the odd position sequence codes in a binary manner to obtain binary codes corresponding to the odd position sequence codes; performing a number system conversion algorithm on the binary codes to obtain test codes for all odd positions.

[0013] Optionally, testing the target key to be tested based on the test mechanism includes: obtaining the actual codes of all odd bits in the level sequence code of the target key to be tested, and obtaining the actual output levels of all even bits in the level sequence code; when the test codes of all odd bits are consistent with the actual codes, and the preset output levels of all even bits are consistent with the actual output levels, determining that the test result of the target key to be tested is qualified; when the test codes of all odd bits are inconsistent with the actual codes, or the preset output levels of all even bits are inconsistent with the actual output levels, determining that the test result of the target key to be tested is unqualified.

[0014] Optionally, after testing the target key to be tested based on the test mechanism, it further includes: obtaining the test results of each test key in the key circuit; when the test result of each test key is qualified, determining that the test result of the key circuit is qualified; when the test result of any test key in the key circuit is unqualified, determining that the test result of the key circuit is unqualified, and displaying the key identifier corresponding to the test key with the unqualified test result.

[0015] Optionally, when the starting code value is odd, the output levels corresponding to all odd bits in the level sequence code are preset output levels, and the output levels corresponding to all even bits in the level sequence code include high level or low level;

[0016] The test mechanism for the target key to be tested by separately counting the output levels of all odd bits and all even bits in the level sequence code includes: performing radix conversion on the high level or low level corresponding to all even bits based on the radix conversion algorithm to obtain the test codes of all even bits in the level sequence code; obtaining the test mechanism for the target key to be tested according to the test codes of all even bits and the preset output levels of all odd bits.

[0017] In a second aspect, the present invention provides a test device for a key circuit, and the device includes:

[0018] A waveform acquisition module, configured to acquire a target waveform diagram corresponding to a target key to be tested in the key circuit, where the target waveform diagram includes at least two output levels;

[0019] A sequence marking module, configured to perform sequence marking on at least two of the output levels to obtain a level sequence code, and one level sequence code corresponds to one of the output levels;

[0020] A level statistics module is used to separately count the output levels of all odd - numbered bits and all even - numbered bits in the level sequence code, obtain the test mechanism of the target key to be measured, and test the target key to be measured based on the test mechanism.

[0021] In a third aspect, the present invention further provides an electronic device, which includes:

[0022] At least one processor; and

[0023] A memory communicatively connected to the at least one processor; wherein,

[0024] The memory stores a computer program executable by the at least one processor. When the computer program is executed by the at least one processor, the at least one processor is enabled to execute the test method of the key circuit according to any embodiment of the present invention.

[0025] In a fourth aspect, the present invention further provides a computer - readable storage medium. The computer - readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the test method of the key circuit according to any embodiment of the present invention when executed.

[0026] In the test solution of the key circuit provided by the embodiments of the present invention, a key circuit includes at least one key to be measured, and one key to be measured corresponds to one waveform diagram. Each waveform diagram includes at least two output levels. Then, for the target key to be measured, at least two output levels in the target waveform diagram are sequentially marked to obtain a level sequence code, and one level sequence code corresponds to one output level; further, by separately analyzing the output levels of all odd - numbered bits and all even - numbered bits in the level sequence code, the output rules of the output levels of all odd - numbered bits and the output rules of the output levels of all even - numbered bits are obtained. Further, the test mechanism of the target key to be measured is determined through the output rules of the output levels of all odd - numbered bits and the output rules of the output levels of all even - numbered bits, so as to test the target key to be measured through the test mechanism. In the test solution provided in this embodiment, by separately analyzing the output levels of all odd - numbered bits and all even - numbered bits in the level sequence code to determine the test mechanism of the target key to be measured, the beneficial effects of simplifying the test process and improving the test efficiency of the key circuit are achieved.

[0027] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present invention, nor is it used to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] To more clearly illustrate the technical solution of the present invention, the accompanying drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following accompanying drawings only show some embodiments of the present invention and should not be regarded as a limitation of the scope. For those of ordinary skill in the art, without creative efforts, other related accompanying drawings can be obtained based on these accompanying drawings.

[0029] Figure 1 It is a schematic flowchart of a test method for a key circuit provided in this embodiment;

[0030] Figure 2 It is a schematic structural diagram of a target waveform diagram provided in this embodiment;

[0031] Figure 3 It is a schematic structural diagram of a test device for a key circuit provided in this embodiment;

[0032] Figure 4 It is a schematic structural diagram of an electronic device provided in this embodiment. Detailed implementation manners

[0033] In order to enable those skilled in the art to better understand the solution of the present invention, the technical solution in the present invention will be clearly and completely described below in conjunction with the accompanying drawings in this embodiment. Obviously, the described embodiments are only some embodiments of the present invention, rather than all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts should fall within the protection scope of the present invention.

[0034] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above accompanying drawings are used to distinguish similar objects and do not necessarily need to describe a specific order or sequence. It should be understood that such used data can be interchanged under appropriate circumstances so that the embodiments of the present invention described here can be implemented in an order other than those illustrated or described here. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device including a series of steps or units does not necessarily have to be limited to those clearly listed steps or units, but may include other steps or units not clearly listed or inherent to these processes, methods, products, or devices.

[0035] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It can be understood that the specific embodiments described here are only used to explain the present invention and are not a limitation of the present invention. Additionally, it should be noted that for the convenience of description, only parts related to the present invention rather than all structures are shown in the accompanying drawings.

[0036] Figure 1 FIG. 1 is a schematic flowchart of a test method for a key circuit provided in this embodiment. This embodiment is applicable to the situation of quickly testing each test key in the key circuit. This method can be executed by a test device for the key circuit. The device can be implemented in the form of hardware and / or software, and the device can be configured in a computer device such as a server. Refer to Figure 1 , and the method specifically may include the following steps:

[0037] S110. Obtain a target waveform diagram corresponding to a target key to be tested in the key circuit.

[0038] The above-mentioned target key to be tested is any key to be tested in the key circuit. Generally, the key circuit includes at least one key to be tested. For example, the number of keys to be tested can be 4×4 (indicating that there are 16 keys to be tested in the current key circuit, and the meaning of the following examples is the same), 4×5, 8×8, etc. To ensure the usability of key products (such as the remote control of various intelligent devices integrated with a key circuit, or a keyboard, etc.), before the product is put on the market, each key included in the key product needs to be tested one by one. The number of keys to be tested specifically included in the key circuit is not limited here.

[0039] Among them, the above-mentioned obtaining of the target waveform diagram corresponding to the target key to be tested in the key circuit can be achieved through the following method: obtain a preset code value corresponding to the target key to be tested, and encode the preset code value to obtain a preset encoding vector; draw a waveform according to the level sequence corresponding to the preset encoding vector to obtain the target waveform diagram. Among them, the preset code value is pre-imported from a database by a test device according to the chip model used in the key circuit. For example, the preset code value can be "1001010100001111". Further according to industry rules, in the code value "1", there are three level periods, which are H-L-L; in the code value "0", there are two level periods, which are H-L, where H represents a high level and L represents a low level. Thus, the code value "1001010100001111" of the test key can be decoded to obtain the encoding vector corresponding to the code value: "HLLHLHLHLLHLHLLHLHLLHLHLHLHLHLLHLLHLLHLLHLL"; finally, obtain the waveform diagram corresponding to the key to be tested according to the high and low levels corresponding to the encoding vector. Specifically, please refer to Figure 2 , Figure 2 FIG. 2 is a schematic structural diagram of the target waveform diagram provided in this embodiment. Figure 2 The example is given with the preset code value corresponding to the target key to be tested being "1001010100001111", and the corresponding target waveform diagram is as shown in Figure 2 .

[0040] Among them, in Figure 2In this case, the leading code indicates that during the process of the test device actually obtaining the code value of the target key to be tested, the leading code of the target key to be tested will be obtained first. After obtaining the leading code, the test device can clarify that the value after the leading code is the preset code value corresponding to the target key to be recorded.

[0041] In this embodiment, the target waveform diagram includes at least two output levels. Among them, the output levels include a high level H and a low level L.

[0042] S120. Sequentially mark at least two output levels to obtain a level sequence code.

[0043] In the current step, the method of sequentially marking at least two output levels can be to mark them sequentially according to Arabic numerals. For example, the obtained level sequence code can be: 1, 2, 3,..., N, etc.; alternatively, when sequentially marking at least two output levels, the obtained level sequence code can also be 0, 1, 2, 3,..., n, etc.

[0044] In this embodiment, the purpose of sequentially marking at least two output levels to obtain a level sequence code is to analyze the odd and even bits in the level sequence code through subsequent steps, so as to obtain different test mechanisms according to the different output levels corresponding to the odd and even bits. Then it can be known that on the basis of different starting code values corresponding to the level sequence code, it also has a certain impact on determining the test mechanism of the target test key in subsequent steps.

[0045] In a preferred embodiment, for the test method of the key circuit provided in this embodiment, the above step S120 can be implemented in the following way: determine the starting code value of the level sequence code, and the starting code value is even or odd; sequentially mark at least two output levels according to whether the starting code value is even or odd to obtain a level sequence code.

[0046] Optionally, the method provided in this embodiment for sequentially marking at least two output levels is not limited by starting with 0 or 1, and can also use any natural number such as 2, 5, or 11 as the starting code value. As long as after the starting code value, the sequence code corresponding to each output level increases by 1 in sequence according to the natural number rule, such as 11, 12, 13,..., m, etc., specifically, the method provided in this embodiment for sequentially marking at least two output levels and the manifestation form of obtaining the level sequence code are not limited here.

[0047] In this embodiment, after sequentially marking at least two output levels in the target waveform diagram, a obtained code is called a level sequence code corresponding to an output level, that is, one level sequence code corresponds to one output level. Please continue to refer to Figure 2For example, taking the case of sequential marking starting from the starting code value 0 in the diagram, where 0 is the level sequence code corresponding to the first output level (high level); 1 is the level sequence code corresponding to the second output level (low level), and so on; among them, the finally obtained 0, 1, 2, 3,..., n are Figure 2 The level sequence codes corresponding to the target waveform diagram of the example, etc.

[0048] S130. Respectively count the output levels of all odd-numbered bits and all even-numbered bits in the level sequence code to obtain the test mechanism of the target key to be tested, and test the target key to be tested based on the test mechanism.

[0049] When the starting code value is different, in the current step, the test mechanisms obtained based on the output levels of all odd-numbered bits and all even-numbered bits in the level sequence code are also different.

[0050] A preferred embodiment. In the current embodiment, taking the starting code value as an even number as an example, in this case, the output levels corresponding to all even-numbered bits in the level sequence code are preset output levels, and the output levels corresponding to all odd-numbered bits in the level sequence code include high level or low level. The specific explanation is as follows:

[0051] Taking the level sequence code as 0, 1, 2, 3,..., n as an example, where n can be odd or even. In this embodiment, taking n as an odd number as an example for illustration, then all odd-numbered bits in the level sequence code include 1, 3, 5, 7,..., n, etc.; all even-numbered bits in the level sequence code include 0, 2, 4, 6,..., n - 1, etc.

[0052] Correspondingly, the method of separately counting the output levels of all odd-numbered bits and all even-numbered bits in the level sequence code can be to use the function of the time synchronization monitoring module (TMU) integrated in the test device to record the high and low level times corresponding to each level sequence code in the target waveform diagram, based on Figure 2 For example, the following results are obtained: CodePulse[0]=500; CodePulse[1]=1000; CodePulse[2]=500; CodePulse[3]=500; CodePulse[4]=500; CodePulse[5]=500; CodePulse[6]=500; CodePulse[7]=1000;... CodePulse

[31] =1000. Among them, 0, 1, 2, 3, 4, 5, 6, 7,..., 31 represent the level sequence codes, and 500 and 1000 represent the output times of the output levels corresponding to each level sequence code. Among them, 500 is the output time corresponding to the output high level, and 1000 is the output time corresponding to the output low level.

[0053] In this embodiment, it can be obtained that when the starting code value of the level sequence code is an even number, the output level time corresponding to the even bit is 500 milliseconds (ms), and the output level time corresponding to the odd bit may be 500 milliseconds (ms) or 1000 milliseconds (ms).

[0054] Based on this, for the test scheme of the key circuit provided in this embodiment, the method of separately counting the output levels of all odd bits and all even bits in the level sequence code to obtain the test mechanism of the target key to be tested can be: performing radix conversion on the high level or low level corresponding to all odd bits based on the radix conversion algorithm to obtain the test codes of all odd bits in the level sequence code; obtaining the test mechanism of the target key to be tested according to the test codes of all odd bits and the preset output levels of all even bits.

[0055] The specific explanation of obtaining the test mechanism of the target key to be tested based on the above method is as follows: when the starting code value of the level sequence code is an even number, for the output level corresponding to the even bit, it is only necessary to analyze whether the corresponding output level time is around 500 milliseconds (ms); for the output level corresponding to the odd bit, which may be 500 milliseconds (ms) or 1000 milliseconds (ms), the output times corresponding to the output levels of all odd bits can be analyzed separately. In this embodiment, the high level or low level corresponding to all odd bits can be converted based on the radix conversion algorithm to obtain the test codes of all odd bits in the level sequence code. Specifically, the conversion method of this radix conversion algorithm is as follows: using 0 to represent 500 milliseconds (ms) and 1 to represent 100 milliseconds (ms) to further analyze the output times corresponding to the output levels of all odd bits. Based on Figure 2 The following results can be obtained through examples: CodeBit[1]=1; CodeBit[3]=0; CodeBit[5]=0; CodeBit[7]=1; CodeBit[9]=0; CodeBit

[11] =1; CodeBit

[13] =0; CodeBit

[15] =1; CodeBit

[17] =0; CodeBit

[19] =0; CodeBit

[21] =0; CodeBit

[23] =0; CodeBit

[25] =1; CodeBit

[27] =1; CodeBit

[29] =1; CodeBit

[31] =1. Among them, 1, 3, 5,..., 31 indicate all odd bits in the level sequence code.

[0056] Further, for the convenience of further analysis, the test codes of all odd bits in the level sequence code can be obtained based on the following method: Sequentially label all odd bits to obtain an odd-bit sequence code. The odd-bit sequence code includes at least two, and one odd-bit sequence code corresponds to a low level or a high level; Represent each low level or high level in the odd-bit sequence code in binary to obtain the binary code corresponding to the odd-bit sequence code; Perform number system conversion on the binary code based on the number system conversion algorithm to obtain the test codes of all odd bits.

[0057] Taking the above Figure 2 as an example, the method of sequentially labeling all odd bits to obtain the odd-bit sequence code is as follows: CodeBit[0]=1; CodeBit[1]=0; CodeBit[2]=0; CodeBit[3]=1; CodeBit[4]=0; CodeBit[5]=1; CodeBit[6]=0; CodeBit[7]=1; CodeBit[8]=0;

[0058] CodeBit[9]=0; CodeBit

[10] =0; CodeBit

[11] =0; CodeBit

[12] =1; CodeBit

[13] =1; CodeBit

[14] =1; CodeBit

[15] =1. Among them, 0 represents the first odd bit in the level sequence code, that is, the above-mentioned first odd-bit sequence code, 1 represents the second odd bit in the level sequence code, that is, the above-mentioned second odd-bit sequence code, and so on. 15 represents the fifteenth odd bit in the level sequence code, that is, the above-mentioned fifteenth odd-bit sequence code.

[0059] Based on the above example analysis, the binary code corresponding to the odd-bit sequence code is 1001010100001111. Further, to reduce the difficulty of odd-bit comparison, the binary code can be converted based on the number system conversion algorithm. The current conversion method can be octal, decimal, or hexadecimal. The specific method of number system conversion is not limited here.

[0060] In a preferred example, in this embodiment, taking the conversion of the above binary code to hexadecimal as an example, the odd-bit coding method of the target key to be tested is as follows: CodeBytes[0]=0x950F. Among them, the current 0 represents the target key to be tested identifier, such as the first key to be tested. The purpose of performing hexadecimal conversion in this embodiment is to shorten the comparison bits and improve the comparison accuracy compared with the existing scheme of comparing based on the preset code value or the compiled vector obtained by parsing; Compared with the existing method of comparing based on the waveform diagram, it reduces the comparison difficulty and improves the test efficiency.

[0061] Based on the test mechanism of the target key to be tested obtained from the test codes of all odd bits and the preset output levels of all even bits provided in this embodiment, when testing the target key to be tested, there is no need to compare the code values (or compilation vectors, or waveform diagrams) of the keys to be tested provided according to the existing solutions one by one. Only the level sequence codes need to be encoded one by one. When the starting code value is even, only the hexadecimal codes finally obtained for the odd bits need to be compared, and whether the output levels of the even bits are the preset time needs to be compared. Compared with the existing solutions, the comparison difficulty is reduced, the test process is simplified, and the test efficiency is improved.

[0062] It should be noted that the test method of the key circuit provided in this embodiment is described based on Figure 2 for the purpose of illustration, but this embodiment is not limited to being applied to Figure 2 the example. The solution provided in this embodiment can be used for all keys in the field of test keys.

[0063] Furthermore, the above embodiment only illustrates the method of obtaining the corresponding test mechanism when the starting code value is even. As another alternative, this embodiment can also be adapted to the case where the starting code value is odd. In this case, the output levels corresponding to all odd bits in the level sequence code are the preset output levels, and the output levels corresponding to all even bits in the level sequence code include high level or low level. It can be seen that when the starting code value is odd, the output level results of all odd bits in the level sequence code and the output level results corresponding to all even bits in the level sequence code are opposite to the case where the starting code value is even.

[0064] Then further, this embodiment separately counts the output levels of all odd bits and all even bits in the level sequence code to obtain the test mechanism of the target key to be tested, including: performing radix conversion on the high level or low level corresponding to all even bits based on the radix conversion algorithm to obtain the test codes of all even bits in the level sequence code; obtaining the test mechanism of the target key to be tested according to the test codes of all even bits and the preset output levels of all odd bits. That is, when the starting code value is odd, the analysis method of the test mechanism of the target key to be tested is opposite to the analysis method when the starting code value is even, and the specific analysis process will not be elaborated here.

[0065] As another alternative, the test solution of the key circuit provided in this embodiment takes the starting code value as an even number as an example. When testing the target key to be tested based on the test mechanism, it specifically includes the following methods:

[0066] Obtain the actual codes of all odd bits in the level sequence code of the target key to be tested, and obtain the actual output levels of all even bits in the level sequence code; when the test codes and actual codes of all odd bits match, and the preset output levels and actual output levels of all even bits match, the test result of the target key to be tested is qualified; when the test codes and actual codes of all odd bits do not match, or the preset output levels and actual output levels of all even bits do not match, the test result of the target key to be tested is unqualified.

[0067] In the solution provided in this embodiment, when determining whether the target key to be tested is qualified, only when the currently obtained actual codes and test codes of all odd bits, and the currently obtained actual output levels and preset output levels of all even bits are exactly the same, does it indicate that the test result of the target key is qualified; otherwise, it is unqualified.

[0068] In another optional manner, the test solution of the key circuit provided in this embodiment, after testing the target key to be tested based on the test mechanism, further includes: obtaining the test results of each test key in the key circuit; when the test result of each test key is qualified, outputting that the test result of the key circuit is qualified; when the test result of any test key in the key circuit is unqualified, outputting that the test result of the key circuit is unqualified, and displaying the key identifier corresponding to the test key with the test result of being unqualified.

[0069] In this embodiment, to ensure the practicability of the key product and improve the user experience, when the test results of all keys to be tested in the key circuit are all qualified, it indicates that the test result of the key circuit is qualified. Otherwise, when the test result of any key to be tested is unqualified, the test result of the key circuit is unqualified, and then the key identifier corresponding to the test key with the test result of being unqualified is output, so that the tester can clearly know which test key is unqualified and conduct targeted detection to improve the test efficiency.

[0070] The test method for the key circuit provided in this embodiment. A key circuit includes at least one key to be tested, and one key to be tested corresponds to one waveform diagram. Each waveform diagram includes at least two output levels. Then, for the target key to be tested, at least two output levels in the target waveform diagram are sequentially marked to obtain a level sequence code, and one level sequence code corresponds to one output level. Further, by separately analyzing the output levels of all odd-numbered bits and all even-numbered bits in the level sequence code, the output rules of the output levels of all odd-numbered bits and the output rules of the output levels of all even-numbered bits are obtained. Further, the test mechanism of the target key to be tested is determined through the output rules of the output levels of all odd-numbered bits and the output rules of the output levels of all even-numbered bits, so as to test the target key to be tested through the test mechanism. The test scheme provided in this embodiment simplifies the test process and improves the test efficiency of the key circuit by separately analyzing the output levels of all odd-numbered bits and all even-numbered bits in the level sequence code to determine the test mechanism of the target key to be tested.

[0071] Figure 3 FIG. 4 is a schematic structural diagram of a test device for a key circuit provided in an embodiment. This device is applicable to execute the test method for the key circuit provided in this embodiment. As Figure 3 shown, the device may specifically include: a waveform acquisition module 310, a sequential marking module 320, and a level statistics module 330, where:

[0072] The waveform acquisition module 310 is configured to acquire a target waveform diagram corresponding to a target key to be tested in the key circuit, and the target waveform diagram includes at least two output levels;

[0073] The sequential marking module 320 is configured to sequentially mark at least two of the output levels to obtain a level sequence code, and one level sequence code corresponds to one of the output levels;

[0074] The level statistics module 330 is configured to separately count the output levels of all odd-numbered bits and all even-numbered bits in the level sequence code to obtain the test mechanism of the target key to be tested, and test the target key to be tested based on the test mechanism.

[0075] The test device for the key circuit provided in this embodiment. A key circuit includes at least one key to be tested, and one key to be tested corresponds to one waveform diagram. Each waveform diagram includes at least two output levels. Then, for the target key to be tested, at least two output levels in the target waveform diagram are sequentially marked to obtain a level sequence code, and one level sequence code corresponds to one output level. Further, by analyzing the output levels of all odd bits and all even bits in the level sequence code respectively, the output rules of the output levels of all odd bits and the output rules of the output levels of all even bits are obtained. Further, the test mechanism of the target key to be tested is determined by the output rules of the output levels of all odd bits and the output rules of the output levels of all even bits, so as to test the target key to be tested through the test mechanism. The test solution provided in this embodiment simplifies the test process and improves the test efficiency of the key circuit by analyzing the output levels of all odd bits and all even bits in the level sequence code to determine the test mechanism of the target key to be tested.

[0076] In one embodiment, the sequential marking module 320 includes: a code value determination unit and a sequential marking unit, where:

[0077] The code value determination unit is configured to determine the starting code value of the level sequence code, and the starting code value is even or odd;

[0078] The sequential marking unit is configured to sequentially mark at least two of the output levels according to whether the starting code value is even or the starting code value is odd, to obtain a level sequence code.

[0079] In one embodiment, when the starting code value is even, the output levels corresponding to all even bits in the level sequence code are preset output levels, and the output levels corresponding to all odd bits in the level sequence code include high level or low level.

[0080] The level statistics module 330 includes a base conversion unit and a mechanism obtaining unit, where:

[0081] The base conversion unit is configured to perform base conversion on the high level or low level corresponding to all odd bits based on a base conversion algorithm to obtain the test codes of all odd bits in the level sequence code;

[0082] The mechanism obtaining unit is configured to obtain the test mechanism of the target key to be tested according to the test codes of all odd bits and the preset output levels of all even bits.

[0083] In one embodiment, the base conversion unit includes: a sequential marking subunit, a level representation subunit, and a base conversion subunit, where:

[0084] A sequential marking subunit, configured to perform sequential marking on all odd bits to obtain odd-bit sequential codes, where there are at least two of the odd-bit sequential codes, and one odd-bit sequential code corresponds to a low level or a high level;

[0085] A level representation subunit, configured to represent each low level or high level in the odd-bit sequential codes based on a binary method to obtain a binary code corresponding to the odd-bit sequential codes;

[0086] A base conversion subunit, configured to perform base conversion on the binary code based on a base conversion algorithm to obtain test codes for all odd bits.

[0087] In one embodiment, the level statistics module 330 further includes a first acquisition unit and a test comparison unit, where:

[0088] The first acquisition unit is configured to acquire actual codes for all odd bits in the level sequential code of the target key to be tested, and acquire actual output levels for all even bits in the level sequential code;

[0089] The test comparison unit is configured to, when the test codes for all odd bits are consistent with the actual codes, and the preset output levels for all even bits are consistent with the actual output levels, determine that the test result of the target key to be tested is qualified; and is further configured to, when the test codes for all odd bits are inconsistent with the actual codes, or the preset output levels for all even bits are inconsistent with the actual output levels, determine that the test result of the target key to be tested is unqualified.

[0090] In one embodiment, the device further includes a result acquisition module and a result output module, where:

[0091] The result acquisition module is configured to acquire test results of each test key in the key circuit;

[0092] The result output module is configured to, when the test result of each test key is qualified, output that the test result of the key circuit is qualified; and is further configured to, when the test result of any test key in the key circuit is unqualified, output that the test result of the key circuit is unqualified, and display the key identifier corresponding to the test key whose test result is unqualified.

[0093] In one embodiment, when the starting code value is odd, the output levels corresponding to all odd bits in the level sequential code are preset output levels, and the output levels corresponding to all even bits in the level sequential code include high levels or low levels.

[0094] The radix conversion unit is further configured to perform radix conversion on the high or low level corresponding to all even bits based on a radix conversion algorithm, so as to obtain test encodings of all even bits in the level sequence code.

[0095] The mechanism obtaining unit is further configured to obtain a test mechanism of the target key to be measured according to the test encodings of all even bits and the preset output levels of all odd bits.

[0096] Those skilled in the art can clearly understand that for the convenience and conciseness of description, only the division of the above functional modules is used as an example. In practical applications, the above functions can be allocated to different functional modules according to needs, that is, the internal structure of the device is divided into different functional modules to complete all or part of the functions described above. The specific working processes of the above-described functional modules can refer to the corresponding processes in the foregoing method embodiments and will not be elaborated herein.

[0097] The present invention also provides an electronic device, which includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein, the memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor, so that the at least one processor can execute the test method for a key circuit according to any embodiment of the present invention.

[0098] The present invention also provides a computer-readable medium, and the computer-readable storage medium stores computer instructions for causing a processor to execute the test method for a key circuit according to any embodiment of the present invention when executed.

[0099] Next, refer to Figure 4 , Figure 4 which is a schematic structural diagram of the electronic device provided in this embodiment. It shows a schematic structural diagram of a computer system 500 of an electronic device suitable for implementing the present invention. Figure 4 The shown electronic device is only an example and should not bring any limitation to the functions and usage scope of this embodiment.

[0100] As Figure 4 shown, the computer system 500 includes a central processing unit (CPU) 501, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 502 or a program loaded from a storage section 508 into a random access memory (RAM) 503. In the RAM 503, various programs and data required for the operation of the system 500 are also stored. The CPU 501, the ROM 502, and the RAM 503 are connected to each other through a bus 504. An input / output (I / O) interface 505 is also connected to the bus 504.

[0101] The following components are connected to the I / O interface 505: an input section 506 including a keyboard, a mouse, etc.; an output section 507 including a cathode ray tube (CRT), a liquid crystal display (LCD), etc. and a speaker, etc.; a storage section 508 including a hard disk, etc.; and a communication section 509 including a network interface card such as a LAN card, a modem, etc. The communication section 509 performs communication processing via a network such as the Internet. A drive 510 is also connected to the I / O interface 505 as needed. A removable medium 511, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., is mounted on the drive 510 as needed so that a computer program read from it is installed into the storage section 508 as needed.

[0102] Specifically, according to the embodiments disclosed in the present invention, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, the embodiments disclosed in the present invention include a computer program product, which includes a computer program carried on a computer-readable medium, and the computer program includes program codes for performing the methods shown in the flowcharts. In such an embodiment, the computer program can be downloaded and installed from a network through the communication section 509, and / or installed from the removable medium 511. When the computer program is executed by a central processing unit (CPU) 501, the above functions defined in the system of the present invention are executed.

[0103] It should be noted that the computer-readable medium shown in the present invention can be a computer-readable signal medium, a computer-readable storage medium, or any combination of the two. A computer-readable storage medium can be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the above. More specific examples of a computer-readable storage medium can include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present invention, a computer-readable storage medium can be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. In the present invention, a computer-readable signal medium can include a data signal propagated in a baseband or as part of a carrier wave, which carries computer-readable program code. Such a propagated data signal can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. A computer-readable signal medium can also be any computer-readable medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or in conjunction with an instruction execution system, apparatus, or device. The program code contained on a computer-readable medium can be transmitted using any appropriate medium, including but not limited to: wireless, wire, and optical cable, etc., or any suitable combination of the above.

[0104] The flowcharts and block diagrams in the accompanying drawings illustrate the possible architectures, functions, and operations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram can represent a module, a program segment, or a part of code that contains one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than that marked in the accompanying drawings. For example, two consecutive blocks shown may actually be executed substantially in parallel, and they may sometimes be executed in the reverse order, depending on the functions involved. It should also be noted that each block in a block diagram or flowchart, and the combination of blocks in a block diagram or flowchart, can be implemented by a dedicated hardware-based system that performs the specified functions or operations, or can be implemented by a combination of dedicated hardware and computer instructions.

[0105] The modules and / or units involved in this embodiment can be implemented in software or in hardware. The described modules and / or units can also be provided in a processor. For example, it can be described as: a processor includes a waveform acquisition module, a sequential marking module, and a level statistics module. Among them, the names of these modules do not constitute a limitation to the module itself in some cases.

[0106] As another aspect, the present invention also provides a computer-readable medium, which can be included in the device described in the above embodiment; or it can exist alone without being assembled into the device. The above computer-readable medium carries one or more programs. When the one or more programs are executed by the device, the device includes: acquiring a target waveform diagram corresponding to a target key to be measured in a key circuit, where the target waveform diagram includes at least two output levels; sequentially marking the at least two output levels to obtain a level sequence code, and one level sequence code corresponds to one output level; respectively counting all the output levels at odd positions and all the output levels at even positions in the level sequence code to obtain a test mechanism for the target key to be measured, and testing the target key to be measured based on the test mechanism.

[0107] According to the technical solution of this embodiment, by analyzing all the output levels at odd positions and all the output levels at even positions in the level sequence code respectively, the output rules of all the output levels at odd positions and the output rules of all the output levels at even positions are obtained. Further, the test mechanism of the target key to be measured is determined through the output rules of all the output levels at odd positions and the output rules of all the output levels at even positions, so as to test the target key to be measured through the test mechanism. This solution achieves the beneficial effects of simplifying the test process and improving the test efficiency of the key circuit.

[0108] The above specific implementation manners do not constitute a limitation to the protection scope of the present invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can occur depending on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principle of the present invention should be included within the protection scope of the present invention.

Claims

1. A testing method for a key circuit, characterized in that, Including: Obtain a target waveform diagram corresponding to a target button to be measured in a button circuit, where the target waveform diagram includes at least two output levels; Sequentially label at least two of the output levels to obtain a level sequence code, and one level sequence code corresponds to one of the output levels; Separate statistics are performed on the output levels of all odd positions and all even positions in the level sequence code to obtain a test mechanism for the target button to be measured, and the target button to be measured is tested based on the test mechanism; Among them, the sequentially labeling at least two of the output levels to obtain a level sequence code includes: Determine the starting code value of the level sequence code, and the starting code value is even or odd; Sequentially label at least two of the output levels according to whether the starting code value is even or the starting code value is odd to obtain the level sequence code; Among them, when the starting code value is even, the output levels corresponding to all even positions in the level sequence code are preset output levels, and the output levels corresponding to all odd positions in the level sequence code include high levels or low levels; The separate statistics are performed on the output levels of all odd positions and all even positions in the level sequence code to obtain a test mechanism for the target button to be measured, including: Based on the output time of the output level, perform number system conversion on the high level or low level corresponding to all odd positions using a number system conversion algorithm to obtain the test codes of all odd positions in the level sequence code; Obtain a test mechanism for the target button to be measured according to the test codes of all odd positions and the preset output levels of all even positions; Among them, the testing the target button to be measured based on the test mechanism includes: Obtain the actual codes of all odd positions in the level sequence code of the target button to be measured, and obtain the actual output levels of all even positions in the level sequence code; When the test codes of all odd positions are consistent with the actual codes, and the preset output levels of all even positions are consistent with the actual output levels, determine that the test result of the target button to be measured is qualified; When the test codes of all odd positions are inconsistent with the actual codes, or the preset output levels of all even positions are inconsistent with the actual output levels, determine that the test result of the target button to be measured is unqualified.

2. The test method for the key circuit according to claim 1, characterized in that, The performing number system conversion on the high level or low level corresponding to all odd positions using a number system conversion algorithm to obtain the test codes of all odd positions in the level sequence code includes: Sequentially label all odd positions to obtain an odd position sequence code, where the odd position sequence code includes at least two, and one odd position sequence code corresponds to one low level or one high level; Represent each low level or high level in the odd position sequence code in binary to obtain the binary code corresponding to the odd position sequence code; Based on the number system conversion algorithm, perform number system conversion on the binary code to obtain the test codes of all odd positions.

3. The test method for the key circuit according to claim 1, characterized in that After testing the target button to be measured based on the test mechanism, it further includes: Obtain the test results of each test key in the key circuit; When the test result of each test key is qualified, determine that the test result of the key circuit is qualified; When the test result of any one of the test keys in the key circuit is unqualified, determine that the test result of the key circuit is unqualified, and display the key identifier corresponding to the test key whose test result is unqualified; 4. The test method for the key circuit according to claim 1, characterized in that, When the starting code value is odd, the output levels corresponding to all odd positions in the level sequence code are preset output levels, and the output levels corresponding to all even positions in the level sequence code include high level or low level; The separately counting the output levels of all odd positions and all even positions in the level sequence code to obtain the test mechanism of the target key to be tested includes: Based on the binary conversion algorithm, convert the high level or low level corresponding to all even positions to obtain the test codes of all even positions in the level sequence code; Obtain the test mechanism of the target key to be tested according to the test codes of all even positions and the preset output levels of all odd positions; 5. A test device for a key circuit, characterized in that Include: A waveform acquisition module, configured to acquire a target waveform diagram corresponding to a target key to be tested in a key circuit, where the target waveform diagram includes at least two output levels; A sequence marking module, configured to sequentially mark at least two of the output levels to obtain a level sequence code, and one level sequence code corresponds to one output level; A level statistics module, configured to separately count the output levels of all odd positions and all even positions in the level sequence code to obtain the test mechanism of the target key to be tested, and test the target key to be tested based on the test mechanism; Wherein, the sequence marking module includes a code value determination unit and a sequence marking unit; The code value determination unit is configured to determine the starting code value of the level sequence code, and the starting code value is even or odd; The sequence marking unit is configured to sequentially mark at least two of the output levels according to whether the starting code value is even or the starting code value is odd to obtain a level sequence code; Wherein, when the starting code value is even, the output levels corresponding to all even positions in the level sequence code are preset output levels, and the output levels corresponding to all odd positions in the level sequence code include high level or low level; the level statistics module includes a binary conversion unit and a mechanism obtaining unit; The binary conversion unit is configured to convert the high level or low level corresponding to all odd positions based on the binary conversion algorithm to obtain the test codes of all odd positions in the level sequence code; The mechanism obtaining unit is configured to obtain the test mechanism of the target key to be tested according to the test codes of all odd positions and the preset output levels of all even positions; Wherein, the level statistics module further includes a first acquisition unit and a test comparison unit; The first acquisition unit is configured to acquire the actual codes of all odd positions in the level sequence code of the target key to be tested, and acquire the actual output levels of all even positions in the level sequence code; The test comparison unit is configured to determine that the test result of the target key to be tested is qualified when the test codes at all odd positions are consistent with the actual codes and the preset output levels at all even positions are consistent with the actual output levels; and is further configured to determine that the test result of the target key to be tested is unqualified when the test codes at all odd positions are inconsistent with the actual codes or the preset output levels at all even positions are inconsistent with the actual output levels.

6. An electronic device, characterized in that, The electronic device includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein, the memory stores a computer program executable by the at least one processor, and when the computer program is executed by the at least one processor, the at least one processor is enabled to execute the test method of the key circuit according to any one of claims 1-4.

7. A computer-readable storage medium having a computer program stored thereon, characterized in that, When executed by the processor, the program implements the test method of the key circuit according to any one of claims 1-4.

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