A control circuit and method thereof, and memory

Abstract

The present disclosure provides a control circuit and a method thereof, and a memory, wherein the control circuit includes: a clock generation module, which is used to generate a first clock signal, a second clock signal, and a third clock signal according to an external clock signal; a command decoding module, which is used to decode a command address signal to obtain a decoding signal, and sample the decoding signal according to a third clock signal to obtain a read command signal; a command processing module, which is used to delay the read command signal according to the third clock signal and a read delay signal to obtain a read control signal; and a command control module, which is used to sample and pulse widen the read control signal according to the first clock signal and the second clock signal to obtain a target control signal. In this way, the interval time between the command address signal and the target control signal meets the preset timing condition, so that when controlling the on / off of the NT ODT function, the energy loss and reflection in the transmission process can be reduced, and the signal integrity can be improved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a control circuit and method thereof, and a memory. Background Art

[0002] With the continuous development of semiconductor technology, people have put forward higher and higher requirements for data transmission speed when manufacturing and using computers and other equipment. In order to obtain faster data transmission speed, a series of devices such as memory that can transmit data at double data rate (DDR) have emerged.

[0003] In a dynamic random access memory (DRAM) chip, for the on-die termination (ODT) function of the chip, the impedance matching of the terminal resistor needs to meet the preset timing conditions. However, due to the different delay times on the transmission lines, there is a deviation in the timing, which affects the ODT function of the DQ module and reduces the signal integrity (SI). Summary of the invention

[0004] Embodiments of the present disclosure provide a control circuit and method thereof, and a memory.

[0005] In a first aspect, an embodiment of the present disclosure provides a control circuit, the control circuit comprising a clock generation module, a command decoding module, a command processing module and a command control module, the clock generation module is respectively connected to the command decoding module, the command processing module and the command control module, and the command processing module is also connected to the command control module, wherein:

[0006] A clock generation module, used for receiving an external clock signal, and generating a first clock signal, a second clock signal and a third clock signal according to the external clock signal; wherein the first clock signal is earlier than the second clock signal, and the second clock signal is earlier than the third clock signal;

[0007] A command decoding module, used for receiving a command address signal and a third clock signal, decoding the command address signal to obtain a decoding signal, and sampling the decoding signal according to the third clock signal to obtain a read command signal;

[0008] A command processing module, configured to receive a third clock signal, a read command signal, and a read delay signal, and perform delay processing on the read command signal according to the third clock signal and the read delay signal to obtain a read control signal, wherein the read delay signal includes read delay (RL) information;

[0009] A command control module is used to receive a first clock signal, a second clock signal and a read control signal, and to sample and pulse widen the read control signal according to the first clock signal and the second clock signal to obtain a target control signal; wherein the interval time between the command address signal and the target control signal meets a preset timing condition, and the target control signal is used to control the conduction state of the terminal resistance.

[0010] In some embodiments, the control circuit further includes a mode register module, and the mode register module is connected to the command processing module, wherein:

[0011] The mode register module is used to set the RL information, generate a read delay signal including the RL information, and provide the read delay signal to the command processing module.

[0012] In some embodiments, a clock generation module is used to perform frequency division and first clock delay processing on an external clock signal to obtain a first clock odd signal and a first clock even signal, wherein the clock periods of the first clock odd signal and the first clock even signal are both twice the clock period of the external clock signal, and the first clock signal is composed of the first clock odd signal and the first clock even signal, and the phase difference between the first clock odd signal and the first clock even signal is 180 degrees; and

[0013] The clock generation module is further used to perform frequency division and second clock delay processing on the external clock signal to obtain a second clock odd signal and a second clock even signal, wherein the clock period of the second clock odd signal and the second clock even signal are both twice the clock period of the external clock signal, and the second clock signal is composed of the second clock odd signal and the second clock even signal, and the phase difference between the second clock odd signal and the second clock even signal is 180 degrees;

[0014] The clock generation module is also used to divide the external clock signal and perform third clock delay processing to obtain a third clock odd signal and a third clock even signal, wherein the clock periods of the third clock odd signal and the third clock even signal are both twice the clock period of the external clock signal, and the third clock signal is composed of the third clock odd signal and the third clock even signal, and the phase difference between the third clock odd signal and the third clock even signal is 180 degrees.

[0015] In some embodiments, the delay time corresponding to the first clock delay process is less than the delay time corresponding to the second clock delay process; the delay time corresponding to the second clock delay process is less than the delay time corresponding to the third clock delay process.

[0016] In some embodiments, the command decoding module is used to decode the command address signal to obtain a decoding odd signal and a decoding even signal; sample the decoding odd signal according to the third clock odd signal to obtain a read command odd signal; and sample the decoding even signal according to the third clock even signal to obtain a read command even signal;

[0017] A command processing module, configured to delay a read command odd signal according to a third clock odd signal and a read delay signal to obtain a read control odd signal; and to delay a read command even signal according to a third clock even signal and a read delay signal to obtain a read control even signal;

[0018] Among them, the decoding signal is composed of a decoding odd signal and a decoding even signal, the read command signal is composed of a read command odd signal and a read command even signal, and the read control signal is composed of a read control odd signal and a read control even signal.

[0019] In some embodiments, the command control module includes a first control module, a second control module, a logic module and a delay adjustable module, wherein:

[0020] A first control module is used to receive a first clock odd signal, a second clock odd signal and a read control odd signal, and perform sampling and pulse widening processing on the read control odd signal according to the first clock odd signal and the second clock odd signal to obtain a first control signal;

[0021] A second control module is used to receive the first clock even signal, the second clock even signal and the read control even signal, and perform sampling and pulse widening processing on the read control even signal according to the first clock even signal and the second clock even signal to obtain a second control signal;

[0022] A logic module, used for performing a logic operation on the first control signal and the second control signal to obtain an initial control signal;

[0023] The delay adjustable module is used for receiving the mode control signal and the initial control signal, and performing delay processing on the initial control signal according to the mode control signal to obtain the target control signal.

[0024] In some embodiments, the logic module includes a first OR gate, wherein:

[0025] The first input end of the first OR gate is connected to the output end of the first control module for receiving a first control signal; the second input end of the first OR gate is connected to the output end of the second control module for receiving a second control signal;

[0026] The output end of the first OR gate is connected to the input end of the delay adjustable module for outputting an initial control signal.

[0027] In some embodiments, the adjustable delay module includes K delay units, where K is an integer greater than 0, wherein:

[0028] The delay adjustable module is used to determine a target number of delay units from K delay units according to a mode control signal, and to delay an initial control signal through the target number of delay units to obtain a target control signal.

[0029] In some embodiments, the first control module includes a first sampling module, a second sampling module and a third sampling module, wherein:

[0030] A first sampling module, used for sampling the read control odd signal according to the second clock odd signal to obtain a first sampling odd signal;

[0031] A second sampling module, used for sampling the first sampling odd signal according to the first clock odd signal to obtain a second sampling odd signal;

[0032] A third sampling module, used for sampling and pulse widening the second sampling odd signal according to the first clock odd signal to obtain a first control signal;

[0033] The second control module includes a fourth sampling module, a fifth sampling module and a sixth sampling module, wherein:

[0034] a fourth sampling module, configured to sample and process the read control even signal according to the second clock even signal to obtain a first sampling even signal;

[0035] a fifth sampling module, configured to perform sampling processing on the first sampling even signal according to the first clock even signal to obtain a second sampling even signal;

[0036] The sixth sampling module is used to sample and perform pulse widening processing on the second sampling even signal according to the first clock even signal to obtain a second control signal.

[0037] In some embodiments, the third sampling module includes a first sampling submodule and at least one second sampling submodule, wherein:

[0038] A first sampling submodule, configured to perform sampling processing on the second sampling odd signal according to the first clock odd signal to obtain a third sampling odd signal;

[0039] at least one second sampling submodule, configured to perform logic processing on the third sampling odd signal and the second sampling odd signal to obtain a fourth sampling odd signal, and perform sampling processing on the fourth sampling odd signal according to the first clock odd signal to obtain a first control signal;

[0040] The sixth sampling module includes a third sampling submodule and at least one fourth sampling submodule, wherein:

[0041] A third sampling submodule, configured to perform sampling processing on the second sampling even signal according to the first clock even signal to obtain a third sampling even signal;

[0042] At least one fourth sampling submodule is used to perform logic processing according to the third sampling even signal and the second sampling even signal to obtain a fourth sampling even signal, and perform sampling processing on the fourth sampling even signal according to the first clock even signal to obtain a second control signal.

[0043] In some embodiments, the first sampling module includes a first trigger, wherein an input terminal of the first trigger is used to receive a read control odd signal, a clock terminal of the first trigger is used to receive a second clock odd signal, and an output terminal of the first trigger is used to output a first sampling odd signal;

[0044] The second sampling module includes a second trigger, wherein the input end of the second trigger is used to receive the first sampling odd signal, the clock end of the second trigger is used to receive the first clock odd signal, and the output end of the second trigger is used to output the second sampling odd signal.

[0045] In some embodiments, the first sampling submodule includes a third trigger, wherein an input terminal of the third trigger is used to receive the second sampling odd signal, a clock terminal of the third trigger is used to receive the first clock odd signal, and an output terminal of the third trigger is used to output the third sampling odd signal;

[0046] The second sampling submodule includes a second OR gate and a fourth trigger, wherein the first input end of the second OR gate is connected to the second sampling odd signal as the first input end of the second sampling submodule, the second input end of the second OR gate is connected to the output end of the previous second sampling submodule as the second input end of the second sampling submodule, the output end of the second OR gate is connected to the input end of the fourth trigger, the clock end of the fourth trigger is connected to the first clock odd signal as the clock end of the second sampling submodule, and the output end of the fourth trigger is used as the output end of the second sampling submodule to output the intermediate signal.

[0047] In some embodiments, when the number of at least one second sampling submodule is N, the first input terminal of the i-th second sampling submodule is connected to the second sampling odd signal, the second input terminal of the i-th second sampling submodule is connected to the i-th input signal, the clock terminal of the i-th second sampling submodule is connected to the first clock odd signal, and the output terminal of the i-th second sampling submodule is used to output the i-th intermediate signal;

[0048] When i is equal to 1, the i-th input signal is the third sampling odd signal; when i is greater than 1, the i-th input signal is the i-1-th intermediate signal; and when i is equal to N, the i-th intermediate signal is the first control signal, wherein i is an integer greater than or equal to 1 and less than or equal to N.

[0049] In some embodiments, the fourth sampling module includes a fifth trigger, wherein the input terminal of the fifth trigger is used to receive the read control even signal, the clock terminal of the fifth trigger is used to receive the second clock even signal, and the output terminal of the fifth trigger is used to output the first sampling even signal;

[0050] The fifth sampling module includes a sixth trigger, wherein the input end of the sixth trigger is used to receive the first sampling even signal, the clock end of the sixth trigger is used to receive the first clock even signal, and the output end of the sixth trigger is used to output the second sampling even signal.

[0051] In some embodiments, the third sampling submodule includes a seventh trigger, wherein the input end of the seventh trigger is used to receive the second sampling even signal, the clock end of the seventh trigger is used to receive the first clock even signal, and the output end of the seventh trigger is used to output the third sampling even signal;

[0052] The fourth sampling submodule includes a second OR gate and an eighth trigger, wherein the first input end of the second OR gate is connected to the second sampling even signal as the first input end of the fourth sampling submodule, the second input end of the second OR gate is connected to the output end of the previous fourth sampling submodule as the second input end of the fourth sampling submodule, the output end of the second OR gate is connected to the input end of the eighth trigger, the clock end of the eighth trigger is connected to the first clock even signal as the clock end of the fourth sampling submodule, and the output end of the eighth trigger is used as the output end of the fourth sampling submodule to output the intermediate signal.

[0053] In some embodiments, when the number of at least one fourth sampling submodule is M, the first input terminal of the i-th fourth sampling submodule is connected to the second sampling even signal, the second input terminal of the i-th fourth sampling submodule is connected to the i-th input signal, the clock terminal of the i-th fourth sampling submodule is connected to the first clock even signal, and the output terminal of the i-th fourth sampling submodule is used to output the i-th intermediate signal; wherein, when i is equal to 1, the i-th input signal is the third sampling even signal; when i is greater than 1, the i-th input signal is the i-1th intermediate signal; and when i is equal to M, the i-th intermediate signal is the second control signal, wherein i is an integer greater than or equal to 1 and less than or equal to M.

[0054] In a second aspect, an embodiment of the present disclosure provides a control method, the method comprising:

[0055] An external clock signal is received through a clock generation module, and a first clock signal, a second clock signal and a third clock signal are generated according to the external clock signal; wherein the first clock signal is earlier than the second clock signal, and the second clock signal is earlier than the third clock signal;

[0056] The command address signal and the third clock signal are received by the command decoding module, and the command address signal is decoded to obtain a decoded signal, and the decoded signal is sampled according to the third clock signal to obtain a read command signal;

[0057] Receiving a third clock signal, a read command signal and a read delay signal through a command processing module, and performing delay processing on the read command signal according to the third clock signal and the read delay signal to obtain a read control signal, wherein the read delay signal includes RL information;

[0058] A first clock signal, a second clock signal and a read control signal are received through a command control module, and the read control signal is sampled and pulse widened according to the first clock signal and the second clock signal to obtain a target control signal; wherein the interval time between the command address signal and the target control signal meets a preset timing condition, and the target control signal is used to control the conduction state of the terminal resistance.

[0059] In a third aspect, an embodiment of the present disclosure provides a memory, which at least includes a control circuit as described in any one of the first aspects.

[0060] The disclosed embodiment provides a control circuit and method thereof, and a memory, in which a clock generation module is respectively connected to a command decoding module, a command processing module, and a command control module, and the command processing module is also connected to the command control module. Specifically, the clock generation module is used to receive an external clock signal, and generate a first clock signal, a second clock signal, and a third clock signal according to the external clock signal; wherein the first clock signal is earlier than the second clock signal, and the second clock signal is earlier than the third clock signal; the command decoding module is used to receive a command address signal and a third clock signal, and decode the command address signal to obtain a decoding signal, and sample the decoding signal according to the third clock signal to obtain a read command signal; the command processing module is used to receive the third clock signal, a read command signal, and a read delay signal, and delay the read command signal according to the third clock signal and the read delay signal to obtain a read control signal; the command control module is used to receive the first clock signal, the second clock signal, and the read control signal, and sample and pulse widen the read control signal according to the first clock signal and the second clock signal to obtain a target control signal; wherein the target control signal is used to control the conduction state of the terminal resistor. In this way, since the read delay signal includes RL information, and the RL information is associated with the preset timing conditions, when the interval time between the command address signal and the target control signal meets the preset timing conditions, the resistance value of the terminal resistor can be changed in time within the specified time in accordance with the technical standards, thereby not only avoiding signal conflicts during the transmission process, but also reducing the energy loss and reflection of the signal during the transmission process, thereby improving the signal integrity; in addition, after receiving the first clock signal and the second clock signal, the command control module can speed up the processing speed by using the relatively fast first clock signal to send out the signal sampled by the relatively slow second clock signal, thereby improving the performance of the memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0061] Figure 1 It is a structural schematic diagram of an ODT functional circuit;

[0062] Figure 2A A schematic diagram of the structure of an ODT functional circuit in a read operation;

[0063] Figure 2B A schematic diagram of the structure of an ODT functional circuit in a write operation;

[0064] Figure 3 A schematic diagram of the control timing of the ODT function during a read operation of a non-target chip;

[0065] Figure 4 A schematic diagram of the structure of a control circuit provided in an embodiment of the present disclosure;

[0066] Figure 5 A schematic diagram of the structure of another control circuit provided in an embodiment of the present disclosure;

[0067] Figure 6 A schematic diagram of the structure of a command control module provided in an embodiment of the present disclosure;

[0068] Fig. 7A A schematic diagram of the structure of a delay adjustable module provided in an embodiment of the present disclosure;

[0069] Figure 7B A detailed structural diagram of a delay adjustable module provided in an embodiment of the present disclosure;

[0070] Fig. 8A A schematic diagram of the composition structure of a first control module provided in an embodiment of the present disclosure;

[0071] Figure 8B A schematic diagram of the structure of a second control module provided in an embodiment of the present disclosure;

[0072] Fig. 9 A detailed structural diagram of a control circuit provided in an embodiment of the present disclosure;

[0073] Fig.10 A schematic diagram of the working timing of a control circuit provided in an embodiment of the present disclosure;

[0074] Fig.11 A flow chart of a control method provided by an embodiment of the present disclosure;

[0075] Fig.12 A schematic diagram of the composition structure of a memory provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0076] The following will be combined with the drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. It is understood that the specific embodiments described herein are only used to explain the relevant application, rather than to limit the application. It should also be noted that, for the convenience of description, only the parts related to the relevant application are shown in the drawings.

[0077] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0078] In the following description, reference is made to “some embodiments”, which describe a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0079] It should be pointed out that the terms "first\second\third" involved in the embodiments of the present disclosure are only used to distinguish similar objects and do not represent a specific ordering of the objects. It can be understood that "first\second\third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of the present disclosure described here can be implemented in an order other than that illustrated or described here.

[0080] It should also be noted that the high level and low level used in the signal involved in the embodiments of the present disclosure refer to the logic level of the signal. There is a difference between a signal having a high level and a signal having a low level. For example, a high level may correspond to a signal having a first voltage, and a low level may correspond to a signal having a second voltage. In some embodiments, the first voltage is greater than the second voltage. In addition, the logic level of the signal may be different from or opposite to the described logic level. For example, a signal described as having a logic "high" level may alternatively have a logic "low" level, and a signal described as having a logic "low" level may alternatively have a logic "high" level.

[0081] With the rapid development of semiconductor technology, the transmission rate of signals is getting faster and faster, resulting in increasingly prominent signal integrity issues. In the process of high-speed signal transmission, in order to better improve the signal integrity of data, in the third-generation double data rate (Double Data Rate 3, DDR3) and fourth-generation double data rate (Double Data Rate 4, DDR4) designs, on-die termination (ODT) resistors are added separately, that is, the transmission line is impedance matched by ODT resistors, which reduces the energy loss and reflection of the signal during transmission, thereby ensuring the signal integrity received by the receiving end.

[0082] Taking DDR4 DRAM as an example, DDR4 DRAM supports ODT function, which can adjust the terminal resistance (also called "termination resistance") of each device's DQ, DQS_t / c, DM_n and TDQS_t / c ports through ODT pin control, write commands or mode registers to set default resistance values. In addition, the purpose of ODT function is to reduce reflections and effectively improve the signal integrity on the memory interface by independently controlling the terminal resistance of all or any DRAM by the controller. Figure 1 As shown, it shows a structural schematic diagram of an ODT functional circuit provided by the related art. Figure 1In the embodiment, the ODT functional circuit may at least include a switch S1, a terminal resistor RTT and a power supply VDDQ. One end of the switch S1 is connected to one end of the terminal resistor RTT, the other end of the terminal resistor RTT is connected to the power supply VDDQ, and the other end of the switch S1 is connected to other circuits (To other circuity like), as well as DQ, DQS, DM, and TDQS ports. It should be noted that DQS can be a pair of differential data selection signals DQS_t and DQS_c, and TDQS can be a pair of differential data selection signals TDQS_t and TDQS_c; in other words, DDR4 DRAM only supports data selection signals as differential signals, and does not support data selection signals of a single signal.

[0083] in addition, Figure 1 The switch S1 in is controlled by the ODT control logic. The ODT control logic contains the external ODT pin input, mode register configuration, and other control information. The value of RTT is controlled by the configuration information in the mode register. In addition, if RTT_NOM is disabled in self-refresh mode or MR1{A10,A9,A8}={0,0,0}, the control of the ODT pin is ignored.

[0084] Specifically, when the configuration bits MR1{A10,A9,A8} or MR2{A10:A9} or MR5{A8:A6} are not all zero, the ODT function is enabled. In this case, the actual resistance of the ODT resistor is determined by these configuration bits. After entering the self-refresh mode, the DDR4 DRAM automatically disables the ODT function, and the terminal resistor is set to high impedance (Hi-Z) to discard all mode register settings.

[0085] For example, in the application scenario of the fourth-generation low-power double data rate 4 (LPDDR4) DRAM, the non-target on-die termination (NT ODT) function can improve the SI performance of write operations in high-speed application scenarios. For the two-rank system, the NT ODT function is turned off for read / write access of the target rank, and the ODT function of the non-target rank is turned on to improve the SI performance.

[0086] Take the NT-ODT function on / off (On / Off) during read operation in the Two Rank system as an example. Figure 2A A schematic diagram of the structure of an ODT functional circuit in a read operation is shown. Figure 2BFIG. 1 shows a schematic diagram of the structure of an ODT functional circuit in a write operation. In which, R0 represents the target chip (Target), R1 represents the non-target chip (Non-Target), and AP represents the system on chip (System on Chip, SOC). For the target chip, Figure 2A In the read operation, the target chip transmits data outward, and no terminal resistor is needed to eliminate reflection. T In the off state; Figure 2B In the write operation, the target chip receives data and needs terminal resistance to eliminate reflection, so ODT T Is turned on.

[0087] Further, Figure 3 FIG. 1 shows a control timing diagram of the ODT function during a read operation of a non-target chip. Figure 3 As shown, t1 represents ODTLon_rd, t2 represents tODTon.Max, t3 represents tODTon.Min; t4 represents ODTLoff_rd, t5 represents tODToff.Max, and t6 represents tODToff.Min. Among them, when the resistance of the terminal resistor switches from the ODT high-impedance state to the ODT on state, it is necessary to wait for ODTLon_rd clock cycles; considering that there is a time jitter value when the state switches, the maximum and minimum values ​​of the time jitter value can be set here, which are: tODTon.Max and tODTon.Min. Correspondingly, when the resistance of the terminal resistor switches from the ODT on state to the ODT high-impedance state, it is necessary to wait for ODTLoff_rd clock cycles; considering that there is a time jitter value when the state switches, the maximum and minimum values ​​of the time jitter value can be set here, which are: tODToff.Max and tODToff.Min.

[0088] Exemplarily, Table 1 shows the correspondence between the ODTLon_rd delay time (ODTLon_rd Latency), the ODTLoff_rd delay time (ODTLoff_rd Latency) and the lower limit value (Lower Clock FrequencyLimit) of the operating clock frequency of the DRAM and the upper limit value (Upper Clock Frequency Limit) of the clock frequency, and Table 2 shows the timing requirements that need to be met when ODT is turned on and off during state switching.

[0089] Table 1

[0090]

[0091]

[0092] Table 2

[0093] Parameter 800~2133MHz Unit tODTon.Min 1.5 Nanoseconds (ns) toD Ton.Max 3.5 Nanoseconds (ns) tODToff.Min 1.5 Nanoseconds (ns) tODToff.Max 3.5 Nanoseconds (ns)

[0094] In simple terms, the resistance value of the terminal resistor can be switched, but how to switch needs to follow certain timing requirements. However, due to the different delay times on the transmission line, there is a deviation in the timing, which makes the resistance state switching abnormal, affecting the NT ODT function of the DQ module, resulting in poor energy loss and reflection effect of the signal during transmission, and even possible signal conflicts, reducing SI performance.

[0095] Based on this, the embodiment of the present disclosure provides a control circuit, the read delay signal includes RL information, and the RL information is associated with the preset timing conditions. Since the interval time between the target control signal and the command address signal obtained after the command address signal passes through the command decoding module, the command processing module and the command control module meets the preset timing conditions, so that the resistance value of the terminal resistor can be changed in time within the specified time in accordance with the technical standards; thereby, not only can signal conflicts during transmission be avoided, but also energy loss and reflection of the signal during transmission can be reduced, thereby improving signal integrity; in addition, since the first clock signal is earlier than the second clock signal, and the second clock signal is earlier than the third clock signal, the processing speed can also be accelerated, and ultimately the performance of the memory can be improved.

[0096] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0097] In one embodiment of the present disclosure, see Figure 4 , which shows a schematic diagram of the composition structure of a control circuit provided by an embodiment of the present disclosure. Figure 4 As shown, the control circuit 40 may include a clock generation module 401, a command decoding module 402, a command processing module 403 and a command control module 404, the clock generation module 401 is respectively connected to the command decoding module 402, the command processing module 403 and the command control module 404, and the command processing module 403 is also connected to the command control module 404, wherein:

[0098] A clock generation module 401 is used to receive an external clock signal and generate a first clock signal, a second clock signal and a third clock signal according to the external clock signal; wherein the first clock signal is earlier than the second clock signal, and the second clock signal is earlier than the third clock signal;

[0099] A command decoding module 402 is used to receive a command address signal and a third clock signal, decode the command address signal to obtain a decoded signal, and sample the decoded signal according to the third clock signal to obtain a read command signal;

[0100] A command processing module 403 is used to receive a third clock signal, a read command signal and a read delay signal, and perform delay processing on the read command signal according to the third clock signal and the read delay signal to obtain a read control signal, wherein the read delay signal includes RL information;

[0101] The command control module 404 is used to receive a first clock signal, a second clock signal and a read control signal, and to sample and pulse widen the read control signal according to the first clock signal and the second clock signal to obtain a target control signal; wherein the interval time between the command address signal and the target control signal meets a preset timing condition, and the target control signal is used to control the conduction state of the terminal resistance.

[0102] It should be noted that in the embodiment of the present disclosure, the control circuit 40 can be applied to a memory. The memory can be, for example, a static random access memory (SRAM), a dynamic random access memory (DRAM), a synchronous dynamic random access memory (SDRAM), a double data rate synchronous dynamic random access memory (DDR SDRAM), etc., which is not specifically limited here.

[0103] It should also be noted that in the embodiment of the present disclosure, the control circuit 40 can specifically be a control circuit applied to the ODT on / off timing (ODT on / off timing), which is mainly implemented for the timing control of NTODT on / off under the read operation (Read Operation). Specifically, the total delay time of the command address signal after passing through the command decoding module 402, the command processing module 403 and the command control module 404 and transmitted to the receiving end (DQ module) of the non-target chip for NT ODT function control needs to meet the preset timing conditions. Among them, there is an association between the preset timing conditions and the RL information. Exemplarily, ODT latency is equal to (RL-n) clock cycles, where the value of n can usually be 2, 3, etc., but is not specifically limited.

[0104] That is to say, in the embodiment of the present disclosure, the interval time between the command address signal and the target control signal meets the preset timing condition. Specifically, the target control signal is a high-level effective pulse signal, wherein the interval time between the command address signal and the rising edge of the target control signal needs to meet the ODT turn-on timing requirement, and the interval time between the command address signal and the falling edge of the target control signal needs to meet the ODT turn-off timing requirement. Here, the ODT turn-on timing requirement can be determined by the sum of ODTLon_rd and tODTon, and the ODT turn-off timing requirement can be determined by the sum of ODTLoff_rd and tODToff.

[0105] In the embodiment of the present disclosure, the value of tODTon needs to be within the range of tODTon.Min and tODTon.Max, and the value of tODToff needs to be within the range of tODToff.Min and tODToff.Max. For the values ​​of tODTon.Min and tODTon.Max, and for the values ​​of tODToff.Min and tODToff.Max, please refer to Table 2. For example, the value of tODTon can be 2.5ns, and the value of tODToff can be 2.5ns, but this is not specifically limited.

[0106] It should also be noted that in the embodiment of the present disclosure, the read delay signal is not a simple delayed signal, but a signal including RL information. In addition, the read delay signal can be a signal or a group of signals, which is not limited here.

[0107] In some embodiments, Figure 4 Based on the control circuit 40 shown, see Figure 5 The control circuit 40 may further include a mode register module 405, which is connected to the command processing module 403, wherein:

[0108] The mode register module 405 is used to set RL information, generate a read delay signal including the RL information, and provide the read delay signal to the command processing module 403 .

[0109] It should be noted that, in the disclosed embodiment, the RL information may be set by the mode register module (ModeRegister), and the read delay signal generated by the Mode Register includes the RL information. In this way, according to the different RL information set by the mode register module 405, the read control signal generated by the command processing module 403 may also be controlled to have different timings; that is, the command processing module 403 may generate read control signals with different timings according to different RL information.

[0110] In the disclosed embodiment, the clock generation module 401 has a clock frequency division function, and the clock generation module 401 also has a clock delay function to generate clock signals with different delay times. In some embodiments, the clock generation module 401 is used to perform frequency division and first clock delay processing on an external clock signal to obtain a first clock odd signal and a first clock even signal; and,

[0111] The clock generation module 401 is further used to perform frequency division and second clock delay processing on the external clock signal to obtain a second clock odd signal and a second clock even signal; and,

[0112] The clock generating module 402 is further used to perform frequency division and third clock delay processing on the external clock signal to obtain a third clock odd signal and a third clock even signal.

[0113] It should be noted that, in the embodiment of the present disclosure, the first clock signal may be composed of a first clock odd signal and a first clock even signal. The frequency of the external clock signal is twice the frequency of the first clock odd signal, and the frequency of the external clock signal is also twice the frequency of the first clock even signal. In other words, the clock periods of the first clock odd signal and the first clock even signal are both twice the clock period of the external clock signal, and the phase difference between the first clock odd signal and the first clock even signal is 180 degrees.

[0114] It should also be noted that, in the disclosed embodiment, the second clock signal may be composed of a second clock odd signal and a second clock even signal. The frequency of the external clock signal is twice the frequency of the second clock odd signal, and the frequency of the external clock signal is also twice the frequency of the second clock even signal. In other words, the clock periods of the second clock odd signal and the second clock even signal are both twice the clock periods of the external clock signal, and the phase difference between the second clock odd signal and the second clock even signal is 180 degrees.

[0115] It should also be noted that, in the disclosed embodiment, the third clock signal may be composed of a third clock odd signal and a third clock even signal. The frequency of the external clock signal is twice the frequency of the third clock odd signal, and the frequency of the external clock signal is also twice the frequency of the third clock even signal. In other words, the clock periods of the third clock odd signal and the third clock even signal are both twice the clock period of the external clock signal, and the phase difference between the third clock odd signal and the third clock even signal is 180 degrees.

[0116] It can be understood that in the embodiment of the present disclosure, the external clock signal can be regarded as a clock source (Clock Source) for sending data to the DQ pad. The clock generation module 401 is used to generate a first clock signal, a second clock signal, and a third clock signal with different phases, and then provided to different modules for use. Among them, the first clock signal and the second clock signal are used as the clock source for the command control module 404 to perform ODT on / off timing, and the third clock signal is used as the clock source for the command decoding module 402 and the command processing module 403 to perform command parsing and RL processing.

[0117] It can also be understood that in the embodiments of the present disclosure, the first clock delay processing, the second clock delay processing and the third clock delay processing can be different, that is, the first clock signal, the second clock signal and the third clock signal are sequential in time. In some embodiments, the delay time corresponding to the first clock delay processing is less than the delay time corresponding to the second clock delay processing; the delay time corresponding to the second clock delay processing is less than the delay time corresponding to the third clock delay processing.

[0118] It should be noted that, in the embodiment of the present disclosure, both the first clock signal and the second clock signal are faster than the third clock signal, that is, the first clock signal and the second clock signal are clock sources used to speed up the command control module 404 to perform ODT on / off timing; in addition, with respect to the first clock signal and the second clock signal, the first clock signal is faster than the second clock signal. Here, the relatively fast first clock signal is used to send out the signal sampled by the relatively slow second clock signal, which can further increase the speed.

[0119] It should also be noted that, in the embodiment of the present disclosure, the first clock signal is earlier than the second clock signal (that is, the first clock signal is faster than the second clock signal), or it can be said that the first clock odd signal is earlier than the second clock odd signal, and the first clock even signal is earlier than the second clock even signal; the second clock signal is earlier than the third clock signal (that is, the second clock signal is faster than the third clock signal), or it can be said that the second clock odd signal is earlier than the third clock odd signal, and the second clock even signal is earlier than the third clock even signal.

[0120] Further, in some embodiments, the command decoding module 402 is used to decode the command address signal to obtain a decoding odd signal and a decoding even signal; sample the decoding odd signal according to the third clock odd signal to obtain a read command odd signal; and sample the decoding even signal according to the third clock even signal to obtain a read command even signal;

[0121] The command processing module 403 is used to delay the read command odd signal according to the third clock odd signal and the read delay signal to obtain a read control odd signal; and to delay the read command even signal according to the third clock even signal and the read delay signal to obtain a read control even signal.

[0122] It should be noted that in the embodiment of the present disclosure, the decoding signal may be composed of a decoding odd signal and a decoding even signal, the read command signal may be composed of a read command odd signal and a read command even signal, and the read control signal may be composed of a read control odd signal and a read control even signal.

[0123] It can be understood that, for the first clock signal, the first clock odd signal can be represented by ClkRd1O, and the first clock even signal can be represented by ClkRd1E; for the second clock signal, the second clock odd signal can be represented by ClkRdO, and the second clock even signal can be represented by ClkRdE; for the third clock signal, the third clock odd signal can be represented by ClkO, and the third clock even signal can be represented by ClkE. Among them, the ClkRd1E / O signal is earlier than the ClkRdE / O signal, and the ClkRdE / O signal is earlier than the ClkE / O signal; that is, the ClkRd1E / O signal is faster than the ClkRdE / O signal, and both the ClkRd1E / O signal and the ClkRdE / O signal are faster than the ClkE / O signal.

[0124] It can also be understood that the command address signal can also be composed of a command address odd signal and a command address even signal. The command address odd signal is decoded according to the command decoding module 402 to obtain a decoded odd signal, and then the decoded odd signal is decoded according to the ClkO signal to obtain a read command odd signal; and the command address even signal is sampled according to the command decoding module 402 to obtain a decoded even signal, and then the decoded even signal is sampled according to the ClkE signal to obtain a read command even signal. Here, the read command odd signal can be represented by RdCmdO, and the read command even signal can be represented by RdCmdE.

[0125] It should also be noted that in the embodiment of the present disclosure, the command address signal can be represented by CA<5:0>. It should be noted that CA<5:0> is not a signal, but represents a group of command address signals, namely CA<5:0>. <0> , CA <1> , CA <2> , CA <3> , CA <4> , CA <5> There are six signals in total. Here, the command address odd signal can be represented by CA<5:0>_O, which specifically represents CA <0> _O, CA <1> _O, CA <2> _O, CA <3> _O, CA <4> _O, CA <5> _O and other signals; the command address even signal can be represented by CA<5:0>_E, which specifically represents CA <0> _E, CA <1> _E, CA <2> _E, CA <3> _E, CA <4> _E, CA <5> _E and other signals.

[0126] In this way, for the command processing module 403, the RdCmdO signal is delayed according to the RL information included in the ClkO signal and the read delay signal to obtain a read control odd signal, which can be represented by Rd1O; and the RdCmdE signal is delayed according to the RL information included in the ClkE signal and the read delay signal to obtain a read control even signal, which can be represented by Rd1E.

[0127] In short, the command address signal is decoded and parsed by the command decoding module 402, and then calculated by the command processing module 403 according to different RL information, and the obtained Rd1E / O signal is output to the command control module 404; and the command processing module 403 can generate Rd1E / O signals with different timings according to different RL information settings, so that the timing control of the NT ODT on / off of the control circuit 40 can meet the preset timing conditions, reduce the energy loss and reflection of the signal during the transmission process, and thus improve the SI performance.

[0128] In some embodiments, for the command control module 404, see Figure 6 , the command control module 404 may include a first control module 411, a second control module 412, a logic module 413 and a delay adjustable module 414, wherein:

[0129] A first control module 411 is used to receive a first clock odd signal, a second clock odd signal and a read control odd signal, and perform sampling and pulse widening processing on the read control odd signal according to the first clock odd signal and the second clock odd signal to obtain a first control signal;

[0130] The second control module 412 is used to receive the first clock even signal, the second clock even signal and the read control even signal, and perform sampling and pulse widening processing on the read control even signal according to the first clock even signal and the second clock even signal to obtain a second control signal;

[0131] The logic module 413 is used to perform a logic operation on the first control signal and the second control signal to obtain an initial control signal;

[0132] The delay adjustable module 414 is used to receive the mode control signal and the initial control signal, and perform delay processing on the initial control signal according to the mode control signal to obtain a target control signal.

[0133] Furthermore, in some embodiments, Figure 6 As shown, the logic module 413 may include a first OR gate a, wherein: the first input end of the first OR gate a is connected to the output end of the first control module 411 for receiving a first control signal; the second input end of the first OR gate a is connected to the output end of the second control module 412 for receiving a second control signal; the output end of the first OR gate a is connected to the input end of the adjustable delay module 414 for outputting an initial control signal.

[0134] In the embodiment of the present disclosure, for the first control signal and the second control signal, if the first control signal is a valid pulse signal, then the second control signal is a low-level signal, and the initial control signal at this time is the first control signal; or, if the second control signal is a valid pulse signal, then the first control signal is a low-level signal, and the initial control signal at this time is the second control signal.

[0135] It should also be noted that, in the embodiment of the present disclosure, the command control module 404 can be used to generate a target control signal to control the opening and closing of the NT ODT function on the DQ module. Among them, the input of the first control module 411 is the first clock odd signal, the second clock odd signal and the read control odd signal, and the output is the first control signal; the input of the second control module 412 is the first clock even signal, the second clock even signal and the read control even signal, and the output is the second control signal; and the output end of the first control module 411 is connected to the first input end of the first OR gate a, the output end of the second control module 412 is connected to the second input end of the first OR gate a, and the output end of the first OR gate a is connected to the input end of the delay adjustable module 414, and the output end of the delay adjustable module 414 is used to output the target control signal.

[0136] Specifically, in Figure 6 In the example, the mode control signal can be used with TrimAdj <n:0>Indicated, the target control signal can be represented by RdOdtEn. In addition, the first clock odd signal can be represented by ClkRd1O, the second clock odd signal can be represented by ClkRdO, the read control odd signal can be represented by Rd1O, and the first control signal can be represented by RdOdtO1; the first clock even signal can be represented by ClkRd1E, the second clock even signal can be represented by ClkRdE, the read control even signal can be represented by Rd1E, and the second control signal can be represented by RdOdtE1.

[0137] Further, in some embodiments, see Fig. 7A , the adjustable delay module 414 may include K delay units, K is an integer greater than 0, wherein:

[0138] The delay adjustable module 414 is used to determine a target number of delay units from the K delay units according to the mode control signal, and perform delay processing on the initial control signal through the target number of delay units to obtain a target control signal.

[0139] It should be noted that, in the embodiment of the present disclosure, for the mode control signal TrimAdj <n:0>, where Trim refers to the test mode, which is controlled by a fuse. In other words, the mode control signal TrimAdj <n:0>It may be generated by a fuse unit in a test mode, or it may be generated by a user by setting a mode register (Mode Register Setting, MRS), and there is no limitation on this.

[0140] It should also be noted that in the embodiment of the present disclosure, since the clocks of the first clock signal and the second clock signal are faster than the third clock signal, the test mode can be used to adjust the delay again when the process changes faster. In addition, it should be noted that for the mode control signal TrimAdj <n:0>, which is not a signal, but represents a group of signals, namely TrimAdj <0> 、TrimAdj <1> 、TrimAdj <2> , …, TrimAdj <n>.

[0141] In a specific embodiment, see Figure 7B , the mode control signal may include K-bit sub-control signals, and there is a corresponding relationship between the j-th delay unit and the j-th sub-control signal, where j is an integer greater than or equal to 0 and less than K, wherein:

[0142] The delay adjustable module 414 is used to determine the jth delay unit to the Kth delay unit as the target number of delay units when the level value of the jth sub-control signal is the first value, and to delay the initial control signal through the jth delay unit to the Kth delay unit to obtain the target control signal.

[0143] In the embodiment of the present disclosure, there is an association relationship between the target number and the mode control signal. Specifically, the mode control signal represents a control code, and the control code can be used to determine how many delay units delay the initial control signal. Different control codes have different target numbers of delay units.

[0144] It can be understood that in the mode control signal, the j-th sub-control signal can be TrimAdj <j>If the level value of the j-th sub-control signal is the first value, it is determined that the level values ​​of the other sub-control signals except the j-th sub-control signal are all the second value; wherein the first value is different from the second value.

[0145] Exemplarily, assuming that the first value is set to logic 1 and the second value is set to logic 0, taking the mode control signal including an eight-bit sub-control signal as an example, the control code can be 0000 0001, 0000 0010, 0000 0100, 0000 1000, or 0001 0000, 0010 0000, 0100 0000, 1000 0000, etc. Here, if the control code is 0000 0100, and j is equal to 5 at this time, then the 5th delay unit, the 6th delay unit and the 7th delay unit, a total of three, are used as the target number of delay units; if the control code is 0001 0000, and j is equal to 3 at this time, then the 3rd delay unit to the 7th delay unit, a total of five, are used as the target number of delay units; if the control code is 1000 0000, and j is equal to 0 at this time, then the 0th delay unit to the 7th delay unit, a total of eight, are used as the target number of delay units.

[0146] Thus, for the mode control signal, when the value of j is different, the corresponding control code is different, and thus the target number of delay units is also different.

[0147] In some embodiments, for the first control module 411, see Fig. 8A , the first control module 411 may include a first sampling module 511, a second sampling module 512 and a third sampling module 513, wherein:

[0148] A first sampling module 511 is used to sample the read control odd signal according to the second clock odd signal to obtain a first sampling odd signal;

[0149] A second sampling module 512, configured to perform sampling processing on the first sampling odd signal according to the first clock odd signal to obtain a second sampling odd signal;

[0150] The third sampling module 513 is used to sample and perform pulse widening processing on the second sampling odd signal according to the first clock odd signal to obtain a first control signal.

[0151] It should be noted that, in the command control module, for the first control module 411, the signal entering the first control module 411 is sampled by the second clock odd signal, and when the signal is output from the first control module 411, the first clock odd signal is used at this time; therefore, the signal sampled by the relatively slow second clock odd signal is sent out with the relatively fast first clock odd signal, which can speed up the processing speed.

[0152] Furthermore, in some embodiments, Fig. 8A As shown, the third sampling module 513 may include a first sampling submodule A1 and at least one second sampling submodule B1, wherein:

[0153] A first sampling submodule A1, configured to sample and process the second sampling odd signal according to the first clock odd signal to obtain a third sampling odd signal;

[0154] At least one second sampling submodule B1 is used to perform logic processing according to the third sampling odd signal and the second sampling odd signal to obtain a fourth sampling odd signal, and sample the fourth sampling odd signal according to the first clock odd signal to obtain a first control signal.

[0155] It should be noted that, in the embodiments of the present disclosure, Fig. 8A As shown, at least one second sampling submodule B1 may include one or more second sampling submodules, which are represented by C1, C2, C3, ..., CN, respectively, and N is a positive integer. The value of N is associated with the pulse width of the first control signal. Specifically, the smaller the value of N, the smaller the pulse width of the first control signal; the larger the value of N, the larger the pulse width of the first control signal (that is, the wider the pulse width).

[0156] Furthermore, in some embodiments, Fig. 8A As shown, the first sampling module 511 may include a first trigger a1, wherein the input end of the first trigger a1 is used to receive the read control odd signal, the clock end of the first trigger a1 is used to receive the second clock odd signal, and the output end of the first trigger a1 is used to output the first sampling odd signal;

[0157] The second sampling module 512 may include a second trigger a2, wherein the input end of the second trigger a2 is used to receive the first sampling odd signal, the clock end of the second trigger a2 is used to receive the first clock odd signal, and the output end of the second trigger a2 is used to output the second sampling odd signal.

[0158] Furthermore, in some embodiments, Fig. 8A As shown, the first sampling submodule A1 may include a third trigger a3, wherein the input end of the third trigger a3 is used to receive the second sampling odd signal, the clock end of the third trigger a3 is used to receive the first clock odd signal, and the output end of the third trigger a3 is used to output the third sampling odd signal.

[0159] Taking the i-th second sampling submodule Ci as an example, the second sampling submodule Ci may include a second OR gate Ui and a fourth trigger Qi, wherein the first input end of the second OR gate Ui (as the first input end of the second sampling submodule Ci) is connected to the second sampling odd signal, the second input end of the second OR gate Ui (as the second input end of the second sampling submodule Ci) is connected to the output end of the previous second sampling submodule Ci-1, the output end of the second OR gate Ui is connected to the input end of the fourth trigger Qi, the clock end of the fourth trigger Qi (as the clock end of the second sampling submodule Ci) is connected to the first clock odd signal, and the output end of the fourth trigger Qi (as the output end of the second sampling submodule Ci) is used to output the intermediate signal.

[0160] It should be noted that no matter the first trigger, the second trigger, the third trigger or the fourth trigger, they can all be D-type triggers (Data Flip-Flop or Delay Flip-Flop, DFF).

[0161] Among them, the D-type flip-flop is an information storage device with memory function and two stable states. It is the most basic logic unit that constitutes a variety of sequential circuits and is also an important unit circuit in digital logic circuits. Here, the D-type flip-flop has two stable states, namely "0" and "1", and can flip from one stable state to another under the action of the clock signal.

[0162] It should also be noted that in the embodiments of the present disclosure, the first trigger, the second trigger, the third trigger or the fourth trigger may include a clock terminal (CK), an input terminal (D) and an output terminal (Q); in addition, a set terminal (SET) and a reset terminal (RST) may also be included, but they are not shown in the figure.

[0163] It should also be noted that, in the embodiment of the present disclosure, the first sampling module 511 uses the second clock odd signal as the clock source, the second sampling module 512 uses the first clock odd signal as the clock source, and the third sampling module 513 (including the first sampling submodule and at least one second sampling submodule) also uses the first clock odd signal as the clock source. In this way, since the first clock odd signal is faster than the second clock odd signal, the signal sampled by the relatively slow second clock odd signal is sent out with the relatively fast first clock odd signal, which can increase the speed, and the pulse widening processing of the first control signal can also be realized through the at least one second sampling submodule.

[0164] For at least one second sampling submodule, in some embodiments, as Fig. 8A As shown, when the number of at least one second sampling submodule is N, still taking the i-th second sampling submodule Ci as an example, the first input end of the i-th second sampling submodule Ci is connected to the second sampling odd signal, the second input end of the i-th second sampling submodule Ci is connected to the i-th input signal, the clock end of the i-th second sampling submodule Ci is connected to the first clock odd signal, and the output end of the i-th second sampling submodule Ci is used to output the i-th intermediate signal.

[0165] In an embodiment of the present disclosure, when i is equal to 1, the i-th input signal is the third sampling odd signal; when i is greater than 1, the i-th input signal is the i-1-th intermediate signal; and when i is equal to N, the i-th intermediate signal is the first control signal, wherein i is an integer greater than or equal to 1 and less than or equal to N.

[0166] It should also be noted that in the embodiment of the present disclosure, the value of N is fixed. Since the command processing module 403 has processed the requirements of different RLs, the output Rd1O signal already contains RL information, so at this time, only a fixed number of second sampling submodules are needed to obtain the first control signal RdOdtO1.

[0167] In some embodiments, for the second control module 412, see Figure 8B , the second control module 412 may include a fourth sampling module 521, a fifth sampling module 522 and a sixth sampling module 523, wherein:

[0168] The fourth sampling module 521 is used to sample the read control even signal according to the second clock even signal to obtain a first sampling even signal;

[0169] A fifth sampling module 522, configured to perform sampling processing on the first sampling even signal according to the first clock even signal to obtain a second sampling even signal;

[0170] The sixth sampling module 523 is used to sample and pulse widen the second sampling even signal according to the first clock even signal to obtain a second control signal.

[0171] It should be noted that, in the command control module, for the second control module 412, the second clock even signal is sampled into the second control module 412, and when the signal is output from the second control module 412, the first clock even signal is used at this time; therefore, the signal sampled by the relatively slow second clock even signal is sent out with the relatively fast first clock even signal, which can speed up the processing speed.

[0172] Furthermore, in some embodiments, Figure 8B As shown, the sixth sampling module 523 may include a third sampling submodule A2 and at least one fourth sampling submodule B2, wherein:

[0173] A third sampling submodule A2, configured to perform sampling processing on the second sampling even signal according to the first clock even signal to obtain a third sampling even signal;

[0174] At least one fourth sampling submodule B2 is used to perform logic processing according to the third sampling even signal and the second sampling even signal to obtain a fourth sampling even signal, and perform sampling processing on the fourth sampling even signal according to the first clock even signal to obtain a second control signal.

[0175] It should be noted that, in the embodiments of the present disclosure, Figure 8B As shown, at least one fourth sampling submodule B2 may include one or more fourth sampling submodules, which are represented by D1, D2, D3, ..., DM, respectively, and M is a positive integer. The value of M is associated with the pulse width of the second control signal. Specifically, the smaller the value of M, the smaller the pulse width of the second control signal; the larger the value of M, the larger the pulse width of the second control signal (that is, the wider the pulse width).

[0176] Furthermore, in some embodiments, Figure 8B As shown, the fourth sampling module 521 may include a fifth trigger b1, wherein the input end of the fifth trigger b1 is used to receive the read control even signal, the clock end of the fifth trigger b1 is used to receive the second clock even signal, and the output end of the fifth trigger b1 is used to output the first sampling even signal;

[0177] The fifth sampling module 522 may include a sixth trigger b2, wherein the input end of the sixth trigger b2 is used to receive the first sampling even signal, the clock end of the sixth trigger b2 is used to receive the first clock even signal, and the output end of the sixth trigger b2 is used to output the second sampling even signal.

[0178] Furthermore, in some embodiments, Figure 8B As shown, the third sampling submodule A2 may include a seventh trigger b3, wherein the input end of the seventh trigger b3 is used to receive the second sampling even signal, the clock end of the seventh trigger b3 is used to receive the first clock even signal, and the output end of the seventh trigger b3 is used to output the third sampling even signal.

[0179] Taking the i-th fourth sampling submodule Di as an example, the fourth sampling submodule Di may include a second OR gate Ui and an eighth trigger Qi, wherein the first input end of the second OR gate Ui (as the first input end of the fourth sampling submodule Di) is connected to the second sampling even signal, the second input end of the second OR gate Ui (as the second input end of the fourth sampling submodule Di) is connected to the output end of the previous fourth sampling submodule Di-1, the output end of the second OR gate Ui is connected to the input end of the eighth trigger Qi, the clock end of the eighth trigger Qi (as the clock end of the fourth sampling submodule Di) is connected to the first clock even signal, and the output end of the eighth trigger Qi (as the output end of the fourth sampling submodule Di) is used to output the intermediate signal.

[0180] It should be noted that no matter the fifth trigger, the sixth trigger, the seventh trigger or the eighth trigger, they can all be D-type triggers.

[0181] It should also be noted that, in the embodiment of the present disclosure, the fourth sampling module 521 uses the second clock even signal as the clock source, the fifth sampling module 522 uses the first clock even signal as the clock source, and the sixth sampling module 523 (including the third sampling submodule and at least one fourth sampling submodule) also uses the first clock even signal as the clock source. In this way, since the first clock even signal is faster than the second clock even signal, the signal sampled by the relatively slow second clock even signal is sent out with the relatively fast first clock even signal, which can increase the speed, and the pulse widening processing of the second control signal can also be realized through the at least one fourth sampling submodule.

[0182] For at least one fourth sampling submodule, in some embodiments, as Figure 8B As shown, when the number of at least one fourth sampling submodule is M, still taking the i-th fourth sampling submodule Di as an example, the first input end of the i-th fourth sampling submodule Di is connected to the second sampling even signal, the second input end of the i-th fourth sampling submodule Di is connected to the i-th input signal, the clock end of the i-th fourth sampling submodule Di is connected to the first clock even signal, and the output end of the i-th fourth sampling submodule Di is used to output the i-th intermediate signal.

[0183] In an embodiment of the present disclosure, when i is equal to 1, the i-th input signal is the third sampled even signal; when i is greater than 1, the i-th input signal is the i-1-th intermediate signal; and when i is equal to M, the i-th intermediate signal is the second control signal, wherein i is an integer greater than or equal to 1 and less than or equal to M.

[0184] It should also be noted that in the embodiment of the present disclosure, the value of M is fixed. Since the command processing module 403 has processed the requirements of different RLs, the output Rd1E signal already contains RL information, so at this time, only the fourth sampling submodule with a fixed number of stages is needed to obtain the first control signal RdOdtE1.

[0185] It should also be noted that in the embodiment of the present disclosure, the values ​​of M and N can be the same. That is to say, the hardware structures of the first control module 411 and the second control module 412 can be the same, except that the input signal and the output signal are different. Among them, when the ClkRd1O signal and the ClkRdO signal are valid pulse signals, and the ClkRd1E signal and the ClkRdE signal are low-level signals, at this time, only the first control signal output by the first control module 411 is a valid signal, and the initial control signal at this time is the first control signal; when the ClkRd1E signal and the ClkRdE signal are valid pulse signals, and the ClkRd1O signal and the ClkRdO signal are low-level signals, at this time, only the second control signal output by the second control module 412 is a valid signal, and the initial control signal at this time is the second control signal. Then, the initial control signal is subjected to adjustable delay processing by the adjustable delay module 414 to obtain the final target control signal.

[0186] The disclosed embodiment provides a control circuit, in which the read delay signal includes RL information, and the RL information is associated with a preset timing condition. Since the interval time between the target control signal and the command address signal obtained after the command address signal passes through the command decoding module, the command processing module and the command control module meets the preset timing condition, so that the resistance value of the terminal resistor can be changed in time within the specified time in accordance with the technical standards; thereby, not only can the signal conflict during the transmission process be avoided, but also the energy loss and reflection of the signal during the transmission process can be reduced, thereby improving the SI performance; in addition, since the first clock signal is earlier than the second clock signal, and for the command control module, the second clock signal is sampled into the command control module, and the first clock signal is used to output the signal from the command control module, so the relatively fast first clock signal is used to send the signal sampled by the relatively slow second clock signal, thereby speeding up the processing speed, and ultimately improving the performance of the memory.

[0187] In another embodiment of the present disclosure, based on the control circuit 40 described in the above embodiment, see Fig. 9 , which shows a detailed structural diagram of a control circuit 40 provided in an embodiment of the present disclosure. Fig. 9 As shown, the control circuit 40 may include a clock receiving module 901, a clock generating (ClkGen) module 902, a command decoding (CmdDec) module 903, a command processing (RdRLCal) module 904, a command control (RdNTOdtCtrl) module 905, a mode register (Mode Register) module 906, a first DQ module 907 and a second DQ module 908. The clock receiving module 901 is used to receive an external clock signal, and the clock receiving module 901 here may be a receiver (represented by Receiver) or a buffer (represented by Buffer).

[0188] It should be noted that, in the embodiment of the present disclosure, the input end of the clock receiving module 901 is the Clk signal, the output end of the clock receiving module 901 is connected to the input end of the clock generating module 902, the first output end of the clock generating module 902 is used to output the ClkRd1E / O signal, the second output end of the clock generating module 902 is used to output the ClkRdE / O signal, and the first output end and the second output end of the clock generating module 902 are both connected to the input end of the command control module 905; in addition, the third output end of the clock generating module 902 is used to output the ClkE / O signal, and the input end of the command decoding module 903 is used to receive CA<5: 0> signal, the output end of the command decoding module 903 is used to output the RdCmdE / O signal, and the output end of the command decoding module 903 is connected to the input end of the command processing module 904, and the clock sources of the command decoding module 903 and the command processing module 904 are both ClkE / O signals; for the command processing module 904, it is also necessary to receive the RL information set by the mode register module 906, and the output end of the command processing module 904 is used to output the Rd1E / O signal; then the input end of the command control module 905 is also connected to the output end of the command processing module 905, and the output end of the command control module 905 is used to output the RdOdtEn signal.

[0189] It should also be noted that, in the disclosed embodiment, for the RL information included in the read delay signal, assuming that the delay time of the command decoding module 903 is a, the delay time of the command processing module 904 is b, the delay time of the command control module 905 is c, and the path delay time from the command control module 905 to the first DQ module 907 or the second DQ module 908 is d, then the sum of a, b, c and d is (RL-n) clock cycles, where n can usually be set to 2, 3, or can also be other positive integers, which are not specifically limited here. In other words, the delay time of the command processing module 904 is b = (RL-n) - acd, where c can be calculated according to the minimum RL; then when RL increases, b can be increased accordingly.

[0190] It can be understood that the embodiments of the present disclosure are mainly aimed at the control circuit implementation of the NT ODT on / off timing in the read operation mode. Among them, the circuit control of the NT ODT in the read operation mode is specifically as follows:

[0191] (1) The Clk signal is the clock source for sending data to the first DQ module 907 and / or the second DQ module 908;

[0192] (2) The ClkE / O signal is generated from the clock generation module 902 and is used as the clock source for command parsing and RL calculations;

[0193] (3) The ClkRd1E / O signal and the ClkRdE / O signal are provided to the command control module 905 and are the clock sources used to speed up the ODT on / off timing;

[0194] (4) The ClkRd1E / O signal is faster than the ClkRdE / O signal;

[0195] (5) The read command will be decoded and analyzed by the command decoding module 903, and then calculated by the command processing module 904 according to different RL information and output to the command control module 905;

[0196] (6) RL information can be output to the command processing module 904 according to the setting of the mode register module 906;

[0197] (7) The command processing module 904 can generate read control Rd1E / O signals with different timings according to different RL information settings.

[0198] It should also be noted that, in the embodiment of the present disclosure, for the command control module 905, its specific circuit structure can be found in Figure 6 , Fig. 7A , Figure 7B , Fig. 8A and Figure 8B The RdOdtEn signal generated by the command control module 905 can control the NT ODT on / off of the DQ module (eg, the first DQ module 907 and / or the second DQ module 908 ).

[0199] Further, based on Fig. 9 The control circuit 40 shown, Fig.10 Figure 2 is a schematic diagram of the working sequence of the control circuit. Fig.10 As shown, Clk is the clock signal, CS is the chip select signal, which is used to characterize the signal that the target chip is selected; the clock cycles of the ClkE / O signal, ClkRdE / O signal and ClkRd1E / O signal are all twice the clock cycle of the Clk signal. In addition, the ClkRd1E / O signal is faster than the ClkRdE / O signal, and the ClkRdE / O signal is faster than the ClkE / O signal, that is, the delay time of the ClkRd1E / O signal compared to the Clk signal is t1, the delay time of the ClkRdE / O signal compared to the Clk signal is t2, and the delay time of the ClkE / O signal compared to the Clk signal is t3, and t3 is greater than t2, and t2 is greater than t1. In this way, not only can the processing speed be accelerated, but also the delay of the clock can be adjusted. If the delay of the previous command address signal input is too large, this module can finally use a faster clock to sample the output, thereby compensating for the previous delay, so that the total delay reaches the preset value.

[0200] It should also be noted that, see Fig.10 , for the command address signal (specifically the read command), after the read command, RL is required to output data through the DQ port; and for the NT ODT on / off, its control logic needs to follow the preset timing conditions. Specifically, for the RdOdtEn signal, it is a high-level valid pulse signal, in which the interval time between the CA<5:0> signal and the rising edge of the RdOdtEn signal needs to meet the ODT turn-on timing requirements (i.e., the sum of ODTLon_rd and tODTon), and the interval time between the CA<5:0> signal and the falling edge of the RdOdtEn signal needs to meet the ODT turn-off timing requirements (i.e., the sum of ODTLoff_rd and tODToff), so that the interval time between the command address signal and the target control signal meets the preset timing conditions.

[0201] The disclosed embodiment provides a control circuit, and the specific implementation of the aforementioned embodiment is described in detail through the above embodiment, from which it can be seen that the read delay signal includes RL information, and the RL information is associated with the preset timing condition. When the interval time between the command address signal and the target control signal meets the preset timing condition, the resistance value of the terminal resistor can be changed in time within the prescribed time in accordance with the technical standards; thereby not only avoiding signal conflicts during transmission, but also reducing the energy loss and reflection of the signal during transmission, thereby improving SI performance, and at the same time speeding up the processing speed, and ultimately improving the performance of the memory.

[0202] In another embodiment of the present disclosure, see Fig.11 , which shows a flow chart of a control method provided by an embodiment of the present disclosure. Fig.11 As shown, the method may include:

[0203] S1101: Receive an external clock signal through a clock generation module, and generate a first clock signal, a second clock signal, and a third clock signal according to the external clock signal.

[0204] S1102: receiving a command address signal and a third clock signal through a command decoding module, decoding the command address signal to obtain a decoded signal, sampling the decoded signal according to the third clock signal to obtain a read command signal.

[0205] S1103: Receive a third clock signal, a read command signal, and a read delay signal through a command processing module, and perform delay processing on the read command signal according to the third clock signal and the read delay signal to obtain a read control signal.

[0206] S1104: Receive the first clock signal, the second clock signal, and the read control signal through the command control module, and perform sampling and pulse widening processing on the read control signal according to the first clock signal and the second clock signal to obtain a target control signal.

[0207] It should be noted that in the embodiment of the present disclosure, the control method is applied to the control circuit 40 described in the above embodiment. In the control circuit 40, a clock generation module, a command decoding module, a command processing module and a command control module may be included, and the clock generation module is connected to the command decoding module, the command processing module and the command control module respectively, and the command processing module is also connected to the command control module.

[0208] It should also be noted that in the embodiment of the present disclosure, the first clock signal is earlier than the second clock signal, and the second clock signal is earlier than the third clock signal. In this way, after receiving the first clock signal and the second clock signal, the command control module can speed up the processing by using the relatively fast first clock signal to send out the signal sampled by the relatively slow second clock signal.

[0209] It should also be noted that in the disclosed embodiment, the read delay signal includes RL information; and the interval time between the command address signal and the target control signal meets the preset timing condition, and the target control signal is used to control the conduction state of the terminal resistor. In this way, the resistance value of the terminal resistor can be changed in time within the prescribed time in accordance with the technical standards, avoiding signal conflicts during the transmission process and improving SI performance.

[0210] Specifically, in the disclosed embodiment, the control method can be applied to the timing control circuit for turning on / off the ODT function, and is mainly implemented for the timing control of turning on / off the NT ODT under the read operation. More specifically, the total delay time of the command address signal after passing through the command decoding module, the command processing module and the command control module to the DQ module of the non-target chip for NT ODT function control needs to meet the preset timing conditions. In addition, there is an association relationship between the preset timing conditions and the RL information.

[0211] In some embodiments, the control circuit may further include a mode register module, wherein the mode register module may set RL information, then generate a read delay signal including the RL information, and provide the read delay signal to the command processing module.

[0212] In some embodiments, the method may further include: sending a target control signal to the DQ module; and controlling a conduction state of a terminal resistor of the DQ module according to the target control signal.

[0213] In some embodiments, controlling the conduction state of the terminal resistor of the DQ module according to the target control signal may include:

[0214] When the target control signal is in a first level state, setting the resistance value of the terminal resistor according to a preset mode register;

[0215] When the target control signal is in the second level state, the terminal resistance is controlled to be in a high impedance state according to the target control signal.

[0216] In the embodiment of the present disclosure, taking DDR4 DRAM as an example, the first level state is a high level, and the second level state is a low level. Exemplarily, the preset mode register may refer to MR1{A10, A9, A8} or MR2{A10:A9} or MR5{A8:A6}. Among them, when the configuration bits of MR1{A10, A9, A8} or MR2{A10:A9} or MR5{A8:A6} are not all zero, the actual resistance value of the terminal resistor is determined by these configuration bits.

[0217] In some embodiments, for the clock generation module, the method may also include: dividing the external clock signal and performing a first clock delay processing to obtain a first clock odd signal and a first clock even signal; and dividing the external clock signal and performing a second clock delay processing to obtain a second clock odd signal and a second clock even signal; and dividing the external clock signal and performing a third clock delay processing to obtain a third clock odd signal and a third clock even signal.

[0218] Among them, the first clock signal is composed of a first clock odd signal and a first clock even signal, and the clock periods of the first clock odd signal and the first clock even signal are twice the clock period of the external clock signal, and the phase difference between the first clock odd signal and the first clock even signal is 180 degrees.

[0219] Among them, the second clock signal is composed of a second clock odd signal and a second clock even signal, and the clock period of the second clock odd signal and the second clock even signal are both twice the clock period of the external clock signal, and the phase difference between the second clock odd signal and the second clock even signal is 180 degrees.

[0220] Among them, the third clock signal is composed of a third clock odd signal and a third clock even signal, and the clock periods of the third clock odd signal and the third clock even signal are twice the clock period of the external clock signal, and the phase difference between the third clock odd signal and the third clock even signal is 180 degrees.

[0221] In the embodiment of the present disclosure, the delay time corresponding to the first clock delay processing is less than the delay time corresponding to the second clock delay processing; the delay time corresponding to the second clock delay processing is less than the delay time corresponding to the third clock delay processing.

[0222] In some embodiments, for the command decoding module, the method also includes: decoding the command address signal to obtain a decoding odd signal and a decoding even signal; sampling the decoding odd signal according to the third clock odd signal to obtain a read command odd signal; and sampling the decoding even signal according to the third clock even signal to obtain a read command even signal.

[0223] In some embodiments, for the command processing module, the method may also include: delaying the read command odd signal according to the third clock odd signal and the read delay signal to obtain a read control odd signal; and delaying the read command even signal according to the third clock even signal and the read delay signal to obtain a read control even signal.

[0224] Among them, the decoding signal is composed of a decoding odd signal and a decoding even signal, the read command signal is composed of a read command odd signal and a read command even signal, and the read control signal is composed of a read control odd signal and a read control even signal.

[0225] In some embodiments, for the command control module, the method may also include: receiving a first clock odd signal, a second clock odd signal and a read control odd signal through a first control module, sampling and pulse widening the read control odd signal according to the first clock odd signal and the second clock odd signal to obtain a first control signal; receiving a first clock even signal, a second clock even signal and a read control even signal through a second control module, sampling and pulse widening the read control even signal according to the first clock even signal and the second clock even signal to obtain a second control signal; performing logical operations on the first control signal and the second control signal through a logic module to obtain an initial control signal; and receiving a mode control signal and an initial control signal through a delay adjustable module, delaying the initial control signal according to the mode control signal to obtain a target control signal.

[0226] In some embodiments, the adjustable delay module includes K delay units, where K is an integer greater than 0. Accordingly, the method may further include: determining a target number of delay units from the K delay units according to the mode control signal, and performing delay processing on the initial control signal through the target number of delay units to obtain a target control signal.

[0227] It can be understood that in the embodiment of the present disclosure, the first control module includes a first sampling module, a second sampling module and a third sampling module. Accordingly, in some embodiments, the method may also include: in the first sampling module, sampling and processing the read control odd signal according to the second clock odd signal to obtain a first sampling odd signal; in the second sampling module, sampling and processing the first sampling odd signal according to the first clock odd signal to obtain a second sampling odd signal; and in the third sampling module, sampling and pulse widening processing the second sampling odd signal according to the first clock odd signal to obtain a first control signal.

[0228] Furthermore, in some embodiments, the third sampling module includes a first sampling submodule and at least one second sampling submodule. Accordingly, the method may also include: in the first sampling submodule, sampling and processing the second sampling odd signal according to the first clock odd signal to obtain a third sampling odd signal; and in at least one second sampling submodule, performing logic processing according to the third sampling odd signal and the second sampling odd signal to obtain a fourth sampling odd signal, and sampling and processing the fourth sampling odd signal according to the first clock odd signal to obtain a first control signal.

[0229] Here, when the number of at least one second sampling submodule is N, the first input end of the i-th second sampling submodule is connected to the second sampling odd signal, the second input end of the i-th second sampling submodule is connected to the i-th input signal, the clock end of the i-th second sampling submodule is connected to the first clock odd signal, and the output end of the i-th second sampling submodule is used to output the i-th intermediate signal; wherein, when i is equal to 1, the i-th input signal is the third sampling odd signal; when i is greater than 1, the i-th input signal is the i-1th intermediate signal; and when i is equal to N, the i-th intermediate signal is the first control signal, wherein i is an integer greater than or equal to 1 and less than or equal to N.

[0230] It can also be understood that in the embodiment of the present disclosure, the second control module includes a fourth sampling module, a fifth sampling module and a sixth sampling module. Accordingly, in some embodiments, the method may also include: in the fourth sampling module, sampling and processing the read control even signal according to the second clock even signal to obtain a first sampling even signal; in the fifth sampling module, sampling and processing the first sampling even signal according to the first clock even signal to obtain a second sampling even signal; and in the sixth sampling module, sampling and pulse widening processing the second sampling even signal according to the first clock even signal to obtain a second control signal.

[0231] Furthermore, in some embodiments, the sixth sampling module includes a third sampling submodule and at least one fourth sampling submodule. Accordingly, the method may also include: in the third sampling submodule, sampling and processing the second sampling even signal according to the first clock even signal to obtain a third sampling even signal; and in at least one fourth sampling submodule, performing logic processing according to the third sampling even signal and the second sampling even signal to obtain a fourth sampling even signal, and sampling and processing the fourth sampling even signal according to the first clock even signal to obtain a second control signal.

[0232] Here, when the number of at least one fourth sampling submodule is M, the first input end of the i-th fourth sampling submodule is connected to the second sampling even signal, the second input end of the i-th fourth sampling submodule is connected to the i-th input signal, the clock end of the i-th fourth sampling submodule is connected to the first clock even signal, and the output end of the i-th fourth sampling submodule is used to output the i-th intermediate signal; wherein, when i is equal to 1, the i-th input signal is the third sampling even signal; when i is greater than 1, the i-th input signal is the i-1th intermediate signal; and when i is equal to M, the i-th intermediate signal is the second control signal, wherein i is an integer greater than or equal to 1 and less than or equal to M.

[0233] The disclosed embodiment provides a control method. Since the read delay signal includes RL information, and the interval time between the command address signal and the target control signal meets the preset timing condition, the resistance value of the terminal resistor can be changed in time within the prescribed time in accordance with the technical standards, thereby not only avoiding signal conflicts during the transmission process, but also reducing the energy loss and reflection of the signal during the transmission process, thereby improving the signal integrity; in addition, since the first clock signal is earlier than the second clock signal, and for the command control module, the second clock signal is sampled into the command control module, and the first clock signal is used to output the signal from the command control module, so the relatively fast first clock signal is used to send the signal sampled by the relatively slow second clock signal, thereby speeding up the processing speed and ultimately improving the performance of the memory.

[0234] In yet another embodiment of the present disclosure, see Fig.12 , which shows a schematic diagram of the composition structure of a memory provided by an embodiment of the present disclosure. Fig.12 As shown, the memory 120 at least includes the control circuit 40 described in any one of the aforementioned embodiments.

[0235] In some embodiments, the memory 120 may include a DRAM chip. The DRAM chip may not only comply with memory specifications such as DDR, DDR2, DDR3, DDR4, DDR5, etc., but may also comply with memory specifications such as LPDDR, LPDDR2, LPDDR3, LPDDR4, LPDDR5, etc., without any limitation here.

[0236] In the embodiment of the present disclosure, the memory 120 mainly involves semiconductor technology, especially the pulse width design of the internal signal of the circuit, and uses the external clock factor and the internal independent delay characteristics to achieve better design performance. In addition, the control circuit of the embodiment of the present disclosure can be applied to various memories.

[0237] Thus, for the memory 120, the read delay signal includes RL information, and the RL information is associated with the preset timing condition. Since the interval between the target control signal and the command address signal obtained after the command address signal passes through the command decoding module, the command processing module and the command control module meets the preset timing condition, the resistance value of the terminal resistor can be changed in time within the specified time in accordance with the technical standards; thus, it can not only avoid signal conflicts during the transmission process, but also reduce the energy loss and reflection of the signal during the transmission process, thereby improving the SI performance; at the same time, since the signal sampled by the relatively fast first clock signal is sent out by the relatively slow second clock signal, the processing speed can be accelerated, and finally the performance of the memory can be improved.

[0238] The above are only preferred embodiments of the present disclosure and are not intended to limit the protection scope of the present disclosure.

[0239] It should be noted that in the present disclosure, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "includes a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0240] The serial numbers of the above-mentioned embodiments of the present disclosure are only for description and do not represent the advantages or disadvantages of the embodiments.

[0241] The methods disclosed in several method embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0242] The features disclosed in several product embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new product embodiments.

[0243] The features disclosed in several method or device embodiments provided in the present disclosure may be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0244] The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.< / j> < / n>

Claims

1. A control circuit, characterized in that: The control circuit includes a clock generation module, a command decoding module, a command processing module and a command control module, wherein the clock generation module is connected to the command decoding module, the command processing module and the command control module respectively, and the command processing module is also connected to the command control module, wherein: The clock generation module is used to receive an external clock signal, and generate a first clock signal, a second clock signal and a third clock signal according to the external clock signal; wherein the first clock signal is earlier than the second clock signal, and the second clock signal is earlier than the third clock signal; The command decoding module is used to receive a command address signal and the third clock signal, decode the command address signal to obtain a decoded signal, and sample the decoded signal according to the third clock signal to obtain a read command signal; The command processing module is used to receive the third clock signal, the read command signal and the read delay signal, and perform delay processing on the read command signal according to the third clock signal and the read delay signal to obtain a read control signal, wherein the read delay signal includes RL information; The command control module is used to receive the first clock signal, the second clock signal and the read control signal, and to sample and pulse widen the read control signal according to the first clock signal and the second clock signal to obtain a target control signal; wherein the interval time between the command address signal and the target control signal meets a preset timing condition, and the target control signal is used to control the conduction state of the terminal resistance.

2. The control circuit according to claim 1, characterized in that: The control circuit further includes a mode register module, which is connected to the command processing module, wherein: The mode register module is used to set RL information, generate the read delay signal including the RL information, and provide the read delay signal to the command processing module.

3. The control circuit according to claim 1, characterized in that: The clock generation module is used to perform frequency division and first clock delay processing on the external clock signal to obtain a first clock odd signal and a first clock even signal, wherein the clock periods of the first clock odd signal and the first clock even signal are both twice the clock period of the external clock signal, and the first clock signal is composed of the first clock odd signal and the first clock even signal, and the phase difference between the first clock odd signal and the first clock even signal is 180 degrees; and The clock generation module is further used to perform frequency division and second clock delay processing on the external clock signal to obtain a second clock odd signal and a second clock even signal, wherein the clock periods of the second clock odd signal and the second clock even signal are both twice the clock period of the external clock signal, and the second clock signal is composed of the second clock odd signal and the second clock even signal, and the phase difference between the second clock odd signal and the second clock even signal is 180 degrees; and The clock generation module is also used to divide the external clock signal and perform third clock delay processing to obtain a third clock odd signal and a third clock even signal, wherein the clock periods of the third clock odd signal and the third clock even signal are both twice the clock period of the external clock signal, and the third clock signal is composed of the third clock odd signal and the third clock even signal, and the phase difference between the third clock odd signal and the third clock even signal is 180 degrees.

4. The control circuit according to claim 3, characterized in that: The delay time corresponding to the first clock delay processing is less than the delay time corresponding to the second clock delay processing; The delay time corresponding to the second clock delay process is smaller than the delay time corresponding to the third clock delay process.

5. The control circuit according to claim 3, characterized in that: The command decoding module is used to decode the command address signal to obtain a decoding odd signal and a decoding even signal; sample the decoding odd signal according to the third clock odd signal to obtain a read command odd signal; and sample the decoding even signal according to the third clock even signal to obtain a read command even signal; The command processing module is used to delay the read command odd signal according to the third clock odd signal and the read delay signal to obtain a read control odd signal; and to delay the read command even signal according to the third clock even signal and the read delay signal to obtain a read control even signal; Among them, the decoding signal is composed of the decoding odd signal and the decoding even signal, the read command signal is composed of the read command odd signal and the read command even signal, and the read control signal is composed of the read control odd signal and the read control even signal.

6. The control circuit according to claim 5, characterized in that: The command control module includes a first control module, a second control module, a logic module and a delay adjustable module, wherein: The first control module is used to receive the first clock odd signal, the second clock odd signal and the read control odd signal, and perform sampling and pulse widening processing on the read control odd signal according to the first clock odd signal and the second clock odd signal to obtain a first control signal; The second control module is used to receive the first clock even signal, the second clock even signal and the read control even signal, and perform sampling and pulse widening processing on the read control even signal according to the first clock even signal and the second clock even signal to obtain a second control signal; The logic module is used to perform a logic operation on the first control signal and the second control signal to obtain an initial control signal; The adjustable delay module is used to receive the mode control signal and the initial control signal, and perform delay processing on the initial control signal according to the mode control signal to obtain the target control signal.

7. The control circuit according to claim 6, characterized in that: The logic module comprises a first OR gate, wherein: The first input end of the first OR gate is connected to the output end of the first control module for receiving the first control signal; the second input end of the first OR gate is connected to the output end of the second control module for receiving the second control signal; The output end of the first OR gate is connected to the input end of the adjustable delay module for outputting the initial control signal.

8. The control circuit according to claim 6, characterized in that: The adjustable delay module includes K delay units, where K is an integer greater than 0, wherein: The adjustable delay module is used to determine a target number of delay units from the K delay units according to the mode control signal, and to perform delay processing on the initial control signal through the target number of delay units to obtain the target control signal.

9. The control circuit according to claim 6, characterized in that: The first control module includes a first sampling module, a second sampling module and a third sampling module, wherein: The first sampling module is used to sample the read control odd signal according to the second clock odd signal to obtain a first sampling odd signal; The second sampling module is used to sample the first sampling odd signal according to the first clock odd signal to obtain a second sampling odd signal; The third sampling module is used to sample and pulse widen the second sampling odd signal according to the first clock odd signal to obtain the first control signal; The second control module includes a fourth sampling module, a fifth sampling module and a sixth sampling module, wherein: The fourth sampling module is used to sample the read control even signal according to the second clock even signal to obtain a first sampling even signal; The fifth sampling module is used to sample the first sampling even signal according to the first clock even signal to obtain a second sampling even signal; The sixth sampling module is used to sample and perform pulse widening processing on the second sampling even signal according to the first clock even signal to obtain the second control signal.

10. The control circuit according to claim 9, characterized in that: The third sampling module includes a first sampling submodule and at least one second sampling submodule, wherein: The first sampling submodule is used to sample the second sampling odd signal according to the first clock odd signal to obtain a third sampling odd signal; The at least one second sampling submodule is used to perform logic processing according to the third sampling odd signal and the second sampling odd signal to obtain a fourth sampling odd signal, and perform sampling processing on the fourth sampling odd signal according to the first clock odd signal to obtain the first control signal; The sixth sampling module includes a third sampling submodule and at least one fourth sampling submodule, wherein: The third sampling submodule is used to sample the second sampling even signal according to the first clock even signal to obtain a third sampling even signal; The at least one fourth sampling submodule is used to perform logic processing according to the third sampling even signal and the second sampling even signal to obtain a fourth sampling even signal, and sample the fourth sampling even signal according to the first clock even signal to obtain the second control signal.

11. The control circuit according to claim 9, characterized in that: The first sampling module includes a first trigger, wherein the input end of the first trigger is used to receive the read control odd signal, the clock end of the first trigger is used to receive the second clock odd signal, and the output end of the first trigger is used to output the first sampling odd signal; The second sampling module includes a second trigger, wherein the input end of the second trigger is used to receive the first sampling odd signal, the clock end of the second trigger is used to receive the first clock odd signal, and the output end of the second trigger is used to output the second sampling odd signal.

12. The control circuit according to claim 10, characterized in that: The first sampling submodule includes a third trigger, wherein an input end of the third trigger is used to receive the second sampling odd signal, a clock end of the third trigger is used to receive the first clock odd signal, and an output end of the third trigger is used to output the third sampling odd signal; The second sampling submodule includes a second OR gate and a fourth trigger, wherein the first input end of the second OR gate is connected to the second sampling odd signal as the first input end of the second sampling submodule, the second input end of the second OR gate is connected to the output end of the previous second sampling submodule as the second input end of the second sampling submodule, the output end of the second OR gate is connected to the input end of the fourth trigger, the clock end of the fourth trigger is connected to the first clock odd signal as the clock end of the second sampling submodule, and the output end of the fourth trigger is used as the output end of the second sampling submodule to output the intermediate signal.

13. The control circuit according to claim 12, characterized in that: When the number of the at least one second sampling submodule is N, the first input end of the i-th second sampling submodule is connected to the second sampling odd signal, the second input end of the i-th second sampling submodule is connected to the i-th input signal, the clock end of the i-th second sampling submodule is connected to the first clock odd signal, and the output end of the i-th second sampling submodule is used to output the i-th intermediate signal; Wherein, when i is equal to 1, the i-th input signal is the third sampling odd signal; when i is greater than 1, the i-th input signal is the i-1th intermediate signal; and when i is equal to N, the i-th intermediate signal is the first control signal, wherein i is an integer greater than or equal to 1 and less than or equal to N, and N is an integer greater than or equal to 2.

14. The control circuit according to claim 9, characterized in that: The fourth sampling module includes a fifth trigger, wherein the input end of the fifth trigger is used to receive the read control even signal, the clock end of the fifth trigger is used to receive the second clock even signal, and the output end of the fifth trigger is used to output the first sampling even signal; The fifth sampling module includes a sixth trigger, wherein the input end of the sixth trigger is used to receive the first sampling even signal, the clock end of the sixth trigger is used to receive the first clock even signal, and the output end of the sixth trigger is used to output the second sampling even signal.

15. The control circuit according to claim 10, characterized in that: The third sampling submodule includes a seventh trigger, wherein the input end of the seventh trigger is used to receive the second sampling even signal, the clock end of the seventh trigger is used to receive the first clock even signal, and the output end of the seventh trigger is used to output the third sampling even signal; The fourth sampling submodule includes a second OR gate and an eighth trigger, wherein the first input end of the second OR gate is connected to the second sampling even signal as the first input end of the fourth sampling submodule, the second input end of the second OR gate is connected to the output end of the previous fourth sampling submodule as the second input end of the fourth sampling submodule, the output end of the second OR gate is connected to the input end of the eighth trigger, the clock end of the eighth trigger is connected to the first clock even signal as the clock end of the fourth sampling submodule, and the output end of the eighth trigger is used as the output end of the fourth sampling submodule to output the intermediate signal.

16. The control circuit according to claim 15, characterized in that: When the number of the at least one fourth sampling submodule is M, the first input end of the i-th fourth sampling submodule is connected to the second sampling even signal, the second input end of the i-th fourth sampling submodule is connected to the i-th input signal, the clock end of the i-th fourth sampling submodule is connected to the first clock even signal, and the output end of the i-th fourth sampling submodule is used to output the i-th intermediate signal; Wherein, when i is equal to 1, the i-th input signal is the third sampling even signal; when i is greater than 1, the i-th input signal is the i-1th intermediate signal; and when i is equal to M, the i-th intermediate signal is the second control signal, wherein i is an integer greater than or equal to 1 and less than or equal to M, and M is an integer greater than or equal to 2.

17. A control method, characterized in that: The method comprises: Receiving an external clock signal through a clock generation module, and generating a first clock signal, a second clock signal and a third clock signal according to the external clock signal; wherein the first clock signal is earlier than the second clock signal, and the second clock signal is earlier than the third clock signal; Receiving a command address signal and the third clock signal through a command decoding module, decoding the command address signal to obtain a decoding signal, and sampling the decoding signal according to the third clock signal to obtain a read command signal; Receiving the third clock signal, the read command signal and the read delay signal through a command processing module, and delaying the read command signal according to the third clock signal and the read delay signal to obtain a read control signal, wherein the read delay signal includes RL information; The first clock signal, the second clock signal and the read control signal are received through a command control module, and the read control signal is sampled and pulse widened according to the first clock signal and the second clock signal to obtain a target control signal; wherein the interval time between the command address signal and the target control signal meets a preset timing condition, and the target control signal is used to control the conduction state of the terminal resistance.

18. A memory, characterized in that: The memory comprises at least the control circuit according to any one of claims 1-16.

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