Decoding circuit

Abstract

The present invention discloses a decoding circuit, whose driving unit includes: a first NMOS tube, a first PMOS tube, and a second NMOS tube. A negative voltage input circuit includes: a first resistor and a first switch tube. The first ends of the first resistor and the first switch tube are both connected to a negative voltage input signal, and the second ends are connected together to output a negative voltage control gate selection signal. During an erase operation, the first switch tube is cut off, and the negative voltage control gate selection signal is transmitted to the selected control gate line through the turned-on first NMOS tube. The gate of the second NMOS tube is connected to the negative voltage input signal and is turned off and has a first leakage. The first leakage causes a first voltage difference to be formed across the first resistor. The first voltage difference is used to deepen the shutdown of the second NMOS tube and suppress the first leakage. The present invention can reduce negative voltage leakage when the chip is erased.

Description

Technical Field

[0001] The present invention relates to a semiconductor integrated circuit, and in particular to a decoding circuit. Background Art

[0002] During the erase operation, NORD flash memory cells utilize a combination of positive and negative voltages: a positive high voltage is applied to the word line (WL) and a negative high voltage is applied to the control gate (CG). Generally speaking, negative charge pumps have limited performance, and increasing their performance requires more area, significantly increasing the size of the intellectual property (IP) core.

[0003] During chip erase, all CGs are fed -8V. Due to leakage, the accumulated leakage in large-capacity flash IPs, such as those with thousands of CG0s and CG1s, can be quite significant. At low process corners and high temperatures, leakage can even reach levels as high as 100μA. Simply increasing the negative charge pump's capability becomes impractical. This is further explained below with reference to the accompanying figures:

[0004] like Figure 1 As shown in FIG, it is a block diagram of an existing decoding circuit; Figure 2 As shown, Figure 2 This is a main circuit structure diagram of the driving unit of the existing decoding circuit; Figure 3 , which is a structural diagram of a storage unit selected by an existing decoding circuit, namely a NORD flash memory unit; the existing decoding circuit includes a decoding unit 1, a level shift unit 2 and a driving unit 3.

[0005] The power supply terminal of the decoding unit 1 is connected to the power supply voltage VDD.

[0006] The input terminal of the decoding unit 1 is connected to an input signal, and the decoding unit 1 decodes the input signal to form a first-level selection signal, wherein the high level of the first-level selection signal is the power supply voltage VDD. The decoding unit 1 is a logic circuit.

[0007] Typically, the input signal is an address signal. By decoding the address signal, a corresponding selection signal, ie, the first-level selection signal, can be obtained to select corresponding storage cells and storage bits in the storage array of the flash memory.

[0008] like Figure 3As shown, the memory cell uses a split-gate floating gate 104 device. The split-gate floating gate 104 device includes: a first source and drain region and a second source and drain region, a plurality of separated first gate structures with floating gates 104 located between the first source and drain regions, and a second gate structure 103 located between the first gate structures; the first gate structure has the control gate 105 located on top of the floating gate 104; each floating gate 104 is used to store charge and corresponds to the storage bit. The split-gate floating gate 104 device is a dual split-gate floating gate 104 device, with two first gate structures. Figure 3 In the figure, the two first gate structures are respectively denoted by reference numerals 102a and 102b.

[0009] In the memory array, the control gates 105 of the first gate structures in the same row are connected together. Figure 3 In the figure, the row line of the control gate connected to the control gate 105 of the first gate structure 102a is represented by CG0, and the row line of the control gate connected to the control gate 105 of the first gate structure 102b is represented by CG1.

[0010] The second gate structures 103 in the same row are connected to the same word line WL.

[0011] The split-gate floating gate 104 device is an N-type device, and the first source and drain regions and the second source and drain regions are both composed of N+ regions. Figure 3 In the embodiment, the first source and drain region is connected to the bit line BLa, and the second source and drain region is connected to the bit line BLb.

[0012] The P-type doped channel region is located between the first source and drain regions and the second source and drain regions and is covered by the first gate structure and the second gate structure 103 . The first gate structure and the second gate structure 103 respectively control the covered region of the channel region.

[0013] Each of the first gate structures is formed by stacking a tunnel dielectric layer, the floating gate 104 , a control gate dielectric layer, and the control gate 105 .

[0014] Each of the second gate structures 103 is formed by stacking a word line gate dielectric layer and a word line gate.

[0015] The components of the decoding unit 1 all operate in the voltage domain of the power supply voltage VDD. During the reading process, the voltage required to be applied to the control gate 105 is greater than the power supply voltage VDD. Therefore, after the decoding unit 1 completes decoding, the first-stage selection signal needs to be level-shifted. This is achieved by using the level shift unit 2.

[0016] The input end of the level shift unit 2 is connected to the first stage selection signal, the first output end of the level shift unit 2 outputs the first negative phase selection signal CGSLb and the second output end outputs the first positive phase selection signal CGSL, the first negative phase selection signal CGSLb and the first positive phase selection signal CGSL are inverted to each other.

[0017] The output end of the driving unit 3 is connected to the corresponding selected control gate line CG, and the selected control gate line CG is connected to the control gates 105 in the same row.

[0018] like Figure 2 As shown, the driving unit 3 includes a first NMOS transistor MN1, a first PMOS transistor MP1 and a second NMOS transistor MN2.

[0019] The source of the first NMOS transistor MN1 is connected to the selected control gate line CG, the drain of the first NMOS transistor MN1 is connected to the first control gate selection signal XPCGN, and the gate of the first NMOS transistor MN1 is connected to the first positive phase selection signal CGSL.

[0020] The drain of the first PMOS transistor MP1 is connected to the selected control gate line CG, the source of the first PMOS transistor MP1 is connected to the second control gate selection signal XPCGP, and the gate of the first PMOS transistor MP1 is connected to the first inverted selection signal CGSLb.

[0021] A drain of the second NMOS transistor MN2 is connected to the selected control gate line CG, a source of the second NMOS transistor MN2 is grounded GND_CG, and a gate of the second NMOS transistor MN2 is connected to the first inverted selection signal CGSLb.

[0022] Figure 2 During the erase process, the low level of the first control gate select signal XPCGN is a negative high voltage (VNEG), and the high level is 0V. The first NMOS transistor MN1 corresponding to the selected control gate line CG conducts the first control gate select signal XPCGN, which is connected to a low level (negative high voltage). In combination with the positive high voltage applied to the word line of the selected memory cell corresponding to the selected bit, the selected memory bit is erased.

[0023] During the erasing process, the first inverted selection signal CGSLb is at a low level, that is, a negative high voltage VNEG, and the second NMOS transistor MN2 is turned off.

[0024] Take VNEG as -8V as an example, Figure 2 In the equation, the voltage of each signal is expressed as:

[0025] CGSELb = -8V;

[0026] CG=-8V;

[0027] VNEG=-8V;

[0028] GND_CG=0V

[0029] CGSEL=0V.

[0030] Wherein, CGSELb represents the first negative phase selection signal CGSLb, CG represents the voltage of the selected control gate line CG, GND_CG represents the ground GND_CG, and CGSEL represents the first positive phase selection signal CGSLb. Typically, VNEG is also connected to the substrate electrodes of the first NMOS transistor MN1 and the second NMOS transistor MN2, and the substrate electrode of the first PMOS transistor MP1 is also connected to a bias voltage.

[0031] The first control gate selection signal XPCGN is connected to VNEG, and the first NMOS transistor MN1 is turned on during erasing, so CG is equal to the first control gate selection signal XPCGN and also equal to VNEG.

[0032] However, in reality, the second NMOS transistor MN2 is not completely turned off, but will generate a certain amount of leakage, such as leakage at the nA or 10nA level.

[0033] VNEG is the negative voltage provided by the negative charge pump.

[0034] The leakage of the second NMOS transistor MN2 is the primary leakage generated by the decoding circuit during an erase operation. Furthermore, because a single erase operation simultaneously selects multiple, for example, thousands to tens of thousands, of control gate lines CG, thereby erasing multiple memory bits in multiple memory cells, the leakage of the second NMOS transistor MN2 corresponding to each selected control gate line CG accumulates during the erase operation, resulting in a significant cumulative leakage. At low process corners or high temperatures, the cumulative leakage can even reach levels as high as 100 μA, making it impractical to simply increase the capacity of the charge pump, specifically the negative voltage charge pump. Summary of the Invention

[0035] The technical problem to be solved by the present invention is to provide a decoding circuit which can reduce negative voltage leakage when a chip is erased.

[0036] To solve the above technical problem, the present invention provides a decoding circuit including a decoding unit, a level shifting unit and a driving unit.

[0037] The driving unit includes: a first NMOS transistor, a first PMOS transistor and a second NMOS transistor.

[0038] The source of the first NMOS transistor is connected to the selected control gate line, the drain of the first NMOS transistor is connected to the first control gate selection signal, and the gate of the first NMOS transistor is connected to the first positive phase selection signal.

[0039] The drain of the first PMOS transistor is connected to the selected control gate line, the source of the first PMOS transistor is connected to the second control gate selection signal, and the gate of the first PMOS transistor is connected to the first inverted selection signal.

[0040] The drain of the second NMOS transistor is connected to the selected control gate line, the source of the second NMOS transistor is grounded, and the gate of the second NMOS transistor is connected to the first inverted selection signal.

[0041] The decoding circuit further includes a negative voltage input circuit, which includes a first resistor and a first switch tube.

[0042] The first end of the first resistor and the first end of the first switch tube are both connected to a negative voltage input signal.

[0043] The second end of the first resistor and the second end of the first switch tube are connected together and output a negative voltage control gate selection signal.

[0044] The control end of the first switch tube is connected to a first setting signal.

[0045] The selected control gate line is a control gate line connected to a control gate of a selected storage bit of a selected storage cell in a storage array of the flash memory.

[0046] When performing an erase operation, the first setting signal turns off the first switch tube, and the first control gate selection signal adopts the negative voltage control gate selection signal.

[0047] The first positive phase selection signal turns on the first NMOS transistor, and the negative voltage control gate selection signal is transmitted to the selected control gate line.

[0048] The first inverted selection signal is connected to the negative voltage input signal, the second NMOS transistor is in a closed state, the second NMOS transistor has a first leakage, the first leakage forms a first voltage difference across the first resistor, and the first voltage difference is used to deepen the shutdown of the second NMOS transistor and suppress the first leakage.

[0049] A further improvement is that the first resistor is an adjustable resistor, and the maximum value of the first leakage current is reduced by increasing the first resistor.

[0050] A further improvement is that, in the erase operation, a plurality of memory cells in the flash memory serve as the selected memory cells, and each memory bit of each selected memory cell is the selected memory bit; the selected memory bits in the same row are connected to the selected control gate line corresponding to the same row;

[0051] The first leakage current corresponding to each of the selected control gate lines flows through the first resistor.

[0052] A further improvement is that the negative voltage input signal is provided by a negative voltage charge pump, and the load current capability of the negative voltage charge pump is greater than or equal to the sum of the first leakage currents corresponding to the selected control gate lines.

[0053] A further improvement is that the maximum value of the sum of the first leakage currents corresponding to the selected control gate lines is several microamperes.

[0054] A further improvement is that the first resistor is in a range of tens to hundreds of Ω.

[0055] A further improvement is that the first resistor is a polysilicon resistor.

[0056] A further improvement is that the first switch tube adopts a third NMOS tube.

[0057] A further improvement is that the decoding unit decodes the input signal to form a first-stage selection signal, and the level shift unit performs level conversion on the first-stage selection signal to form the first positive-phase selection signal and the first negative-phase selection signal.

[0058] A further improvement is that, in the erase operation, the maximum number of the selected control gate lines is more than thousands or more than tens of thousands.

[0059] A further improvement is that, during the erase operation, the first PMOS transistor is turned off.

[0060] A further improvement is that the memory cell adopts a split-gate floating-gate device.

[0061] The split-gate floating-gate device includes: a first source-drain region and a second source-drain region, a plurality of separated first gate structures with floating gates located between the first source-drain region and the second source-drain region, and a second gate structure located between the first gate structures; the first gate structure has the control gate located on top of the floating gate; each floating gate is used to store charge and corresponds to the storage bit.

[0062] In the memory array, the control gates of the first gate structures in the same row are connected together.

[0063] The second gate structures in the same row are connected to the same word line.

[0064] A further improvement is that the split-gate floating-gate device is a double split-gate floating-gate device, and the number of the first gate structures is two.

[0065] A further improvement is that the split-gate floating-gate device is an N-type device, and the first source and drain regions and the second source and drain regions are both composed of N+ regions.

[0066] The P-type doped channel region is located between the first source and drain regions and the second source and drain regions and is covered by the first gate structure and the second gate structure. The first gate structure and the second gate structure respectively control the covered region segment of the channel region.

[0067] A further improvement is that each of the first gate structures is formed by stacking a tunnel dielectric layer, the floating gate, a control gate dielectric layer and the control gate;

[0068] Each of the second gate structures is formed by stacking a word line gate dielectric layer and a word line gate.

[0069] Unlike the prior art, in which the negative voltage input signal provided by the negative voltage charge pump during erasing is directly provided to the first control gate selection signal connected to the drain of the first NMOS tube of the driving unit, the present invention adds a negative voltage input circuit. During erasing, the negative voltage input signal passes through a larger first resistor before being connected to the first control gate selection signal connected to the drain of the first NMOS tube of the driving unit. In this way, when there is leakage in the second NMOS tube of the driving unit, the leakage will also flow through the first resistor and form a first voltage difference across the first resistor. The first voltage difference is the voltage difference between the negative voltage input signal and the negative voltage control gate selection signal. For the second NMOS tube with negative voltage leakage, the second The first inverted selection signal connected to the gate of the NMOS tube is provided by a negative voltage input signal, and the drain of the second NMOS tube is connected to the first control gate selection signal through the conductive first NMOS tube. The first control gate selection signal is provided by a negative voltage control gate selection signal. Therefore, the voltage difference between the gate and the drain of the second NMOS tube is the first voltage difference. The first voltage difference is a negative value. For the second NMOS tube, the first voltage difference can deepen the shutdown of the second NMOS tube, and the first leakage current will decrease by an order of magnitude, that is, exponentially. In this way, the first leakage current will be suppressed. When the first leakage current increases to a certain value, the first voltage difference will also increase to a certain value, so that the first leakage current will not increase further.

[0070] For flash memory, an erase operation will erase the storage bits of multiple storage cells. The selected control gate lines corresponding to the storage bits in each row will be connected to the second NMOS tube of a driving unit, and the first leakage current of the second NMOS tube corresponding to each selected control gate line will flow through the first resistor. The present invention can adjust the total size of the first leakage currents by adjusting the size of the first resistor, and finally reduce the maximum value of the total size of the first leakage currents. In this way, the load current capacity of the negative voltage charge pump that provides the negative voltage input signal can be reduced. For example, the present invention can reduce the load current capacity of the negative voltage charge pump from the 100μA level to below 5μA, which can greatly reduce the area of ​​the negative voltage charge pump, thereby reducing the area of ​​the entire chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0071] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:

[0072] Figure 1 is a block diagram of an existing decoding circuit;

[0073] Figure 2 This is a main circuit structure diagram of a driving unit of an existing decoding circuit;

[0074] Figure 3 It is a schematic diagram of the structure of the storage unit selected by the existing decoding circuit;

[0075] Figure 4 4 is a circuit diagram of a negative voltage input circuit of a decoding circuit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0076] Please also refer to the block diagram of the decoding circuit of the embodiment of the present invention. Figure 1 As shown, please refer to the main circuit structure diagram of the drive unit 3 Figure 2 As shown, please refer to the structural diagram of the storage unit 101. Figure 3 As shown, the decoding circuit according to the embodiment of the present invention includes a decoding unit 1 , a level shifting unit 2 and a driving unit 3 .

[0077] like Figure 2 As shown, the driving unit 3 includes: a first NMOS transistor MN1, a first PMOS transistor MP1 and a second NMOS transistor MN2.

[0078] The source of the first NMOS transistor MN1 is connected to the selected control gate line CG, the drain of the first NMOS transistor MN1 is connected to the first control gate selection signal XPCGN, and the gate of the first NMOS transistor MN1 is connected to the first positive phase selection signal CGSEL.

[0079] The drain of the first PMOS transistor MP1 is connected to the selected control gate line CG, the source of the first PMOS transistor MP1 is connected to the second control gate selection signal XPCGP, and the gate of the first PMOS transistor MP1 is connected to the first inverted selection signal CGSELb.

[0080] A drain of the second NMOS transistor MN2 is connected to the selected control gate line CG, a source of the second NMOS transistor MN2 is grounded GND_CG, and a gate of the second NMOS transistor MN2 is connected to the first inverted selection signal CGSELb.

[0081] like Figure 4 , which is a circuit diagram of a negative voltage input circuit of a decoding circuit according to an embodiment of the present invention; the decoding circuit further includes a negative voltage input circuit, which includes: a first resistor R1 and a first switch tube 201.

[0082] The first end of the first resistor R1 and the first end of the first switch 201 are both connected to a negative voltage input signal VNEG_IN.

[0083] The second end of the first resistor R1 and the second end of the first switch tube 201 are connected together and output a negative voltage control gate selection signal VNEG_XPCG.

[0084] The control terminal of the first switch tube 201 is connected to a first setting signal set.

[0085] The selected control gate line CG is a control gate line connected to the control gate of a selected storage bit of a selected storage cell 101 in a storage array of the flash memory.

[0086] When performing an erase operation, the first setting signal set turns off the first switch tube 201, and the first control gate selection signal XPCG adopts the negative voltage control gate selection signal VNEG_XPCG. That is, the negative voltage input signal VNEG_IN is not directly used as the first control gate selection signal XPCG and connected to the drain of the first NMOS tube MN1, but is converted into the negative voltage control gate selection signal VNEG_XPCG through the first resistor R1 and then connected to the first control gate selection signal XPCG.

[0087] The first positive phase selection signal CGSEL turns on the first NMOS transistor MN1 , and the negative voltage control gate selection signal VNEG_XPCG is transmitted to the selected control gate line CG.

[0088] The first inverting selection signal CGSELb is connected to the negative voltage input signal VNEG_IN, the second NMOS transistor MN2 is in a turned-off state, and the second NMOS transistor MN2 has a first leakage current. The first leakage current forms a first voltage difference across the first resistor R1. The first voltage difference is used to deepen the turn-off of the second NMOS transistor MN2 and suppress the first leakage current.

[0089] In the embodiment of the present invention, the first resistor R1 is an adjustable resistor, and the maximum value of the first leakage current can be reduced by increasing the first resistor R1.

[0090] The first resistor R1 is a polysilicon resistor.

[0091] The first switch tube 201 is a third NMOS tube MN3.

[0092] During the erase operation, multiple memory cells 101 in the flash memory serve as the selected memory cells 101 , and each memory bit of each selected memory cell 101 is the selected memory bit; the selected memory bits in the same row are connected to the selected control gate line CG corresponding to the same row.

[0093] The first leakage current corresponding to each of the selected control gate lines CG flows through the first resistor R1 .

[0094] The negative voltage input signal VNEG_IN is provided by a negative voltage charge pump, and the load current capability of the negative voltage charge pump is greater than or equal to the sum of the first leakage currents corresponding to the selected control gate lines CG.

[0095] In some embodiments, during the erase operation, the maximum number of the selected control gate lines CG is more than thousands or more than tens of thousands.

[0096] During the erasing operation, the first PMOS transistor MP1 is turned off.

[0097] The maximum value of the sum of the first leakage currents corresponding to the selected control gate lines CG is several microamperes.

[0098] The first resistor R1 is in a range of tens to hundreds of Ω.

[0099] In the erase operation, the voltage applied to the second NMOS transistor MN2 is expressed as follows:

[0100] CGSELb = -8V;

[0101] CG=-7.8V;

[0102] VNEG=-8V;

[0103] GND_CG=0V

[0104] Wherein, CGSELb represents the first inverted selection signal CGSLb, which is applied to the gate of the second NMOS transistor MN2. CGSELb is directly provided by VNEG_IN, so it is -8V;

[0105] CG represents the voltage of the selected control gate line CG, where CG is provided by the first control gate selection signal XPCGN, and the first control gate selection signal XPCGN is provided by the negative voltage control gate selection signal VNEG_XPCG. It is assumed here that the sum of the first leakage currents corresponding to the selected control gate lines CG is 4 μA. In this way, the voltage drop on the first resistor R1, that is, the first voltage difference, is 0.2 V, so CG is -7.8 V.

[0106] VNEG is VNEG_IN, which is -8V. The substrate electrode of the second NMOS transistor MN2 is connected to VNEG.

[0107] GND_CG represents ground GND_CG, which is 0V.

[0108] It can be seen that the voltage difference between the gate and drain of the second NMOS transistor MN2 is the first voltage difference, i.e., -0.2V. When the second NMOS transistor MN2 is leaking, the drain and source are aligned, i.e., the actual Vgs = -0.2V. Compared to the positive voltage Vgs required to turn on the second NMOS transistor MN2, -0.2V achieves a back bias, thus deepening the turn-off state of the second NMOS transistor MN2 and reducing leakage by orders of magnitude. Ultimately, leakage is suppressed and prevented from increasing further. Finally, the negative charge pump only needs a capacity of no more than 5μA.

[0109] like Figure 1 As shown, in the embodiment of the present invention, the power supply terminal of the decoding unit 1 is connected to the power supply voltage VDD.

[0110] The input terminal of the decoding unit 1 is connected to an input signal, and the decoding unit 1 decodes the input signal to form a first-level selection signal, wherein the high level of the first-level selection signal is the power supply voltage VDD. The decoding unit 1 is a logic circuit.

[0111] Typically, the input signal is an address signal. By decoding the address signal, a corresponding selection signal, ie, the first-level selection signal, can be obtained to select corresponding storage cells and storage bits in the storage array of the flash memory.

[0112] The level shift unit 2 performs level conversion on the first stage selection signal to generate the first positive phase selection signal CGSEL and the first negative phase selection signal CGSELb.

[0113] like Figure 3 As shown, the memory cell uses a split-gate floating gate 104 device. The split-gate floating gate 104 device includes: a first source and drain region and a second source and drain region, a plurality of separated first gate structures with floating gates 104 located between the first source and drain regions, and a second gate structure 103 located between the first gate structures; the first gate structure has the control gate 105 located on top of the floating gate 104; each floating gate 104 is used to store charge and corresponds to the storage bit. The split-gate floating gate 104 device is a dual split-gate floating gate 104 device, with two first gate structures. Figure 3 In the figure, the two first gate structures are respectively denoted by reference numerals 102a and 102b.

[0114] In the memory array, the control gates 105 of the first gate structures in the same row are connected together. Figure 3 In the figure, the row line of the control gate connected to the control gate 105 of the first gate structure 102a is represented by CG0, and the row line of the control gate connected to the control gate 105 of the first gate structure 102b is represented by CG1.

[0115] The second gate structures 103 in the same row are connected to the same word line WL.

[0116] The split-gate floating gate 104 device is an N-type device, and the first source and drain regions and the second source and drain regions are both composed of N+ regions. Figure 3 In the embodiment, the first source and drain region is connected to the bit line BLa, and the second source and drain region is connected to the bit line BLb.

[0117] The P-type doped channel region is located between the first source and drain regions and the second source and drain regions and is covered by the first gate structure and the second gate structure 103 . The first gate structure and the second gate structure 103 respectively control the covered region of the channel region.

[0118] Each of the first gate structures is formed by stacking a tunnel dielectric layer, the floating gate 104 , a control gate dielectric layer, and the control gate 105 .

[0119] Each of the second gate structures 103 is formed by stacking a word line gate dielectric layer and a word line gate.

[0120] Unlike the prior art, in which the negative voltage input signal VNEG_IN provided by the negative voltage charge pump during erasing is directly provided to the first control gate selection signal XPCGN connected to the drain of the first NMOS transistor MN1 of the driving unit 3, a negative voltage input circuit is added in the embodiment of the present invention. During erasing, the negative voltage input signal VNEG_IN passes through the larger first resistor R1 and is then connected to the first control gate selection signal XPCGN connected to the drain of the first NMOS transistor MN1 of the driving unit 3. In this way, when there is leakage in the second NMOS transistor MN2 of the driving unit 3, the leakage will also flow through the first resistor R1 and form a first voltage difference across the first resistor R1. The first voltage difference is the voltage difference between the negative voltage input signal VNEG_IN and the negative voltage control gate selection signal VNEG_XPCG. For the second NMOS transistor MN2 with negative voltage leakage, the negative voltage input signal VNEG_IN is connected to the first control gate selection signal XPCGN connected to the drain of the first NMOS transistor MN1 of the driving unit 3. The gate of the second NMOS transistor MN2 is connected to a first inverted selection signal CGSELb provided by the negative voltage input signal VNEG_IN. The drain of the second NMOS transistor MN2 is connected to the first control gate selection signal XPCG via the conductive first NMOS transistor MN1. The first control gate selection signal XPCG is provided by the negative voltage control gate selection signal VNEG_XPCG. Therefore, the voltage difference between the gate and drain of the second NMOS transistor MN2 is the first voltage difference. The first voltage difference is a negative value. For the second NMOS transistor MN2, the first voltage difference can deepen the shutdown of the second NMOS transistor MN2, and the first leakage current will decrease by an order of magnitude, that is, exponentially. In this way, the first leakage current can be suppressed. When the first leakage current increases to a certain value, the first voltage difference will also increase to a certain value, so that the first leakage current will not increase further.

[0121] For a flash memory, an erase operation erases the storage bits of multiple storage cells 101. The selected control gate line CG corresponding to each row of storage bits is connected to the second NMOS transistor MN2 of a drive unit 3. The first leakage current of the second NMOS transistor MN2 corresponding to each selected control gate line CG flows through the first resistor R1. The embodiment of the present invention can adjust the total size of the first leakage currents by adjusting the size of the first resistor R1, and finally reduce the maximum value of the total first leakage currents. In this way, the load current capability of the negative voltage charge pump that provides the negative voltage input signal VNEG_IN can be reduced. For example, the embodiment of the present invention can reduce the load current capability of the negative voltage charge pump from the 100 μA level to below 5 μA, which can greatly reduce the area of ​​the negative voltage charge pump, thereby reducing the area of ​​the entire chip.

[0122] The present invention has been described in detail above by means of specific embodiments, but these do not constitute limitations of the present invention. Without departing from the principles of the present invention, those skilled in the art may make many variations and improvements, which should also be considered as the scope of protection of the present invention.

Claims

1. A decoding circuit, characterized in that: The decoding circuit includes a decoding unit, a level shift unit and a driving unit; The driving unit includes: a first NMOS transistor, a first PMOS transistor and a second NMOS transistor; The source of the first NMOS transistor is connected to the selected control gate line, the drain of the first NMOS transistor is connected to the first control gate selection signal, and the gate of the first NMOS transistor is connected to the first positive phase selection signal; The drain of the first PMOS transistor is connected to the selected control gate line, the source of the first PMOS transistor is connected to the second control gate selection signal, and the gate of the first PMOS transistor is connected to the first inverted selection signal; The drain of the second NMOS transistor is connected to the selected control gate line, the source of the second NMOS transistor is grounded, and the gate of the second NMOS transistor is connected to the first inverted selection signal; The decoding circuit further includes a negative voltage input circuit, and the negative voltage input circuit includes: a first resistor and a first switch tube; The first end of the first resistor and the first end of the first switch tube are both connected to a negative voltage input signal; The second end of the first resistor and the second end of the first switch tube are connected together and output a negative voltage control gate selection signal; The control end of the first switch tube is connected to a first setting signal; The selected control gate line is a control gate line connected to the control gate of the selected storage bit of the selected storage cell in the storage array of the flash memory; During an erase operation, the first setting signal turns off the first switch tube, and the first control gate selection signal adopts the negative voltage control gate selection signal; The first positive phase selection signal turns on the first NMOS transistor, and the negative voltage control gate selection signal is transmitted to the selected control gate line; The first inverted selection signal is connected to the negative voltage input signal, the second NMOS transistor is in a closed state, the second NMOS transistor has a first leakage, the first leakage forms a first voltage difference across the first resistor, and the first voltage difference is used to deepen the shutdown of the second NMOS transistor and suppress the first leakage.

2. The decoding circuit according to claim 1, wherein: The first resistor is an adjustable resistor, and the maximum value of the first leakage current is reduced by increasing the first resistor.

3. The decoding circuit according to claim 2, wherein: During the erase operation, a plurality of memory cells in the flash memory serve as the selected memory cells, and each memory bit of each selected memory cell is the selected memory bit; the selected memory bits in the same row are connected to the selected control gate line corresponding to the same row; The first leakage current corresponding to each of the selected control gate lines flows through the first resistor.

4. The decoding circuit according to claim 3, wherein: The negative voltage input signal is provided by a negative voltage charge pump, and the load current capability of the negative voltage charge pump is greater than or equal to the sum of the first leakage currents corresponding to the selected control gate lines.

5. The decoding circuit according to claim 4, wherein: The maximum value of the sum of the first leakage currents corresponding to the selected control gate lines is several microamperes.

6. The decoding circuit according to claim 5, wherein: The first resistor is in a range of tens to hundreds of Ω.

7. The decoding circuit according to claim 2, wherein: The first resistor is a polysilicon resistor.

8. The decoding circuit according to claim 1, wherein: The first switch tube is a third NMOS tube.

9. The decoding circuit according to claim 1, wherein: The decoding unit decodes the input signal to form a first-stage selection signal, and the level shift unit performs level conversion on the first-stage selection signal to form the first positive-phase selection signal and the first negative-phase selection signal.

10. The decoding circuit according to claim 3, wherein: During the erase operation, the maximum number of the selected control gate lines is more than thousands or more than tens of thousands.

11. The decoding circuit according to claim 1, wherein: During the erasing operation, the first PMOS transistor is turned off.

12. The decoding circuit according to claim 3, wherein: The memory cell adopts a split-gate floating-gate device; The split-gate floating-gate device comprises: a first source-drain region and a second source-drain region, a plurality of separated first gate structures having floating gates located between the first source-drain region and the second source-drain region, and a second gate structure located between the first gate structures; the first gate structure has the control gate located on top of the floating gate; each floating gate is used to store charge and corresponds to a storage bit; In the memory array, the control gates of the first gate structures in the same row are connected together; The second gate structures in the same row are connected to the same word line.

13. The decoding circuit according to claim 12, wherein: The split-gate floating-gate device is a double split-gate floating-gate device, and the number of the first gate structures is two.

14. The decoding circuit according to claim 12, wherein: The split-gate floating-gate device is an N-type device, and the first source and drain regions and the second source and drain regions are both composed of N+ regions; The P-type doped channel region is located between the first source and drain regions and the second source and drain regions and is covered by the first gate structure and the second gate structure. The first gate structure and the second gate structure respectively control the covered region segment of the channel region.

15. The decoding circuit according to claim 12, wherein: Each of the first gate structures is formed by stacking a tunnel dielectric layer, the floating gate, a control gate dielectric layer and the control gate; Each of the second gate structures is formed by stacking a word line gate dielectric layer and a word line gate.

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