Solar cell and method for manufacturing the same

Abstract

The present application provides a solar cell and a preparation method thereof, comprising a silicon substrate, an emitter layer and a passivation layer, wherein the emitter layer is arranged on the surface of the silicon substrate; the surface of the emitter layer comprises a first doping region and a second doping region, the square resistance of the emitter layer in the first doping region is greater than the square resistance of the emitter layer in the second doping region; the passivation layer is arranged on the side of the emitter layer away from the silicon substrate, the passivation layer comprises a first passivation layer and a second passivation layer, the first passivation layer is correspondingly arranged on the first doping region, and the second passivation layer is correspondingly arranged on the second doping region; the passivation capacity at the first passivation layer is greater than the passivation capacity at the second passivation layer. The present application effectively improves the conversion efficiency of the solar cell by matching the emitter layer and the passivation layer.

Description

Technical Field

[0001] The present application relates to the technical field of photovoltaic devices, and in particular to a solar cell and a method for preparing the same. Background Art

[0002] In the process of preparing the emitter layer of solar cells by diffusion, the uneven distribution of the airflow carrying the phosphorus source can easily cause uneven distribution of the square resistance of the silicon wafer after diffusion, resulting in higher square resistance in some areas and lower square resistance in some areas. Due to the uneven distribution of square resistance, the different regions of the emitter use different wavelengths of sunlight, and carriers in different regions of the emitter are prone to recombination, resulting in electrical and optical losses, thereby reducing the utilization rate of sunlight. Summary of the invention

[0003] Based on this, an embodiment of the present application provides a solar cell with high sunlight utilization rate and a method for preparing the same.

[0004] In a first aspect, the present application provides a solar cell, the solar cell comprising a silicon substrate, an emitter layer and a passivation layer, wherein the emitter layer is disposed on a surface of the silicon substrate;

[0005] The surface of the emitter layer has a first doping region and a second doping region, and the sheet resistance of the emitter layer in the first doping region is greater than the sheet resistance of the emitter layer in the second doping region;

[0006] The passivation layer is arranged on the side of the emitter layer away from the silicon substrate, and the passivation layer includes a first passivation layer and a second passivation layer. The first passivation layer is correspondingly arranged on the first doped region, and the second passivation layer is correspondingly arranged on the second doped region; the passivation ability at the first passivation layer is greater than the passivation ability at the second passivation layer.

[0007] In some embodiments, the first doping region is located in a central area of ​​a surface of the emitter layer, and the second doping region is located around the first doping region.

[0008] In some embodiments, the sheet resistance of the first doped region is 190Ω / sqr-200Ω / sqr.

[0009] In some embodiments, the sheet resistance of the second doped region is 170Ω / sqr-190Ω / sqr.

[0010] In some embodiments, the thickness of the first passivation layer is greater than the thickness of the second passivation layer.

[0011] In some embodiments, the thickness of the first passivation layer is 65 nm to 85 nm.

[0012] In some embodiments, the second passivation layer has a thickness of 65 nm to 85 nm.

[0013] In some embodiments, the refractive index of the first passivation layer is greater than the refractive index of the second passivation layer.

[0014] In some embodiments, the refractive index of the first passivation layer is 2.00-2.20.

[0015] In some embodiments, the refractive index of the second passivation layer is 2.00-2.20.

[0016] In some embodiments, the material of the first passivation layer and the material of the second passivation layer each independently include at least one of silicon oxynitride, silicon nitride, and silicon oxide.

[0017] In some embodiments, the solar cell further comprises an electrode disposed on a surface of the passivation layer away from the emitter layer, the electrode passes through the passivation layer and contacts the emitter layer, and the electrode comprises a main grid and a fine grid.

[0018] In some embodiments, a gate line width of a fine gate in the electrode located in the first doping region is smaller than a gate line width of a fine gate in the electrode located in the second doping region.

[0019] In some embodiments, a pitch of fine gates in the electrode located in the first doping region is smaller than a pitch of fine gates in the electrode located in the second doping region.

[0020] In some embodiments, a gate line width of a fine gate in the electrode located in the first doping region is 10 μm to 25 μm.

[0021] In some embodiments, a pitch of fine gates in the electrode located in the first doping region is 0.90 mm to 1.10 mm.

[0022] In some embodiments, the gate line width of the fine gate in the electrode located in the second doping region is 20 μm-35 μm.

[0023] In some embodiments, a pitch of fine gates in the electrode located in the second doping region is 1.05 mm to 1.40 mm.

[0024] In some embodiments, the second doped region includes a first partition and a second partition, the second partition is located in the edge region of the emitter layer, the first partition is located between the second partition and the first doped region, and the square resistance of the first partition is greater than the square resistance of the second partition; the second passivation layer includes a first partition passivation layer and a second partition passivation layer, the first partition passivation layer is correspondingly arranged on the first partition, the second partition passivation layer is correspondingly arranged on the second partition, and the passivation ability of the first partition passivation layer is greater than the passivation ability of the second partition passivation layer.

[0025] Optionally, the square resistance of the first partition is 180Ω / sqr~190Ω / sqr.

[0026] Optionally, the square resistance of the second partition is 170Ω / sqr~180Ω / sqr.

[0027] In some embodiments, a thickness of the first partition passivation layer is greater than a thickness of the second partition passivation layer.

[0028] In some embodiments, a refractive index of the first sub-area passivation layer is greater than a refractive index of the second sub-area passivation layer.

[0029] In some embodiments, a gate line width of a fine gate in the electrode located in the second sub-area is greater than a gate line width of a fine gate in the electrode located in the first sub-area.

[0030] In some embodiments, a pitch of fine grids in the electrode located in the second sub-area is greater than a pitch of fine grids in the electrode located in the first sub-area.

[0031] In some embodiments, the gate line width of the fine grid in the electrode located in the first sub-area is 20 μm-30 μm; the spacing of the fine grid in the electrode located in the first sub-area is 1 mm-1.1 mm.

[0032] In some embodiments, the gate line width of the fine grid in the electrode located in the second sub-area is 25 μm-35 μm; the spacing of the fine grid in the electrode located in the second sub-area is 1.1 mm-1.3 mm.

[0033] In a second aspect, the present application provides a method for preparing a solar cell as described in the first aspect, the method comprising:

[0034] Doping one side of the silicon substrate to form an emitter layer, wherein a surface of the emitter layer is divided into the first doping region and the second doping region;

[0035] A first passivation layer is formed on the first doping region of the emitter layer, and a second passivation layer is formed on the second doping region of the emitter layer.

[0036] In some embodiments, the method for preparing the passivation layer includes:

[0037] shielding the second doping region of the emitter layer, and forming the first passivation layer at a position of the emitter layer located at the first doping region;

[0038] The first doping region of the emitter layer is shielded, and the second passivation layer is formed at a position of the emitter layer where the second doping region is located.

[0039] Compared with the traditional technology, this application has at least the following beneficial effects:

[0040] The present application divides the emitter layer into a first doping region and a second doping region according to the square resistance, and matches the first passivation layer and the second passivation layer. The passivation ability of the first passivation layer is better than the passivation ability of the second passivation layer, thereby adjusting the passivation anti-reflection state of sunlight in different regions, increasing the absorption of sunlight, and increasing the probability of photons being converted into electrons and holes. Among them, the high passivation ability of the first passivation layer matches the high square resistance of the first doping region, ensuring the shallow PN junction depth in the first doping region, absorbing short-wave sunlight, significantly reducing the surface carrier recombination velocity, and the second passivation layer with low passivation ability matches the second doping region with low square resistance, which can increase the transmission distance of sunlight and realize the absorption of long-wave sunlight by the second doping region, thereby comprehensively improving the utilization rate of sunlight. In addition, the present application controls the passivation ability of the first passivation layer and the second passivation layer to match the emitter layer, which can reduce the non-equilibrium carrier recombination between different doping regions in the emitter layer and improve the conversion efficiency of solar cells. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 A schematic diagram of the area division of the emitter layer provided in a specific embodiment of the present application.

[0042] Figure 2 This is a schematic diagram of the electrode structure provided in a specific embodiment of the present application.

[0043] 10 - first doped region; 20 - second doped region; 21 - first subarea; 22 - second subarea. DETAILED DESCRIPTION

[0044] Below in conjunction with the embodiments and examples, the present application is further described in detail. These embodiments and examples are only used to illustrate the present application and are not used to limit the scope of the present application. The purpose of providing these embodiments and examples is to make the understanding of the disclosure of the present application more thorough and comprehensive. It should also be understood that the present application can be implemented in many different forms, and is not limited to the embodiments and examples described herein. Those skilled in the art can make various changes or modifications without violating the connotation of the present application, and the equivalent form obtained also falls within the protection scope of the present application. In addition, in the description below, a large number of specific details are given in order to provide a more comprehensive understanding of the present application. It should be understood that the present application can be implemented without one or more of these details.

[0045] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0046] In this application, "optionally", "optional", and "optional" mean optional or dispensable, that is, any one of the two parallel schemes of "yes" or "no". If multiple "options" appear in a technical solution, unless otherwise specified and there is no contradiction or mutual restriction, each "optional" is independent.

[0047] In this application, the terms "first", "second", etc. in "the first aspect", "the second aspect", etc. are used only for descriptive purposes and cannot be understood as indicating or implying relative importance or quantity, nor can they be understood as implicitly indicating the importance or quantity of the indicated technical features. Moreover, "first", "second", etc. only serve the purpose of non-exhaustive enumeration and description, and it should be understood that they do not constitute a closed limitation on quantity.

[0048] In the present application, the technical features described in an open manner include closed technical solutions composed of the listed features, and also include open technical solutions containing the listed features.

[0049] In the present application, when it comes to a numerical interval (i.e., a numerical range), unless otherwise specified, the distribution of the optional numerical values ​​in the numerical interval is considered to be continuous, and includes the two numerical endpoints (i.e., the minimum and maximum values) of the numerical interval, and each numerical value between the two numerical endpoints. Unless otherwise specified, when the numerical interval only refers to an integer in the numerical interval, it includes the two endpoint integers of the numerical range, and each integer between the two endpoints, which is equivalent to directly listing each integer. When multiple numerical ranges are provided to describe features or characteristics, these numerical ranges can be combined. In other words, unless otherwise specified, the numerical range disclosed in the present application should be understood to include any and all sub-ranges included therein. The "numerical value" in the numerical interval can be any quantitative value, such as a number, a percentage, a ratio, etc. "Numerical interval" allows for a broad range of quantitative intervals such as percentage intervals, ratio intervals, and ratio intervals.

[0050] All documents mentioned in this application are cited as references in this application, just as each document is cited as reference separately. Unless they conflict with the invention purpose and / or technical solution of this application, the cited documents involved in this application are cited with all contents and all purposes. When the cited documents are involved in this application, the definitions of relevant technical features, terms, nouns, phrases, etc. in the cited documents are also cited. When the cited documents are involved in this application, the examples and preferred methods of the cited relevant technical features can also be incorporated into this application as references, but are limited to the implementation of this application. It should be understood that when the cited content conflicts with the description in this application, the present application shall prevail or be modified adaptively according to the description of this application.

[0051] In the conventional technology, when the emitter layer of the solar cell is prepared by diffusion, the uneven distribution of the phosphorus source in the gas source easily causes the square resistance of the central area of ​​the emitter layer to be larger and the square resistance of the edge area to be smaller. Due to the uneven distribution of the square resistance, different doping regions have different absorption and utilization effects on sunlight, which causes carrier recombination losses and reduces the conversion efficiency of the solar cell. However, the present application divides the emitter layer into a first doping region and a second doping region according to the square resistance, thereby matching different first passivation layers and second passivation layers to different doping regions, so that the passivation capacity at the first passivation layer is greater than the passivation capacity at the second passivation layer, thereby improving the absorption of sunlight by the first doping region and the second doping region, reducing carrier recombination, and improving the conversion efficiency of the solar cell.

[0052] In a first aspect, the present application provides a solar cell, the solar cell comprising a silicon substrate, an emitter layer and a passivation layer, wherein the emitter layer is arranged on a surface of the silicon substrate;

[0053] The surface of the emitter layer has a first doping region and a second doping region, and the sheet resistance of the emitter layer in the first doping region is greater than the sheet resistance of the emitter layer in the second doping region;

[0054] The passivation layer is arranged on the side of the emitter layer away from the silicon substrate, and the passivation layer includes a first passivation layer and a second passivation layer. The first passivation layer is correspondingly arranged on the first doped region, and the second passivation layer is correspondingly arranged on the second doped region; the passivation ability at the first passivation layer is greater than the passivation ability at the second passivation layer.

[0055] The present application divides the emitter layer into a first doped region and a second doped region according to the square resistance, and matches the first passivation layer and the second passivation layer, so that the passivation ability of the first passivation layer is better than the passivation ability of the second passivation layer, thereby adjusting the anti-reflection state of sunlight in different regions, increasing the absorption of sunlight, and increasing the probability of photons being converted into electrons and holes. Among them, the absorption of short-wave sunlight in the first doped region and the absorption of long-wave sunlight in the second doped region are increased, thereby comprehensively improving the utilization rate of sunlight. In addition, the present application controls the passivation abilities of the first passivation layer and the second passivation layer to be different, and matches them with the emitter layer, which can reduce the non-equilibrium carrier recombination between different doped regions in the emitter layer and improve the conversion efficiency of solar cells.

[0056] It can be understood that the better the passivation ability of the passivation layer is, the longer the minority carrier lifetime of the passivation layer is. The passivation ability of the passivation layer is related to parameters such as the material, thickness and refractive index of the passivation layer.

[0057] In some embodiments, Figure 1 As shown, the first doping region 10 is located in the central area of ​​the surface of the emitter layer, and the second doping region 20 is located around the first doping region 10 .

[0058] In some embodiments, the square resistance of the first doped region is 190Ω / sqr~200Ω / sqr, for example, it can be 190Ω / sqr, 191Ω / sqr, 192Ω / sqr, 193Ω / sqr, 194Ω / sqr, 195Ω / sqr, 196Ω / sqr, 197Ω / sqr, 198Ω / sqr, 199Ω / sqr or 200Ω / sqr.

[0059] In some embodiments, the square resistance of the second doped region is 170Ω / sqr~190Ω / sqr, for example, it can be 170Ω / sqr, 175Ω / sqr, 180Ω / sqr, 181Ω / sqr, 182Ω / sqr, 183Ω / sqr, 184Ω / sqr, 185Ω / sqr, 186Ω / sqr, 187Ω / sqr, 188Ω / sqr, 189Ω / sqr or 190Ω / sqr.

[0060] In some embodiments, the thickness of the first passivation layer is greater than the thickness of the second passivation layer.

[0061] In some embodiments, the thickness of the first passivation layer is 65nm~85nm, for example, it can be 65nm, 66nm, 67nm, 68nm, 69nm, 70nm, 71nm, 72nm, 73nm, 74nm, 75nm, 76nm, 77nm, 78nm, 79nm, 80nm, 81nm, 82nm, 83nm, 84nm or 85nm.

[0062] In the present application, the thickness of the first passivation layer is greater than that of the second passivation layer. The first passivation layer not only has good passivation ability, but also can protect the emitter layer of the first doped region, thereby preventing the small PN junction depth in the high-doped region from being easily damaged and forming gap defects.

[0063] In some embodiments, the thickness of the second passivation layer is 65nm~85nm, for example, it can be 65nm, 66nm, 67nm, 68nm, 69nm, 70nm, 71nm, 72nm, 73nm, 74nm, 75nm, 76nm, 77nm, 78nm, 79nm, 80nm, 81nm, 82nm, 83nm, 84nm or 85nm.

[0064] In some embodiments, a refractive index of the first passivation layer is greater than a refractive index of the second passivation layer.

[0065] In some embodiments, the refractive index of the first passivation layer is 2.00-2.20, for example, 2.00, 2.01, 2.02, 2.03, 2.04, 2.05, 2.06, 2.07, 2.08, 2.09, 2.10, 2.11, 2.12, 2.13, 2.14, 2.15, 2.16, 2.17, 2.18, 2.19 or 2.20.

[0066] In some embodiments, the refractive index of the second passivation layer is 2.00-2.10, for example, 2.00, 2.01, 2.02, 2.03, 2.04, 2.05, 2.06, 2.07, 2.08, 2.09, 2.10, 2.11, 2.12, 2.13, 2.14, 2.15, 2.16, 2.17, 2.18, 2.19 or 2.20.

[0067] In some embodiments, the material of the first passivation layer and the material of the second passivation layer each independently include at least one of silicon oxynitride, silicon nitride, and silicon oxide.

[0068] In some embodiments, the solar cell further comprises an electrode disposed on a surface of the passivation layer away from the emitter layer, the electrode passes through the passivation layer and contacts the emitter layer, and the electrode comprises a main grid and a fine grid.

[0069] In some embodiments, Figure 2 As shown, the gate line width of the fine gate in the electrode located in the first doping region 10 is smaller than the gate line width of the fine gate in the electrode located in the second doping region 20 .

[0070] In some embodiments, a pitch of fine gates in the electrode located in the first doping region 10 is smaller than a pitch of fine gates in the electrode located in the second doping region 20 .

[0071] The present application further controls the width and spacing of the fine gates on the first doping region and the second doping region. The fine gates are mainly responsible for collecting current and are located in the first doping region with higher square resistance. The fine gates with small width and small spacing are arranged to reduce the lateral resistance of the emitter layer with high square resistance, thereby reducing power loss and improving the conversion efficiency of the battery cell; and through the difference in the width and spacing of the fine gates, the light-receiving area of ​​the solar cell is effectively increased, which is beneficial to the ability to generate photogenerated carriers; in addition, in the present application, the first doping region is located in the central area of ​​the solar cell, and the second doping region is located in the edge area of ​​the solar cell. The fine gate width in the second doping region is large, which can avoid problems such as broken gates and virtual printing caused by the small width of the fine gates at the edges during the printing process.

[0072] In some embodiments, the gate line width of the fine gate in the electrode located in the first doping region is 10μm~25μm, for example, it can be 10μm, 11μm, 12μm, 13μm, 14μm, 15μm, 16μm, 17μm, 18μm, 19μm, 20μm, 21μm, 22μm, 23μm, 24μm or 25μm.

[0073] In some embodiments, the spacing of the fine gates in the electrode located in the first doping region is 0.90 mm to 1.10 mm, for example, it can be 0.90 mm, 0.92 mm, 0.94 mm, 0.96 mm, 0.98 mm, 1.00 mm, 1.02 mm, 1.04 mm, 1.06 mm, 1.08 mm or 1.10 mm.

[0074] In some embodiments, the gate line width of the fine gate in the electrode located in the second doping region is 20μm~35μm, for example, it can be 20μm, 21μm, 22μm, 23μm, 24μm, 25μm, 26μm, 27μm, 28μm, 29μm, 30μm, 31μm, 32μm, 33μm, 34μm or 35μm.

[0075] In some embodiments, a spacing of fine gates in the electrode located in the second doping region is 1.05 mm to 1.40 mm, for example, 1.05 mm, 1.08 mm, 1.12 mm, 1.16 mm, 1.20 mm, 1.24 mm, 1.28 mm, 1.32 mm, 1.36 mm or 1.40 mm.

[0076] In some embodiments, Figure 1 As shown, the second doping region 20 includes a first partition 21 and a second partition 22, the second partition 22 is located in the edge area of ​​the emitter layer, the first partition 21 is located between the second partition 22 and the first doping region 10, and the square resistance of the first partition 21 is greater than the square resistance of the second partition 22; the second passivation layer includes a first partition passivation layer and a second partition passivation layer, the first partition passivation layer is correspondingly arranged on the first partition 21, the second partition passivation layer is correspondingly arranged on the second partition 22, and the passivation ability of the first partition passivation layer is greater than the passivation ability of the second partition passivation layer.

[0077] In some embodiments, the square resistance of the first partition is 180Ω / sqr~190Ω / sqr, for example, it can be 180Ω / sqr, 181Ω / sqr, 182Ω / sqr, 183Ω / sqr, 184Ω / sqr, 185Ω / sqr, 186Ω / sqr, 187Ω / sqr, 188Ω / sqr, 189Ω / sqr or 190Ω / sqr.

[0078] In some embodiments, the square resistance of the second partition is 170Ω / sqr~180Ω / sqr, for example, it can be 170Ω / sqr, 171Ω / sqr, 172Ω / sqr, 173Ω / sqr, 174Ω / sqr, 175Ω / sqr, 176Ω / sqr, 177Ω / sqr, 178Ω / sqr, 179Ω / sqr or 180Ω / sqr.

[0079] In some embodiments, a thickness of the first partition passivation layer is greater than a thickness of the second partition passivation layer.

[0080] In some embodiments, the refractive index of the first sub-area passivation layer is greater than the refractive index of the second sub-area passivation layer.

[0081] In some embodiments, Figure 2 As shown, the gate line width of the fine gate in the electrode located in the second partition 22 is greater than the gate line width of the fine gate in the electrode located in the first partition 21 .

[0082] In some embodiments, a pitch of fine grids in the electrode located in the second sub-area 22 is greater than a pitch of fine grids in the electrode located in the first sub-area 21 .

[0083] In some embodiments, the gate line width of the fine gate in the electrode located in the first partition is 20μm~30μm, for example, it can be 20μm, 21μm, 22μm, 23μm, 24μm, 25μm, 26μm, 27μm, 28μm, 29μm or 30μm.

[0084] In some embodiments, the spacing of the fine grids in the electrode located in the first partition is 1 mm to 1.1 mm, for example, it can be 1.01 mm, 1.02 mm, 1.03 mm, 1.04 mm, 1.05 mm, 1.06 mm, 1.07 mm, 1.08 mm, 1.09 mm or 1.10 mm.

[0085] In some embodiments, the gate line width of the fine gate in the electrode located in the second partition is 25μm~35μm, for example, it can be 25μm, 26μm, 27μm, 28μm, 29μm, 30μm, 31μm, 32μm, 33μm, 34μm or 35μm.

[0086] In some embodiments, the spacing of the fine grids in the electrode located in the second partition is 1.1 mm to 1.3 mm, for example, it can be 1.10 mm, 1.12 mm, 1.14 mm, 1.16 mm, 1.18 mm, 1.20 mm, 1.22 mm, 1.24 mm, 1.26 mm, 1.28 mm or 1.30 mm.

[0087] In some embodiments, the solar cell is a PERC cell or a TOPCon cell.

[0088] A second aspect of the present application provides a method for preparing a solar cell as described in the first aspect, the method comprising:

[0089] Doping one side of the silicon substrate to form an emitter layer, wherein a surface of the emitter layer is divided into the first doping region and the second doping region;

[0090] A first passivation layer is formed on the first doping region of the emitter layer, and a second passivation layer is formed on the second doping region of the emitter layer.

[0091] In some embodiments, the method for preparing the passivation layer includes:

[0092] shielding the second doping region of the emitter layer, and forming the first passivation layer at a position of the emitter layer located at the first doping region;

[0093] The first doping region of the emitter layer is shielded, and the second passivation layer is formed at a position of the emitter layer where the second doping region is located.

[0094] The embodiments of the present application will be described in detail below in conjunction with examples. It should be understood that these examples are only used to illustrate the present application and are not intended to limit the scope of the present application. The experimental methods for which specific conditions are not specified in the following examples are preferably referred to the guidance provided in the present application, and can also be based on the experimental manual or normal conditions in this area, can also be based on the conditions recommended by the manufacturer, or refer to experimental methods known in the art.

[0095] Example 1

[0096] S1. Clean and texturize a P-type silicon wafer with a thickness of 150 μm and a size of 210 mm × 210 mm;

[0097] S2, using a tubular diffusion furnace to diffuse phosphorus on the front side of the silicon wafer, after which the silicon wafer forms an emitter layer, wherein the central area of ​​the emitter layer is a first doping area, with a square resistance of 190Ω / sqr and a size of 100mm×100mm, the surrounding area with a size of 30mm from the central area is a first partition, with a square resistance of 180Ω / sqr, and the remaining area is a second partition, with a square resistance of 170Ω / sqr;

[0098] S3, the silicon substrate is subjected to a chain pre-oxidation treatment at 700° C. to form a first silicon oxide layer with a thickness of 2 nm on the front side of the silicon substrate;

[0099] S4, using a sodium hydroxide solution with a mass concentration of 3% to etch the back and edge of the silicon substrate, and remove the surface phosphosilicate glass at the same time;

[0100] S5, performing a tubular post-oxidation treatment on the silicon substrate at 690° C. to form a second silicon oxide layer with a thickness of 2 nm on the front side of the silicon substrate;

[0101] S6, shielding the first partition and the second partition, and depositing a first passivation layer in the first doping region by PECVD; shielding the first doping region and the second partition, and forming a first partition passivation layer in the first partition; shielding the first doping region and the first partition, and forming a second partition passivation layer in the second partition;

[0102] Among them, the thickness of the first passivation layer is 74.5nm, and the refractive index is 2.088; the first passivation layer is composed of a first silicon nitride layer, a second silicon nitride layer and a silicon oxynitride layer arranged in sequence away from the silicon substrate, the thickness of the first silicon nitride layer is 9nm, and the silicon-nitrogen ratio is 1:4.2; the thickness of the second silicon nitride layer is 37nm, and the silicon-nitrogen ratio is 1:8.8; the thickness of the silicon oxynitride layer is 28.5, and the silicon-nitrogen ratio is 1:5.4. The test shows that the minority carrier lifetime of the first passivation layer is 85μs;

[0103] The thickness of the first partition passivation layer is 74.1nm, and the refractive index is 2.083; the first partition passivation layer includes a first silicon nitride layer, a second silicon nitride layer, and a silicon oxynitride layer stacked in sequence away from the silicon substrate, the thickness of the first silicon nitride layer is 12nm, and the silicon nitrogen ratio is 1:4.2; the thickness of the second silicon nitride layer is 34.5nm, and the silicon nitrogen ratio is 1:8.8; the thickness of the silicon oxynitride layer is 27.6nm, and the silicon nitrogen ratio is 1:5.4. The minority carrier lifetime of the first partition passivation layer is 76μs.

[0104] The thickness of the second partition passivation layer is 73.2nm, and the refractive index is 2.079; the second partition passivation layer includes a first silicon nitride layer, a second silicon nitride layer, and a silicon oxynitride layer stacked in sequence in a direction away from the silicon substrate, the thickness of the first silicon nitride layer is 7nm, and the silicon nitrogen ratio is 1:5.0; the thickness of the second silicon nitride layer is 39.5nm, and the silicon nitrogen ratio is 1:8.8; the thickness of the silicon oxynitride layer is 26.7nm, and the silicon nitrogen ratio is 1:5.4. The test shows that the minority carrier lifetime of the second partition passivation layer is 64μs;

[0105] Aluminum oxide and three silicon nitride layers with a total thickness of 83 nm are formed on the back side by PECVD to form a back passivation layer, wherein the back passivation layer comprises an aluminum oxide layer, a first silicon nitride layer, a second silicon nitride layer and a third silicon nitride layer stacked in sequence in a direction away from the silicon substrate, wherein the aluminum oxide layer has a thickness of 16 nm, the first silicon nitride layer has a thickness of 20 nm, and the silicon-nitrogen ratio is 1:4; the second silicon nitride layer has a thickness of 16 nm, and the silicon-nitrogen ratio is 1:7.5; the third silicon nitride layer has a thickness of 31 nm, and the silicon-nitrogen ratio is 1:10.3;

[0106] S7, laser grooving the back passivation layer, using printed silver paste to form pads, printing aluminum paste to form grid lines, and sintering to form a back metallization layer;

[0107] S8, printing silver paste on the front passivation layer to form pads and gate lines, and sintering to form front electrodes; the printing width of the main grid in the front electrode is 35 μm, and the spacing is 17.3 mm;

[0108] The width of the fine gate formed in the first doping region is 24 μm, and the spacing is 1.053 mm;

[0109] The fine gate width formed in the first partition is 26μm and the spacing is 1.121mm;

[0110] The fine grid width formed in the second partition was 29 μm and the spacing was 1.198 mm, and a solar cell was prepared.

[0111] Example 2

[0112] A solar cell was prepared according to the method of Example 1, with the only difference being that in step S7, the width of the front fine grid printing was 24 μm and the spacing was 1.053 mm.

[0113] Comparative Example 1

[0114] A solar cell is prepared according to the method of Example 1, the only difference being that in step S5, the front passivation layer uses the first passivation layer, that is, the first sub-area passivation layer and the second sub-area passivation layer are all replaced by the first passivation layer.

[0115] The performance of the solar cells prepared in the above examples and comparative examples was tested under standard test conditions (AM1.5, 25°C, 1000 W / m 2 ), the steady-state test was performed on an IV tester, and the test results are shown in Table 1.

[0116] Table 1

[0117]

[0118] Among them, Voc represents the open circuit voltage, Isc represents the short circuit current, Fill Factor represents the fill factor, and Eta represents the battery conversion efficiency.

[0119] From the above table we can see that:

[0120] (1) Compared with Example 2, it can be seen that the present application further controls the width and spacing of the fine gates on the first doping region and the second doping region. The fine gates are mainly responsible for collecting current and are located in the first doping region with higher square resistance. The fine gates with small width and small spacing are arranged to reduce the lateral resistance of the emitter layer with high square resistance, thereby reducing power loss and improving the conversion efficiency of the battery cell; and through the difference in the width and spacing of the fine gates, the light receiving area of ​​the solar cell is effectively increased, which is beneficial to the ability to generate photogenerated carriers; in addition, in the present application, the first doping region is located in the central area of ​​the solar cell, and the second doping region is located in the edge area of ​​the solar cell. The fine gate width in the second doping region is large, which can avoid problems such as broken gates and virtual printing caused by the small width of the fine gates at the edge during printing.

[0121] (2) Compared with Example 1, it can be seen that the present application divides the emitter layer into a first doping region and a second doping region according to the square resistance, and matches the first passivation layer and the second passivation layer, so that the passivation ability of the first passivation layer is better than the passivation ability of the second passivation layer, thereby adjusting the anti-reflection state of sunlight in different regions, increasing the absorption of sunlight, and increasing the probability of photons being converted into electrons and holes. Among them, the absorption of short-wave sunlight in the first doping region and the absorption of long-wave sunlight in the second doping region are increased, thereby comprehensively improving the utilization rate of sunlight. In addition, the present application controls the passivation ability of the first passivation layer and the second passivation layer to be different, and matches them with the emitter layer, which can reduce the non-equilibrium carrier recombination between different doping regions in the emitter layer and improve the conversion efficiency of solar cells.

[0122] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0123] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

Claims

1. A solar cell, characterized in that: The solar cell comprises a silicon substrate, an emitter layer and a passivation layer, wherein the emitter layer is arranged on the surface of the silicon substrate; The surface of the emitter layer has a first doping region and a second doping region, and the sheet resistance of the emitter layer in the first doping region is greater than the sheet resistance of the emitter layer in the second doping region; The passivation layer is arranged on a side of the emitter layer away from the silicon substrate, and the passivation layer includes a first passivation layer and a second passivation layer, the first passivation layer is correspondingly arranged on the first doped region, and the second passivation layer is correspondingly arranged on the second doped region; The passivation capability at the first passivation layer is greater than the passivation capability at the second passivation layer, and the minority carrier lifetime at the first passivation layer is greater than the minority carrier lifetime at the second passivation layer; The first doping region is located in a central area of ​​a surface of the emitter layer, and the second doping region is located around the first doping region.

2. The solar cell according to claim 1, wherein: The sheet resistance of the first doped region is 190Ω / sqr to 200Ω / sqr.

3. The solar cell according to claim 1, wherein: The sheet resistance of the second doping region is 170Ω / sqr to 190Ω / sqr.

4. The solar cell according to claim 1, wherein: The thickness of the first passivation layer is greater than the thickness of the second passivation layer.

5. The solar cell according to claim 1, wherein: The thickness of the first passivation layer is 65 nm to 85 nm.

6. The solar cell according to claim 1, wherein: The thickness of the second passivation layer is 65 nm to 85 nm.

7. The solar cell according to claim 1, wherein: The refractive index of the first passivation layer is greater than the refractive index of the second passivation layer.

8. The solar cell according to claim 7, wherein: The refractive index of the first passivation layer is 2.00-2.

20.

9. The solar cell according to claim 7, wherein: The refractive index of the second passivation layer is 2.00-2.

20.

10. The solar cell according to claim 1, wherein: The material of the first passivation layer and the material of the second passivation layer respectively and independently include at least one of silicon oxynitride, silicon nitride and silicon oxide.

11. The solar cell according to any one of claims 1 to 10, characterized in that: The solar cell further comprises an electrode disposed on a surface of the passivation layer away from the emitter layer, the electrode passes through the passivation layer and contacts the emitter layer, the electrode comprises a main grid and a fine grid, and the electrode satisfies at least one of the following conditions: (1) The gate line width of the fine gate in the electrode located in the first doping region is smaller than the gate line width of the fine gate in the electrode located in the second doping region; (2) A pitch of fine gates in the electrode located in the first doping region is smaller than a pitch of fine gates in the electrode located in the second doping region.

12. The solar cell according to claim 11, wherein: The gate line width of the fine gate in the electrode located in the first doping region is 10 μm to 25 μm; The spacing of the fine gates in the electrode located in the first doping region is 0.90 mm to 1.10 mm.

13. The solar cell according to claim 11, wherein: The gate line width of the fine gate in the electrode located in the second doping region is 20 μm to 35 μm; The spacing of the fine gates in the electrode located in the second doping region is 1.05 mm to 1.40 mm.

14. The solar cell according to claim 11, wherein: The second doping region includes a first partition and a second partition, the second partition is located in the edge region of the emitter layer, the first partition is located between the second partition and the first doping region, and the sheet resistance of the first partition is greater than the sheet resistance of the second partition; The second passivation layer includes a first partition passivation layer and a second partition passivation layer. The first partition passivation layer is correspondingly arranged on the first partition, and the second partition passivation layer is correspondingly arranged on the second partition. The passivation capability of the first partition passivation layer is greater than the passivation capability of the second partition passivation layer.

15. The solar cell according to claim 14, wherein: The square resistance of the first partition is 180Ω / sqr to 190Ω / sqr.

16. The solar cell according to claim 14, wherein: The sheet resistance of the second partition is 170Ω / sqr to 180Ω / sqr.

17. The solar cell according to claim 14, wherein: The thickness of the first sub-area passivation layer is greater than the thickness of the second sub-area passivation layer.

18. The solar cell according to claim 14, wherein: The refractive index of the first sub-area passivation layer is greater than the refractive index of the second sub-area passivation layer.

19. The solar cell according to claim 14, wherein: The gate line width of the fine gate in the electrode located in the second sub-area is greater than the gate line width of the fine gate in the electrode located in the first sub-area.

20. The solar cell according to claim 14, wherein: A pitch of fine grids in the electrode located in the second sub-area is greater than a pitch of fine grids in the electrode located in the first sub-area.

21. The solar cell according to claim 14, wherein: The gate line width of the fine grid in the electrode located in the first sub-area is 20 μm to 30 μm; the spacing of the fine grid in the electrode located in the first sub-area is 1 mm to 1.1 mm; The gate line width of the fine grid in the electrode located in the second sub-area is 25 μm to 35 μm; the spacing of the fine grid in the electrode located in the second sub-area is 1.1 mm to 1.3 mm.

22. A method for preparing a solar cell according to any one of claims 1 to 21, characterized in that: The preparation method comprises: Doping one side of the silicon substrate to form an emitter layer, wherein a surface of the emitter layer is divided into the first doping region and the second doping region; forming a first passivation layer on the first doped region of the emitter layer, and forming a second passivation layer on the second doped region of the emitter layer; The first doping region is located in a central area of ​​a surface of the emitter layer, and the second doping region is located around the first doping region.

23. The preparation method according to claim 22, characterized in that: The preparation method of the passivation layer comprises: shielding the second doping region of the emitter layer, and forming the first passivation layer at a position of the emitter layer located at the first doping region; The first doping region of the emitter layer is shielded, and the second passivation layer is formed at a position of the emitter layer where the second doping region is located.

Images