CXL switch card, CXL memory allocation system, allocation method and device

Abstract

The present invention relates to the field of computer technology, and provides a CXL switching board, a CXL memory allocation system, an allocation method and a device. The CXL switching board is provided with a CXL switching unit and a micro control unit, the CXL switching unit includes at least one first port and at least one second port, the first port is used to connect a CPU, and the second port is used to connect a CXL memory board; the micro control unit is used to obtain the memory capacity of the local memory corresponding to the CPU after the CXL switching unit is powered on, and the micro control unit or the CXL switching unit is used to calculate the CXL memory start address according to the memory capacity; the CXL switching unit is used to write the CXL memory start address into the register of the first port corresponding to the CPU, and use the CXL memory start address as the first address of the CXL memory to allocate the CXL memory in the CXL memory board to the CPU. The present invention realizes automatic and efficient allocation of CXL memory to the CPU.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a CXL switch board, a CXL memory allocation system, an allocation method and a device. Background Art

[0002] With the development of artificial intelligence and high-performance computing, the complexity of artificial intelligence models and the amount of data calculation have increased significantly, and the demand for memory resources has increased exponentially. In order to meet the growing demand for memory resources, the existing solution is to allocate CXL (Compute Express Link) memory resources to the CPU in the server system.

[0003] In the above solution, it is necessary to manually determine the memory capacity of the local memory corresponding to each CPU, and then calculate the starting address of the CXL memory to be allocated based on the memory capacity of the local memory, and finally complete the CXL memory allocation. Since CXL memory allocation requires a lot of manual input, CXL memory allocation efficiency is low, and additional labor costs are added. In addition, manual calculations are prone to errors, which will cause CXL memory allocation to fail. Summary of the invention

[0004] The present invention provides a CXL switch card, a CXL memory allocation system, an allocation method and a device, which are used to solve the problem in the prior art that CXL memory allocation requires a lot of manual input, resulting in low CXL memory allocation efficiency, high labor cost and easy allocation failure.

[0005] The present invention provides a CXL switch board, wherein the CXL switch board is provided with a CXL switch unit and a micro control unit connected to the CXL switch unit, wherein the CXL switch unit comprises at least one first port and at least one second port, wherein the first port is used to connect to a CPU, and the second port is used to connect to a CXL memory board to obtain a CXL memory in the CXL memory board;

[0006] The micro control unit is used to obtain the memory capacity of the local memory corresponding to the CPU after the CXL switching unit is powered on, and the micro control unit or the CXL switching unit is used to calculate the CXL memory start address according to the memory capacity;

[0007] The CXL switching unit is used to write the CXL memory start address into the register of the first port corresponding to the CPU, use the CXL memory start address as the first address of the CXL memory, and allocate the CXL memory in the CXL memory card to the CPU.

[0008] According to a CXL switch board provided by the present invention, a first voltage regulator and a first power-on controller are also provided on the CXL switch board, the first power-on controller is connected to the micro control unit and the first voltage regulator, the first voltage regulator is connected to the CXL switch unit, the first power-on controller is used to control the first voltage regulator to power the CXL switch unit, after the CXL switch unit is powered on, the first voltage regulator feeds back a power-on completion signal of the CXL switch unit to the first power-on controller, and the first power-on controller feeds back the power-on completion signal of the CXL switch unit to the micro control unit.

[0009] According to a CXL switch board provided by the present invention, the micro control unit is used to control the CXL memory board to power on after receiving the power-on completion signal of the CXL switch unit, and obtain the memory capacity of the local memory corresponding to the CPU.

[0010] According to a CXL switch board provided by the present invention, the CXL switch unit is further used to send a write completion signal to the micro control unit after writing the CXL memory start address into the register of the first port corresponding to the CPU. The micro control unit is further used to control the CPU to power on after receiving the write completion signal. After the CPU is powered on, the CXL switch unit uses the CXL memory start address as the first address of the CXL memory to allocate the CXL memory in the CXL memory board to the CPU.

[0011] The present invention also provides a CXL memory allocation system, comprising: a host board, a CXL switch board and a CXL memory board, wherein the host board is provided with at least one CPU and local memory respectively corresponding to the CPU, the CXL switch board is provided with a CXL switch unit and a micro control unit connected to the CXL switch unit, the CXL switch unit comprises at least one first port and at least one second port, each of the CPUs is respectively connected to the first port, one of the first ports is connected to only one CPU, and the CXL switch unit is connected to the CXL memory board via the second port to obtain the CXL memory in the CXL memory board;

[0012] The micro control unit is used to obtain the memory capacity of the local memory corresponding to the CPU after the CXL switching unit is powered on, and the micro control unit or the CXL switching unit is used to calculate the CXL memory start address according to the memory capacity;

[0013] The CXL switching unit is used to write the CXL memory start address into the register of the first port corresponding to the CPU, use the CXL memory start address as the first address of the CXL memory, and allocate the CXL memory in the CXL memory card to the CPU.

[0014] According to a CXL memory allocation system provided by the present invention, a first voltage regulator and a first power-on controller are also provided on the CXL switch board, the first power-on controller is connected to the micro control unit and the first voltage regulator, the first voltage regulator is connected to the CXL switch unit, the first power-on controller is used to control the first voltage regulator to power the CXL switch unit, after the CXL switch unit is powered on, the first voltage regulator feeds back a power-on completion signal of the CXL switch unit to the first power-on controller, and the first power-on controller feeds back the power-on completion signal of the CXL switch unit to the micro control unit.

[0015] According to a CXL memory allocation system provided by the present invention, the CXL memory board is provided with at least one CXL memory and a memory controller and a second voltage regulator corresponding to the CXL memory, the memory controller is connected to the corresponding CXL memory and the second voltage regulator, the micro control unit is connected to the second voltage regulator, and is further used to control the second voltage regulator to supply power to the corresponding memory controller after the CXL switching unit is powered on, and receive a memory controller power-on completion signal fed back by the second voltage regulator;

[0016] The second port is connected to the memory controller, and one memory controller is only connected to one second port. The CXL switching unit is used to establish a communication link with the memory controller based on the second port after the memory controller is powered on, and to feed back a communication link completion signal to the micro control unit. The CXL switching unit is used to obtain the CXL memory through the second port after the communication link is established.

[0017] According to a CXL memory allocation system provided by the present invention, at least one second port is connected to a plurality of the memory controllers.

[0018] According to a CXL memory allocation system provided by the present invention, the host board is further provided with a baseboard controller, and the baseboard controller is connected to the micro control unit and the local memory;

[0019] The microcontroller unit is used to send a memory capacity read instruction to the baseboard controller after the CXL memory board is powered on. The baseboard controller is used to obtain the memory capacity of the local memory corresponding to the CPU after receiving the memory capacity read instruction, and send the memory capacity to the microcontroller unit.

[0020] According to a CXL memory allocation system provided by the present invention, the host board is also provided with an I3C hub. When there are multiple CPUs on the host board, the baseboard controller is connected to the local memories corresponding to the multiple CPUs through the I3C hub.

[0021] According to a CXL memory allocation system provided by the present invention, the local memory includes a serial detection chip, and the baseboard controller is connected to the serial detection chip to read the serial detection chip to obtain the memory capacity.

[0022] According to a CXL memory allocation system provided by the present invention, the host board is further provided with a second power-on controller and a third voltage regulator corresponding to the CPU, and the second power-on controller is connected to the baseboard controller and the third voltage regulator;

[0023] The CXL switching unit is further configured to send a write completion signal to the micro control unit after writing the CXL memory start address into the register of the first port corresponding to the CPU;

[0024] The microcontroller unit is also used to send a host power-on instruction to the substrate controller after receiving the write completion signal. The substrate controller is also used to send the host power-on instruction to the second power-on controller. The second power-on controller is used to control the third voltage regulator to power on the corresponding CPU after receiving the host power-on instruction. After the CPU is powered on, a communication link is established with the first port. After power-on is completed, the third voltage regulator sends a host power-on completion signal to the microcontroller unit through the second power-on controller and the substrate controller.

[0025] According to a CXL memory allocation system provided by the present invention, at least one of the CPUs is connected to a plurality of the first ports.

[0026] According to a CXL memory allocation system provided by the present invention, the micro control unit is also used to obtain the local memory identifier while obtaining the memory capacity of the local memory corresponding to the CPU, and send the local memory identifier to the CXL switching unit, and the CXL switching unit is used to write the CXL memory start address into the register of the first port corresponding to the local memory identifier according to a preset identifier mapping table, and the identifier mapping table records the mapping relationship between the first port identifier and the local memory identifier.

[0027] The present invention further provides a CXL memory allocation method, which is implemented based on any of the above CXL memory allocation systems and applied to the microcontroller unit, and the method comprises:

[0028] After the CXL switching unit is powered on, obtaining the memory capacity of the local memory corresponding to the CPU;

[0029] The memory capacity is sent to the CXL switching unit, where the memory capacity is used to instruct the CXL switching unit to calculate a CXL memory start address according to the memory capacity, and write the CXL memory start address into a register of a first port corresponding to the CPU, and use the CXL memory start address as the first address of the CXL memory to allocate the CXL memory in the CXL memory board to the CPU; or the CXL memory start address is calculated according to the memory capacity, and the CXL memory start address is sent to the CXL switching unit, where the CXL memory start address is used to instruct the CXL switching unit to write the CXL memory start address into the register of the first port corresponding to the CPU, and use the CXL memory start address as the first address of the CXL memory to allocate the CXL memory in the CXL memory board to the CPU.

[0030] According to a CXL memory allocation method provided by the present invention, after the CXL switching unit is powered on, the memory capacity of the local memory corresponding to the CPU is obtained, including:

[0031] After the CXL switching unit is powered on, control the CXL memory board to power on;

[0032] After the CXL memory board is powered on, the memory capacity of the local memory corresponding to the CPU is obtained.

[0033] A CXL memory allocation method provided by the present invention further includes:

[0034] receiving a write completion signal sent by the CXL switch unit, and controlling the CPU in the host board to power on, so that after the CPU is powered on, the CXL switch unit uses the CXL memory start address as the first address of the CXL memory, and allocates the CXL memory in the CXL memory board to the CPU;

[0035] The write completion signal is sent after the CXL switch unit writes the CXL memory start address into the register of the first port corresponding to the CPU.

[0036] The present invention further provides a CXL memory allocation device, which is implemented based on any one of the CXL memory allocation systems described above and is applied to the microcontroller unit, and the device comprises:

[0037] A memory capacity acquisition module, used to acquire the memory capacity of the local memory corresponding to the CPU after the CXL switching unit is powered on;

[0038] a memory capacity processing module, configured to send the memory capacity to the CXL switching unit, wherein the memory capacity is used to instruct the CXL switching unit to calculate a CXL memory start address according to the memory capacity, and write the CXL memory start address into a register of a first port corresponding to the CPU, and use the CXL memory start address as the first address of the CXL memory to allocate a CXL memory in a CXL memory board to the CPU; or calculate a CXL memory start address according to the memory capacity, and send the CXL memory start address to the CXL switching unit, wherein the CXL memory start address is used to instruct the CXL switching unit to write the CXL memory start address into the register of the first port corresponding to the CPU, and use the CXL memory start address as the first address of the CXL memory to allocate a CXL memory in a CXL memory board to the CPU.

[0039] The present invention further provides a non-transitory computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the CXL memory allocation method described above is implemented.

[0040] The present invention provides a CXL switch board, a CXL memory allocation system, an allocation method and a device. The CXL switch board is provided with a CXL switch unit and a micro control unit connected to the CXL switch unit. The CXL switch unit includes at least one first port and at least one second port. The first port is used to connect to a CPU, and the second port is used to connect to a CXL memory board to obtain a CXL memory in the CXL memory board. The micro control unit is used to obtain the memory capacity of the local memory corresponding to the CPU after the CXL switch unit is powered on. The micro control unit or the CXL switch unit is used to calculate a CXL memory start address according to the memory capacity. The CXL switch unit is used to write the CXL memory start address into a register of a first port corresponding to the CPU, and use the CXL memory start address as the first address of the CXL memory to allocate the CXL memory in the CXL memory board to the CPU. After the CXL switching unit is powered on, the microcontroller unit on the CXL switching board will automatically obtain the memory capacity of the local memory corresponding to the CPU, and the microcontroller unit or the CXL switching unit will calculate the CXL memory start address according to the memory capacity. The CXL switching unit automatically writes the CXL memory start address to the register of the first port, thereby realizing automatic allocation of the CXL memory to the CPU, and there is no need to manually obtain the memory capacity of the local memory corresponding to the CPU, nor to manually calculate the register of the first port, which reduces labor costs, avoids manual allocation errors, and improves the memory allocation efficiency of the entire CXL memory allocation system. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0042] Figure 1 It is a schematic diagram of the framework structure of the CXL memory allocation system provided by the present invention;

[0043] Figure 2 It is a specific structural diagram of the CXL memory allocation system provided by the present invention;

[0044] Figure 3 This is one of the flow charts of the CXL memory allocation method provided by the present invention;

[0045] Figure 4 This is the second flow chart of the CXL memory allocation method provided by the present invention;

[0046] Figure 5 It is a structural schematic diagram of the CXL memory allocation device provided by the present invention. DETAILED DESCRIPTION

[0047] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0048] In order to facilitate understanding of the embodiments of the present invention, the relevant English abbreviations in the embodiments of the present invention are explained as follows:

[0049] CXL: Compute Express Link, a high-speed interconnect technology designed to improve the communication efficiency between processors, memory devices, and accelerators (such as GPUs, FPGAs, etc.) in data centers and high-performance computing environments.

[0050] DIMM: Dual-Inline-Memory-Modules, dual inline memory modules.

[0051] CPLD: Complex Programmable Logic Device, complex programmable logic device.

[0052] SPD: Serial Presence Detect, the module has serial presence detection. The SPD chip on the memory records various information of the memory, including: identification, frequency, timing, voltage, manufacturer, capacity, production date and other information.

[0053] VR: Voltage Regulated, voltage regulation.

[0054] BMC: Baseboard Management Controller, baseboard management controller.

[0055] MCU: Microcontroller Unit, micro control unit.

[0056] USP: upstream port.

[0057] DSP: downstream port.

[0058] I2C: Inter-Integrated Circuit, integrated circuit bus.

[0059] I3C: Improved Inter Integrated Circuit, the evolution of the I2C protocol.

[0060] The CXL switch card of the first embodiment of the present invention is as follows: Figure 1 and 2 As shown, the CXL switch board is provided with a CXL switch unit CXL SW and a micro control unit MCU connected to the CXL switch unit CXL SW. The CXL switch unit CXLSW includes at least one first port and at least one second port. In this embodiment, the first port is a USP port (upstream port), and the second port is a DSP port (downstream port). Figure 2 Two first ports USP_0 and USP_1 and two second ports DSP_0 and DSP_1 are shown respectively. The first port is used to connect to the CPU, and the second port is used to connect to the CXL memory board to obtain the CXL memory in the CXL memory board, wherein the CPU is located in the upstream host board, and each CPU corresponds to a local memory, and the CXL memory board is provided with at least one CXL memory.

[0061] In this embodiment, the micro control unit MCU is used to obtain the memory capacity of the local memory corresponding to the CPU after the CXL switch unit CXL SW is powered on, and the micro control unit MCU or the CXL switch unit CXL SW is used to calculate the CXL memory start address according to the memory capacity. For example: a simple calculation method, the capacity of the CPU local memory is 64GB, then the logical address of the last byte in 64GB + 1 is used as the CXL memory start address.

[0062] The CXL switch unit CXL SW is used to write the CXL memory start address into the register of the first port corresponding to the CPU, use the CXL memory start address as the first address of the CXL memory, and allocate the CXL memory in the CXL memory board to the CPU, thereby realizing the function of automatically allocating CXL memory to the CPU.

[0063] In the CXL switching board of the present embodiment, the microcontroller unit MCU automatically obtains the memory capacity of the local memory corresponding to the CPU after the CXL switching unit is powered on, and the microcontroller unit or the CXL switching unit calculates the CXL memory start address according to the memory capacity, and the CXL switching unit automatically writes the CXL memory start address to the register of the first port, thereby realizing the CXL memory allocation to the CPU, and there is no need to manually obtain the memory capacity of the local memory corresponding to the CPU, nor to manually calculate the register of the first port, which reduces labor costs, avoids manual allocation errors, and improves the memory allocation efficiency of the entire CXL memory allocation system.

[0064] In this embodiment, the CXL switch board is further provided with a first voltage regulator VR_SW and a first power-on controller CPLD_1, the first power-on controller CPLD_1 is connected to the micro control unit MCU and the first voltage regulator VR_SW, and the first voltage regulator VR_SW is connected to the CXL switch unit CXL SW. The first power-on controller CPLD_1 is used to control the first voltage regulator VR_SW to supply power to the CXL switch unit CXL SW, and after the CXL switch unit CXL SW is powered on, the first voltage regulator VR_SW feeds back a CXL switch unit power-on completion signal to the first power-on controller CPLD_1, and the first power-on controller CPLD_1 feeds back the CXL switch unit power-on completion signal to the micro control unit MCU.

[0065] Specifically, the micro control unit MCU is connected to the first power-on controller CPLD_1 via UART, the micro control unit MCU and the CXL switch unit CXL SW are connected via I2C, and the micro control unit MCU sends the memory capacity or the CXL memory start address to the CXL switch unit CXL SW via I2C. Of course, the CXL switch board is also provided with a power supply (PowerSupply) switch button PWR_button, and PWR_button is connected to the first power-on controller CPLD_1. After pressing PWR_button, the first power-on controller CPLD_1 receives the power-on signal and sends a power-on enable signal PWREN_SW to the first voltage regulator VR_SW. The first voltage regulator VR_SW outputs a voltage to the CXL switching unit CXL SW. The CXL switching unit CXL SW completes its own initialization and enables the first port and the second port. The first voltage regulator VR_SW sends a CXL switching unit power-on completion signal PWRGD_SW to the first power-on controller CPLD_1. The first power-on controller CPLD_1 transmits the CXL switching unit power-on completion signal to the microcontroller unit MCU through the UART interface.

[0066] The micro control unit MCU is used for controlling the CXL memory board to power on after receiving the power-on completion signal of the CXL switching unit, and obtaining the memory capacity of the local memory corresponding to the CPU.

[0067] In this embodiment, the first power-on controller CPLD_1 controls the power-on of the CXL switch unit CXL SW, and feeds back the power-on completion signal of the CXL switch unit to the microcontroller unit MCU, which is conducive to the microcontroller unit MCU controlling the power-on timing of the CXL memory board, that is, after the CXL switch unit CXL SW is powered on, the microcontroller unit MCU controls the power-on of the CXL memory board. Moreover, after the CXL memory board is powered on, the memory capacity of the local memory corresponding to the CPU is obtained. This avoids the problem of CXL memory allocation failure caused by the failure to power on the CXL memory board after the memory capacity is obtained.

[0068] In this embodiment, the CXL switching unit CXL SW is also used to send a write completion signal to the micro control unit MCU after writing the CXL memory start address into the register of the first port corresponding to the CPU. Specifically, the write completion signal is sent to the micro control unit MCU via I2C. The micro control unit MCU is also used to control the CPU to power on after receiving the write completion signal. After the CPU is powered on, the CXL switching unit uses the CXL memory start address as the first address of the CXL memory to allocate the CXL memory in the CXL memory board to the CPU. That is, after the CXL memory start address is written successfully, the CPU is controlled to power on, so as to avoid the problem that the CXL memory start address is not written into the corresponding first port after the CPU is powered on, resulting in the failure of CXL memory allocation.

[0069] The CXL memory allocation system of the second embodiment of the present invention is as follows: Figure 1 and 2 As shown, it includes: a host board, a CXL switch board and a CXL memory board.

[0070] The host board is provided with at least one CPU and local memory corresponding to the CPU. Figure 2 Two CPUs in a host board are shown: CPU_0 and CPU_1, and CPU_0 and CPU_1 are connected to local memory DIMM_0 and DIMM_1 respectively through DDR5 bus. The CXL switch board can be the CXL switch board of the above embodiment, and the CXL switch board is provided with a CXL switch unit CXL SW and a micro control unit MCU connected to the CXL switch unit CXL SW, and the CXL switch unit CXL SW includes at least one first port and at least one second port, each of the CPUs is connected to the first port respectively, and one of the first ports is connected to only one CPU (if multiple CPUs are connected, the register corresponding to the first port will be written with the CXL memory start address corresponding to multiple CPUs, and conflicts will occur when allocating CXL memory), and the CXL switch unit CXL SW is connected to the CXL memory board through the second port to obtain the CXL memory in the CXL memory board. Specifically, the CPU and the first port are connected through the CXL bus (MCIO cable), and the second port and the CXL memory board are also connected through the CXL bus (MCIO cable).

[0071] The micro control unit MCU is used for obtaining the memory capacity of the local memory corresponding to the CPU after the CXL switch unit CXL SW is powered on. The micro control unit MCU or the CXL switch unit CXL SW is used for calculating the CXL memory start address according to the memory capacity.

[0072] The CXL switch unit CXL SW is used for writing the CXL memory start address into the register of the first port corresponding to the CPU, using the CXL memory start address as the first address of the CXL memory, and allocating the CXL memory in the CXL memory card to the CPU.

[0073] In the CXL memory allocation system of the present embodiment, the microcontroller unit MCU automatically obtains the memory capacity of the local memory corresponding to the CPU after the CXL switching unit is powered on, and the microcontroller unit or the CXL switching unit calculates the CXL memory start address according to the memory capacity, and the CXL switching unit automatically writes the CXL memory start address to the register of the first port, thereby realizing automatic allocation of the CXL memory to the CPU, and there is no need to manually obtain the memory capacity of the local memory corresponding to the CPU, nor to manually calculate the register of the first port, which reduces labor costs, avoids manual allocation errors, and improves the memory allocation efficiency of the entire CXL memory allocation system.

[0074] In this embodiment, the CXL switch board is further provided with a first voltage regulator VR_SW and a first power-on controller CPLD_1, the first power-on controller CPLD_1 is connected to the micro control unit MCU and the first voltage regulator VR_SW, the first voltage regulator VR_SW is connected to the CXL switch unit CXL SW, the first power-on controller CPLD_1 is used to control the first voltage regulator VR_SW to power the CXL switch unit CXL SW, the first voltage regulator VR_SW feeds back a CXL switch unit power-on completion signal to the first power-on controller CPLD_1 after the CXL switch unit CXLSW is powered on, and the first power-on controller CPLD_1 feeds back a CXL switch unit power-on completion signal to the micro control unit MCU. The specific internal structure of the CXL switch board is shown in the first embodiment above, which will not be repeated here.

[0075] In this embodiment, at least one CXL memory ( Figure 1 and 2 DIMM in the CXL memory) and a memory controller and a second voltage regulator corresponding to the CXL memory, Figure 2Two CXL memories, two corresponding memory controllers MXC_0 and MXC_1, and two second voltage regulators VR_MXC_0 and VR_MXC_1 corresponding to the two memory controllers MXC_0 and MXC_1 are shown respectively. The memory controller is connected to the corresponding CXL memory and the second voltage regulator, and the micro control unit MCU is connected to the second voltage regulator, and is also used to control the second voltage regulator to supply power to the corresponding memory controller after the CXL switching unit CXL SW is powered on, and receive the memory controller power-on completion signal fed back by the second voltage regulator.

[0076] The second port is connected to the memory controller, and one memory controller is only connected to one second port. The CXL switching unit CXL SW is used to establish a communication link (i.e., a CXL bus communication protocol link) with the memory controller based on the second port after the memory controller is powered on, and feed back a communication link completion signal to the micro control unit MCU, and the CXL switching unit CXL SW is used to obtain the CXL memory through the second port after the communication link is established. In this embodiment, the second voltage regulator feeds back the memory controller power-on completion signal to the micro control unit MCU, and the CXL switching unit CXL SW feeds back the communication link completion signal to the micro control unit MCU, so that the micro control unit MCU performs timing control, and after the CXL memory board is powered on and the CXL switching unit CXL SW establishes a communication link with the CXL memory board, the memory capacity of the local memory corresponding to the CPU is obtained, so as to avoid the situation where the CXL memory board fails to power on or fails to establish a communication link, resulting in a failure in CXL memory allocation.

[0077] Specifically, if Figure 2As shown, the microcontroller unit MCU is connected to two second voltage regulators VR_MXC_0 and VR_MXC_1 through a low-speed cable, and the memory controller is connected to the corresponding CXL memory through the DDR5 bus. The microcontroller unit MCU sends PWREN_MXC0 and PWREN_MXC1 power-on enable signals to VR_MXC_0 and VR_MXC_1 respectively, so that VR_MXC_0 and VR_MXC_1 power on the two memory controllers MXC_0 and MXC_1 respectively. After MXC_0 and MXC_1 are powered on and complete their own initialization, they obtain DIMM memory resources through the DDR5 bus. At the same time, the two second ports DSP_0 and DSP_1 of the CXL switch unit CXL SW establish communication links with MXC_0 and MXC_1 respectively, thereby obtaining CXL memory resources. The CXL switching unit CXL SW sends a communication link completion signal to the micro control unit MCU through I2C, and at the same time the micro control unit MCU receives the memory controller power-on completion signals PWRGD_MXC0 and PWRGD_MXC1 sent by VR_MXC_0 and VR_MXC_1 respectively.

[0078] In this embodiment, at least one second port is connected to a plurality of the memory controllers. One second port is connected to a plurality of memory controllers, which can maximize the use of second port resources, connect more CXL memories, and maximize the performance of the CXL bus.

[0079] In this embodiment, a baseboard controller BMC is also provided on the host board, and the baseboard controller BMC is connected to the micro control unit MCU and the local memory.

[0080] The microcontroller unit MCU is used to send a memory capacity read instruction to the baseboard controller BMC after the CXL memory board is powered on. Specifically, after the memory controller is powered on and the communication link between the second port and the memory controller is established, the microcontroller unit MCU sends the memory capacity read instruction to the baseboard controller BMC through the network (Eth, i.e., Ethereum).

[0081] The baseboard controller BMC is used to obtain the memory capacity of the local memory corresponding to the CPU after receiving the memory capacity reading instruction, and send the memory capacity to the microcontroller unit MCU. Specifically, the baseboard controller BMC is connected to the local memory of the CPU via I3C, and the memory capacity of the local memory is obtained via I3C.

[0082] In this embodiment, the host board is also provided with an I3C hub. When there are multiple CPUs on the host board, the baseboard controller BMC is connected to the local memory corresponding to the multiple CPUs through the I3C hub. The interface occupation of the baseboard controller BMC is reduced through the I3C hub, and it is not limited by the interface of the baseboard controller BMC, and can meet the memory capacity reading requirements of the local memory corresponding to the multiple CPUs on the host board.

[0083] In this embodiment, the local memory includes a serial detection chip SPD, and the baseboard controller BMC is connected to the serial detection chip SPD for reading the serial detection chip SPD to obtain the memory capacity. Specifically, the baseboard controller BMC is connected to the serial detection chip SPD via I3C.

[0084] In this embodiment, the host board is further provided with a second power-on controller CPLD_2 and a third voltage regulator corresponding to the CPU, and the second power-on controller CPLD_2 is connected to the baseboard controller BMC and the third voltage regulator. Figure 2 The third voltage regulators VR_0 and VR_1 corresponding to the two CPU_0 and CPU_1 are shown in FIG. 1 , and the baseboard controller BMC is connected to the second power-on controller CPLD_2 via I2C.

[0085] The CXL switch unit CXL SW is further used to send a write completion signal to the micro control unit MCU after writing the CXL memory start address into the register of the first port corresponding to the CPU. Specifically, the write completion signal is sent via I2C between the micro control unit MCU and the CXL switch unit CXL SW.

[0086] The microcontroller unit MCU is also used to send a host power-on instruction to the baseboard controller BMC after receiving the write completion signal. The baseboard controller BMC is also used to send the host power-on instruction to the second power-on controller CPLD_2. The second power-on controller CPLD_2 is used to control the third voltage regulator to power on the corresponding CPU after receiving the host power-on instruction. After the CPU is powered on, a communication link is established with the first port. After the power-on is completed, the third voltage regulator sends a host power-on completion signal to the microcontroller unit MCU through the second power-on controller CPLD_2 and the baseboard controller BMC.

[0087] Specifically, the microcontroller unit MCU sends a power-on signal to the baseboard controller BMC to start the host node through Eth, and the BMC transmits the host power-on signal to the second power-on controller CPLD_2 through I2C. The second power-on controller CPLD_2 sends the corresponding PWREN_0 and PWREN_1 to the third voltage regulators VR_0 and VR_1. VR_0 and VR_1 output voltages to CPU_0 and CPU_1 to complete initialization. CPU_0 and CPU_1 establish a communication link with the first ports USP_0 and USP_1 in the CXL switch unit CXL SW through the CXL bus, and then obtain the CXL memory. At the same time, VR_0 and VR_1 output host power-on completion signals PWRGD_0 and PWRGD_1 to the second power-on controller CPLD_2, and the second power-on controller CPLD_2 forwards the power-on completion signal to the BMC through the I2C bus. The BMC then forwards the host power-on completion signal to the MCU through Eth.

[0088] The microcontroller unit MCU is also connected with an indicator light. After the microcontroller unit MCU receives a power-on completion signal from the host, the start indicator light is turned on or changes from red to green, reminding the user that the CXL memory allocation has been completed.

[0089] In this embodiment, at least one of the CPUs is connected to a plurality of the first ports. When a CPU is connected to a plurality of first ports, a plurality of CXL memories can be accessed simultaneously, thereby improving the access efficiency of the CXL memory and increasing the data processing bandwidth of the CPU.

[0090] In this embodiment, the microcontroller unit MCU is also used to obtain the local memory identifier while obtaining the memory capacity of the local memory corresponding to the CPU, and send the local memory identifier (sent via I2C) to the CXL switching unit CXL SW, and the CXL switching unit CXL SW is used to write the CXL memory start address into the register of the first port corresponding to the local memory identifier according to a preset identifier mapping table, and the mapping relationship between the first port identifier and the local memory identifier is recorded in the identifier mapping table. Since the CPU corresponds to the local memory and the CPU is connected to the first port, the local memory identifier also corresponds to the first port identifier. By setting the identifier mapping table in the CXL switching unit CXL SW in advance, after the CXL memory start address is calculated, there is no need to manually specify the write port, and the CXL memory start address can be quickly and accurately written into the register of the corresponding first port.

[0091] The CXL switching unit CXL SW will perform CXL memory allocation according to the built-in CXL memory allocation mechanism. To achieve on-demand allocation, the CXL switching unit CXL SW pre-stores a first relationship table between the CPU identifier and the first port identifier, and a second relationship table between the CXL memory identifier and the second port identifier. The CXL switching unit CXL SW is also used to obtain the CXL memory identifier and the remaining capacity in real time after the memory controller is powered on, and send the CXL memory identifier and the remaining capacity to the micro control unit MCU. The micro control unit MCU is also used to obtain the CPU memory expansion demand and the CPU identifier in real time after the CPU is powered on, select the target CXL memory identifier corresponding to the remaining capacity with the smallest difference with the CPU memory expansion demand, and send the CPU identifier and the target CXL memory identifier to the CXL switching unit CXL SW. The CXL switching unit CXL SW is also used to determine the target first port according to the CPU identifier and the first relationship table, determine the target second port according to the target CXL memory identifier and the second relationship table, and establish a data path between the CPU target first port and the target second port (such as Figure 2 As shown, the physical connection between the first port and the second port in the CXL switch unit CXL SW is usually in a fully connected form, and each first port and any second port can form a data path), so as to realize the allocation of CXL memory to the CPU on demand, avoiding the problem that a small capacity needs to occupy a CXL memory with a large remaining capacity, resulting in low utilization rate of a single CXL memory and a lot of memory fragmentation.

[0092] In the case where the CPU memory expansion requirement is greater than the remaining capacity of all CXL memories, the microcontroller unit MCU is further used to select a minimum number of multiple target CXL memory identifiers, the sum of the remaining capacity of the CXL memory corresponding to the multiple target CXL memory identifiers is greater than the CPU memory expansion requirement, and send the CPU identifier and the corresponding multiple target CXL memory identifiers to the CXL switching unit CXL SW. The CXL switching unit CXL SW determines the target first port and multiple target second ports according to the CPU identifier and the corresponding multiple target CXL memory identifiers, as well as the first relationship table and the second relationship table, and establishes a data path between the target first port and the multiple target second ports. The minimum number of target CXL memory identifiers is selected, so that the CPU with a larger memory requirement is allocated enough memory space in a smaller number of CXL memories, and the CPU accesses less CXL memories, thereby improving the CPU access efficiency.

[0093] The CXL memory allocation method provided in the third embodiment of the present invention is implemented based on the above-mentioned CXL memory allocation system and is applied to a microcontroller unit MCU, such as Figure 3 As shown, the method includes:

[0094] Step S310: After the CXL switching unit is powered on, the memory capacity of the local memory corresponding to the CPU is obtained.

[0095] Step S320: Send the memory capacity to the CXL switching unit, the memory capacity is used to instruct the CXL switching unit to calculate the CXL memory start address according to the memory capacity, and write the CXL memory start address into the register of the first port corresponding to the CPU, and use the CXL memory start address as the first address of the CXL memory to allocate the CXL memory in the CXL memory board to the CPU, or calculate the CXL memory start address according to the memory capacity, and send the CXL memory start address to the CXL switching unit, the CXL memory start address is used to instruct the CXL switching unit to write the CXL memory start address into the register of the first port corresponding to the CPU, and use the CXL memory start address as the first address of the CXL memory to allocate the CXL memory in the CXL memory board to the CPU.

[0096] In this embodiment, step S310 specifically includes:

[0097] After the CXL switching unit is powered on, control the CXL memory board to power on.

[0098] After the CXL memory board is powered on, the memory capacity of the local memory corresponding to the CPU is obtained. That is, after the CXL switching unit and the CXL memory board are powered on, the memory capacity of the local memory corresponding to the CPU is obtained to ensure the correctness of the CXL memory allocation timing and avoid the problem of CXL memory allocation failure caused by failure to power on the CXL memory board after the memory capacity is obtained.

[0099] The CXL memory allocation method of this embodiment also includes: receiving a write completion signal sent by the CXL switching unit, and controlling the CPU in the host board to power on, so that after the CPU is powered on, the CXL switching unit uses the CXL memory start address as the first address of the CXL memory to allocate the CXL memory in the CXL memory board to the CPU. Wherein, the write completion signal is issued after the CXL switching unit writes the CXL memory start address into the register of the first port corresponding to the CPU. In this embodiment, after the CXL memory start address is written successfully, the CPU is controlled to power on, so as to avoid the problem that the CXL memory allocation fails because the CXL memory start address is not written into the corresponding first port after the CPU is powered on.

[0100] Below Figure 2Taking the CXL memory allocation system shown in the figure as an example, the CXL memory start address is calculated by the microcontroller unit MCU as an example, and the CXL memory allocation method is explained from the perspective of the interaction between the host board, the CXL switch board and the CXL memory board. Figure 4 As shown, including:

[0101] Step S410: the user presses the power button PWR_button, the first power-on controller CPLD_1 controls the first voltage regulator VR_SW to power on the CXL switch unit CXL SW, and the CXL switch unit CXL SW returns a power-on completion signal to the micro control unit MCU after being powered on.

[0102] Step S420: The microcontroller unit MCU sends a power-on instruction to the memory controller, and the second voltage regulator powers on the memory controller after receiving the power-on instruction, and the microcontroller unit MCU receives a power-on completion signal for the memory controller. Specifically, the two second voltage regulators VR_MXC_0 and VR_MXC_1 respectively power on the two memory controllers MXC_0 and MXC_1, and receive the power-on completion signal for the memory controller returned by the second voltage regulators VR_MXC_0 and VR_MXC_1.

[0103] Step S430: The microcontroller unit MCU sends a memory capacity read instruction to the baseboard controller BMC. The BMC reads the SPD of the CPU local memory through I3C to obtain the memory capacity, and sends the memory capacity to the MCU. The MCU calculates the CXL memory start address according to the memory capacity, and sends the CXL memory start address to the CXL switch unit CXL SW. Specifically, the BMC reads the SPD of the CPU local memory through the I3C hub, and sends the memory capacity to the microcontroller unit MCU through the network. The microcontroller unit MCU sends the CXL memory start address to the CXL switch unit CXL SW through I2C.

[0104] Step S440: The CXL switch unit CXL SW writes the CXL memory start address into the register of the first port corresponding to the CPU, and sends a write completion signal to the micro control unit MCU. Specifically, the CXL switch unit CXL SW sends the write completion signal to the micro control unit MCU via I2C.

[0105] Step S450: the micro control unit MCU sends a CPU power-on instruction to the baseboard controller BMC, the baseboard controller BMC controls the CPU to power on, and sends a CPU power-on completion signal to the micro control unit MCU.

[0106] The above process realizes the CXL memory allocation of the CPU, and there is no need to manually obtain the memory capacity of the CPU corresponding to the local memory, nor is there any need to manually calculate the register of the first port, which reduces the labor cost, avoids the situation of manual allocation errors, and improves the memory allocation efficiency of the entire CXL memory allocation system.

[0107] The CXL memory allocation device provided by the present invention is described below. The CXL memory allocation device described below and the CXL memory allocation method described above can be referred to each other.

[0108] The CXL memory allocation device provided in the fourth embodiment of the present invention is implemented based on the CXL memory allocation system described in the above embodiment and is applied to the micro control unit, such as Figure 5 As shown, the device comprises:

[0109] The memory capacity acquisition module 510 is used to acquire the memory capacity of the local memory corresponding to the CPU after the CXL switching unit is powered on.

[0110] The memory capacity processing module 520 is used to send the memory capacity to the CXL switching unit, where the memory capacity is used to instruct the CXL switching unit to calculate a CXL memory start address according to the memory capacity, and write the CXL memory start address into the register of the first port corresponding to the CPU, and use the CXL memory start address as the first address of the CXL memory to allocate the CXL memory in the CXL memory board to the CPU, or calculate the CXL memory start address according to the memory capacity, and send the CXL memory start address to the CXL switching unit, where the CXL memory start address is used to instruct the CXL switching unit to write the CXL memory start address into the register of the first port corresponding to the CPU, and use the CXL memory start address as the first address of the CXL memory to allocate the CXL memory in the CXL memory board to the CPU.

[0111] In the CXL memory allocation device of the present invention, after the CXL switching unit is powered on, the micro control unit automatically obtains the memory capacity of the local memory corresponding to the CPU, and the micro control unit or the CXL switching unit calculates the CXL memory start address according to the memory capacity, and the CXL switching unit automatically writes the CXL memory start address to the register of the first port, thereby realizing automatic allocation of the CXL memory to the CPU, and there is no need to manually obtain the memory capacity of the local memory corresponding to the CPU, nor is there any need to manually calculate the register of the first port, which reduces labor costs, avoids manual allocation errors, and improves the memory allocation efficiency of the entire CXL memory allocation system.

[0112] Optionally, the memory capacity acquisition module 510 is specifically configured to control the CXL memory board to power on after the CXL switch unit is powered on; and to acquire the memory capacity of the local memory corresponding to the CPU after the CXL memory board is powered on.

[0113] Optionally, the CXL memory allocation device further includes:

[0114] The host power-on control module is used to receive the write completion signal sent by the CXL switching unit, and control the power-on of the CPU in the host board, so that after the CPU is powered on, the CXL switching unit uses the CXL memory start address as the first address of the CXL memory to allocate the CXL memory in the CXL memory board to the CPU; wherein the write completion signal is sent after the CXL switching unit writes the CXL memory start address into the register of the first port corresponding to the CPU.

[0115] On the other hand, the present invention further provides a computer program product, the computer program product comprising a computer program, the computer program can be stored on a non-transitory computer-readable storage medium, when the computer program is executed by a processor, the computer can execute the CXL memory allocation method provided by the above methods, the method comprising:

[0116] After the CXL switching unit is powered on, the memory capacity of the local memory corresponding to the CPU is obtained.

[0117] The memory capacity is sent to the CXL switching unit, where the memory capacity is used to instruct the CXL switching unit to calculate a CXL memory start address according to the memory capacity, and write the CXL memory start address into a register of a first port corresponding to the CPU, and use the CXL memory start address as the first address of the CXL memory to allocate the CXL memory in the CXL memory board to the CPU; or the CXL memory start address is calculated according to the memory capacity, and the CXL memory start address is sent to the CXL switching unit, where the CXL memory start address is used to instruct the CXL switching unit to write the CXL memory start address into the register of the first port corresponding to the CPU, and use the CXL memory start address as the first address of the CXL memory to allocate the CXL memory in the CXL memory board to the CPU.

[0118] In another aspect, the present invention further provides a non-transitory computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the CXL memory allocation method provided by the above methods is implemented, and the method includes:

[0119] After the CXL switching unit is powered on, the memory capacity of the local memory corresponding to the CPU is obtained.

[0120] The memory capacity is sent to the CXL switching unit, where the memory capacity is used to instruct the CXL switching unit to calculate a CXL memory start address according to the memory capacity, and write the CXL memory start address into a register of a first port corresponding to the CPU, and use the CXL memory start address as the first address of the CXL memory to allocate the CXL memory in the CXL memory board to the CPU; or the CXL memory start address is calculated according to the memory capacity, and the CXL memory start address is sent to the CXL switching unit, where the CXL memory start address is used to instruct the CXL switching unit to write the CXL memory start address into the register of the first port corresponding to the CPU, and use the CXL memory start address as the first address of the CXL memory to allocate the CXL memory in the CXL memory board to the CPU.

[0121] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative labor.

[0122] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0123] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A CXL switch card, characterized in that: The CXL switch board is provided with a CXL switch unit and a micro control unit connected to the CXL switch unit, the CXL switch unit includes at least one first port and at least one second port, the first port is used to connect to the CPU in the host board, and the second port is used to connect to the CXL memory board to obtain the CXL memory in the CXL memory board; The micro control unit is used to send a memory capacity reading instruction to the baseboard controller in the host board after the CXL switching unit is powered on and before the CPU is powered on. After receiving the memory capacity reading instruction, the baseboard controller obtains the memory capacity of the local memory corresponding to the CPU by reading the serial detection chip of the local memory corresponding to the CPU, and sends the memory capacity to the micro control unit. The micro control unit or the CXL switching unit is used to calculate the CXL memory start address according to the memory capacity. The CXL switching unit is used to write the CXL memory start address into the register of the first port corresponding to the CPU, use the CXL memory start address as the first address of the CXL memory, and allocate the CXL memory in the CXL memory card to the CPU; The CXL switch board is also provided with a first voltage regulator and a first power-on controller, the first power-on controller is connected to the micro control unit and the first voltage regulator, the first voltage regulator is connected to the CXL switch unit, the first power-on controller is used to control the first voltage regulator to supply power to the CXL switch unit, after the CXL switch unit is powered on, the first voltage regulator feeds back a power-on completion signal of the CXL switch unit to the first power-on controller, and the first power-on controller feeds back a power-on completion signal of the CXL switch unit to the micro control unit; The micro control unit is used to control the CXL memory board to power on after receiving the power-on completion signal of the CXL switching unit, and obtain the memory capacity of the local memory corresponding to the CPU; The CXL switching unit is further used to send a write completion signal to the micro control unit after writing the CXL memory start address into the register of the first port corresponding to the CPU. The micro control unit is further used to control the CPU to power on after receiving the write completion signal. After the CPU is powered on, the CXL switching unit uses the CXL memory start address as the first address of the CXL memory to allocate the CXL memory in the CXL memory card to the CPU. The CXL switching unit pre-stores a first relationship table between a CPU identifier and a first port identifier, and a second relationship table between a CXL memory identifier and a second port identifier. The CXL switching unit is further used to obtain the CXL memory identifier and the remaining capacity in real time after the memory controller in the CXL memory board is powered on, and send the CXL memory identifier and the remaining capacity to the micro control unit MCU; the micro control unit MCU is further used to obtain the CPU memory expansion requirement and the CPU identifier in real time after the CPU is powered on, select a target CXL memory identifier corresponding to the remaining capacity with the smallest difference from the CPU memory expansion requirement, and send the CPU identifier and the target CXL memory identifier to the CXL switching unit. The CXL switching unit is further used to determine the target first port according to the CPU identifier and the first relationship table, determine the target second port according to the target CXL memory identifier and the second relationship table, and establish a data path between the CPU target first port and the target second port.

2. A CXL memory allocation system, characterized in that: include: A host board, a CXL switch board and a CXL memory board, wherein the host board is provided with at least one CPU and local memories respectively corresponding to the CPUs, the CXL switch board is provided with a CXL switch unit and a micro control unit connected to the CXL switch unit, the CXL switch unit comprises at least one first port and at least one second port, each of the CPUs is respectively connected to the first port, one first port is only connected to one CPU, the CXL switch unit is connected to the CXL memory board through the second port to obtain the CXL memory in the CXL memory board; the host board is also provided with a baseboard controller, the baseboard controller is connected to the micro control unit and the local memory; the local memory comprises a serial detection chip, the baseboard controller is connected to the serial detection chip, and is used to read the serial detection chip to obtain the memory capacity; The micro control unit is used to send a memory capacity reading instruction to the baseboard controller after the CXL switching unit is powered on and before the CPU is powered on. The baseboard controller is used to obtain the memory capacity of the local memory corresponding to the CPU after receiving the memory capacity reading instruction, and send the memory capacity to the micro control unit. The micro control unit or the CXL switching unit is used to calculate the CXL memory start address according to the memory capacity. The CXL switching unit is used to write the CXL memory start address into the register of the first port corresponding to the CPU, use the CXL memory start address as the first address of the CXL memory, and allocate the CXL memory in the CXL memory card to the CPU; The CXL switch board is also provided with a first voltage regulator and a first power-on controller, the first power-on controller is connected to the micro control unit and the first voltage regulator, the first voltage regulator is connected to the CXL switch unit, the first power-on controller is used to control the first voltage regulator to supply power to the CXL switch unit, after the CXL switch unit is powered on, the first voltage regulator feeds back a power-on completion signal of the CXL switch unit to the first power-on controller, and the first power-on controller feeds back a power-on completion signal of the CXL switch unit to the micro control unit; The micro control unit is used to control the CXL memory board to power on after receiving the power-on completion signal of the CXL switching unit, and obtain the memory capacity of the local memory corresponding to the CPU; The CXL switching unit is further used to send a write completion signal to the micro control unit after writing the CXL memory start address into the register of the first port corresponding to the CPU. The micro control unit is further used to control the CPU to power on after receiving the write completion signal. After the CPU is powered on, the CXL switching unit uses the CXL memory start address as the first address of the CXL memory to allocate the CXL memory in the CXL memory card to the CPU. The CXL switching unit pre-stores a first relationship table between a CPU identifier and a first port identifier, and a second relationship table between a CXL memory identifier and a second port identifier. The CXL switching unit is further used to obtain the CXL memory identifier and the remaining capacity in real time after the memory controller in the CXL memory board is powered on, and send the CXL memory identifier and the remaining capacity to the micro control unit MCU; the micro control unit MCU is further used to obtain the CPU memory expansion requirement and the CPU identifier in real time after the CPU is powered on, select a target CXL memory identifier corresponding to the remaining capacity with the smallest difference from the CPU memory expansion requirement, and send the CPU identifier and the target CXL memory identifier to the CXL switching unit. The CXL switching unit is further used to determine the target first port according to the CPU identifier and the first relationship table, determine the target second port according to the target CXL memory identifier and the second relationship table, and establish a data path between the CPU target first port and the target second port.

3. The CXL memory allocation system according to claim 2, characterized in that: The CXL memory board is provided with at least one CXL memory and a memory controller and a second voltage regulator corresponding to the CXL memory. The memory controller is connected to the corresponding CXL memory and the second voltage regulator. The micro control unit is connected to the second voltage regulator and is further used to control the second voltage regulator to supply power to the corresponding memory controller after the CXL switching unit is powered on, and receive a memory controller power-on completion signal fed back by the second voltage regulator. The second port is connected to the memory controller, and one memory controller is only connected to one second port. The CXL switching unit is used to establish a communication link with the memory controller based on the second port after the memory controller is powered on, and to feed back a communication link completion signal to the micro control unit. The CXL switching unit is used to obtain the CXL memory through the second port after the communication link is established.

4. The CXL memory allocation system according to claim 3, characterized in that: At least one second port is connected to a plurality of the memory controllers.

5. The CXL memory allocation system according to claim 2, characterized in that: The host board is also provided with an I3C hub. When there are multiple CPUs on the host board, the baseboard controller is connected to the local memories corresponding to the multiple CPUs through the I3C hub.

6. The CXL memory allocation system according to claim 2, characterized in that: The host board is also provided with a second power-on controller and a third voltage regulator corresponding to the CPU, wherein the second power-on controller is connected to the baseboard controller and the third voltage regulator; The CXL switching unit is further configured to send a write completion signal to the micro control unit after writing the CXL memory start address into the register of the first port corresponding to the CPU; The microcontroller unit is also used to send a host power-on instruction to the substrate controller after receiving the write completion signal. The substrate controller is also used to send the host power-on instruction to the second power-on controller. The second power-on controller is used to control the third voltage regulator to power on the corresponding CPU after receiving the host power-on instruction. After the CPU is powered on, a communication link is established with the first port. After power-on is completed, the third voltage regulator sends a host power-on completion signal to the microcontroller unit through the second power-on controller and the substrate controller.

7. The CXL memory allocation system according to claim 2, characterized in that: At least one of the CPUs is connected to a plurality of the first ports.

8. The CXL memory allocation system according to any one of claims 2 to 7, characterized in that: The micro control unit is also used to obtain the local memory identifier while obtaining the memory capacity of the local memory corresponding to the CPU, and send the local memory identifier to the CXL switching unit. The CXL switching unit is used to write the CXL memory start address into the register of the first port corresponding to the local memory identifier according to a preset identifier mapping table, and the identifier mapping table records the mapping relationship between the first port identifier and the local memory identifier.

9. A CXL memory allocation method, characterized in that: The CXL memory allocation system according to any one of claims 2 to 8 is implemented and applied to the microcontroller unit, and the method comprises: After the CXL switching unit is powered on, obtaining the memory capacity of the local memory corresponding to the CPU; The memory capacity is sent to the CXL switching unit, where the memory capacity is used to instruct the CXL switching unit to calculate a CXL memory start address according to the memory capacity, and write the CXL memory start address into a register of a first port corresponding to the CPU, and use the CXL memory start address as the first address of the CXL memory to allocate the CXL memory in the CXL memory board to the CPU; or the CXL memory start address is calculated according to the memory capacity, and the CXL memory start address is sent to the CXL switching unit, where the CXL memory start address is used to instruct the CXL switching unit to write the CXL memory start address into the register of the first port corresponding to the CPU, and use the CXL memory start address as the first address of the CXL memory to allocate the CXL memory in the CXL memory board to the CPU.

10. The CXL memory allocation method according to claim 9, characterized in that: After the CXL switching unit is powered on, the memory capacity of the local memory corresponding to the CPU is obtained, including: After the CXL switching unit is powered on, control the CXL memory board to power on; After the CXL memory board is powered on, the memory capacity of the local memory corresponding to the CPU is obtained.

11. The CXL memory allocation method according to claim 9, characterized in that: Also includes: receiving a write completion signal sent by the CXL switch unit, and controlling the CPU in the host board to power on, so that after the CPU is powered on, the CXL switch unit uses the CXL memory start address as the first address of the CXL memory, and allocates the CXL memory in the CXL memory board to the CPU; The write completion signal is sent after the CXL switch unit writes the CXL memory start address into the register of the first port corresponding to the CPU.

12. A CXL memory allocation device, characterized in that: The CXL memory allocation system according to any one of claims 2 to 8 is implemented and applied to the microcontroller unit, and the device comprises: A memory capacity acquisition module, used to acquire the memory capacity of the local memory corresponding to the CPU after the CXL switching unit is powered on; a memory capacity processing module, configured to send the memory capacity to the CXL switching unit, wherein the memory capacity is used to instruct the CXL switching unit to calculate a CXL memory start address according to the memory capacity, and write the CXL memory start address into a register of a first port corresponding to the CPU, and use the CXL memory start address as the first address of the CXL memory to allocate a CXL memory in a CXL memory board to the CPU; or calculate a CXL memory start address according to the memory capacity, and send the CXL memory start address to the CXL switching unit, wherein the CXL memory start address is used to instruct the CXL switching unit to write the CXL memory start address into the register of the first port corresponding to the CPU, and use the CXL memory start address as the first address of the CXL memory to allocate a CXL memory in a CXL memory board to the CPU.

13. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the CXL memory allocation method according to any one of claims 9 to 11 is implemented.

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